Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.61	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	44	2	42	95.45

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_sig_index_cp	4	0	4	100.00	100	1	1	0
esc_sig_len_cp	11	0	11	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
len_per_esc_sig	44	2	42	95.45	100	1	1	0

Summary for Variable esc_sig_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_sig_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
index[0x0]	170	1			T2	2		T45	1		T23	1
index[0x1]	183	1			T4	1		T5	1		T19	3
index[0x2]	164	1			T17	1		T18	1		T19	1
index[0x3]	185	1			T1	4		T2	3		T45	1

---

Summary for Variable esc_sig_len_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for esc_sig_len_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
lens_less_than_1000[0]	261	1			T1	4		T2	1		T17	1
lens_less_than_1000[1]	114	1			T19	4		T26	1		T27	1
lens_less_than_1000[2]	106	1			T2	2		T5	1		T18	1
lens_less_than_1000[3]	56	1			T4	1		T49	1		T27	1
lens_less_than_1000[4]	45	1			T45	1		T26	1		T272	1
lens_less_than_1000[5]	39	1			T2	2		T26	1		T51	1
lens_less_than_1000[6]	27	1			T26	1		T31	2		T239	1
lens_less_than_1000[7]	20	1			T45	1		T79	1		T92	1
lens_less_than_1000[8]	20	1			T79	2		T91	1		T273	1
lens_less_than_1000[9]	3	1			T274	1		T249	2		-	-
len_2	11	1			T53	1		T275	1		T276	1

---

Summary for Cross len_per_esc_sig

Samples crossed: esc_sig_index_cp esc_sig_len_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	44	2	42	95.45	2

Automatically Generated Cross Bins for len_per_esc_sig

Uncovered bins

esc_sig_index_cp	esc_sig_len_cp	COUNT	AT LEAST	NUMBER	STATUS
[index[0x1]]	[lens_less_than_1000[9]]	0	1	1
[index[0x3]]	[lens_less_than_1000[9]]	0	1	1

Covered bins

esc_sig_index_cp	esc_sig_len_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
index[0x0]	lens_less_than_1000[0]	67	1			T23	1		T244	1		T63	1
index[0x0]	lens_less_than_1000[1]	16	1			T27	1		T215	1		T38	1
index[0x0]	lens_less_than_1000[2]	31	1			T2	1		T231	1		T24	1
index[0x0]	lens_less_than_1000[3]	15	1			T61	1		T215	1		T273	1
index[0x0]	lens_less_than_1000[4]	7	1			T277	1		T38	1		T92	1
index[0x0]	lens_less_than_1000[5]	11	1			T2	1		T26	1		T51	1
index[0x0]	lens_less_than_1000[6]	6	1			T31	1		T278	1		T42	1
index[0x0]	lens_less_than_1000[7]	8	1			T45	1		T92	1		T279	1
index[0x0]	lens_less_than_1000[8]	5	1			T280	5		-	-		-	-
index[0x0]	lens_less_than_1000[9]	2	1			T274	1		T249	1		-	-
index[0x0]	len_2	2	1			T276	1		T103	1		-	-
index[0x1]	lens_less_than_1000[0]	65	1			T49	1		T232	1		T51	1
index[0x1]	lens_less_than_1000[1]	30	1			T19	3		T223	1		T281	2
index[0x1]	lens_less_than_1000[2]	31	1			T5	1		T23	1		T26	1
index[0x1]	lens_less_than_1000[3]	14	1			T4	1		T27	1		T282	1
index[0x1]	lens_less_than_1000[4]	13	1			T31	1		T215	1		T53	1
index[0x1]	lens_less_than_1000[5]	9	1			T79	1		T283	1		T273	1
index[0x1]	lens_less_than_1000[6]	7	1			T26	1		T239	1		T258	1
index[0x1]	lens_less_than_1000[7]	6	1			T255	1		T284	1		T285	1
index[0x1]	lens_less_than_1000[8]	6	1			T273	1		T284	1		T257	1
index[0x1]	len_2	2	1			T53	1		T286	1		-	-
index[0x2]	lens_less_than_1000[0]	58	1			T17	1		T48	1		T62	2
index[0x2]	lens_less_than_1000[1]	29	1			T19	1		T241	1		T287	1
index[0x2]	lens_less_than_1000[2]	22	1			T18	1		T26	1		T31	1
index[0x2]	lens_less_than_1000[3]	14	1			T49	1		T79	1		T76	1
index[0x2]	lens_less_than_1000[4]	10	1			T67	1		T82	1		T73	1
index[0x2]	lens_less_than_1000[5]	10	1			T91	1		T76	1		T92	1
index[0x2]	lens_less_than_1000[6]	12	1			T31	1		T71	1		T288	1
index[0x2]	lens_less_than_1000[7]	3	1			T79	1		T289	1		T290	1
index[0x2]	lens_less_than_1000[8]	1	1			T91	1		-	-		-	-
index[0x2]	lens_less_than_1000[9]	1	1			T249	1		-	-		-	-
index[0x2]	len_2	4	1			T275	1		T288	1		T291	1
index[0x3]	lens_less_than_1000[0]	71	1			T1	4		T2	1		T26	3
index[0x3]	lens_less_than_1000[1]	39	1			T26	1		T31	1		T78	1
index[0x3]	lens_less_than_1000[2]	22	1			T2	1		T15	1		T26	1
index[0x3]	lens_less_than_1000[3]	13	1			T292	1		T76	1		T223	1
index[0x3]	lens_less_than_1000[4]	15	1			T45	1		T26	1		T272	1
index[0x3]	lens_less_than_1000[5]	9	1			T2	1		T79	1		T187	1
index[0x3]	lens_less_than_1000[6]	2	1			T293	1		T294	1		-	-
index[0x3]	lens_less_than_1000[7]	3	1			T284	1		T295	1		T296	1
index[0x3]	lens_less_than_1000[8]	8	1			T79	2		T297	1		T257	1
index[0x3]	len_2	3	1			T288	2		T298	1		-	-