Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.89	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	40	6	34	85.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
intr_timeout_cnt_cp	10	0	10	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	40	6	34	85.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	80	1			T1	2		T18	1		T49	1
class_index[0x1]	79	1			T5	1		T19	3		T26	1
class_index[0x2]	67	1			T1	2		T26	1		T30	1
class_index[0x3]	60	1			T19	1		T65	1		T30	1

---

Summary for Variable intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for intr_timeout_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
intr_timeout_cnt[0]	111	1			T5	1		T18	1		T19	1
intr_timeout_cnt[1]	81	1			T1	2		T26	2		T30	1
intr_timeout_cnt[2]	26	1			T19	3		T67	1		T53	1
intr_timeout_cnt[3]	9	1			T70	1		T92	1		T98	1
intr_timeout_cnt[4]	12	1			T1	2		T29	1		T75	1
intr_timeout_cnt[5]	13	1			T53	1		T72	1		T96	1
intr_timeout_cnt[6]	13	1			T51	1		T38	3		T57	1
intr_timeout_cnt[7]	8	1			T37	1		T246	1		T247	1
intr_timeout_cnt[8]	10	1			T26	1		T51	1		T96	1
intr_timeout_cnt[9]	3	1			T84	1		T248	1		T249	1

---

Summary for Cross class_cnt_cross

Samples crossed: class_index_cp intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	6	34	85.00	6

Automatically Generated Cross Bins for class_cnt_cross

Uncovered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	NUMBER	STATUS
[class_index[0x0] , class_index[0x1]]	[intr_timeout_cnt[7]]	--	--	2
[class_index[0x2]]	[intr_timeout_cnt[6]]	0	1	1
[class_index[0x2]]	[intr_timeout_cnt[9]]	0	1	1
[class_index[0x3]]	[intr_timeout_cnt[4]]	0	1	1
[class_index[0x3]]	[intr_timeout_cnt[9]]	0	1	1

Covered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	intr_timeout_cnt[0]	39	1			T18	1		T49	1		T26	1
class_index[0x0]	intr_timeout_cnt[1]	20	1			T26	2		T69	2		T71	1
class_index[0x0]	intr_timeout_cnt[2]	2	1			T250	2		-	-		-	-
class_index[0x0]	intr_timeout_cnt[3]	2	1			T70	1		T251	1		-	-
class_index[0x0]	intr_timeout_cnt[4]	7	1			T1	2		T252	1		T94	1
class_index[0x0]	intr_timeout_cnt[5]	2	1			T53	1		T253	1		-	-
class_index[0x0]	intr_timeout_cnt[6]	4	1			T51	1		T247	1		T252	1
class_index[0x0]	intr_timeout_cnt[8]	2	1			T96	1		T254	1		-	-
class_index[0x0]	intr_timeout_cnt[9]	2	1			T84	1		T248	1		-	-
class_index[0x1]	intr_timeout_cnt[0]	28	1			T5	1		T26	1		T24	1
class_index[0x1]	intr_timeout_cnt[1]	22	1			T28	4		T71	7		T255	1
class_index[0x1]	intr_timeout_cnt[2]	10	1			T19	3		T67	1		T74	1
class_index[0x1]	intr_timeout_cnt[3]	2	1			T98	1		T252	1		-	-
class_index[0x1]	intr_timeout_cnt[4]	3	1			T75	1		T98	1		T256	1
class_index[0x1]	intr_timeout_cnt[5]	6	1			T72	1		T257	2		T258	1
class_index[0x1]	intr_timeout_cnt[6]	5	1			T57	1		T259	2		T88	1
class_index[0x1]	intr_timeout_cnt[8]	2	1			T253	1		T260	1		-	-
class_index[0x1]	intr_timeout_cnt[9]	1	1			T249	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[0]	22	1			T30	1		T261	3		T262	1
class_index[0x2]	intr_timeout_cnt[1]	24	1			T1	2		T71	1		T53	3
class_index[0x2]	intr_timeout_cnt[2]	6	1			T73	1		T76	1		T263	1
class_index[0x2]	intr_timeout_cnt[3]	2	1			T252	1		T264	1		-	-
class_index[0x2]	intr_timeout_cnt[4]	2	1			T29	1		T265	1		-	-
class_index[0x2]	intr_timeout_cnt[5]	2	1			T261	1		T259	1		-	-
class_index[0x2]	intr_timeout_cnt[7]	4	1			T247	1		T266	1		T257	1
class_index[0x2]	intr_timeout_cnt[8]	5	1			T26	1		T51	1		T247	1
class_index[0x3]	intr_timeout_cnt[0]	22	1			T19	1		T65	1		T105	1
class_index[0x3]	intr_timeout_cnt[1]	15	1			T30	1		T73	4		T261	1
class_index[0x3]	intr_timeout_cnt[2]	8	1			T53	1		T74	1		T267	5
class_index[0x3]	intr_timeout_cnt[3]	3	1			T92	1		T268	1		T269	1
class_index[0x3]	intr_timeout_cnt[5]	3	1			T96	1		T76	1		T270	1
class_index[0x3]	intr_timeout_cnt[6]	4	1			T38	3		T252	1		-	-
class_index[0x3]	intr_timeout_cnt[7]	4	1			T37	1		T246	1		T271	2
class_index[0x3]	intr_timeout_cnt[8]	1	1			T248	1		-	-		-	-