Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	379771	1			T1	2192		T2	1168		T3	3
all_values[1]	379771	1			T1	2192		T2	1168		T3	3
all_values[2]	379771	1			T1	2192		T2	1168		T3	3
all_values[3]	379771	1			T1	2192		T2	1168		T3	3

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

755989

1

T1

4396

T2

2369

T3

6

auto[1]

763095

1

T1

4372

T2

2303

T3

6

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

893305

1

T1

4957

T2

2645

T3

12

auto[1]

625779

1

T1

3811

T2

2027

T4

30

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	108465	1			T1	600		T2	309		T3	3
all_values[0]	auto[0]	auto[1]	80268	1			T1	478		T2	280		T5	405
all_values[0]	auto[1]	auto[0]	110360	1			T1	622		T2	301		T4	53
all_values[0]	auto[1]	auto[1]	80678	1			T1	492		T2	278		T5	454
all_values[1]	auto[0]	auto[0]	112061	1			T1	610		T2	370		T5	451
all_values[1]	auto[0]	auto[1]	77744	1			T1	527		T2	249		T5	435
all_values[1]	auto[1]	auto[0]	112540	1			T1	565		T2	333		T3	3
all_values[1]	auto[1]	auto[1]	77426	1			T1	490		T2	216		T4	4
all_values[2]	auto[0]	auto[0]	111096	1			T1	644		T2	324		T3	3
all_values[2]	auto[0]	auto[1]	77700	1			T1	451		T2	243		T5	427
all_values[2]	auto[1]	auto[0]	112882	1			T1	643		T2	351		T4	49
all_values[2]	auto[1]	auto[1]	78093	1			T1	454		T2	250		T4	4
all_values[3]	auto[0]	auto[0]	112076	1			T1	626		T2	333		T5	452
all_values[3]	auto[0]	auto[1]	76579	1			T1	460		T2	261		T5	448
all_values[3]	auto[1]	auto[0]	113825	1			T1	647		T2	324		T3	3
all_values[3]	auto[1]	auto[1]	77291	1			T1	459		T2	250		T4	22