Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	4	0	4	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	379771	1			T1	2192		T2	1168		T3	3
all_pins[1]	379771	1			T1	2192		T2	1168		T3	3
all_pins[2]	379771	1			T1	2192		T2	1168		T3	3
all_pins[3]	379771	1			T1	2192		T2	1168		T3	3

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1205596	1			T1	6873		T2	3678		T3	12
values[0x1]	313488	1			T1	1895		T2	994		T4	30
transitions[0x0=>0x1]	207733	1			T1	1278		T2	668		T4	26
transitions[0x1=>0x0]	207999	1			T1	1278		T2	668		T4	26

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	299093	1			T1	1700		T2	890		T3	3
all_pins[0]	values[0x1]	80678	1			T1	492		T2	278		T5	454
all_pins[0]	transitions[0x0=>0x1]	79949	1			T1	491		T2	276		T5	454
all_pins[0]	transitions[0x1=>0x0]	76828	1			T1	458		T2	248		T4	22
all_pins[1]	values[0x0]	302345	1			T1	1702		T2	952		T3	3
all_pins[1]	values[0x1]	77426	1			T1	490		T2	216		T4	4
all_pins[1]	transitions[0x0=>0x1]	42450	1			T1	273		T2	109		T4	4
all_pins[1]	transitions[0x1=>0x0]	45702	1			T1	275		T2	171		T5	229
all_pins[2]	values[0x0]	301678	1			T1	1738		T2	918		T3	3
all_pins[2]	values[0x1]	78093	1			T1	454		T2	250		T4	4
all_pins[2]	transitions[0x0=>0x1]	43131	1			T1	251		T2	155		T5	226
all_pins[2]	transitions[0x1=>0x0]	42464	1			T1	287		T2	121		T5	203
all_pins[3]	values[0x0]	302480	1			T1	1733		T2	918		T3	3
all_pins[3]	values[0x1]	77291	1			T1	459		T2	250		T4	22
all_pins[3]	transitions[0x0=>0x1]	42203	1			T1	263		T2	128		T4	22
all_pins[3]	transitions[0x1=>0x0]	43005	1			T1	258		T2	128		T4	4