Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	269	1			T148	7		T149	7		T226	4
all_values[1]	269	1			T148	7		T149	7		T226	4
all_values[2]	269	1			T148	7		T149	7		T226	4
all_values[3]	269	1			T148	7		T149	7		T226	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

648

1

T148

18

T149

15

T226

9

auto[1]

428

1

T148

10

T149

13

T226

7

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

407

1

T148

7

T149

10

T226

5

auto[1]

669

1

T148

21

T149

18

T226

11

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

637

1

T148

12

T149

17

T226

10

auto[1]

439

1

T148

16

T149

11

T226

6

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	24	0	24	100.00
Automatically Generated Cross Bins	24	0	24	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr

cp_intr_test

cp_intr_en

cp_intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_values[0]

auto[0]

auto[0]

auto[0]

60

1

T149

2

T337

1

T338

1

all_values[0]

auto[0]

auto[0]

auto[1]

36

1

T226

2

T337

1

T338

2

all_values[0]

auto[0]

auto[1]

auto[0]

46

1

T148

1

T149

1

T337

1

all_values[0]

auto[0]

auto[1]

auto[1]

24

1

T148

1

T149

2

T337

2

all_values[0]

auto[1]

auto[0]

auto[1]

65

1

T148

4

T149

1

T226

1

all_values[0]

auto[1]

auto[1]

auto[1]

38

1

T148

1

T149

1

T226

1

all_values[1]

auto[0]

auto[0]

auto[0]

50

1

T148

1

T149

1

T338

1

all_values[1]

auto[0]

auto[0]

auto[1]

33

1

T148

1

T149

1

T226

1

all_values[1]

auto[0]

auto[1]

auto[0]

41

1

T148

1

T149

2

T226

1

all_values[1]

auto[0]

auto[1]

auto[1]

25

1

T339

1

T340

1

T341

1

all_values[1]

auto[1]

auto[0]

auto[1]

69

1

T148

3

T149

2

T226

2

all_values[1]

auto[1]

auto[1]

auto[1]

51

1

T148

1

T149

1

T337

1

all_values[2]

auto[0]

auto[0]

auto[0]

74

1

T148

2

T149

1

T226

1

all_values[2]

auto[0]

auto[0]

auto[1]

40

1

T148

2

T149

1

T226

1

all_values[2]

auto[0]

auto[1]

auto[0]

41

1

T149

1

T226

1

T337

1

all_values[2]

auto[0]

auto[1]

auto[1]

15

1

T149

1

T340

1

T342

1

all_values[2]

auto[1]

auto[0]

auto[1]

65

1

T148

3

T149

2

T337

3

all_values[2]

auto[1]

auto[1]

auto[1]

34

1

T149

1

T226

1

T337

1

all_values[3]

auto[0]

auto[0]

auto[0]

64

1

T148

2

T149

1

T337

1

all_values[3]

auto[0]

auto[0]

auto[1]

30

1

T149

2

T338

2

T343

2

all_values[3]

auto[0]

auto[1]

auto[0]

31

1

T149

1

T226

2

T343

1

all_values[3]

auto[0]

auto[1]

auto[1]

27

1

T148

1

T226

1

T337

2

all_values[3]

auto[1]

auto[0]

auto[1]

62

1

T149

1

T226

1

T337

2

all_values[3]

auto[1]

auto[1]

auto[1]

55

1

T148

4

T149

2

T337

2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal