Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
accum_cnt_cp	6	0	6	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	24	0	24	100.00	100	1	1	0

Summary for Variable accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for accum_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
accum_cnt_2000	86748	1			T1	73		T5	971		T6	277
accum_cnt_1000	241861	1			T1	2722		T2	557		T5	1177
accum_cnt_100	27977	1			T1	159		T2	138		T5	55
accum_cnt_50	63985	1			T1	146		T2	112		T4	5
accum_cnt_10	202220	1			T1	140		T2	1431		T4	42
accum_cnt_0	445673	1			T1	3208		T2	1166		T3	8

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	279449	1			T1	1612		T2	851		T3	2
class_index[0x1]	279449	1			T1	1612		T2	851		T3	2
class_index[0x2]	279449	1			T1	1612		T2	851		T3	2
class_index[0x3]	279449	1			T1	1612		T2	851		T3	2

---

Summary for Cross class_cnt_cross

Samples crossed: class_index_cp accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for class_cnt_cross

Bins

class_index_cp	accum_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	accum_cnt_2000	24836	1			T23	507		T49	601		T62	364
class_index[0x0]	accum_cnt_1000	60525	1			T1	697		T2	3		T23	494
class_index[0x0]	accum_cnt_100	7462	1			T1	36		T2	43		T23	36
class_index[0x0]	accum_cnt_50	20698	1			T1	47		T2	30		T18	16
class_index[0x0]	accum_cnt_10	49880	1			T1	59		T2	681		T17	2
class_index[0x0]	accum_cnt_0	98759	1			T1	773		T2	94		T3	2
class_index[0x1]	accum_cnt_2000	20057	1			T1	73		T5	480		T62	358
class_index[0x1]	accum_cnt_1000	59448	1			T1	1337		T2	526		T5	731
class_index[0x1]	accum_cnt_100	7935	1			T1	71		T2	56		T5	35
class_index[0x1]	accum_cnt_50	15930	1			T1	57		T2	44		T5	33
class_index[0x1]	accum_cnt_10	47282	1			T1	26		T2	40		T4	18
class_index[0x1]	accum_cnt_0	119734	1			T1	48		T2	185		T3	2
class_index[0x2]	accum_cnt_2000	20263	1			T5	491		T23	220		T49	156
class_index[0x2]	accum_cnt_1000	65011	1			T1	688		T5	446		T43	39
class_index[0x2]	accum_cnt_100	6847	1			T1	29		T5	20		T43	19
class_index[0x2]	accum_cnt_50	12232	1			T1	27		T2	4		T5	16
class_index[0x2]	accum_cnt_10	54280	1			T1	52		T2	658		T6	1046
class_index[0x2]	accum_cnt_0	109763	1			T1	816		T2	189		T3	2
class_index[0x3]	accum_cnt_2000	21592	1			T6	277		T23	59		T31	492
class_index[0x3]	accum_cnt_1000	56877	1			T2	28		T6	680		T43	38
class_index[0x3]	accum_cnt_100	5733	1			T1	23		T2	39		T6	45
class_index[0x3]	accum_cnt_50	15125	1			T1	15		T2	34		T4	5
class_index[0x3]	accum_cnt_10	50778	1			T1	3		T2	52		T4	24
class_index[0x3]	accum_cnt_0	117417	1			T1	1571		T2	698		T3	2