Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	71	0	71	100.00
Crosses	138	0	138	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
alert_index_cp	65	0	65	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	130	0	130	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for alert_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	4179	1			T1	9		T49	51		T227	2
alert[0x1]	4788	1			T194	1		T49	85		T26	1
alert[0x2]	13254	1			T1	9		T4	1		T6	28
alert[0x3]	7196	1			T1	43		T4	1		T31	184
alert[0x4]	7755	1			T1	27		T2	19		T4	1
alert[0x5]	18218	1			T4	1		T7	1		T14	1
alert[0x6]	7477	1			T2	3		T23	42		T26	3
alert[0x7]	5362	1			T49	209		T229	1		T28	63
alert[0x8]	6430	1			T1	12		T4	1		T49	73
alert[0x9]	5212	1			T14	1		T15	2		T194	1
alert[0xa]	12488	1			T4	1		T7	1		T31	155
alert[0xb]	4295	1			T7	1		T49	572		T302	1
alert[0xc]	4889	1			T6	28		T23	16		T31	134
alert[0xd]	5526	1			T2	1		T6	596		T23	9
alert[0xe]	6680	1			T4	1		T5	18		T14	1
alert[0xf]	7680	1			T4	1		T6	86		T7	1
alert[0x10]	12456	1			T24	24		T241	3342		T303	1
alert[0x11]	8555	1			T9	1		T23	68		T49	202
alert[0x12]	3519	1			T4	1		T9	1		T15	1
alert[0x13]	11178	1			T26	3		T61	1		T231	167
alert[0x14]	14039	1			T1	116		T6	2642		T14	1
alert[0x15]	11491	1			T1	25		T4	1		T5	2
alert[0x16]	6678	1			T15	2		T23	214		T26	6
alert[0x17]	4524	1			T1	3		T4	1		T14	1
alert[0x18]	10274	1			T7	1		T49	75		T231	67
alert[0x19]	989	1			T15	1		T304	1		T52	31
alert[0x1a]	10190	1			T1	32		T4	1		T6	1515
alert[0x1b]	8208	1			T6	155		T15	1		T31	30
alert[0x1c]	13673	1			T232	1		T31	3		T52	111
alert[0x1d]	8801	1			T6	4586		T15	1		T241	398
alert[0x1e]	3956	1			T6	628		T31	209		T28	211
alert[0x1f]	9778	1			T1	37		T4	1		T5	2
alert[0x20]	3818	1			T9	1		T23	20		T49	380
alert[0x21]	7991	1			T194	1		T49	1502		T26	27
alert[0x22]	3615	1			T194	2		T31	78		T241	97
alert[0x23]	3110	1			T2	5		T9	1		T49	70
alert[0x24]	2863	1			T31	50		T231	2		T241	19
alert[0x25]	4461	1			T9	1		T23	39		T194	1
alert[0x26]	3967	1			T1	50		T4	1		T6	58
alert[0x27]	12523	1			T1	146		T4	1		T15	1
alert[0x28]	8385	1			T1	22		T4	1		T49	29
alert[0x29]	10049	1			T14	1		T26	2		T302	1
alert[0x2a]	4251	1			T5	1		T23	82		T194	1
alert[0x2b]	9554	1			T1	1		T15	1		T26	1
alert[0x2c]	14405	1			T15	1		T49	830		T232	1
alert[0x2d]	12066	1			T4	1		T6	33		T9	1
alert[0x2e]	7155	1			T2	1		T49	145		T28	79
alert[0x2f]	11274	1			T4	1		T31	159		T229	2
alert[0x30]	6690	1			T2	2		T4	1		T6	639
alert[0x31]	12800	1			T15	1		T49	123		T26	6
alert[0x32]	8111	1			T4	1		T14	1		T49	36
alert[0x33]	5431	1			T1	2		T9	1		T23	472
alert[0x34]	12418	1			T1	28		T48	7		T26	1
alert[0x35]	3438	1			T49	89		T26	1		T304	2
alert[0x36]	6218	1			T1	1		T4	1		T6	211
alert[0x37]	8137	1			T49	64		T26	3		T232	1
alert[0x38]	7625	1			T7	1		T23	81		T31	98
alert[0x39]	7005	1			T4	1		T9	1		T15	1
alert[0x3a]	7561	1			T5	8		T7	1		T14	1
alert[0x3b]	18493	1			T23	68		T26	1		T232	1
alert[0x3c]	6840	1			T6	195		T49	67		T24	91
alert[0x3d]	2834	1			T5	11		T7	2		T14	1
alert[0x3e]	9355	1			T2	1		T5	1		T31	64
alert[0x3f]	6516	1			T304	1		T231	193		T28	28
alert[0x40]	6256	1			T5	22		T23	2		T28	485

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	201949	1			T1	1		T2	5		T9	1
class_i[0x1]	79242	1			T5	27		T6	11400		T9	6
class_i[0x2]	109102	1			T1	556		T5	31		T9	1
class_i[0x3]	124660	1			T1	6		T2	27		T4	22

---

Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

alert_integrity_fail

514267

1

T1

563

T2

32

T5

65

alert_ping_fail

686

1

T4

22

T7

13

T9

9

---

Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	0	130	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	alert_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	alert[0x0]	4169	1			T1	9		T49	51		T28	1091
alert_integrity_fail	alert[0x1]	4782	1			T49	85		T26	1		T28	73
alert_integrity_fail	alert[0x2]	13246	1			T1	9		T6	28		T24	404
alert_integrity_fail	alert[0x3]	7189	1			T1	43		T31	184		T231	490
alert_integrity_fail	alert[0x4]	7741	1			T1	27		T2	19		T23	158
alert_integrity_fail	alert[0x5]	18202	1			T23	191		T231	15		T29	6
alert_integrity_fail	alert[0x6]	7461	1			T2	3		T23	42		T26	3
alert_integrity_fail	alert[0x7]	5355	1			T49	209		T28	63		T52	480
alert_integrity_fail	alert[0x8]	6411	1			T1	12		T49	73		T231	44
alert_integrity_fail	alert[0x9]	5200	1			T49	213		T231	9		T71	49
alert_integrity_fail	alert[0xa]	12468	1			T31	155		T231	181		T28	12
alert_integrity_fail	alert[0xb]	4287	1			T49	572		T31	208		T51	12
alert_integrity_fail	alert[0xc]	4886	1			T6	28		T23	16		T31	134
alert_integrity_fail	alert[0xd]	5520	1			T2	1		T6	596		T23	9
alert_integrity_fail	alert[0xe]	6667	1			T5	18		T23	17		T31	32
alert_integrity_fail	alert[0xf]	7671	1			T6	86		T48	27		T23	104
alert_integrity_fail	alert[0x10]	12444	1			T24	24		T241	3342		T303	1
alert_integrity_fail	alert[0x11]	8547	1			T23	68		T49	202		T31	273
alert_integrity_fail	alert[0x12]	3506	1			T49	58		T31	205		T24	34
alert_integrity_fail	alert[0x13]	11166	1			T26	3		T231	167		T28	727
alert_integrity_fail	alert[0x14]	14021	1			T1	116		T6	2642		T23	61
alert_integrity_fail	alert[0x15]	11480	1			T1	25		T5	2		T23	2
alert_integrity_fail	alert[0x16]	6666	1			T23	214		T26	6		T31	1233
alert_integrity_fail	alert[0x17]	4516	1			T1	3		T49	112		T231	224
alert_integrity_fail	alert[0x18]	10265	1			T49	75		T231	67		T28	126
alert_integrity_fail	alert[0x19]	979	1			T52	31		T71	33		T85	13
alert_integrity_fail	alert[0x1a]	10177	1			T1	32		T6	1515		T49	162
alert_integrity_fail	alert[0x1b]	8198	1			T6	155		T31	30		T231	41
alert_integrity_fail	alert[0x1c]	13659	1			T31	3		T52	111		T71	4619
alert_integrity_fail	alert[0x1d]	8795	1			T6	4586		T241	398		T53	2
alert_integrity_fail	alert[0x1e]	3951	1			T6	628		T31	209		T28	211
alert_integrity_fail	alert[0x1f]	9765	1			T1	37		T5	2		T49	92
alert_integrity_fail	alert[0x20]	3803	1			T23	20		T49	380		T28	27
alert_integrity_fail	alert[0x21]	7984	1			T49	1502		T26	27		T31	35
alert_integrity_fail	alert[0x22]	3606	1			T31	78		T241	97		T303	5
alert_integrity_fail	alert[0x23]	3097	1			T2	5		T49	70		T31	40
alert_integrity_fail	alert[0x24]	2852	1			T31	50		T231	2		T241	19
alert_integrity_fail	alert[0x25]	4450	1			T23	39		T26	23		T31	248
alert_integrity_fail	alert[0x26]	3954	1			T1	50		T6	58		T48	5
alert_integrity_fail	alert[0x27]	12510	1			T1	146		T49	22		T28	134
alert_integrity_fail	alert[0x28]	8369	1			T1	22		T49	29		T31	24
alert_integrity_fail	alert[0x29]	10037	1			T26	2		T31	57		T231	1110
alert_integrity_fail	alert[0x2a]	4238	1			T5	1		T23	82		T49	46
alert_integrity_fail	alert[0x2b]	9542	1			T1	1		T26	1		T31	1648
alert_integrity_fail	alert[0x2c]	14388	1			T49	830		T31	85		T231	7
alert_integrity_fail	alert[0x2d]	12056	1			T6	33		T31	1173		T28	1887
alert_integrity_fail	alert[0x2e]	7150	1			T2	1		T49	145		T28	79
alert_integrity_fail	alert[0x2f]	11261	1			T31	159		T231	220		T28	18
alert_integrity_fail	alert[0x30]	6681	1			T2	2		T6	639		T231	189
alert_integrity_fail	alert[0x31]	12787	1			T49	123		T26	6		T231	2042
alert_integrity_fail	alert[0x32]	8104	1			T49	36		T28	132		T24	7
alert_integrity_fail	alert[0x33]	5424	1			T1	2		T23	472		T31	490
alert_integrity_fail	alert[0x34]	12409	1			T1	28		T48	7		T26	1
alert_integrity_fail	alert[0x35]	3431	1			T49	89		T26	1		T231	51
alert_integrity_fail	alert[0x36]	6207	1			T1	1		T6	211		T31	111
alert_integrity_fail	alert[0x37]	8129	1			T49	64		T26	3		T231	794
alert_integrity_fail	alert[0x38]	7617	1			T23	81		T31	98		T241	68
alert_integrity_fail	alert[0x39]	6992	1			T23	1		T49	730		T31	335
alert_integrity_fail	alert[0x3a]	7552	1			T5	8		T49	18		T231	68
alert_integrity_fail	alert[0x3b]	18485	1			T23	68		T26	1		T31	11
alert_integrity_fail	alert[0x3c]	6832	1			T6	195		T49	67		T24	91
alert_integrity_fail	alert[0x3d]	2822	1			T5	11		T49	1		T231	7
alert_integrity_fail	alert[0x3e]	9347	1			T2	1		T5	1		T31	64
alert_integrity_fail	alert[0x3f]	6510	1			T231	193		T28	28		T24	199
alert_integrity_fail	alert[0x40]	6251	1			T5	22		T23	2		T28	485
alert_ping_fail	alert[0x0]	10	1			T227	2		T305	1		T282	1
alert_ping_fail	alert[0x1]	6	1			T194	1		T304	1		T305	1
alert_ping_fail	alert[0x2]	8	1			T4	1		T232	1		T306	1
alert_ping_fail	alert[0x3]	7	1			T4	1		T307	1		T308	1
alert_ping_fail	alert[0x4]	14	1			T4	1		T7	1		T9	1
alert_ping_fail	alert[0x5]	16	1			T4	1		T7	1		T14	1
alert_ping_fail	alert[0x6]	16	1			T302	2		T304	1		T309	1
alert_ping_fail	alert[0x7]	7	1			T229	1		T277	1		T310	1
alert_ping_fail	alert[0x8]	19	1			T4	1		T305	2		T191	1
alert_ping_fail	alert[0x9]	12	1			T14	1		T15	2		T194	1
alert_ping_fail	alert[0xa]	20	1			T4	1		T7	1		T306	1
alert_ping_fail	alert[0xb]	8	1			T7	1		T302	1		T306	1
alert_ping_fail	alert[0xc]	3	1			T311	2		T312	1		-	-
alert_ping_fail	alert[0xd]	6	1			T313	1		T314	1		T315	1
alert_ping_fail	alert[0xe]	13	1			T4	1		T14	1		T15	2
alert_ping_fail	alert[0xf]	9	1			T4	1		T7	1		T14	1
alert_ping_fail	alert[0x10]	12	1			T307	1		T316	1		T224	1
alert_ping_fail	alert[0x11]	8	1			T9	1		T227	1		T306	2
alert_ping_fail	alert[0x12]	13	1			T4	1		T9	1		T15	1
alert_ping_fail	alert[0x13]	12	1			T61	1		T300	1		T41	1
alert_ping_fail	alert[0x14]	18	1			T14	1		T15	1		T61	1
alert_ping_fail	alert[0x15]	11	1			T4	1		T7	1		T302	2
alert_ping_fail	alert[0x16]	12	1			T15	2		T304	1		T278	1
alert_ping_fail	alert[0x17]	8	1			T4	1		T14	1		T316	1
alert_ping_fail	alert[0x18]	9	1			T7	1		T306	1		T41	1
alert_ping_fail	alert[0x19]	10	1			T15	1		T304	1		T307	1
alert_ping_fail	alert[0x1a]	13	1			T4	1		T7	1		T14	1
alert_ping_fail	alert[0x1b]	10	1			T15	1		T41	1		T317	1
alert_ping_fail	alert[0x1c]	14	1			T232	1		T306	2		T305	1
alert_ping_fail	alert[0x1d]	6	1			T15	1		T213	1		T282	1
alert_ping_fail	alert[0x1e]	5	1			T213	1		T41	1		T309	1
alert_ping_fail	alert[0x1f]	13	1			T4	1		T14	1		T15	1
alert_ping_fail	alert[0x20]	15	1			T9	1		T227	1		T232	1
alert_ping_fail	alert[0x21]	7	1			T194	1		T307	1		T224	1
alert_ping_fail	alert[0x22]	9	1			T194	2		T318	1		T319	2
alert_ping_fail	alert[0x23]	13	1			T9	1		T304	1		T307	1
alert_ping_fail	alert[0x24]	11	1			T305	1		T307	1		T282	2
alert_ping_fail	alert[0x25]	11	1			T9	1		T194	1		T232	1
alert_ping_fail	alert[0x26]	13	1			T4	1		T14	1		T302	1
alert_ping_fail	alert[0x27]	13	1			T4	1		T15	1		T316	1
alert_ping_fail	alert[0x28]	16	1			T4	1		T278	1		T277	1
alert_ping_fail	alert[0x29]	12	1			T14	1		T302	1		T306	2
alert_ping_fail	alert[0x2a]	13	1			T194	1		T306	1		T305	1
alert_ping_fail	alert[0x2b]	12	1			T15	1		T304	1		T282	1
alert_ping_fail	alert[0x2c]	17	1			T15	1		T232	1		T304	1
alert_ping_fail	alert[0x2d]	10	1			T4	1		T9	1		T213	1
alert_ping_fail	alert[0x2e]	5	1			T320	1		T285	2		T321	1
alert_ping_fail	alert[0x2f]	13	1			T4	1		T229	2		T306	1
alert_ping_fail	alert[0x30]	9	1			T4	1		T14	1		T302	1
alert_ping_fail	alert[0x31]	13	1			T15	1		T302	1		T305	1
alert_ping_fail	alert[0x32]	7	1			T4	1		T14	1		T232	1
alert_ping_fail	alert[0x33]	7	1			T9	1		T213	1		T306	1
alert_ping_fail	alert[0x34]	9	1			T306	1		T277	1		T307	1
alert_ping_fail	alert[0x35]	7	1			T304	2		T41	1		T307	1
alert_ping_fail	alert[0x36]	11	1			T4	1		T7	1		T304	1
alert_ping_fail	alert[0x37]	8	1			T232	1		T282	1		T316	2
alert_ping_fail	alert[0x38]	8	1			T7	1		T306	1		T317	1
alert_ping_fail	alert[0x39]	13	1			T4	1		T9	1		T15	1
alert_ping_fail	alert[0x3a]	9	1			T7	1		T14	1		T194	1
alert_ping_fail	alert[0x3b]	8	1			T232	1		T282	1		T309	1
alert_ping_fail	alert[0x3c]	8	1			T213	1		T282	1		T313	1
alert_ping_fail	alert[0x3d]	12	1			T7	2		T14	1		T15	1
alert_ping_fail	alert[0x3e]	8	1			T304	1		T317	1		T308	1
alert_ping_fail	alert[0x3f]	6	1			T304	1		T306	1		T322	1
alert_ping_fail	alert[0x40]	5	1			T224	1		T323	1		T324	2

---

Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	class_i[0x0]	201806	1			T1	1		T2	5		T48	7
alert_integrity_fail	class_i[0x1]	79050	1			T5	27		T6	11400		T23	95
alert_integrity_fail	class_i[0x2]	108944	1			T1	556		T5	31		T48	27
alert_integrity_fail	class_i[0x3]	124467	1			T1	6		T2	27		T5	7
alert_ping_fail	class_i[0x0]	143	1			T9	1		T15	1		T194	6
alert_ping_fail	class_i[0x1]	192	1			T9	6		T15	1		T194	1
alert_ping_fail	class_i[0x2]	158	1			T9	1		T15	16		T194	1
alert_ping_fail	class_i[0x3]	193	1			T4	22		T7	13		T9	1