Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.66 99.99 98.78 100.00 100.00 100.00 99.38 99.48


Total test records in report: 833
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html
T130 /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.1467805705 Jul 10 04:50:40 PM PDT 24 Jul 10 05:01:22 PM PDT 24 9044263877 ps
T134 /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.3763437195 Jul 10 04:51:06 PM PDT 24 Jul 10 05:08:06 PM PDT 24 75548994792 ps
T121 /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.1487044397 Jul 10 04:50:53 PM PDT 24 Jul 10 04:52:38 PM PDT 24 8019679861 ps
T775 /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.924203822 Jul 10 04:51:20 PM PDT 24 Jul 10 04:51:24 PM PDT 24 11099494 ps
T776 /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.433463581 Jul 10 04:50:52 PM PDT 24 Jul 10 04:50:56 PM PDT 24 30330074 ps
T777 /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.3461297133 Jul 10 04:50:53 PM PDT 24 Jul 10 04:51:02 PM PDT 24 75596074 ps
T778 /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.484149368 Jul 10 04:50:59 PM PDT 24 Jul 10 04:51:15 PM PDT 24 665586681 ps
T779 /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.1946262320 Jul 10 04:51:02 PM PDT 24 Jul 10 04:51:11 PM PDT 24 178885652 ps
T780 /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.2165000907 Jul 10 04:51:19 PM PDT 24 Jul 10 04:51:22 PM PDT 24 19066623 ps
T781 /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.2998834801 Jul 10 04:50:39 PM PDT 24 Jul 10 04:50:42 PM PDT 24 35688539 ps
T782 /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.1309334498 Jul 10 04:50:54 PM PDT 24 Jul 10 04:51:07 PM PDT 24 87719397 ps
T783 /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.3757124244 Jul 10 04:50:40 PM PDT 24 Jul 10 04:53:36 PM PDT 24 2972602051 ps
T784 /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.2503530890 Jul 10 04:51:00 PM PDT 24 Jul 10 04:51:28 PM PDT 24 3174416633 ps
T123 /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.2685166541 Jul 10 04:50:58 PM PDT 24 Jul 10 04:52:54 PM PDT 24 850658373 ps
T785 /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.2336839055 Jul 10 04:51:06 PM PDT 24 Jul 10 04:51:11 PM PDT 24 24366721 ps
T786 /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.2988215392 Jul 10 04:51:20 PM PDT 24 Jul 10 04:51:23 PM PDT 24 36598764 ps
T787 /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.2585312230 Jul 10 04:50:54 PM PDT 24 Jul 10 04:51:01 PM PDT 24 91720740 ps
T788 /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.1270856242 Jul 10 04:51:14 PM PDT 24 Jul 10 04:51:21 PM PDT 24 53081905 ps
T789 /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.2704960463 Jul 10 04:50:46 PM PDT 24 Jul 10 04:52:07 PM PDT 24 580242245 ps
T790 /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.267982054 Jul 10 04:51:00 PM PDT 24 Jul 10 04:51:12 PM PDT 24 65764695 ps
T791 /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.1126722248 Jul 10 04:50:53 PM PDT 24 Jul 10 04:51:00 PM PDT 24 53803665 ps
T792 /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.3661223779 Jul 10 04:50:51 PM PDT 24 Jul 10 04:51:40 PM PDT 24 745798216 ps
T793 /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.282885086 Jul 10 04:50:39 PM PDT 24 Jul 10 04:50:42 PM PDT 24 7795119 ps
T794 /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.2335937493 Jul 10 04:50:41 PM PDT 24 Jul 10 04:52:24 PM PDT 24 965992492 ps
T133 /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.2179555755 Jul 10 04:50:53 PM PDT 24 Jul 10 04:59:40 PM PDT 24 12055022510 ps
T795 /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.405876401 Jul 10 04:51:20 PM PDT 24 Jul 10 04:51:23 PM PDT 24 6380281 ps
T135 /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.785802117 Jul 10 04:51:13 PM PDT 24 Jul 10 05:00:03 PM PDT 24 6567498203 ps
T796 /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.2326359156 Jul 10 04:50:58 PM PDT 24 Jul 10 04:51:26 PM PDT 24 357132819 ps
T153 /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.386027819 Jul 10 04:50:55 PM PDT 24 Jul 10 04:51:45 PM PDT 24 585850705 ps
T797 /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.2266624327 Jul 10 04:51:02 PM PDT 24 Jul 10 04:51:08 PM PDT 24 499348389 ps
T798 /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.1246090713 Jul 10 04:51:07 PM PDT 24 Jul 10 04:51:18 PM PDT 24 885652556 ps
T799 /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.3978709756 Jul 10 04:51:20 PM PDT 24 Jul 10 04:51:23 PM PDT 24 10021240 ps
T131 /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.2069848994 Jul 10 04:51:07 PM PDT 24 Jul 10 05:12:35 PM PDT 24 66477321090 ps
T800 /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.905391282 Jul 10 04:51:05 PM PDT 24 Jul 10 04:51:13 PM PDT 24 43173389 ps
T801 /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.4020084368 Jul 10 04:51:21 PM PDT 24 Jul 10 04:51:36 PM PDT 24 165338358 ps
T802 /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.2286683924 Jul 10 04:51:19 PM PDT 24 Jul 10 04:51:27 PM PDT 24 297594724 ps
T803 /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.2335666910 Jul 10 04:51:18 PM PDT 24 Jul 10 04:51:21 PM PDT 24 14502853 ps
T804 /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.4197934331 Jul 10 04:50:52 PM PDT 24 Jul 10 04:50:59 PM PDT 24 76920847 ps
T805 /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.686389449 Jul 10 04:50:55 PM PDT 24 Jul 10 04:51:08 PM PDT 24 153170272 ps
T806 /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.1238397527 Jul 10 04:51:26 PM PDT 24 Jul 10 04:51:28 PM PDT 24 6484335 ps
T136 /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.3560545761 Jul 10 04:51:15 PM PDT 24 Jul 10 04:57:16 PM PDT 24 2212097958 ps
T807 /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.1410631305 Jul 10 04:51:00 PM PDT 24 Jul 10 04:51:12 PM PDT 24 142649876 ps
T808 /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.2766122748 Jul 10 04:51:18 PM PDT 24 Jul 10 04:51:21 PM PDT 24 30142952 ps
T128 /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.3711856576 Jul 10 04:51:06 PM PDT 24 Jul 10 05:09:01 PM PDT 24 12294483705 ps
T809 /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.3395419178 Jul 10 04:51:08 PM PDT 24 Jul 10 04:51:19 PM PDT 24 70652874 ps
T810 /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.2106772954 Jul 10 04:50:40 PM PDT 24 Jul 10 04:50:51 PM PDT 24 83325300 ps
T162 /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.4281238436 Jul 10 04:50:47 PM PDT 24 Jul 10 04:50:51 PM PDT 24 37868643 ps
T125 /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.1392700792 Jul 10 04:51:05 PM PDT 24 Jul 10 04:52:38 PM PDT 24 817717637 ps
T811 /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.3328363764 Jul 10 04:50:52 PM PDT 24 Jul 10 04:50:58 PM PDT 24 59171529 ps
T812 /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.393332954 Jul 10 04:50:38 PM PDT 24 Jul 10 04:59:53 PM PDT 24 34203832842 ps
T140 /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.1603061199 Jul 10 04:50:59 PM PDT 24 Jul 10 04:57:37 PM PDT 24 42857063643 ps
T813 /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.3877575486 Jul 10 04:51:19 PM PDT 24 Jul 10 04:51:22 PM PDT 24 20038798 ps
T137 /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.2106155670 Jul 10 04:50:54 PM PDT 24 Jul 10 04:55:34 PM PDT 24 4495616864 ps
T814 /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.2351833846 Jul 10 04:51:00 PM PDT 24 Jul 10 04:51:12 PM PDT 24 66249850 ps
T815 /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.489955502 Jul 10 04:51:27 PM PDT 24 Jul 10 04:51:30 PM PDT 24 16955953 ps
T816 /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.1368052983 Jul 10 04:51:08 PM PDT 24 Jul 10 04:51:52 PM PDT 24 597228465 ps
T144 /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.3064584200 Jul 10 04:51:13 PM PDT 24 Jul 10 04:53:08 PM PDT 24 842422690 ps
T817 /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.3282076446 Jul 10 04:50:52 PM PDT 24 Jul 10 04:51:06 PM PDT 24 205395291 ps
T818 /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.3484738104 Jul 10 04:50:53 PM PDT 24 Jul 10 04:50:56 PM PDT 24 13877811 ps
T167 /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.1904734087 Jul 10 04:51:21 PM PDT 24 Jul 10 04:51:26 PM PDT 24 58732913 ps
T141 /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.2241851800 Jul 10 04:50:37 PM PDT 24 Jul 10 04:54:33 PM PDT 24 1807771870 ps
T819 /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.3149312799 Jul 10 04:50:38 PM PDT 24 Jul 10 04:50:43 PM PDT 24 28487393 ps
T142 /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.565160204 Jul 10 04:50:55 PM PDT 24 Jul 10 04:59:16 PM PDT 24 27769007643 ps
T820 /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.4098580123 Jul 10 04:51:20 PM PDT 24 Jul 10 04:51:23 PM PDT 24 9461750 ps
T156 /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.108882018 Jul 10 04:51:13 PM PDT 24 Jul 10 04:52:08 PM PDT 24 612718358 ps
T821 /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.2359404445 Jul 10 04:50:39 PM PDT 24 Jul 10 04:52:42 PM PDT 24 20559855474 ps
T822 /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.2739309608 Jul 10 04:51:05 PM PDT 24 Jul 10 04:51:21 PM PDT 24 263912968 ps
T823 /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.49572429 Jul 10 04:50:37 PM PDT 24 Jul 10 04:51:00 PM PDT 24 259338833 ps
T139 /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.3829094499 Jul 10 04:51:20 PM PDT 24 Jul 10 05:00:14 PM PDT 24 60284246134 ps
T824 /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.2116859136 Jul 10 04:50:57 PM PDT 24 Jul 10 04:51:00 PM PDT 24 7819145 ps
T138 /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.3545172667 Jul 10 04:51:07 PM PDT 24 Jul 10 04:53:00 PM PDT 24 802702709 ps
T160 /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.1220595059 Jul 10 04:50:40 PM PDT 24 Jul 10 04:50:45 PM PDT 24 27664795 ps
T825 /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.740500049 Jul 10 04:50:33 PM PDT 24 Jul 10 04:50:42 PM PDT 24 118140784 ps
T826 /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.953836754 Jul 10 04:50:33 PM PDT 24 Jul 10 04:50:43 PM PDT 24 37633639 ps
T827 /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.3518865226 Jul 10 04:50:46 PM PDT 24 Jul 10 04:51:01 PM PDT 24 181969366 ps
T828 /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.1124150561 Jul 10 04:50:40 PM PDT 24 Jul 10 04:50:50 PM PDT 24 97543638 ps
T829 /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.812340113 Jul 10 04:50:41 PM PDT 24 Jul 10 04:50:52 PM PDT 24 166908412 ps
T830 /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.3531742184 Jul 10 04:51:20 PM PDT 24 Jul 10 04:51:24 PM PDT 24 16690727 ps
T143 /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.3789747145 Jul 10 04:51:03 PM PDT 24 Jul 10 04:54:31 PM PDT 24 3492623965 ps
T122 /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.1352830138 Jul 10 04:51:07 PM PDT 24 Jul 10 04:53:58 PM PDT 24 1501826592 ps
T831 /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.153072993 Jul 10 04:50:39 PM PDT 24 Jul 10 04:55:40 PM PDT 24 7971452020 ps
T832 /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.1713692410 Jul 10 04:51:27 PM PDT 24 Jul 10 04:51:30 PM PDT 24 24446418 ps
T833 /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.3883942529 Jul 10 04:51:14 PM PDT 24 Jul 10 04:51:25 PM PDT 24 515374862 ps

Test location /workspace/coverage/default/36.alert_handler_stress_all_with_rand_reset.3062952092
Short name T1
Test name
Test status
Simulation time 179555782416 ps
CPU time 6022.87 seconds
Started Jul 10 05:30:31 PM PDT 24
Finished Jul 10 07:10:55 PM PDT 24
Peak memory 320164 kb
Host smart-6d20445c-ed24-477e-b664-91b5f81c7b8c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062952092 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 36.alert_handler_stress_all_with_rand_reset.3062952092
Directory /workspace/36.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all.3127321679
Short name T26
Test name
Test status
Simulation time 73542011409 ps
CPU time 4203.09 seconds
Started Jul 10 05:32:23 PM PDT 24
Finished Jul 10 06:42:28 PM PDT 24
Peak memory 305484 kb
Host smart-81e7fa67-2153-4119-bda8-c31d46b7d451
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127321679 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_ha
ndler_stress_all.3127321679
Directory /workspace/45.alert_handler_stress_all/latest

Test location /workspace/coverage/default/0.alert_handler_sec_cm.1878840907
Short name T10
Test name
Test status
Simulation time 270186269 ps
CPU time 16.51 seconds
Started Jul 10 05:27:19 PM PDT 24
Finished Jul 10 05:27:36 PM PDT 24
Peak memory 270360 kb
Host smart-ebce79a9-96a5-4ecd-94e4-8681d8c6e15b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1878840907 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sec_cm.1878840907
Directory /workspace/0.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all.1685456668
Short name T31
Test name
Test status
Simulation time 225104710493 ps
CPU time 3142.49 seconds
Started Jul 10 05:27:53 PM PDT 24
Finished Jul 10 06:20:17 PM PDT 24
Peak memory 297948 kb
Host smart-7c23f3d9-8e00-4d48-9d3d-54fe4ea972f0
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685456668 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_ha
ndler_stress_all.1685456668
Directory /workspace/14.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.574478536
Short name T146
Test name
Test status
Simulation time 181658667 ps
CPU time 26.88 seconds
Started Jul 10 04:50:41 PM PDT 24
Finished Jul 10 04:51:10 PM PDT 24
Peak memory 240380 kb
Host smart-9124534c-74d6-415e-a0bf-1705ee3584cf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=574478536 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_intg_err.574478536
Directory /workspace/3.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all_with_rand_reset.309678448
Short name T52
Test name
Test status
Simulation time 73181967412 ps
CPU time 2559.6 seconds
Started Jul 10 05:28:49 PM PDT 24
Finished Jul 10 06:11:30 PM PDT 24
Peak memory 289548 kb
Host smart-7149a459-0c7d-4d5e-9314-6a90ea4b662f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309678448 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 23.alert_handler_stress_all_with_rand_reset.309678448
Directory /workspace/23.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.alert_handler_lpg.3576040989
Short name T61
Test name
Test status
Simulation time 87500831479 ps
CPU time 2551.65 seconds
Started Jul 10 05:32:59 PM PDT 24
Finished Jul 10 06:15:32 PM PDT 24
Peak memory 290380 kb
Host smart-9d7f0fe8-ea38-4440-beba-8ea3a8ddf4dd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576040989 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg.3576040989
Directory /workspace/48.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.4075207726
Short name T116
Test name
Test status
Simulation time 4911215464 ps
CPU time 391.65 seconds
Started Jul 10 04:51:19 PM PDT 24
Finished Jul 10 04:57:52 PM PDT 24
Peak memory 265332 kb
Host smart-b6b9bc4c-7657-41bc-8fb5-0b041e39b849
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4075207726 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shadow_reg_err
ors.4075207726
Directory /workspace/19.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all_with_rand_reset.2660998780
Short name T79
Test name
Test status
Simulation time 70282411720 ps
CPU time 4448.29 seconds
Started Jul 10 05:27:42 PM PDT 24
Finished Jul 10 06:41:54 PM PDT 24
Peak memory 306884 kb
Host smart-e5cf4bb2-d287-4b16-b29f-d5773fd6ca41
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660998780 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 9.alert_handler_stress_all_with_rand_reset.2660998780
Directory /workspace/9.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all_with_rand_reset.2071881671
Short name T27
Test name
Test status
Simulation time 44849426265 ps
CPU time 1020.99 seconds
Started Jul 10 05:28:36 PM PDT 24
Finished Jul 10 05:45:38 PM PDT 24
Peak memory 273656 kb
Host smart-8520ea05-e542-4be8-81f9-f7f3d191797d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071881671 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 20.alert_handler_stress_all_with_rand_reset.2071881671
Directory /workspace/20.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all.61949258
Short name T2
Test name
Test status
Simulation time 41365341479 ps
CPU time 721 seconds
Started Jul 10 05:29:58 PM PDT 24
Finished Jul 10 05:42:00 PM PDT 24
Peak memory 273092 kb
Host smart-b55b378e-b31e-406c-8572-26b405f0eaab
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61949258 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_hand
ler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_hand
ler_stress_all.61949258
Directory /workspace/33.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.824175051
Short name T111
Test name
Test status
Simulation time 16950470912 ps
CPU time 1295.06 seconds
Started Jul 10 04:50:46 PM PDT 24
Finished Jul 10 05:12:22 PM PDT 24
Peak memory 265292 kb
Host smart-e6125829-fa78-4274-922e-1da961c2124a
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824175051 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.alert_handler_shadow_reg_errors_with_csr_rw.824175051
Directory /workspace/6.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.3689295370
Short name T112
Test name
Test status
Simulation time 5197219100 ps
CPU time 560.44 seconds
Started Jul 10 04:51:06 PM PDT 24
Finished Jul 10 05:00:29 PM PDT 24
Peak memory 265240 kb
Host smart-3c2c8c4e-3793-400b-8887-be72775e9399
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689295370 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 12.alert_handler_shadow_reg_errors_with_csr_rw.3689295370
Directory /workspace/12.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/29.alert_handler_lpg.4118767812
Short name T640
Test name
Test status
Simulation time 40940604935 ps
CPU time 2133.04 seconds
Started Jul 10 05:29:18 PM PDT 24
Finished Jul 10 06:04:52 PM PDT 24
Peak memory 290288 kb
Host smart-01388e5c-76b8-45db-996b-8e997d39f041
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118767812 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg.4118767812
Directory /workspace/29.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.634505638
Short name T119
Test name
Test status
Simulation time 3846473183 ps
CPU time 206.32 seconds
Started Jul 10 04:51:03 PM PDT 24
Finished Jul 10 04:54:30 PM PDT 24
Peak memory 265460 kb
Host smart-22e021b3-aacb-424e-8d0b-6652ca7f0811
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=634505638 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shadow_reg_erro
rs.634505638
Directory /workspace/13.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/49.alert_handler_ping_timeout.1915319973
Short name T4
Test name
Test status
Simulation time 28995802847 ps
CPU time 554.6 seconds
Started Jul 10 05:33:17 PM PDT 24
Finished Jul 10 05:42:33 PM PDT 24
Peak memory 249380 kb
Host smart-edd5b0ab-2212-4005-8b44-4df403f0e877
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915319973 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_ping_timeout.1915319973
Directory /workspace/49.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_lpg.2568211962
Short name T325
Test name
Test status
Simulation time 65966614047 ps
CPU time 1800.08 seconds
Started Jul 10 05:27:42 PM PDT 24
Finished Jul 10 05:57:45 PM PDT 24
Peak memory 290440 kb
Host smart-a7ba1bd1-1b24-4634-937e-72f6518e9c19
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568211962 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg.2568211962
Directory /workspace/9.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.2853184396
Short name T149
Test name
Test status
Simulation time 91158409 ps
CPU time 1.39 seconds
Started Jul 10 04:51:06 PM PDT 24
Finished Jul 10 04:51:11 PM PDT 24
Peak memory 236528 kb
Host smart-84fa632d-73af-4f9e-b242-dbd0ef1abaa2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2853184396 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_intr_test.2853184396
Directory /workspace/11.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.1612964527
Short name T113
Test name
Test status
Simulation time 12793310913 ps
CPU time 980.01 seconds
Started Jul 10 04:51:00 PM PDT 24
Finished Jul 10 05:07:22 PM PDT 24
Peak memory 265364 kb
Host smart-542cb806-8511-4b6e-8122-55ccce9032ea
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612964527 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 13.alert_handler_shadow_reg_errors_with_csr_rw.1612964527
Directory /workspace/13.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/39.alert_handler_lpg.1753958591
Short name T276
Test name
Test status
Simulation time 31437908311 ps
CPU time 2083.16 seconds
Started Jul 10 05:31:04 PM PDT 24
Finished Jul 10 06:05:48 PM PDT 24
Peak memory 285980 kb
Host smart-8785199a-c96f-4ab8-a55e-6b08b00bc76b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753958591 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg.1753958591
Directory /workspace/39.alert_handler_lpg/latest

Test location /workspace/coverage/default/1.alert_handler_ping_timeout.2829034214
Short name T304
Test name
Test status
Simulation time 22133916241 ps
CPU time 450.28 seconds
Started Jul 10 05:27:15 PM PDT 24
Finished Jul 10 05:34:47 PM PDT 24
Peak memory 249408 kb
Host smart-977759e9-a9aa-4ecf-ab11-d3f41cc3550a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829034214 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_ping_timeout.2829034214
Directory /workspace/1.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.4186990491
Short name T118
Test name
Test status
Simulation time 32022924689 ps
CPU time 1059.6 seconds
Started Jul 10 04:50:54 PM PDT 24
Finished Jul 10 05:08:35 PM PDT 24
Peak memory 265192 kb
Host smart-e61a266f-c6ae-4e60-9a7a-0fd70e52e782
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186990491 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.alert_handler_shadow_reg_errors_with_csr_rw.4186990491
Directory /workspace/4.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.2241851800
Short name T141
Test name
Test status
Simulation time 1807771870 ps
CPU time 233.49 seconds
Started Jul 10 04:50:37 PM PDT 24
Finished Jul 10 04:54:33 PM PDT 24
Peak memory 264848 kb
Host smart-d1d71028-296f-4f63-8a70-f65e7d7b256a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2241851800 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shadow_reg_erro
rs.2241851800
Directory /workspace/1.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/27.alert_handler_lpg.2961467309
Short name T279
Test name
Test status
Simulation time 44857521694 ps
CPU time 2535.38 seconds
Started Jul 10 05:29:08 PM PDT 24
Finished Jul 10 06:11:25 PM PDT 24
Peak memory 283004 kb
Host smart-16484990-71bb-43d9-9d28-e5c3d394759b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961467309 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg.2961467309
Directory /workspace/27.alert_handler_lpg/latest

Test location /workspace/coverage/default/45.alert_handler_ping_timeout.2998156408
Short name T224
Test name
Test status
Simulation time 17092689937 ps
CPU time 698.48 seconds
Started Jul 10 05:32:18 PM PDT 24
Finished Jul 10 05:43:57 PM PDT 24
Peak memory 256040 kb
Host smart-b7cebc39-5d12-4a76-bf6b-e001411b26d9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998156408 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_ping_timeout.2998156408
Directory /workspace/45.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all.3570476629
Short name T38
Test name
Test status
Simulation time 304671765780 ps
CPU time 3681.66 seconds
Started Jul 10 05:29:55 PM PDT 24
Finished Jul 10 06:31:17 PM PDT 24
Peak memory 298416 kb
Host smart-6a014cb4-bd2c-498e-8f1f-5d60120e2693
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570476629 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_ha
ndler_stress_all.3570476629
Directory /workspace/32.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.805459565
Short name T106
Test name
Test status
Simulation time 6176052083 ps
CPU time 172.94 seconds
Started Jul 10 04:50:53 PM PDT 24
Finished Jul 10 04:53:47 PM PDT 24
Peak memory 273484 kb
Host smart-138ff284-83e0-4fba-ae67-79d432989eb8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=805459565 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shadow_reg_error
s.805459565
Directory /workspace/9.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all_with_rand_reset.2430360776
Short name T257
Test name
Test status
Simulation time 92196212144 ps
CPU time 8877.48 seconds
Started Jul 10 05:27:25 PM PDT 24
Finished Jul 10 07:55:26 PM PDT 24
Peak memory 371616 kb
Host smart-a8729ddb-57b0-4142-96b8-da8b82bdb790
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430360776 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.alert_handler_stress_all_with_rand_reset.2430360776
Directory /workspace/1.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.alert_handler_ping_timeout.971196053
Short name T310
Test name
Test status
Simulation time 11923911184 ps
CPU time 261.81 seconds
Started Jul 10 05:28:35 PM PDT 24
Finished Jul 10 05:32:57 PM PDT 24
Peak memory 249320 kb
Host smart-abcf3aee-abd1-4748-b9e2-599e0a8a1c27
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971196053 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_ping_timeout.971196053
Directory /workspace/21.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.181222743
Short name T110
Test name
Test status
Simulation time 123339514404 ps
CPU time 1090.12 seconds
Started Jul 10 04:50:53 PM PDT 24
Finished Jul 10 05:09:04 PM PDT 24
Peak memory 265392 kb
Host smart-40c2f4cd-699b-4310-bc6d-1edea04c041b
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181222743 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.alert_handler_shadow_reg_errors_with_csr_rw.181222743
Directory /workspace/9.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/12.alert_handler_lpg.2765235149
Short name T329
Test name
Test status
Simulation time 50279978650 ps
CPU time 2796.51 seconds
Started Jul 10 05:27:41 PM PDT 24
Finished Jul 10 06:14:22 PM PDT 24
Peak memory 286540 kb
Host smart-cb2e6a2b-1808-4044-ad1f-d6711cab4fb0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765235149 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg.2765235149
Directory /workspace/12.alert_handler_lpg/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all_with_rand_reset.3413778478
Short name T76
Test name
Test status
Simulation time 193225508497 ps
CPU time 4151.06 seconds
Started Jul 10 05:32:53 PM PDT 24
Finished Jul 10 06:42:05 PM PDT 24
Peak memory 350544 kb
Host smart-9e1f53a5-c275-42bf-a676-e9ba98314ff0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413778478 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 47.alert_handler_stress_all_with_rand_reset.3413778478
Directory /workspace/47.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all_with_rand_reset.3468955640
Short name T98
Test name
Test status
Simulation time 14610860981 ps
CPU time 855.48 seconds
Started Jul 10 05:27:43 PM PDT 24
Finished Jul 10 05:42:02 PM PDT 24
Peak memory 274300 kb
Host smart-aad6c210-949a-42c9-b817-729f3d25d7f1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468955640 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 11.alert_handler_stress_all_with_rand_reset.3468955640
Directory /workspace/11.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.alert_handler_sig_int_fail.3008639560
Short name T249
Test name
Test status
Simulation time 1048336071 ps
CPU time 32.6 seconds
Started Jul 10 05:27:52 PM PDT 24
Finished Jul 10 05:28:26 PM PDT 24
Peak memory 248360 kb
Host smart-105cd4c3-9813-4d97-9866-761801659827
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30086
39560 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_sig_int_fail.3008639560
Directory /workspace/13.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/14.alert_handler_lpg.1920893533
Short name T333
Test name
Test status
Simulation time 24728621940 ps
CPU time 1689.72 seconds
Started Jul 10 05:27:47 PM PDT 24
Finished Jul 10 05:55:59 PM PDT 24
Peak memory 273624 kb
Host smart-e031e42e-6657-48fd-81e7-8fb6f2b187aa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920893533 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg.1920893533
Directory /workspace/14.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.1236822670
Short name T129
Test name
Test status
Simulation time 1126888310 ps
CPU time 111.4 seconds
Started Jul 10 04:50:34 PM PDT 24
Finished Jul 10 04:52:28 PM PDT 24
Peak memory 265344 kb
Host smart-c743b102-cf80-49d6-b229-e684837a3fde
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1236822670 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shadow_reg_erro
rs.1236822670
Directory /workspace/0.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/14.alert_handler_ping_timeout.2755092011
Short name T667
Test name
Test status
Simulation time 9168986826 ps
CPU time 359.47 seconds
Started Jul 10 05:27:48 PM PDT 24
Finished Jul 10 05:33:49 PM PDT 24
Peak memory 256196 kb
Host smart-4393eab7-14b2-464e-a7e5-e6718a0d46c1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755092011 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_ping_timeout.2755092011
Directory /workspace/14.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.3716677092
Short name T159
Test name
Test status
Simulation time 316011702 ps
CPU time 26.6 seconds
Started Jul 10 04:51:06 PM PDT 24
Finished Jul 10 04:51:35 PM PDT 24
Peak memory 240376 kb
Host smart-a84f8aef-e63f-4fc7-91fe-470d824715d4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3716677092 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_intg_err.3716677092
Directory /workspace/13.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.2069848994
Short name T131
Test name
Test status
Simulation time 66477321090 ps
CPU time 1285.16 seconds
Started Jul 10 04:51:07 PM PDT 24
Finished Jul 10 05:12:35 PM PDT 24
Peak memory 265496 kb
Host smart-56ab198c-ec8e-4b8b-a6df-96146745ace3
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069848994 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 16.alert_handler_shadow_reg_errors_with_csr_rw.2069848994
Directory /workspace/16.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/13.alert_handler_ping_timeout.4031999555
Short name T311
Test name
Test status
Simulation time 26853793765 ps
CPU time 531.3 seconds
Started Jul 10 05:27:49 PM PDT 24
Finished Jul 10 05:36:42 PM PDT 24
Peak memory 249256 kb
Host smart-ffe63103-5b5a-4eb7-8949-8a296821d75e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031999555 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_ping_timeout.4031999555
Directory /workspace/13.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_ping_timeout.4267762802
Short name T306
Test name
Test status
Simulation time 47249023017 ps
CPU time 528.12 seconds
Started Jul 10 05:29:14 PM PDT 24
Finished Jul 10 05:38:02 PM PDT 24
Peak memory 249380 kb
Host smart-51dd087f-d336-41eb-bec3-3c7fc4ef531b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267762802 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_ping_timeout.4267762802
Directory /workspace/28.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all_with_rand_reset.771247632
Short name T53
Test name
Test status
Simulation time 192274939039 ps
CPU time 2433.85 seconds
Started Jul 10 05:27:34 PM PDT 24
Finished Jul 10 06:08:10 PM PDT 24
Peak memory 290520 kb
Host smart-8bb6cccf-6a1c-4c76-94e3-2c8333196700
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771247632 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 5.alert_handler_stress_all_with_rand_reset.771247632
Directory /workspace/5.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.3516453541
Short name T155
Test name
Test status
Simulation time 112049205 ps
CPU time 4.52 seconds
Started Jul 10 04:50:59 PM PDT 24
Finished Jul 10 04:51:05 PM PDT 24
Peak memory 239652 kb
Host smart-dcb5fe99-8b07-420c-ad24-6baa6594a59e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3516453541 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_intg_err.3516453541
Directory /workspace/11.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.1467805705
Short name T130
Test name
Test status
Simulation time 9044263877 ps
CPU time 640.21 seconds
Started Jul 10 04:50:40 PM PDT 24
Finished Jul 10 05:01:22 PM PDT 24
Peak memory 265304 kb
Host smart-171e0004-54c9-4c22-9f63-decc4d2b4e8f
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467805705 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.alert_handler_shadow_reg_errors_with_csr_rw.1467805705
Directory /workspace/2.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/0.alert_handler_alert_accum_saturation.3271536852
Short name T195
Test name
Test status
Simulation time 45925388 ps
CPU time 3.53 seconds
Started Jul 10 05:27:25 PM PDT 24
Finished Jul 10 05:27:32 PM PDT 24
Peak memory 249588 kb
Host smart-7a604a87-593f-4bfc-b354-641d3ca5e786
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3271536852 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_alert_accum_saturation.3271536852
Directory /workspace/0.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/1.alert_handler_alert_accum_saturation.530728874
Short name T200
Test name
Test status
Simulation time 17686907 ps
CPU time 2.92 seconds
Started Jul 10 05:27:21 PM PDT 24
Finished Jul 10 05:27:25 PM PDT 24
Peak memory 249560 kb
Host smart-b1eb3c64-f8c3-46b2-be7b-a6a7d7fcb680
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=530728874 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_alert_accum_saturation.530728874
Directory /workspace/1.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/15.alert_handler_alert_accum_saturation.2720565760
Short name T197
Test name
Test status
Simulation time 37520639 ps
CPU time 3.53 seconds
Started Jul 10 05:27:52 PM PDT 24
Finished Jul 10 05:27:57 PM PDT 24
Peak memory 249584 kb
Host smart-fed09949-8c40-4ba8-93fa-2020536d2183
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2720565760 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_alert_accum_saturation.2720565760
Directory /workspace/15.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/16.alert_handler_alert_accum_saturation.1659052076
Short name T196
Test name
Test status
Simulation time 40890068 ps
CPU time 3.94 seconds
Started Jul 10 05:28:12 PM PDT 24
Finished Jul 10 05:28:17 PM PDT 24
Peak memory 249536 kb
Host smart-1c595df7-3264-428e-9fd1-832b2bba4ced
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1659052076 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_alert_accum_saturation.1659052076
Directory /workspace/16.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.3789747145
Short name T143
Test name
Test status
Simulation time 3492623965 ps
CPU time 207.97 seconds
Started Jul 10 04:51:03 PM PDT 24
Finished Jul 10 04:54:31 PM PDT 24
Peak memory 265308 kb
Host smart-721ae7d2-5855-4569-8dbb-8d1c94844407
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3789747145 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shadow_reg_err
ors.3789747145
Directory /workspace/11.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.2756401735
Short name T340
Test name
Test status
Simulation time 6523823 ps
CPU time 1.5 seconds
Started Jul 10 04:50:33 PM PDT 24
Finished Jul 10 04:50:36 PM PDT 24
Peak memory 237460 kb
Host smart-b54ac4a4-c2d4-4e9a-89f8-c73b2b7e7741
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2756401735 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_intr_test.2756401735
Directory /workspace/0.alert_handler_intr_test/latest

Test location /workspace/coverage/default/13.alert_handler_lpg.3654523556
Short name T294
Test name
Test status
Simulation time 127375881671 ps
CPU time 3333.85 seconds
Started Jul 10 05:27:49 PM PDT 24
Finished Jul 10 06:23:25 PM PDT 24
Peak memory 290288 kb
Host smart-45418a75-9a7a-44d3-8dbb-00bb41710ad0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654523556 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg.3654523556
Directory /workspace/13.alert_handler_lpg/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all_with_rand_reset.2026437335
Short name T24
Test name
Test status
Simulation time 41264068362 ps
CPU time 4087.66 seconds
Started Jul 10 05:28:30 PM PDT 24
Finished Jul 10 06:36:39 PM PDT 24
Peak memory 322604 kb
Host smart-0cb33e05-14e3-44d1-8149-f3cc29cb90d3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026437335 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 19.alert_handler_stress_all_with_rand_reset.2026437335
Directory /workspace/19.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.alert_handler_random_classes.730946940
Short name T284
Test name
Test status
Simulation time 638650719 ps
CPU time 22.56 seconds
Started Jul 10 05:28:34 PM PDT 24
Finished Jul 10 05:28:57 PM PDT 24
Peak memory 248820 kb
Host smart-0802ca0e-4a6b-45f1-a5ea-b65019b6a08c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73094
6940 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_classes.730946940
Directory /workspace/21.alert_handler_random_classes/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all.4069030501
Short name T248
Test name
Test status
Simulation time 2933159392 ps
CPU time 168.8 seconds
Started Jul 10 05:29:03 PM PDT 24
Finished Jul 10 05:31:53 PM PDT 24
Peak memory 257596 kb
Host smart-780b89f1-351c-48eb-aab7-b73a39f48fa4
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069030501 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_ha
ndler_stress_all.4069030501
Directory /workspace/25.alert_handler_stress_all/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all_with_rand_reset.178603735
Short name T259
Test name
Test status
Simulation time 54547369388 ps
CPU time 2356.18 seconds
Started Jul 10 05:30:52 PM PDT 24
Finished Jul 10 06:10:09 PM PDT 24
Peak memory 287348 kb
Host smart-d43963ff-d11f-425f-9953-3d0795ff0142
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178603735 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 37.alert_handler_stress_all_with_rand_reset.178603735
Directory /workspace/37.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all.1958252284
Short name T252
Test name
Test status
Simulation time 67132474728 ps
CPU time 2057.69 seconds
Started Jul 10 05:27:29 PM PDT 24
Finished Jul 10 06:01:49 PM PDT 24
Peak memory 290088 kb
Host smart-0f19fe75-1ca5-4b2c-a951-f56cfe319fdc
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958252284 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_han
dler_stress_all.1958252284
Directory /workspace/4.alert_handler_stress_all/latest

Test location /workspace/coverage/default/43.alert_handler_lpg.4277285786
Short name T328
Test name
Test status
Simulation time 693515457103 ps
CPU time 2504.63 seconds
Started Jul 10 05:31:58 PM PDT 24
Finished Jul 10 06:13:43 PM PDT 24
Peak memory 289952 kb
Host smart-71861706-47e6-475e-8adc-dd144c324f50
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277285786 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg.4277285786
Directory /workspace/43.alert_handler_lpg/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all.2479756637
Short name T288
Test name
Test status
Simulation time 28097573939 ps
CPU time 1351.68 seconds
Started Jul 10 05:33:06 PM PDT 24
Finished Jul 10 05:55:39 PM PDT 24
Peak memory 287908 kb
Host smart-0908c677-70bc-48cc-a8e9-63983ab30627
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479756637 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_ha
ndler_stress_all.2479756637
Directory /workspace/48.alert_handler_stress_all/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all_with_rand_reset.4275900077
Short name T94
Test name
Test status
Simulation time 669463443344 ps
CPU time 6145.09 seconds
Started Jul 10 05:29:38 PM PDT 24
Finished Jul 10 07:12:04 PM PDT 24
Peak memory 355148 kb
Host smart-205e0031-a2fa-45e5-baa6-b78f28eafa8f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275900077 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.alert_handler_stress_all_with_rand_reset.4275900077
Directory /workspace/30.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.3851196924
Short name T132
Test name
Test status
Simulation time 8419191528 ps
CPU time 186.49 seconds
Started Jul 10 04:51:10 PM PDT 24
Finished Jul 10 04:54:19 PM PDT 24
Peak memory 265244 kb
Host smart-62322c9a-5fea-4a32-a030-e9c0738a584e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3851196924 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shadow_reg_err
ors.3851196924
Directory /workspace/17.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/40.alert_handler_random_classes.1603931628
Short name T21
Test name
Test status
Simulation time 3532539062 ps
CPU time 37.03 seconds
Started Jul 10 05:31:09 PM PDT 24
Finished Jul 10 05:31:47 PM PDT 24
Peak memory 257076 kb
Host smart-56f769db-b3bd-41cf-adc6-0630cbf0e8c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16039
31628 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_classes.1603931628
Directory /workspace/40.alert_handler_random_classes/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.3064584200
Short name T144
Test name
Test status
Simulation time 842422690 ps
CPU time 113.26 seconds
Started Jul 10 04:51:13 PM PDT 24
Finished Jul 10 04:53:08 PM PDT 24
Peak memory 264664 kb
Host smart-32ec16bf-e12d-4002-9b26-fac89e59d86a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3064584200 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shadow_reg_err
ors.3064584200
Directory /workspace/18.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.723551072
Short name T114
Test name
Test status
Simulation time 11561485269 ps
CPU time 357.92 seconds
Started Jul 10 04:50:40 PM PDT 24
Finished Jul 10 04:56:41 PM PDT 24
Peak memory 272572 kb
Host smart-8e50a644-0f02-456c-b3bd-e188adb38744
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=723551072 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shadow_reg_error
s.723551072
Directory /workspace/2.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.747366413
Short name T337
Test name
Test status
Simulation time 8895722 ps
CPU time 1.55 seconds
Started Jul 10 04:50:58 PM PDT 24
Finished Jul 10 04:51:01 PM PDT 24
Peak memory 237464 kb
Host smart-be07e602-5fae-4050-93e3-d7469f4bf43c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=747366413 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_intr_test.747366413
Directory /workspace/10.alert_handler_intr_test/latest

Test location /workspace/coverage/default/0.alert_handler_esc_intr_timeout.1806948370
Short name T461
Test name
Test status
Simulation time 1326363205 ps
CPU time 29.84 seconds
Started Jul 10 05:27:11 PM PDT 24
Finished Jul 10 05:27:43 PM PDT 24
Peak memory 249656 kb
Host smart-5d9c8441-0cdd-49c7-837a-e3d9e8d35cca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18069
48370 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_intr_timeout.1806948370
Directory /workspace/0.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_ping_timeout.3498402849
Short name T308
Test name
Test status
Simulation time 53719742579 ps
CPU time 295.26 seconds
Started Jul 10 05:27:16 PM PDT 24
Finished Jul 10 05:32:12 PM PDT 24
Peak memory 248380 kb
Host smart-a4ea2939-f5bf-4760-8943-d2a6ed39759b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3498402849 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_ping_timeout.3498402849
Directory /workspace/0.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_sig_int_fail.361619382
Short name T254
Test name
Test status
Simulation time 714226597 ps
CPU time 49.96 seconds
Started Jul 10 05:27:19 PM PDT 24
Finished Jul 10 05:28:10 PM PDT 24
Peak memory 256896 kb
Host smart-9eaf3e81-aadd-4b7e-920c-81b203ce3cab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36161
9382 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sig_int_fail.361619382
Directory /workspace/1.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/10.alert_handler_lpg.3903041122
Short name T320
Test name
Test status
Simulation time 410326718082 ps
CPU time 1620.54 seconds
Started Jul 10 05:27:43 PM PDT 24
Finished Jul 10 05:54:47 PM PDT 24
Peak memory 273348 kb
Host smart-cc2a5d95-ea4a-479c-bb27-578ba4d86f6e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903041122 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg.3903041122
Directory /workspace/10.alert_handler_lpg/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all_with_rand_reset.1110817457
Short name T265
Test name
Test status
Simulation time 122142777258 ps
CPU time 3067.44 seconds
Started Jul 10 05:27:46 PM PDT 24
Finished Jul 10 06:18:57 PM PDT 24
Peak memory 322924 kb
Host smart-fb333808-c467-4427-9a47-c6d5e385ac9a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110817457 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 10.alert_handler_stress_all_with_rand_reset.1110817457
Directory /workspace/10.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.alert_handler_sig_int_fail.1016179835
Short name T268
Test name
Test status
Simulation time 799728178 ps
CPU time 21.29 seconds
Started Jul 10 05:27:50 PM PDT 24
Finished Jul 10 05:28:13 PM PDT 24
Peak memory 249128 kb
Host smart-b2d6ff3b-ee99-477a-9e97-1dd389ccd474
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10161
79835 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_sig_int_fail.1016179835
Directory /workspace/15.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/27.alert_handler_sig_int_fail.1284394883
Short name T251
Test name
Test status
Simulation time 244935476 ps
CPU time 12.85 seconds
Started Jul 10 05:29:09 PM PDT 24
Finished Jul 10 05:29:22 PM PDT 24
Peak memory 248564 kb
Host smart-5dabc528-8299-45f6-abaa-0c4fcece22f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12843
94883 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_sig_int_fail.1284394883
Directory /workspace/27.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all_with_rand_reset.3374921895
Short name T260
Test name
Test status
Simulation time 299755720152 ps
CPU time 5195.32 seconds
Started Jul 10 05:29:07 PM PDT 24
Finished Jul 10 06:55:44 PM PDT 24
Peak memory 322800 kb
Host smart-9bed4156-eee1-445d-82ba-ef4201bc5d54
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374921895 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.alert_handler_stress_all_with_rand_reset.3374921895
Directory /workspace/27.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.alert_handler_random_classes.1658118062
Short name T91
Test name
Test status
Simulation time 483334451 ps
CPU time 41.43 seconds
Started Jul 10 05:27:27 PM PDT 24
Finished Jul 10 05:28:11 PM PDT 24
Peak memory 248996 kb
Host smart-32d94f3b-d6f4-4c46-b8ae-bc737771a1a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16581
18062 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_classes.1658118062
Directory /workspace/3.alert_handler_random_classes/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all_with_rand_reset.3606237119
Short name T250
Test name
Test status
Simulation time 23503896485 ps
CPU time 1394.18 seconds
Started Jul 10 05:29:56 PM PDT 24
Finished Jul 10 05:53:10 PM PDT 24
Peak memory 274092 kb
Host smart-e23e9157-9ecc-4535-8488-873a5772ab6d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606237119 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 32.alert_handler_stress_all_with_rand_reset.3606237119
Directory /workspace/32.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.alert_handler_sig_int_fail.2089636540
Short name T246
Test name
Test status
Simulation time 188971226 ps
CPU time 12.37 seconds
Started Jul 10 05:30:03 PM PDT 24
Finished Jul 10 05:30:16 PM PDT 24
Peak memory 248776 kb
Host smart-bb561d40-c377-4992-ab57-87bab31dec16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20896
36540 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_sig_int_fail.2089636540
Directory /workspace/33.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/35.alert_handler_entropy.2891149272
Short name T280
Test name
Test status
Simulation time 65471369483 ps
CPU time 723.6 seconds
Started Jul 10 05:30:20 PM PDT 24
Finished Jul 10 05:42:24 PM PDT 24
Peak memory 273888 kb
Host smart-31a2594f-8e5e-433b-894f-0e1011c87ebb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891149272 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_entropy.2891149272
Directory /workspace/35.alert_handler_entropy/latest

Test location /workspace/coverage/default/1.alert_handler_sec_cm.3504085851
Short name T32
Test name
Test status
Simulation time 539788073 ps
CPU time 27.24 seconds
Started Jul 10 05:27:25 PM PDT 24
Finished Jul 10 05:27:55 PM PDT 24
Peak memory 277396 kb
Host smart-d890ea17-8383-4746-8133-93c158bde7f2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3504085851 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sec_cm.3504085851
Directory /workspace/1.alert_handler_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.108882018
Short name T156
Test name
Test status
Simulation time 612718358 ps
CPU time 53.98 seconds
Started Jul 10 04:51:13 PM PDT 24
Finished Jul 10 04:52:08 PM PDT 24
Peak memory 240392 kb
Host smart-91717f79-70fe-4e26-8c70-df26ef0fffc3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=108882018 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_intg_err.108882018
Directory /workspace/17.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.2058782870
Short name T157
Test name
Test status
Simulation time 109886792 ps
CPU time 3.48 seconds
Started Jul 10 04:50:52 PM PDT 24
Finished Jul 10 04:50:57 PM PDT 24
Peak memory 237384 kb
Host smart-b1a2cda3-02ee-4024-80f9-72d73733cb7a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2058782870 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_intg_err.2058782870
Directory /workspace/7.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.4096146669
Short name T161
Test name
Test status
Simulation time 84485022 ps
CPU time 5.25 seconds
Started Jul 10 04:51:05 PM PDT 24
Finished Jul 10 04:51:12 PM PDT 24
Peak memory 236512 kb
Host smart-1cfbcb05-e90a-4b57-9b29-21a4a062d5ee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4096146669 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_intg_err.4096146669
Directory /workspace/15.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.2556101750
Short name T152
Test name
Test status
Simulation time 4428655971 ps
CPU time 90.42 seconds
Started Jul 10 04:50:46 PM PDT 24
Finished Jul 10 04:52:18 PM PDT 24
Peak memory 240556 kb
Host smart-59a05509-dfc6-40d4-b02a-f5c427c92562
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2556101750 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_intg_err.2556101750
Directory /workspace/5.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.3630925234
Short name T163
Test name
Test status
Simulation time 1249424723 ps
CPU time 89.04 seconds
Started Jul 10 04:50:33 PM PDT 24
Finished Jul 10 04:52:04 PM PDT 24
Peak memory 245664 kb
Host smart-4143760a-e91c-4cfb-92dc-2c76262bcacb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3630925234 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_intg_err.3630925234
Directory /workspace/0.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.3154879476
Short name T147
Test name
Test status
Simulation time 86075529 ps
CPU time 5.18 seconds
Started Jul 10 04:50:39 PM PDT 24
Finished Jul 10 04:50:46 PM PDT 24
Peak memory 237440 kb
Host smart-d88d922a-afa9-479f-bc7d-3e6d6bd29579
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3154879476 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_intg_err.3154879476
Directory /workspace/1.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.2748001230
Short name T151
Test name
Test status
Simulation time 1832683234 ps
CPU time 35.99 seconds
Started Jul 10 04:51:02 PM PDT 24
Finished Jul 10 04:51:39 PM PDT 24
Peak memory 240384 kb
Host smart-590d2a9b-4d94-46fa-a6ef-63b95b148313
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2748001230 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_intg_err.2748001230
Directory /workspace/10.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.1110200197
Short name T115
Test name
Test status
Simulation time 49220616710 ps
CPU time 922.9 seconds
Started Jul 10 04:50:53 PM PDT 24
Finished Jul 10 05:06:18 PM PDT 24
Peak memory 265220 kb
Host smart-0c0dcebf-d9f3-4996-9c1b-99997ee6335d
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110200197 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.alert_handler_shadow_reg_errors_with_csr_rw.1110200197
Directory /workspace/1.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.1555770390
Short name T145
Test name
Test status
Simulation time 132192449 ps
CPU time 2.18 seconds
Started Jul 10 04:51:07 PM PDT 24
Finished Jul 10 04:51:12 PM PDT 24
Peak memory 239012 kb
Host smart-ff753a94-275b-4d11-81ed-afe76ab7852a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1555770390 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_intg_err.1555770390
Directory /workspace/14.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.3956756422
Short name T154
Test name
Test status
Simulation time 497897834 ps
CPU time 41.03 seconds
Started Jul 10 04:50:39 PM PDT 24
Finished Jul 10 04:51:22 PM PDT 24
Peak memory 246172 kb
Host smart-11c1bdb0-5fcb-4219-ab3c-39da9fd2f41a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3956756422 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_intg_err.3956756422
Directory /workspace/2.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.1220595059
Short name T160
Test name
Test status
Simulation time 27664795 ps
CPU time 2.77 seconds
Started Jul 10 04:50:40 PM PDT 24
Finished Jul 10 04:50:45 PM PDT 24
Peak memory 237720 kb
Host smart-09a58ff3-4f7b-45b7-9820-2676c8638d69
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1220595059 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_intg_err.1220595059
Directory /workspace/4.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.386027819
Short name T153
Test name
Test status
Simulation time 585850705 ps
CPU time 48.46 seconds
Started Jul 10 04:50:55 PM PDT 24
Finished Jul 10 04:51:45 PM PDT 24
Peak memory 240492 kb
Host smart-4e47276c-8d87-4180-b8c6-aa6f3f8e0b0c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=386027819 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_intg_err.386027819
Directory /workspace/9.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.1940008247
Short name T168
Test name
Test status
Simulation time 114867177 ps
CPU time 2.78 seconds
Started Jul 10 04:51:06 PM PDT 24
Finished Jul 10 04:51:11 PM PDT 24
Peak memory 237676 kb
Host smart-598e3370-1616-4cc5-b7c1-519a3f55baa6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1940008247 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_intg_err.1940008247
Directory /workspace/16.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.2474163756
Short name T158
Test name
Test status
Simulation time 585747569 ps
CPU time 28.64 seconds
Started Jul 10 04:51:15 PM PDT 24
Finished Jul 10 04:51:45 PM PDT 24
Peak memory 240392 kb
Host smart-f8686383-4953-4ed1-9a43-3c8f0a86b6ab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2474163756 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_intg_err.2474163756
Directory /workspace/18.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.1904734087
Short name T167
Test name
Test status
Simulation time 58732913 ps
CPU time 2.86 seconds
Started Jul 10 04:51:21 PM PDT 24
Finished Jul 10 04:51:26 PM PDT 24
Peak memory 237812 kb
Host smart-818413f2-2d37-4d16-a802-508a96574667
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1904734087 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_intg_err.1904734087
Directory /workspace/19.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.4281238436
Short name T162
Test name
Test status
Simulation time 37868643 ps
CPU time 3.05 seconds
Started Jul 10 04:50:47 PM PDT 24
Finished Jul 10 04:50:51 PM PDT 24
Peak memory 237728 kb
Host smart-60516eac-1eb7-4448-ab36-aee35946413c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4281238436 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_intg_err.4281238436
Directory /workspace/6.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/12.alert_handler_random_classes.592628562
Short name T20
Test name
Test status
Simulation time 217229532 ps
CPU time 15.13 seconds
Started Jul 10 05:27:44 PM PDT 24
Finished Jul 10 05:28:03 PM PDT 24
Peak memory 248792 kb
Host smart-6b2380e8-3c34-4d25-9590-22cb75c25564
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59262
8562 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_classes.592628562
Directory /workspace/12.alert_handler_random_classes/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.2112539812
Short name T756
Test name
Test status
Simulation time 2634068350 ps
CPU time 71.83 seconds
Started Jul 10 04:50:33 PM PDT 24
Finished Jul 10 04:51:47 PM PDT 24
Peak memory 237516 kb
Host smart-e1baacd9-dd34-4e57-bc79-ff91eda58ad6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2112539812 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_aliasing.2112539812
Directory /workspace/0.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.1024926627
Short name T181
Test name
Test status
Simulation time 17829305947 ps
CPU time 278.82 seconds
Started Jul 10 04:50:33 PM PDT 24
Finished Jul 10 04:55:15 PM PDT 24
Peak memory 237504 kb
Host smart-88ecfac2-5f33-422b-8823-3136cb2e75e1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1024926627 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_bit_bash.1024926627
Directory /workspace/0.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.953836754
Short name T826
Test name
Test status
Simulation time 37633639 ps
CPU time 7.97 seconds
Started Jul 10 04:50:33 PM PDT 24
Finished Jul 10 04:50:43 PM PDT 24
Peak memory 249056 kb
Host smart-25dfe53c-06af-4257-ae2f-f746ef075f88
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=953836754 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_hw_reset.953836754
Directory /workspace/0.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.1124150561
Short name T828
Test name
Test status
Simulation time 97543638 ps
CPU time 8.02 seconds
Started Jul 10 04:50:40 PM PDT 24
Finished Jul 10 04:50:50 PM PDT 24
Peak memory 240428 kb
Host smart-35f1245f-9bea-47d8-92cf-8d4c7c9d7b2a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124150561 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 0.alert_handler_csr_mem_rw_with_rand_reset.1124150561
Directory /workspace/0.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.740500049
Short name T825
Test name
Test status
Simulation time 118140784 ps
CPU time 5.92 seconds
Started Jul 10 04:50:33 PM PDT 24
Finished Jul 10 04:50:42 PM PDT 24
Peak memory 240332 kb
Host smart-b8a13829-d1de-48eb-9061-94b59f718e57
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=740500049 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_rw.740500049
Directory /workspace/0.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.49572429
Short name T823
Test name
Test status
Simulation time 259338833 ps
CPU time 20.67 seconds
Started Jul 10 04:50:37 PM PDT 24
Finished Jul 10 04:51:00 PM PDT 24
Peak memory 244684 kb
Host smart-a3fac3f7-8661-47a6-b0d2-705c01f1650a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=49572429 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_same_csr_outst
anding.49572429
Directory /workspace/0.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.4154676182
Short name T127
Test name
Test status
Simulation time 4204066770 ps
CPU time 319.89 seconds
Started Jul 10 04:50:34 PM PDT 24
Finished Jul 10 04:55:57 PM PDT 24
Peak memory 265476 kb
Host smart-f628a03f-5ad0-4b62-a96e-1544308f0bec
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154676182 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.alert_handler_shadow_reg_errors_with_csr_rw.4154676182
Directory /workspace/0.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.3041075694
Short name T727
Test name
Test status
Simulation time 185543705 ps
CPU time 14.86 seconds
Started Jul 10 04:50:33 PM PDT 24
Finished Jul 10 04:50:50 PM PDT 24
Peak memory 248604 kb
Host smart-97c6a05d-3da7-4f12-b0aa-c47eb73e7b7e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3041075694 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_errors.3041075694
Directory /workspace/0.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.3114290581
Short name T733
Test name
Test status
Simulation time 7064276857 ps
CPU time 144.48 seconds
Started Jul 10 04:50:38 PM PDT 24
Finished Jul 10 04:53:04 PM PDT 24
Peak memory 237504 kb
Host smart-fe03a546-2d6f-41c5-a137-9271f5bf85bb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3114290581 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_aliasing.3114290581
Directory /workspace/1.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.393332954
Short name T812
Test name
Test status
Simulation time 34203832842 ps
CPU time 553.31 seconds
Started Jul 10 04:50:38 PM PDT 24
Finished Jul 10 04:59:53 PM PDT 24
Peak memory 240416 kb
Host smart-03d51a76-3cfd-4b3d-8153-2f0603aad7b9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=393332954 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_bit_bash.393332954
Directory /workspace/1.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.684624650
Short name T730
Test name
Test status
Simulation time 397153581 ps
CPU time 8.66 seconds
Started Jul 10 04:50:39 PM PDT 24
Finished Jul 10 04:50:49 PM PDT 24
Peak memory 240780 kb
Host smart-be2473d9-2272-4f0a-b4fc-a087faa35018
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=684624650 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_hw_reset.684624650
Directory /workspace/1.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.2106772954
Short name T810
Test name
Test status
Simulation time 83325300 ps
CPU time 8.9 seconds
Started Jul 10 04:50:40 PM PDT 24
Finished Jul 10 04:50:51 PM PDT 24
Peak memory 251804 kb
Host smart-0dcc8755-9124-4248-a653-ba8c7ddc2d68
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106772954 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 1.alert_handler_csr_mem_rw_with_rand_reset.2106772954
Directory /workspace/1.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.3242343022
Short name T757
Test name
Test status
Simulation time 87673195 ps
CPU time 6.02 seconds
Started Jul 10 04:50:38 PM PDT 24
Finished Jul 10 04:50:45 PM PDT 24
Peak memory 237448 kb
Host smart-035e0c9c-0466-493f-8031-53e34f4747b1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3242343022 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_rw.3242343022
Directory /workspace/1.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.3686534262
Short name T742
Test name
Test status
Simulation time 31510480 ps
CPU time 1.38 seconds
Started Jul 10 04:50:38 PM PDT 24
Finished Jul 10 04:50:40 PM PDT 24
Peak memory 236612 kb
Host smart-8d65ebae-9cbd-40fd-9e8a-d190e910240a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3686534262 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_intr_test.3686534262
Directory /workspace/1.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.1683694758
Short name T183
Test name
Test status
Simulation time 172146777 ps
CPU time 23.22 seconds
Started Jul 10 04:50:53 PM PDT 24
Finished Jul 10 04:51:17 PM PDT 24
Peak memory 245588 kb
Host smart-23e6935e-ab71-4e2c-8566-f244dbd77e09
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1683694758 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_same_csr_out
standing.1683694758
Directory /workspace/1.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.1557898102
Short name T737
Test name
Test status
Simulation time 94686809 ps
CPU time 7.69 seconds
Started Jul 10 04:50:39 PM PDT 24
Finished Jul 10 04:50:49 PM PDT 24
Peak memory 248284 kb
Host smart-56857e89-1762-4ec8-bab2-bf95a4f225dc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1557898102 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_errors.1557898102
Directory /workspace/1.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.267982054
Short name T790
Test name
Test status
Simulation time 65764695 ps
CPU time 10.34 seconds
Started Jul 10 04:51:00 PM PDT 24
Finished Jul 10 04:51:12 PM PDT 24
Peak memory 252416 kb
Host smart-b8194cf6-0fc4-4dea-9535-9c6ff5d1a9a3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267982054 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 10.alert_handler_csr_mem_rw_with_rand_reset.267982054
Directory /workspace/10.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.1946262320
Short name T779
Test name
Test status
Simulation time 178885652 ps
CPU time 8.13 seconds
Started Jul 10 04:51:02 PM PDT 24
Finished Jul 10 04:51:11 PM PDT 24
Peak memory 237428 kb
Host smart-d4326f37-9501-44d8-b552-7b0f11150f4e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1946262320 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_csr_rw.1946262320
Directory /workspace/10.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.2735284076
Short name T179
Test name
Test status
Simulation time 521589295 ps
CPU time 37.52 seconds
Started Jul 10 04:51:01 PM PDT 24
Finished Jul 10 04:51:40 PM PDT 24
Peak memory 248612 kb
Host smart-762dac72-f144-47b0-a7c9-06b92d45b11a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2735284076 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_same_csr_ou
tstanding.2735284076
Directory /workspace/10.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.1352830138
Short name T122
Test name
Test status
Simulation time 1501826592 ps
CPU time 167.36 seconds
Started Jul 10 04:51:07 PM PDT 24
Finished Jul 10 04:53:58 PM PDT 24
Peak memory 265204 kb
Host smart-61839945-c89f-4d44-ab34-e63e053cbea0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1352830138 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shadow_reg_err
ors.1352830138
Directory /workspace/10.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.1603061199
Short name T140
Test name
Test status
Simulation time 42857063643 ps
CPU time 396.93 seconds
Started Jul 10 04:50:59 PM PDT 24
Finished Jul 10 04:57:37 PM PDT 24
Peak memory 265276 kb
Host smart-377c867d-8b78-41be-b379-e41d5c38fa4a
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603061199 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 10.alert_handler_shadow_reg_errors_with_csr_rw.1603061199
Directory /workspace/10.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.1410631305
Short name T807
Test name
Test status
Simulation time 142649876 ps
CPU time 10.56 seconds
Started Jul 10 04:51:00 PM PDT 24
Finished Jul 10 04:51:12 PM PDT 24
Peak memory 253176 kb
Host smart-93b70aaa-e3a1-4fe6-9c88-73f097207ab7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1410631305 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_errors.1410631305
Directory /workspace/10.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.2351833846
Short name T814
Test name
Test status
Simulation time 66249850 ps
CPU time 10.44 seconds
Started Jul 10 04:51:00 PM PDT 24
Finished Jul 10 04:51:12 PM PDT 24
Peak memory 252020 kb
Host smart-8037f14b-8875-4519-8865-bc4481b753b0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351833846 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 11.alert_handler_csr_mem_rw_with_rand_reset.2351833846
Directory /workspace/11.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.189960135
Short name T748
Test name
Test status
Simulation time 141825790 ps
CPU time 5.24 seconds
Started Jul 10 04:51:01 PM PDT 24
Finished Jul 10 04:51:07 PM PDT 24
Peak memory 240412 kb
Host smart-67dded1d-0c19-47c3-87b7-c46a36afcfcd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=189960135 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_csr_rw.189960135
Directory /workspace/11.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.1110553888
Short name T729
Test name
Test status
Simulation time 518416773 ps
CPU time 19.86 seconds
Started Jul 10 04:50:59 PM PDT 24
Finished Jul 10 04:51:21 PM PDT 24
Peak memory 248512 kb
Host smart-03487bb1-27a9-4c1f-a5a9-a02e53747a67
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1110553888 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_same_csr_ou
tstanding.1110553888
Directory /workspace/11.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.1976954188
Short name T120
Test name
Test status
Simulation time 19244257697 ps
CPU time 498.29 seconds
Started Jul 10 04:51:07 PM PDT 24
Finished Jul 10 04:59:29 PM PDT 24
Peak memory 265340 kb
Host smart-aae2b10d-5093-4eab-b1a1-6f1571152fab
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976954188 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 11.alert_handler_shadow_reg_errors_with_csr_rw.1976954188
Directory /workspace/11.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.1333439524
Short name T721
Test name
Test status
Simulation time 109207569 ps
CPU time 7.61 seconds
Started Jul 10 04:51:03 PM PDT 24
Finished Jul 10 04:51:11 PM PDT 24
Peak memory 253992 kb
Host smart-29a8b21c-bba8-431d-b449-53b02609d370
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1333439524 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_errors.1333439524
Directory /workspace/11.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.484149368
Short name T778
Test name
Test status
Simulation time 665586681 ps
CPU time 14.06 seconds
Started Jul 10 04:50:59 PM PDT 24
Finished Jul 10 04:51:15 PM PDT 24
Peak memory 252204 kb
Host smart-1312e03d-dcf4-4cee-882d-7f78d74864fa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484149368 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 12.alert_handler_csr_mem_rw_with_rand_reset.484149368
Directory /workspace/12.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.2266624327
Short name T797
Test name
Test status
Simulation time 499348389 ps
CPU time 5.66 seconds
Started Jul 10 04:51:02 PM PDT 24
Finished Jul 10 04:51:08 PM PDT 24
Peak memory 237428 kb
Host smart-185198a9-5936-4b54-b3c9-2143708fa43a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2266624327 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_csr_rw.2266624327
Directory /workspace/12.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.4030317093
Short name T751
Test name
Test status
Simulation time 9913235 ps
CPU time 1.39 seconds
Started Jul 10 04:50:59 PM PDT 24
Finished Jul 10 04:51:01 PM PDT 24
Peak memory 235548 kb
Host smart-314380fb-e431-4e0c-b004-6f01ebcdc74a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4030317093 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_intr_test.4030317093
Directory /workspace/12.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.2503530890
Short name T784
Test name
Test status
Simulation time 3174416633 ps
CPU time 25.79 seconds
Started Jul 10 04:51:00 PM PDT 24
Finished Jul 10 04:51:28 PM PDT 24
Peak memory 245788 kb
Host smart-1531b2f7-9e86-4b3b-bd39-14f59b47628a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2503530890 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_same_csr_ou
tstanding.2503530890
Directory /workspace/12.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.2685166541
Short name T123
Test name
Test status
Simulation time 850658373 ps
CPU time 115.21 seconds
Started Jul 10 04:50:58 PM PDT 24
Finished Jul 10 04:52:54 PM PDT 24
Peak memory 265236 kb
Host smart-6a9bb0f1-2c69-44c0-8a56-76818712ced0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2685166541 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shadow_reg_err
ors.2685166541
Directory /workspace/12.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.2309012589
Short name T235
Test name
Test status
Simulation time 1099502385 ps
CPU time 20.58 seconds
Started Jul 10 04:51:00 PM PDT 24
Finished Jul 10 04:51:22 PM PDT 24
Peak memory 248672 kb
Host smart-e55eb087-9924-4bfd-a3c7-313644a7109b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2309012589 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_errors.2309012589
Directory /workspace/12.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_intg_err.3880290355
Short name T736
Test name
Test status
Simulation time 38471771 ps
CPU time 2.26 seconds
Started Jul 10 04:51:07 PM PDT 24
Finished Jul 10 04:51:13 PM PDT 24
Peak memory 237792 kb
Host smart-1e385ac1-b65d-4b89-818b-fd7c89db3ec2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3880290355 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_intg_err.3880290355
Directory /workspace/12.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.3395419178
Short name T809
Test name
Test status
Simulation time 70652874 ps
CPU time 7.5 seconds
Started Jul 10 04:51:08 PM PDT 24
Finished Jul 10 04:51:19 PM PDT 24
Peak memory 256760 kb
Host smart-2ce045db-c2e5-46b7-96df-a652c621a447
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395419178 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 13.alert_handler_csr_mem_rw_with_rand_reset.3395419178
Directory /workspace/13.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.905391282
Short name T800
Test name
Test status
Simulation time 43173389 ps
CPU time 6.06 seconds
Started Jul 10 04:51:05 PM PDT 24
Finished Jul 10 04:51:13 PM PDT 24
Peak memory 237452 kb
Host smart-c8a85527-acc4-4bdd-8393-82003e898689
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=905391282 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_csr_rw.905391282
Directory /workspace/13.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.3634654195
Short name T726
Test name
Test status
Simulation time 13031651 ps
CPU time 1.66 seconds
Started Jul 10 04:51:05 PM PDT 24
Finished Jul 10 04:51:08 PM PDT 24
Peak memory 236524 kb
Host smart-18aa10ed-5046-4313-a775-30d0ee1df1a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3634654195 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_intr_test.3634654195
Directory /workspace/13.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.1368052983
Short name T816
Test name
Test status
Simulation time 597228465 ps
CPU time 39.96 seconds
Started Jul 10 04:51:08 PM PDT 24
Finished Jul 10 04:51:52 PM PDT 24
Peak memory 245724 kb
Host smart-6805e3db-d745-4560-9eff-331bcc7c7fb0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1368052983 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_same_csr_ou
tstanding.1368052983
Directory /workspace/13.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.1038031091
Short name T236
Test name
Test status
Simulation time 303929186 ps
CPU time 18.94 seconds
Started Jul 10 04:51:06 PM PDT 24
Finished Jul 10 04:51:28 PM PDT 24
Peak memory 248856 kb
Host smart-3e6b2742-8c8b-4dec-af6a-bb9ec023a9a0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1038031091 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_errors.1038031091
Directory /workspace/13.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.2739309608
Short name T822
Test name
Test status
Simulation time 263912968 ps
CPU time 13.43 seconds
Started Jul 10 04:51:05 PM PDT 24
Finished Jul 10 04:51:21 PM PDT 24
Peak memory 248760 kb
Host smart-ba8cc541-d86b-402a-97b6-a27dc725917b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739309608 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 14.alert_handler_csr_mem_rw_with_rand_reset.2739309608
Directory /workspace/14.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.1661421552
Short name T237
Test name
Test status
Simulation time 209966136 ps
CPU time 9.91 seconds
Started Jul 10 04:51:05 PM PDT 24
Finished Jul 10 04:51:17 PM PDT 24
Peak memory 237456 kb
Host smart-36054496-31c6-4a7d-9dea-01fd5d8d15cb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1661421552 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_csr_rw.1661421552
Directory /workspace/14.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.3071468283
Short name T724
Test name
Test status
Simulation time 30033980 ps
CPU time 2.37 seconds
Started Jul 10 04:51:05 PM PDT 24
Finished Jul 10 04:51:10 PM PDT 24
Peak memory 236500 kb
Host smart-636e6870-ad7b-4366-b372-1321531c86c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3071468283 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_intr_test.3071468283
Directory /workspace/14.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.2134476913
Short name T741
Test name
Test status
Simulation time 642221938 ps
CPU time 41.6 seconds
Started Jul 10 04:51:07 PM PDT 24
Finished Jul 10 04:51:52 PM PDT 24
Peak memory 244704 kb
Host smart-758be0f5-a891-45f1-b236-fd254d5ea260
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2134476913 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_same_csr_ou
tstanding.2134476913
Directory /workspace/14.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.3545172667
Short name T138
Test name
Test status
Simulation time 802702709 ps
CPU time 110.49 seconds
Started Jul 10 04:51:07 PM PDT 24
Finished Jul 10 04:53:00 PM PDT 24
Peak memory 265220 kb
Host smart-7b1d8924-4cf9-454c-9931-f14af1b667ae
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3545172667 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shadow_reg_err
ors.3545172667
Directory /workspace/14.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.3711856576
Short name T128
Test name
Test status
Simulation time 12294483705 ps
CPU time 1071.98 seconds
Started Jul 10 04:51:06 PM PDT 24
Finished Jul 10 05:09:01 PM PDT 24
Peak memory 265168 kb
Host smart-8265a990-9dfe-4ae6-8a86-56114214cbd9
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711856576 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 14.alert_handler_shadow_reg_errors_with_csr_rw.3711856576
Directory /workspace/14.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.695962917
Short name T238
Test name
Test status
Simulation time 663568109 ps
CPU time 13.86 seconds
Started Jul 10 04:51:05 PM PDT 24
Finished Jul 10 04:51:21 PM PDT 24
Peak memory 254432 kb
Host smart-e482d7ed-3f3b-4c16-b95b-9fb52082572c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=695962917 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_errors.695962917
Directory /workspace/14.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.1086275952
Short name T760
Test name
Test status
Simulation time 31434328 ps
CPU time 4.97 seconds
Started Jul 10 04:51:05 PM PDT 24
Finished Jul 10 04:51:11 PM PDT 24
Peak memory 240012 kb
Host smart-3e0dc081-bd71-4021-86c6-61954b1dc631
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086275952 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 15.alert_handler_csr_mem_rw_with_rand_reset.1086275952
Directory /workspace/15.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.259258307
Short name T182
Test name
Test status
Simulation time 1761279412 ps
CPU time 8.94 seconds
Started Jul 10 04:51:05 PM PDT 24
Finished Jul 10 04:51:15 PM PDT 24
Peak memory 240392 kb
Host smart-1a77de47-b1b5-4fc9-8933-9dc63f93c942
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=259258307 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_csr_rw.259258307
Directory /workspace/15.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.2336839055
Short name T785
Test name
Test status
Simulation time 24366721 ps
CPU time 1.49 seconds
Started Jul 10 04:51:06 PM PDT 24
Finished Jul 10 04:51:11 PM PDT 24
Peak memory 236524 kb
Host smart-876e0889-7e42-4c9a-8d24-85ac6476963f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2336839055 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_intr_test.2336839055
Directory /workspace/15.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.4087597463
Short name T759
Test name
Test status
Simulation time 2033036367 ps
CPU time 40.18 seconds
Started Jul 10 04:51:07 PM PDT 24
Finished Jul 10 04:51:51 PM PDT 24
Peak memory 245668 kb
Host smart-fad5fb4b-ca53-4c5f-9a0c-5fdd7ac67867
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4087597463 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_same_csr_ou
tstanding.4087597463
Directory /workspace/15.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.1817911503
Short name T124
Test name
Test status
Simulation time 15450015995 ps
CPU time 340.61 seconds
Started Jul 10 04:51:06 PM PDT 24
Finished Jul 10 04:56:50 PM PDT 24
Peak memory 270924 kb
Host smart-5ab62d41-c6cd-4ba9-97c0-786a388ba001
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1817911503 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shadow_reg_err
ors.1817911503
Directory /workspace/15.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.3763437195
Short name T134
Test name
Test status
Simulation time 75548994792 ps
CPU time 1017.19 seconds
Started Jul 10 04:51:06 PM PDT 24
Finished Jul 10 05:08:06 PM PDT 24
Peak memory 272240 kb
Host smart-11bbcef8-1da6-4821-8621-3171106c410d
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763437195 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 15.alert_handler_shadow_reg_errors_with_csr_rw.3763437195
Directory /workspace/15.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.2365808546
Short name T754
Test name
Test status
Simulation time 2026441483 ps
CPU time 18.95 seconds
Started Jul 10 04:51:05 PM PDT 24
Finished Jul 10 04:51:26 PM PDT 24
Peak memory 248068 kb
Host smart-fc41443e-f56c-4ee0-9c87-435fa44aaf94
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2365808546 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_errors.2365808546
Directory /workspace/15.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.683162950
Short name T746
Test name
Test status
Simulation time 81836527 ps
CPU time 6.7 seconds
Started Jul 10 04:51:15 PM PDT 24
Finished Jul 10 04:51:23 PM PDT 24
Peak memory 252160 kb
Host smart-26f0bafe-8448-4b1b-97fe-d46ab55978c5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683162950 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 16.alert_handler_csr_mem_rw_with_rand_reset.683162950
Directory /workspace/16.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.1270856242
Short name T788
Test name
Test status
Simulation time 53081905 ps
CPU time 5.64 seconds
Started Jul 10 04:51:14 PM PDT 24
Finished Jul 10 04:51:21 PM PDT 24
Peak memory 240352 kb
Host smart-0fcbdc4f-3336-484f-bfc8-19d675eedf84
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1270856242 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_csr_rw.1270856242
Directory /workspace/16.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.2472415354
Short name T763
Test name
Test status
Simulation time 30419036 ps
CPU time 1.36 seconds
Started Jul 10 04:51:12 PM PDT 24
Finished Jul 10 04:51:15 PM PDT 24
Peak memory 235488 kb
Host smart-189acc96-421f-4166-8dc2-fd934fb81403
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2472415354 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_intr_test.2472415354
Directory /workspace/16.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.2244921287
Short name T773
Test name
Test status
Simulation time 4975079568 ps
CPU time 35.44 seconds
Started Jul 10 04:51:15 PM PDT 24
Finished Jul 10 04:51:52 PM PDT 24
Peak memory 244620 kb
Host smart-0d75b307-f9cd-4797-bdc0-24ae84ac5e83
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2244921287 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_same_csr_ou
tstanding.2244921287
Directory /workspace/16.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.1392700792
Short name T125
Test name
Test status
Simulation time 817717637 ps
CPU time 91.77 seconds
Started Jul 10 04:51:05 PM PDT 24
Finished Jul 10 04:52:38 PM PDT 24
Peak memory 265736 kb
Host smart-402fb050-efb6-4589-ad77-4a6a3ea49db8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1392700792 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shadow_reg_err
ors.1392700792
Directory /workspace/16.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.3921770201
Short name T752
Test name
Test status
Simulation time 412261654 ps
CPU time 18.49 seconds
Started Jul 10 04:51:07 PM PDT 24
Finished Jul 10 04:51:29 PM PDT 24
Peak memory 248776 kb
Host smart-556f05ea-6bc0-418a-adc0-de22476ae90e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3921770201 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_errors.3921770201
Directory /workspace/16.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.37372900
Short name T740
Test name
Test status
Simulation time 894021544 ps
CPU time 7.13 seconds
Started Jul 10 04:51:14 PM PDT 24
Finished Jul 10 04:51:23 PM PDT 24
Peak memory 240448 kb
Host smart-be974593-5a80-4863-b2dc-077640a3c551
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37372900 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 17.alert_handler_csr_mem_rw_with_rand_reset.37372900
Directory /workspace/17.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.1566673536
Short name T180
Test name
Test status
Simulation time 170576575 ps
CPU time 4.57 seconds
Started Jul 10 04:51:16 PM PDT 24
Finished Jul 10 04:51:22 PM PDT 24
Peak memory 237440 kb
Host smart-49250fd7-19be-4592-aadc-3d4eedc66cd9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1566673536 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_csr_rw.1566673536
Directory /workspace/17.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.2737497925
Short name T750
Test name
Test status
Simulation time 9580184 ps
CPU time 1.56 seconds
Started Jul 10 04:51:13 PM PDT 24
Finished Jul 10 04:51:16 PM PDT 24
Peak memory 236904 kb
Host smart-aae3b4c9-878f-4f18-b9f6-7b5728881846
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2737497925 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_intr_test.2737497925
Directory /workspace/17.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.2816609372
Short name T722
Test name
Test status
Simulation time 89575465 ps
CPU time 14.57 seconds
Started Jul 10 04:51:13 PM PDT 24
Finished Jul 10 04:51:29 PM PDT 24
Peak memory 245640 kb
Host smart-453414ae-faeb-4069-bf74-e76fc215f50e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2816609372 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_same_csr_ou
tstanding.2816609372
Directory /workspace/17.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.785802117
Short name T135
Test name
Test status
Simulation time 6567498203 ps
CPU time 529.14 seconds
Started Jul 10 04:51:13 PM PDT 24
Finished Jul 10 05:00:03 PM PDT 24
Peak memory 270608 kb
Host smart-9abdaeca-e196-4be0-8c44-d03449378db5
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785802117 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 17.alert_handler_shadow_reg_errors_with_csr_rw.785802117
Directory /workspace/17.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.4117855470
Short name T714
Test name
Test status
Simulation time 1396790822 ps
CPU time 24.87 seconds
Started Jul 10 04:51:13 PM PDT 24
Finished Jul 10 04:51:40 PM PDT 24
Peak memory 248672 kb
Host smart-83e3301f-5ab6-4b29-a8ba-f2474866bf03
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4117855470 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_errors.4117855470
Directory /workspace/17.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.4020084368
Short name T801
Test name
Test status
Simulation time 165338358 ps
CPU time 12.7 seconds
Started Jul 10 04:51:21 PM PDT 24
Finished Jul 10 04:51:36 PM PDT 24
Peak memory 256772 kb
Host smart-4e9d0516-fbb3-4d99-a0fa-eba381dbc598
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020084368 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 18.alert_handler_csr_mem_rw_with_rand_reset.4020084368
Directory /workspace/18.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.3883942529
Short name T833
Test name
Test status
Simulation time 515374862 ps
CPU time 9.24 seconds
Started Jul 10 04:51:14 PM PDT 24
Finished Jul 10 04:51:25 PM PDT 24
Peak memory 240388 kb
Host smart-0e941440-fc50-4ae2-b90c-c459c93caccf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3883942529 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_csr_rw.3883942529
Directory /workspace/18.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.1643843630
Short name T341
Test name
Test status
Simulation time 9860133 ps
CPU time 1.37 seconds
Started Jul 10 04:51:13 PM PDT 24
Finished Jul 10 04:51:16 PM PDT 24
Peak memory 237468 kb
Host smart-333b22f8-9272-4523-95b6-401019fc038a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1643843630 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_intr_test.1643843630
Directory /workspace/18.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.237066573
Short name T186
Test name
Test status
Simulation time 591502430 ps
CPU time 12.75 seconds
Started Jul 10 04:51:12 PM PDT 24
Finished Jul 10 04:51:27 PM PDT 24
Peak memory 245648 kb
Host smart-4054e7a4-4eab-4760-951a-1ea60d461322
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=237066573 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_same_csr_out
standing.237066573
Directory /workspace/18.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.3560545761
Short name T136
Test name
Test status
Simulation time 2212097958 ps
CPU time 359.25 seconds
Started Jul 10 04:51:15 PM PDT 24
Finished Jul 10 04:57:16 PM PDT 24
Peak memory 265372 kb
Host smart-0eac318f-9232-4960-adb1-bb8a3135f2bf
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560545761 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 18.alert_handler_shadow_reg_errors_with_csr_rw.3560545761
Directory /workspace/18.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.1801439613
Short name T764
Test name
Test status
Simulation time 1079354821 ps
CPU time 20.55 seconds
Started Jul 10 04:51:13 PM PDT 24
Finished Jul 10 04:51:35 PM PDT 24
Peak memory 248804 kb
Host smart-5650c244-381a-4448-8841-894a1c10e269
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1801439613 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_errors.1801439613
Directory /workspace/18.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.2286683924
Short name T802
Test name
Test status
Simulation time 297594724 ps
CPU time 7.39 seconds
Started Jul 10 04:51:19 PM PDT 24
Finished Jul 10 04:51:27 PM PDT 24
Peak memory 241112 kb
Host smart-1f1acc3d-c35c-426c-9c7c-21cc68a80e91
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286683924 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 19.alert_handler_csr_mem_rw_with_rand_reset.2286683924
Directory /workspace/19.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.1720658391
Short name T772
Test name
Test status
Simulation time 135060081 ps
CPU time 6.03 seconds
Started Jul 10 04:51:20 PM PDT 24
Finished Jul 10 04:51:28 PM PDT 24
Peak memory 237436 kb
Host smart-9a6c0abe-e092-4e0b-b7b7-2d3ab32c851f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1720658391 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_csr_rw.1720658391
Directory /workspace/19.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.2766122748
Short name T808
Test name
Test status
Simulation time 30142952 ps
CPU time 1.5 seconds
Started Jul 10 04:51:18 PM PDT 24
Finished Jul 10 04:51:21 PM PDT 24
Peak memory 236508 kb
Host smart-6b4767df-63ce-4341-80c8-fe13ad39094e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2766122748 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_intr_test.2766122748
Directory /workspace/19.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.2781136117
Short name T747
Test name
Test status
Simulation time 184362970 ps
CPU time 33.7 seconds
Started Jul 10 04:51:19 PM PDT 24
Finished Jul 10 04:51:55 PM PDT 24
Peak memory 248856 kb
Host smart-794cda97-c6ce-40fd-9469-9d28b9114924
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2781136117 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_same_csr_ou
tstanding.2781136117
Directory /workspace/19.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.3829094499
Short name T139
Test name
Test status
Simulation time 60284246134 ps
CPU time 531.26 seconds
Started Jul 10 04:51:20 PM PDT 24
Finished Jul 10 05:00:14 PM PDT 24
Peak memory 265224 kb
Host smart-9451f0b7-2e16-4466-b15a-a101d07765ee
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829094499 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 19.alert_handler_shadow_reg_errors_with_csr_rw.3829094499
Directory /workspace/19.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.4020121843
Short name T744
Test name
Test status
Simulation time 506118939 ps
CPU time 10.46 seconds
Started Jul 10 04:51:21 PM PDT 24
Finished Jul 10 04:51:33 PM PDT 24
Peak memory 251452 kb
Host smart-446fa929-698f-4cc9-bef8-814ba5de9b1c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4020121843 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_errors.4020121843
Directory /workspace/19.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.2359404445
Short name T821
Test name
Test status
Simulation time 20559855474 ps
CPU time 121.26 seconds
Started Jul 10 04:50:39 PM PDT 24
Finished Jul 10 04:52:42 PM PDT 24
Peak memory 236932 kb
Host smart-d0b934d7-5737-4c11-a4b8-f5607e958d3f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2359404445 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_aliasing.2359404445
Directory /workspace/2.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.3757124244
Short name T783
Test name
Test status
Simulation time 2972602051 ps
CPU time 173.49 seconds
Started Jul 10 04:50:40 PM PDT 24
Finished Jul 10 04:53:36 PM PDT 24
Peak memory 236564 kb
Host smart-d25401d5-90ef-4f9c-a952-c52f80f580e2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3757124244 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_bit_bash.3757124244
Directory /workspace/2.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.1517589730
Short name T716
Test name
Test status
Simulation time 72295586 ps
CPU time 3.76 seconds
Started Jul 10 04:50:39 PM PDT 24
Finished Jul 10 04:50:44 PM PDT 24
Peak memory 240364 kb
Host smart-714fc1f5-d21c-4eaf-bdc1-405e09913173
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1517589730 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_hw_reset.1517589730
Directory /workspace/2.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.4199365072
Short name T719
Test name
Test status
Simulation time 68328731 ps
CPU time 5.15 seconds
Started Jul 10 04:50:40 PM PDT 24
Finished Jul 10 04:50:47 PM PDT 24
Peak memory 240448 kb
Host smart-a4199e27-d969-4595-94d7-a753c696c747
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199365072 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 2.alert_handler_csr_mem_rw_with_rand_reset.4199365072
Directory /workspace/2.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.4286913977
Short name T723
Test name
Test status
Simulation time 37307980 ps
CPU time 3.46 seconds
Started Jul 10 04:50:38 PM PDT 24
Finished Jul 10 04:50:42 PM PDT 24
Peak memory 237444 kb
Host smart-d62ba4be-2d9d-47ef-bc0b-57f429029c7b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4286913977 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_rw.4286913977
Directory /workspace/2.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.282885086
Short name T793
Test name
Test status
Simulation time 7795119 ps
CPU time 1.36 seconds
Started Jul 10 04:50:39 PM PDT 24
Finished Jul 10 04:50:42 PM PDT 24
Peak memory 236500 kb
Host smart-93a38488-1bc3-4700-9bf8-fb515921c948
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=282885086 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_intr_test.282885086
Directory /workspace/2.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.2364189579
Short name T728
Test name
Test status
Simulation time 110417384 ps
CPU time 12.36 seconds
Started Jul 10 04:50:40 PM PDT 24
Finished Jul 10 04:50:55 PM PDT 24
Peak memory 240364 kb
Host smart-8e1e40e1-ab0e-400b-aa9c-118f57c9ea0a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2364189579 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_same_csr_out
standing.2364189579
Directory /workspace/2.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.617516227
Short name T745
Test name
Test status
Simulation time 23621743 ps
CPU time 2.78 seconds
Started Jul 10 04:50:37 PM PDT 24
Finished Jul 10 04:50:42 PM PDT 24
Peak memory 248720 kb
Host smart-f92de107-3a23-47fa-aae4-5d766667aeeb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=617516227 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_errors.617516227
Directory /workspace/2.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.4052034180
Short name T761
Test name
Test status
Simulation time 10501634 ps
CPU time 1.58 seconds
Started Jul 10 04:51:19 PM PDT 24
Finished Jul 10 04:51:22 PM PDT 24
Peak memory 236604 kb
Host smart-4efe2e95-7a98-4ae0-9384-511707c8ed08
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4052034180 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.alert_handler_intr_test.4052034180
Directory /workspace/20.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.3881428519
Short name T732
Test name
Test status
Simulation time 7274695 ps
CPU time 1.53 seconds
Started Jul 10 04:51:18 PM PDT 24
Finished Jul 10 04:51:20 PM PDT 24
Peak memory 237476 kb
Host smart-5661c588-2cea-4e0c-8413-b29dfc31826a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3881428519 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.alert_handler_intr_test.3881428519
Directory /workspace/21.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.2988215392
Short name T786
Test name
Test status
Simulation time 36598764 ps
CPU time 1.35 seconds
Started Jul 10 04:51:20 PM PDT 24
Finished Jul 10 04:51:23 PM PDT 24
Peak memory 237328 kb
Host smart-0b60c9dc-a9ec-4cbb-8bc9-7307fb6d28b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2988215392 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.alert_handler_intr_test.2988215392
Directory /workspace/22.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.1059163307
Short name T717
Test name
Test status
Simulation time 10064342 ps
CPU time 1.28 seconds
Started Jul 10 04:51:21 PM PDT 24
Finished Jul 10 04:51:25 PM PDT 24
Peak memory 237432 kb
Host smart-3b35c850-33c9-40e7-9eee-53f6145fbef7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1059163307 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.alert_handler_intr_test.1059163307
Directory /workspace/23.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.3171404359
Short name T769
Test name
Test status
Simulation time 10091576 ps
CPU time 1.36 seconds
Started Jul 10 04:51:20 PM PDT 24
Finished Jul 10 04:51:24 PM PDT 24
Peak memory 237464 kb
Host smart-d79eeb99-6614-4c79-9197-6062fa9add1b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3171404359 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.alert_handler_intr_test.3171404359
Directory /workspace/24.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.924203822
Short name T775
Test name
Test status
Simulation time 11099494 ps
CPU time 1.36 seconds
Started Jul 10 04:51:20 PM PDT 24
Finished Jul 10 04:51:24 PM PDT 24
Peak memory 237444 kb
Host smart-ff33b1ef-8076-49f5-b5d5-c7ef72943b2d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=924203822 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.alert_handler_intr_test.924203822
Directory /workspace/25.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.861779568
Short name T148
Test name
Test status
Simulation time 10914836 ps
CPU time 1.7 seconds
Started Jul 10 04:51:20 PM PDT 24
Finished Jul 10 04:51:23 PM PDT 24
Peak memory 236520 kb
Host smart-d6a5115f-185f-4fcf-a272-849705261ba2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=861779568 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.alert_handler_intr_test.861779568
Directory /workspace/26.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.1508332589
Short name T738
Test name
Test status
Simulation time 11250285 ps
CPU time 1.54 seconds
Started Jul 10 04:51:20 PM PDT 24
Finished Jul 10 04:51:24 PM PDT 24
Peak memory 237548 kb
Host smart-b648c465-e3c2-42b5-bfe5-9b5a72ab1743
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1508332589 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.alert_handler_intr_test.1508332589
Directory /workspace/27.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.3333554411
Short name T771
Test name
Test status
Simulation time 13229084 ps
CPU time 1.76 seconds
Started Jul 10 04:51:20 PM PDT 24
Finished Jul 10 04:51:24 PM PDT 24
Peak memory 237460 kb
Host smart-105c0d82-d1a6-48b3-958b-79662628d421
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3333554411 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.alert_handler_intr_test.3333554411
Directory /workspace/28.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.405876401
Short name T795
Test name
Test status
Simulation time 6380281 ps
CPU time 1.47 seconds
Started Jul 10 04:51:20 PM PDT 24
Finished Jul 10 04:51:23 PM PDT 24
Peak memory 237468 kb
Host smart-d3435f3e-e188-4402-9612-2bdd7666fb27
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=405876401 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.alert_handler_intr_test.405876401
Directory /workspace/29.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.9586841
Short name T731
Test name
Test status
Simulation time 4589340208 ps
CPU time 173.53 seconds
Started Jul 10 04:50:38 PM PDT 24
Finished Jul 10 04:53:33 PM PDT 24
Peak memory 240464 kb
Host smart-8137bcc0-f8fb-41f4-9ed9-e0ee5e6fdc69
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=9586841 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_aliasing.9586841
Directory /workspace/3.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.2335937493
Short name T794
Test name
Test status
Simulation time 965992492 ps
CPU time 101.28 seconds
Started Jul 10 04:50:41 PM PDT 24
Finished Jul 10 04:52:24 PM PDT 24
Peak memory 236504 kb
Host smart-ef4f1544-b918-4acf-96b0-6e210138a59f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2335937493 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_bit_bash.2335937493
Directory /workspace/3.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.1722486274
Short name T234
Test name
Test status
Simulation time 367941515 ps
CPU time 9.45 seconds
Started Jul 10 04:50:40 PM PDT 24
Finished Jul 10 04:50:52 PM PDT 24
Peak memory 240464 kb
Host smart-58204b7a-3683-46f5-9d0d-71d91ca51e8f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1722486274 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_hw_reset.1722486274
Directory /workspace/3.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.812340113
Short name T829
Test name
Test status
Simulation time 166908412 ps
CPU time 8.94 seconds
Started Jul 10 04:50:41 PM PDT 24
Finished Jul 10 04:50:52 PM PDT 24
Peak memory 240492 kb
Host smart-83e1028b-afe1-4bc5-a562-ccbcdb0a44c0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812340113 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 3.alert_handler_csr_mem_rw_with_rand_reset.812340113
Directory /workspace/3.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.3149312799
Short name T819
Test name
Test status
Simulation time 28487393 ps
CPU time 3.77 seconds
Started Jul 10 04:50:38 PM PDT 24
Finished Jul 10 04:50:43 PM PDT 24
Peak memory 237500 kb
Host smart-9cc198ee-2c56-42f8-aff0-ba77b707ee16
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3149312799 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_rw.3149312799
Directory /workspace/3.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.2998834801
Short name T781
Test name
Test status
Simulation time 35688539 ps
CPU time 1.44 seconds
Started Jul 10 04:50:39 PM PDT 24
Finished Jul 10 04:50:42 PM PDT 24
Peak memory 236524 kb
Host smart-524dd9de-02c4-43e7-80f2-91ffd674e6c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2998834801 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_intr_test.2998834801
Directory /workspace/3.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.38153160
Short name T185
Test name
Test status
Simulation time 950488890 ps
CPU time 35.57 seconds
Started Jul 10 04:50:51 PM PDT 24
Finished Jul 10 04:51:27 PM PDT 24
Peak memory 245588 kb
Host smart-2b038dd1-3232-4b1e-b127-e40237094551
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=38153160 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_same_csr_outst
anding.38153160
Directory /workspace/3.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.1589721510
Short name T126
Test name
Test status
Simulation time 2503269577 ps
CPU time 138.89 seconds
Started Jul 10 04:50:39 PM PDT 24
Finished Jul 10 04:53:00 PM PDT 24
Peak memory 265336 kb
Host smart-15c2d409-c7c5-4a33-b120-aa6b436cb2ec
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1589721510 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shadow_reg_erro
rs.1589721510
Directory /workspace/3.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.1883971319
Short name T117
Test name
Test status
Simulation time 28357470443 ps
CPU time 1011.98 seconds
Started Jul 10 04:50:39 PM PDT 24
Finished Jul 10 05:07:33 PM PDT 24
Peak memory 265344 kb
Host smart-f0decede-01ed-44cf-8391-c3b38f0fff65
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883971319 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.alert_handler_shadow_reg_errors_with_csr_rw.1883971319
Directory /workspace/3.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.316037121
Short name T749
Test name
Test status
Simulation time 161848695 ps
CPU time 4.34 seconds
Started Jul 10 04:50:53 PM PDT 24
Finished Jul 10 04:50:59 PM PDT 24
Peak memory 248592 kb
Host smart-f0a422af-85e0-4f58-a9f1-60b21e840ba7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=316037121 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_errors.316037121
Directory /workspace/3.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.2233336715
Short name T735
Test name
Test status
Simulation time 8996625 ps
CPU time 1.45 seconds
Started Jul 10 04:51:20 PM PDT 24
Finished Jul 10 04:51:23 PM PDT 24
Peak memory 237464 kb
Host smart-1caa83f7-e824-4a7f-bc88-e40fae6ef993
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2233336715 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.alert_handler_intr_test.2233336715
Directory /workspace/30.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.3978709756
Short name T799
Test name
Test status
Simulation time 10021240 ps
CPU time 1.38 seconds
Started Jul 10 04:51:20 PM PDT 24
Finished Jul 10 04:51:23 PM PDT 24
Peak memory 237468 kb
Host smart-e092f4b4-3147-4efd-b519-5afb4fe73468
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3978709756 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.alert_handler_intr_test.3978709756
Directory /workspace/31.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.4098580123
Short name T820
Test name
Test status
Simulation time 9461750 ps
CPU time 1.5 seconds
Started Jul 10 04:51:20 PM PDT 24
Finished Jul 10 04:51:23 PM PDT 24
Peak memory 236524 kb
Host smart-e29ccfdf-a88c-4f76-b7da-98a170318410
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4098580123 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.alert_handler_intr_test.4098580123
Directory /workspace/32.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.alert_handler_intr_test.1160979879
Short name T342
Test name
Test status
Simulation time 6751207 ps
CPU time 1.58 seconds
Started Jul 10 04:51:23 PM PDT 24
Finished Jul 10 04:51:26 PM PDT 24
Peak memory 236560 kb
Host smart-a5c28963-4fc7-4f89-bb20-608893aceb2b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1160979879 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.alert_handler_intr_test.1160979879
Directory /workspace/33.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.2281030148
Short name T226
Test name
Test status
Simulation time 9273678 ps
CPU time 1.42 seconds
Started Jul 10 04:51:20 PM PDT 24
Finished Jul 10 04:51:24 PM PDT 24
Peak memory 235504 kb
Host smart-70b96e03-bfe2-449c-8558-dcd7c15becd5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2281030148 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.alert_handler_intr_test.2281030148
Directory /workspace/34.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.3435324709
Short name T715
Test name
Test status
Simulation time 10769915 ps
CPU time 1.6 seconds
Started Jul 10 04:51:18 PM PDT 24
Finished Jul 10 04:51:21 PM PDT 24
Peak memory 237468 kb
Host smart-6f3c602f-9046-4523-988b-a5bf21ef1d83
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3435324709 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.alert_handler_intr_test.3435324709
Directory /workspace/35.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.2165000907
Short name T780
Test name
Test status
Simulation time 19066623 ps
CPU time 1.59 seconds
Started Jul 10 04:51:19 PM PDT 24
Finished Jul 10 04:51:22 PM PDT 24
Peak memory 237440 kb
Host smart-941b883a-e5f7-4b30-a56a-d15f802746c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2165000907 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.alert_handler_intr_test.2165000907
Directory /workspace/36.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.3573466989
Short name T720
Test name
Test status
Simulation time 10461792 ps
CPU time 1.64 seconds
Started Jul 10 04:51:20 PM PDT 24
Finished Jul 10 04:51:24 PM PDT 24
Peak memory 236500 kb
Host smart-4a319ba5-6aa6-442d-8836-889ab8e33268
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3573466989 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.alert_handler_intr_test.3573466989
Directory /workspace/37.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.3877575486
Short name T813
Test name
Test status
Simulation time 20038798 ps
CPU time 1.51 seconds
Started Jul 10 04:51:19 PM PDT 24
Finished Jul 10 04:51:22 PM PDT 24
Peak memory 236528 kb
Host smart-f3df3706-feb6-4072-b24e-a5f9d24530ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3877575486 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.alert_handler_intr_test.3877575486
Directory /workspace/38.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.3531742184
Short name T830
Test name
Test status
Simulation time 16690727 ps
CPU time 1.43 seconds
Started Jul 10 04:51:20 PM PDT 24
Finished Jul 10 04:51:24 PM PDT 24
Peak memory 236552 kb
Host smart-5e27b59a-76ca-4154-b0ea-2de9fe1bf6f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3531742184 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.alert_handler_intr_test.3531742184
Directory /workspace/39.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.2704960463
Short name T789
Test name
Test status
Simulation time 580242245 ps
CPU time 79.91 seconds
Started Jul 10 04:50:46 PM PDT 24
Finished Jul 10 04:52:07 PM PDT 24
Peak memory 237540 kb
Host smart-cc2ec6c5-4da1-4d20-bbe2-bcdf833d7c46
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2704960463 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_aliasing.2704960463
Directory /workspace/4.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.4029244391
Short name T193
Test name
Test status
Simulation time 95087828573 ps
CPU time 440.28 seconds
Started Jul 10 04:50:55 PM PDT 24
Finished Jul 10 04:58:16 PM PDT 24
Peak memory 237448 kb
Host smart-69385693-c196-4623-ad8a-2984e435e306
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4029244391 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_bit_bash.4029244391
Directory /workspace/4.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.2327299936
Short name T150
Test name
Test status
Simulation time 177801727 ps
CPU time 5.73 seconds
Started Jul 10 04:50:46 PM PDT 24
Finished Jul 10 04:50:52 PM PDT 24
Peak memory 240392 kb
Host smart-fbf3ac6a-4209-433f-817a-1de70a77f6d1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2327299936 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_hw_reset.2327299936
Directory /workspace/4.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.2282688945
Short name T718
Test name
Test status
Simulation time 62462085 ps
CPU time 11.68 seconds
Started Jul 10 04:50:46 PM PDT 24
Finished Jul 10 04:50:59 PM PDT 24
Peak memory 243596 kb
Host smart-ac56d15e-c077-44c0-908f-d623301e2b08
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282688945 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 4.alert_handler_csr_mem_rw_with_rand_reset.2282688945
Directory /workspace/4.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.3739161733
Short name T758
Test name
Test status
Simulation time 516442763 ps
CPU time 5.57 seconds
Started Jul 10 04:50:47 PM PDT 24
Finished Jul 10 04:50:53 PM PDT 24
Peak memory 236496 kb
Host smart-19246b6e-d075-42ad-9031-202a3c946b88
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3739161733 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_rw.3739161733
Directory /workspace/4.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.549140127
Short name T338
Test name
Test status
Simulation time 7641181 ps
CPU time 1.25 seconds
Started Jul 10 04:50:53 PM PDT 24
Finished Jul 10 04:50:56 PM PDT 24
Peak memory 235472 kb
Host smart-0cda5230-8ed1-4fb6-bf7e-34218497c8e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=549140127 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_intr_test.549140127
Directory /workspace/4.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.3518865226
Short name T827
Test name
Test status
Simulation time 181969366 ps
CPU time 13.83 seconds
Started Jul 10 04:50:46 PM PDT 24
Finished Jul 10 04:51:01 PM PDT 24
Peak memory 245668 kb
Host smart-1a0f1aef-1a45-480c-8d90-9d27210fcfc0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3518865226 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_same_csr_out
standing.3518865226
Directory /workspace/4.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.153072993
Short name T831
Test name
Test status
Simulation time 7971452020 ps
CPU time 299.09 seconds
Started Jul 10 04:50:39 PM PDT 24
Finished Jul 10 04:55:40 PM PDT 24
Peak memory 265292 kb
Host smart-81ec54b6-1ea6-4641-b77d-e9bd91291ac0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=153072993 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shadow_reg_error
s.153072993
Directory /workspace/4.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.2429018716
Short name T739
Test name
Test status
Simulation time 47806419 ps
CPU time 7.05 seconds
Started Jul 10 04:50:40 PM PDT 24
Finished Jul 10 04:50:50 PM PDT 24
Peak memory 254372 kb
Host smart-6f5d9529-b7c2-46cf-a011-9dafb956be71
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2429018716 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_errors.2429018716
Directory /workspace/4.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.2335666910
Short name T803
Test name
Test status
Simulation time 14502853 ps
CPU time 1.45 seconds
Started Jul 10 04:51:18 PM PDT 24
Finished Jul 10 04:51:21 PM PDT 24
Peak memory 237460 kb
Host smart-3a0b2a39-fcf2-40d6-b8d1-f363195eb57e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2335666910 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.alert_handler_intr_test.2335666910
Directory /workspace/40.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.1238397527
Short name T806
Test name
Test status
Simulation time 6484335 ps
CPU time 1.53 seconds
Started Jul 10 04:51:26 PM PDT 24
Finished Jul 10 04:51:28 PM PDT 24
Peak memory 235476 kb
Host smart-b8515de3-a653-404d-b6d6-36dc0b6a25a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1238397527 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.alert_handler_intr_test.1238397527
Directory /workspace/41.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.2998096686
Short name T343
Test name
Test status
Simulation time 9249201 ps
CPU time 1.57 seconds
Started Jul 10 04:51:25 PM PDT 24
Finished Jul 10 04:51:28 PM PDT 24
Peak memory 237560 kb
Host smart-1ae18907-fbdc-4857-ac0b-53208c3da820
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2998096686 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.alert_handler_intr_test.2998096686
Directory /workspace/42.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.3995155404
Short name T765
Test name
Test status
Simulation time 22721305 ps
CPU time 1.41 seconds
Started Jul 10 04:51:26 PM PDT 24
Finished Jul 10 04:51:29 PM PDT 24
Peak memory 236536 kb
Host smart-963898a7-1ac2-4cee-9e58-28e88e092051
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3995155404 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.alert_handler_intr_test.3995155404
Directory /workspace/43.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.498806163
Short name T339
Test name
Test status
Simulation time 17201237 ps
CPU time 1.33 seconds
Started Jul 10 04:51:27 PM PDT 24
Finished Jul 10 04:51:30 PM PDT 24
Peak memory 237448 kb
Host smart-355b9f29-f686-4592-a115-560e2156a1d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=498806163 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.alert_handler_intr_test.498806163
Directory /workspace/44.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.1823627640
Short name T755
Test name
Test status
Simulation time 7278287 ps
CPU time 1.54 seconds
Started Jul 10 04:51:26 PM PDT 24
Finished Jul 10 04:51:28 PM PDT 24
Peak memory 237532 kb
Host smart-bf110154-6669-4565-85c3-552efea2adce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1823627640 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.alert_handler_intr_test.1823627640
Directory /workspace/45.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.489955502
Short name T815
Test name
Test status
Simulation time 16955953 ps
CPU time 1.38 seconds
Started Jul 10 04:51:27 PM PDT 24
Finished Jul 10 04:51:30 PM PDT 24
Peak memory 236520 kb
Host smart-49261c31-17b6-4ccb-8857-8f08cd7094a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=489955502 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.alert_handler_intr_test.489955502
Directory /workspace/46.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.1713692410
Short name T832
Test name
Test status
Simulation time 24446418 ps
CPU time 2.26 seconds
Started Jul 10 04:51:27 PM PDT 24
Finished Jul 10 04:51:30 PM PDT 24
Peak memory 237468 kb
Host smart-26b4a5cb-a77c-4ff1-acf2-d8de10fb613d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1713692410 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.alert_handler_intr_test.1713692410
Directory /workspace/47.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.2155388585
Short name T770
Test name
Test status
Simulation time 16610788 ps
CPU time 1.4 seconds
Started Jul 10 04:51:27 PM PDT 24
Finished Jul 10 04:51:30 PM PDT 24
Peak memory 236532 kb
Host smart-0c9d0fe6-bf32-43f6-bb08-73c2f8b83d66
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2155388585 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.alert_handler_intr_test.2155388585
Directory /workspace/48.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.3381186690
Short name T762
Test name
Test status
Simulation time 10754576 ps
CPU time 1.58 seconds
Started Jul 10 04:51:26 PM PDT 24
Finished Jul 10 04:51:29 PM PDT 24
Peak memory 236524 kb
Host smart-0b4be896-282d-4b8b-9933-763605247a04
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3381186690 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.alert_handler_intr_test.3381186690
Directory /workspace/49.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.2558066329
Short name T164
Test name
Test status
Simulation time 270037674 ps
CPU time 12.27 seconds
Started Jul 10 04:50:47 PM PDT 24
Finished Jul 10 04:51:01 PM PDT 24
Peak memory 251708 kb
Host smart-a23aa84c-b124-41df-9adb-6325c4fc9775
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558066329 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 5.alert_handler_csr_mem_rw_with_rand_reset.2558066329
Directory /workspace/5.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.3747349585
Short name T725
Test name
Test status
Simulation time 93475946 ps
CPU time 5.43 seconds
Started Jul 10 04:50:46 PM PDT 24
Finished Jul 10 04:50:53 PM PDT 24
Peak memory 240588 kb
Host smart-8065e1c9-5e56-4eca-9920-96f1a594a262
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3747349585 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_csr_rw.3747349585
Directory /workspace/5.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.3641575468
Short name T766
Test name
Test status
Simulation time 9773892 ps
CPU time 1.27 seconds
Started Jul 10 04:50:46 PM PDT 24
Finished Jul 10 04:50:48 PM PDT 24
Peak memory 237312 kb
Host smart-f9610953-6e1d-4159-8ca3-3639ede85674
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3641575468 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_intr_test.3641575468
Directory /workspace/5.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.3188330808
Short name T768
Test name
Test status
Simulation time 99600100 ps
CPU time 13.11 seconds
Started Jul 10 04:50:46 PM PDT 24
Finished Jul 10 04:51:01 PM PDT 24
Peak memory 240412 kb
Host smart-a7091a66-66ba-4be5-8fb6-8f18e01e7ef7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3188330808 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_same_csr_out
standing.3188330808
Directory /workspace/5.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.4033202282
Short name T107
Test name
Test status
Simulation time 2920980186 ps
CPU time 111.47 seconds
Started Jul 10 04:50:46 PM PDT 24
Finished Jul 10 04:52:38 PM PDT 24
Peak memory 266096 kb
Host smart-f620c365-0ad9-45c4-835f-bbb8b15348fc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4033202282 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shadow_reg_erro
rs.4033202282
Directory /workspace/5.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.3306018586
Short name T108
Test name
Test status
Simulation time 4024278769 ps
CPU time 313.39 seconds
Started Jul 10 04:50:49 PM PDT 24
Finished Jul 10 04:56:04 PM PDT 24
Peak memory 268144 kb
Host smart-47e12f4c-c1b7-4482-aadb-0e02f441d69a
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306018586 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.alert_handler_shadow_reg_errors_with_csr_rw.3306018586
Directory /workspace/5.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.115707586
Short name T774
Test name
Test status
Simulation time 1733785551 ps
CPU time 13.97 seconds
Started Jul 10 04:50:54 PM PDT 24
Finished Jul 10 04:51:10 PM PDT 24
Peak memory 248532 kb
Host smart-e4eae94b-c349-431a-b258-b86d81a04b29
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=115707586 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_errors.115707586
Directory /workspace/5.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.4197934331
Short name T804
Test name
Test status
Simulation time 76920847 ps
CPU time 6.23 seconds
Started Jul 10 04:50:52 PM PDT 24
Finished Jul 10 04:50:59 PM PDT 24
Peak memory 240436 kb
Host smart-426d8de0-dc70-4815-a052-441ffb3750ba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197934331 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 6.alert_handler_csr_mem_rw_with_rand_reset.4197934331
Directory /workspace/6.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.2585312230
Short name T787
Test name
Test status
Simulation time 91720740 ps
CPU time 5.17 seconds
Started Jul 10 04:50:54 PM PDT 24
Finished Jul 10 04:51:01 PM PDT 24
Peak memory 236420 kb
Host smart-9a56ea99-8454-4830-8857-12a597b91a6d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2585312230 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_csr_rw.2585312230
Directory /workspace/6.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.1195522208
Short name T734
Test name
Test status
Simulation time 8608832 ps
CPU time 1.49 seconds
Started Jul 10 04:50:54 PM PDT 24
Finished Jul 10 04:50:57 PM PDT 24
Peak memory 237388 kb
Host smart-c77174ba-1472-4dd3-a508-b32ad2b1b2b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1195522208 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_intr_test.1195522208
Directory /workspace/6.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.3661223779
Short name T792
Test name
Test status
Simulation time 745798216 ps
CPU time 49.29 seconds
Started Jul 10 04:50:51 PM PDT 24
Finished Jul 10 04:51:40 PM PDT 24
Peak memory 248596 kb
Host smart-dd43fd0b-3e6a-4e50-9a81-c753cd1d0fad
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3661223779 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_same_csr_out
standing.3661223779
Directory /workspace/6.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.1639368217
Short name T109
Test name
Test status
Simulation time 5517247356 ps
CPU time 134.29 seconds
Started Jul 10 04:50:46 PM PDT 24
Finished Jul 10 04:53:01 PM PDT 24
Peak memory 266172 kb
Host smart-8ba60afd-61da-4f25-8938-ed516f40a3ec
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1639368217 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shadow_reg_erro
rs.1639368217
Directory /workspace/6.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.653590941
Short name T743
Test name
Test status
Simulation time 277954864 ps
CPU time 14.24 seconds
Started Jul 10 04:50:47 PM PDT 24
Finished Jul 10 04:51:02 PM PDT 24
Peak memory 253468 kb
Host smart-39422196-13d1-46a2-afa3-2a4f586559bf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=653590941 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_errors.653590941
Directory /workspace/6.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.3461297133
Short name T777
Test name
Test status
Simulation time 75596074 ps
CPU time 7.26 seconds
Started Jul 10 04:50:53 PM PDT 24
Finished Jul 10 04:51:02 PM PDT 24
Peak memory 239964 kb
Host smart-554082d8-33b5-48c8-a670-55ca4be4bec9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461297133 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 7.alert_handler_csr_mem_rw_with_rand_reset.3461297133
Directory /workspace/7.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.3328363764
Short name T811
Test name
Test status
Simulation time 59171529 ps
CPU time 4.73 seconds
Started Jul 10 04:50:52 PM PDT 24
Finished Jul 10 04:50:58 PM PDT 24
Peak memory 237448 kb
Host smart-73e18bae-0a79-47b3-8c76-32552a87c4ca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3328363764 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_csr_rw.3328363764
Directory /workspace/7.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.4234170156
Short name T767
Test name
Test status
Simulation time 9014788 ps
CPU time 1.54 seconds
Started Jul 10 04:50:52 PM PDT 24
Finished Jul 10 04:50:55 PM PDT 24
Peak memory 237468 kb
Host smart-d4bfce57-0bc2-41de-84e8-b2755641181e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4234170156 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_intr_test.4234170156
Directory /workspace/7.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.4067053088
Short name T184
Test name
Test status
Simulation time 525429051 ps
CPU time 38.19 seconds
Started Jul 10 04:50:53 PM PDT 24
Finished Jul 10 04:51:33 PM PDT 24
Peak memory 244692 kb
Host smart-0c737e1f-ed35-4796-be6d-9c6e69620735
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4067053088 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_same_csr_out
standing.4067053088
Directory /workspace/7.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.2106155670
Short name T137
Test name
Test status
Simulation time 4495616864 ps
CPU time 278.67 seconds
Started Jul 10 04:50:54 PM PDT 24
Finished Jul 10 04:55:34 PM PDT 24
Peak memory 265340 kb
Host smart-42e89dc6-d8d9-4c06-960c-1b79de9dc1c1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2106155670 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shadow_reg_erro
rs.2106155670
Directory /workspace/7.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.565160204
Short name T142
Test name
Test status
Simulation time 27769007643 ps
CPU time 499.93 seconds
Started Jul 10 04:50:55 PM PDT 24
Finished Jul 10 04:59:16 PM PDT 24
Peak memory 266360 kb
Host smart-0fa4ef5a-2ca9-4ddf-9cf1-9da0b79d955c
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565160204 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.alert_handler_shadow_reg_errors_with_csr_rw.565160204
Directory /workspace/7.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.3282076446
Short name T817
Test name
Test status
Simulation time 205395291 ps
CPU time 12.46 seconds
Started Jul 10 04:50:52 PM PDT 24
Finished Jul 10 04:51:06 PM PDT 24
Peak memory 253604 kb
Host smart-b921c874-7a5b-4c00-869c-a515fcc37267
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3282076446 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_errors.3282076446
Directory /workspace/7.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.1126722248
Short name T791
Test name
Test status
Simulation time 53803665 ps
CPU time 4.71 seconds
Started Jul 10 04:50:53 PM PDT 24
Finished Jul 10 04:51:00 PM PDT 24
Peak memory 240464 kb
Host smart-0f13d3da-3374-40b2-907a-1d17b5c681d7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126722248 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 8.alert_handler_csr_mem_rw_with_rand_reset.1126722248
Directory /workspace/8.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.433463581
Short name T776
Test name
Test status
Simulation time 30330074 ps
CPU time 3.5 seconds
Started Jul 10 04:50:52 PM PDT 24
Finished Jul 10 04:50:56 PM PDT 24
Peak memory 237456 kb
Host smart-8baaf643-8133-43c1-a6ac-05bfee0bbf73
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=433463581 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_csr_rw.433463581
Directory /workspace/8.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.3484738104
Short name T818
Test name
Test status
Simulation time 13877811 ps
CPU time 1.43 seconds
Started Jul 10 04:50:53 PM PDT 24
Finished Jul 10 04:50:56 PM PDT 24
Peak memory 237468 kb
Host smart-4505b5c3-0365-468c-90cf-3d73d69e4a6f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3484738104 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_intr_test.3484738104
Directory /workspace/8.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.1309334498
Short name T782
Test name
Test status
Simulation time 87719397 ps
CPU time 11.5 seconds
Started Jul 10 04:50:54 PM PDT 24
Finished Jul 10 04:51:07 PM PDT 24
Peak memory 248580 kb
Host smart-fb3e56a6-1784-4e58-9e71-63580ee24c0d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1309334498 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_same_csr_out
standing.1309334498
Directory /workspace/8.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.1487044397
Short name T121
Test name
Test status
Simulation time 8019679861 ps
CPU time 102.76 seconds
Started Jul 10 04:50:53 PM PDT 24
Finished Jul 10 04:52:38 PM PDT 24
Peak memory 265332 kb
Host smart-4d5e7247-386f-4b58-b48e-c83945f6d4f2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1487044397 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shadow_reg_erro
rs.1487044397
Directory /workspace/8.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.2179555755
Short name T133
Test name
Test status
Simulation time 12055022510 ps
CPU time 525.79 seconds
Started Jul 10 04:50:53 PM PDT 24
Finished Jul 10 04:59:40 PM PDT 24
Peak memory 265260 kb
Host smart-d2bd6b41-3138-4ac8-90ba-5ae85b3cca92
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179555755 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.alert_handler_shadow_reg_errors_with_csr_rw.2179555755
Directory /workspace/8.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.686389449
Short name T805
Test name
Test status
Simulation time 153170272 ps
CPU time 11.84 seconds
Started Jul 10 04:50:55 PM PDT 24
Finished Jul 10 04:51:08 PM PDT 24
Peak memory 253464 kb
Host smart-955a6015-2f0f-4910-9332-f755759f999c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=686389449 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_errors.686389449
Directory /workspace/8.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.406942566
Short name T166
Test name
Test status
Simulation time 628517503 ps
CPU time 42.4 seconds
Started Jul 10 04:50:52 PM PDT 24
Finished Jul 10 04:51:35 PM PDT 24
Peak memory 240412 kb
Host smart-5ae365af-4421-41aa-85c9-65cc3c51dcb5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=406942566 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_intg_err.406942566
Directory /workspace/8.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.1246090713
Short name T798
Test name
Test status
Simulation time 885652556 ps
CPU time 8.3 seconds
Started Jul 10 04:51:07 PM PDT 24
Finished Jul 10 04:51:18 PM PDT 24
Peak memory 248628 kb
Host smart-6397f4a5-e2b7-46f5-97d4-47212f25abc0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246090713 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 9.alert_handler_csr_mem_rw_with_rand_reset.1246090713
Directory /workspace/9.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.3530124559
Short name T165
Test name
Test status
Simulation time 308599145 ps
CPU time 9.6 seconds
Started Jul 10 04:50:59 PM PDT 24
Finished Jul 10 04:51:09 PM PDT 24
Peak memory 237448 kb
Host smart-016f13ca-8d75-4f7f-be82-5755eae0980f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3530124559 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_csr_rw.3530124559
Directory /workspace/9.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.2116859136
Short name T824
Test name
Test status
Simulation time 7819145 ps
CPU time 1.58 seconds
Started Jul 10 04:50:57 PM PDT 24
Finished Jul 10 04:51:00 PM PDT 24
Peak memory 236524 kb
Host smart-aef6c343-d78a-4145-9655-63a51b389432
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2116859136 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_intr_test.2116859136
Directory /workspace/9.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.2326359156
Short name T796
Test name
Test status
Simulation time 357132819 ps
CPU time 27.46 seconds
Started Jul 10 04:50:58 PM PDT 24
Finished Jul 10 04:51:26 PM PDT 24
Peak memory 248612 kb
Host smart-da8f38e4-a856-46c3-be81-30c3760aa079
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2326359156 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_same_csr_out
standing.2326359156
Directory /workspace/9.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.723892858
Short name T753
Test name
Test status
Simulation time 443128411 ps
CPU time 20.54 seconds
Started Jul 10 04:50:52 PM PDT 24
Finished Jul 10 04:51:14 PM PDT 24
Peak memory 248656 kb
Host smart-503c905d-0fd7-454d-ba84-f8475cf87bef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=723892858 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_errors.723892858
Directory /workspace/9.alert_handler_tl_errors/latest

Test location /workspace/coverage/default/0.alert_handler_entropy.3206548161
Short name T592
Test name
Test status
Simulation time 62123206040 ps
CPU time 1390.48 seconds
Started Jul 10 05:27:16 PM PDT 24
Finished Jul 10 05:50:28 PM PDT 24
Peak memory 273964 kb
Host smart-3e0d9395-a287-4be6-bb65-68ded2829c3e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206548161 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy.3206548161
Directory /workspace/0.alert_handler_entropy/latest

Test location /workspace/coverage/default/0.alert_handler_entropy_stress.1466756161
Short name T559
Test name
Test status
Simulation time 345906363 ps
CPU time 10.5 seconds
Started Jul 10 05:27:14 PM PDT 24
Finished Jul 10 05:27:27 PM PDT 24
Peak memory 249164 kb
Host smart-66ab5dbe-cdb0-4bff-ab39-60ac30b9132f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1466756161 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy_stress.1466756161
Directory /workspace/0.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/0.alert_handler_esc_alert_accum.3399418331
Short name T244
Test name
Test status
Simulation time 20969522647 ps
CPU time 301.39 seconds
Started Jul 10 05:27:12 PM PDT 24
Finished Jul 10 05:32:17 PM PDT 24
Peak memory 257560 kb
Host smart-8209fe33-201b-4e7c-a874-98a92400d25b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33994
18331 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_alert_accum.3399418331
Directory /workspace/0.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/0.alert_handler_lpg.4128588663
Short name T301
Test name
Test status
Simulation time 64735532956 ps
CPU time 2518.84 seconds
Started Jul 10 05:27:10 PM PDT 24
Finished Jul 10 06:09:11 PM PDT 24
Peak memory 289576 kb
Host smart-f04701a3-a487-4967-b2d4-c4dffad40767
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128588663 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg.4128588663
Directory /workspace/0.alert_handler_lpg/latest

Test location /workspace/coverage/default/0.alert_handler_lpg_stub_clk.1414466885
Short name T469
Test name
Test status
Simulation time 146791357155 ps
CPU time 1597.11 seconds
Started Jul 10 05:27:12 PM PDT 24
Finished Jul 10 05:53:52 PM PDT 24
Peak memory 273884 kb
Host smart-91b0872c-0929-412c-b548-c762ea92495e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414466885 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg_stub_clk.1414466885
Directory /workspace/0.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/0.alert_handler_random_alerts.1449935074
Short name T35
Test name
Test status
Simulation time 1623717648 ps
CPU time 32.77 seconds
Started Jul 10 05:27:12 PM PDT 24
Finished Jul 10 05:27:47 PM PDT 24
Peak memory 256728 kb
Host smart-119b5a40-ed09-4011-950c-3ff276f4d4b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14499
35074 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_alerts.1449935074
Directory /workspace/0.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/0.alert_handler_random_classes.3169275639
Short name T45
Test name
Test status
Simulation time 1242804621 ps
CPU time 34.05 seconds
Started Jul 10 05:27:13 PM PDT 24
Finished Jul 10 05:27:50 PM PDT 24
Peak memory 248748 kb
Host smart-3827c5dd-9aa2-4ed6-ba87-497f5949c208
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31692
75639 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_classes.3169275639
Directory /workspace/0.alert_handler_random_classes/latest

Test location /workspace/coverage/default/0.alert_handler_sig_int_fail.1041679055
Short name T594
Test name
Test status
Simulation time 474672134 ps
CPU time 18.37 seconds
Started Jul 10 05:27:11 PM PDT 24
Finished Jul 10 05:27:32 PM PDT 24
Peak memory 257400 kb
Host smart-c49af91f-2e9a-4459-8939-c36f9d0921ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10416
79055 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sig_int_fail.1041679055
Directory /workspace/0.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/0.alert_handler_smoke.21299348
Short name T626
Test name
Test status
Simulation time 1534263163 ps
CPU time 58.34 seconds
Started Jul 10 05:27:10 PM PDT 24
Finished Jul 10 05:28:10 PM PDT 24
Peak memory 257308 kb
Host smart-59878081-4a37-43d2-8d25-eda1d3a09cd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21299
348 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_smoke.21299348
Directory /workspace/0.alert_handler_smoke/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all.3503687631
Short name T87
Test name
Test status
Simulation time 27168615893 ps
CPU time 1305.68 seconds
Started Jul 10 05:27:19 PM PDT 24
Finished Jul 10 05:49:06 PM PDT 24
Peak memory 287004 kb
Host smart-5245b16a-0526-4746-8f9a-bbe03889e890
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503687631 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_han
dler_stress_all.3503687631
Directory /workspace/0.alert_handler_stress_all/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all_with_rand_reset.1971220797
Short name T73
Test name
Test status
Simulation time 37964051582 ps
CPU time 3524.6 seconds
Started Jul 10 05:27:18 PM PDT 24
Finished Jul 10 06:26:04 PM PDT 24
Peak memory 306744 kb
Host smart-618b5c2d-6263-4b22-b6d3-aaf24a078c53
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971220797 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.alert_handler_stress_all_with_rand_reset.1971220797
Directory /workspace/0.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.alert_handler_entropy.2909156307
Short name T231
Test name
Test status
Simulation time 10710952419 ps
CPU time 969.91 seconds
Started Jul 10 05:27:18 PM PDT 24
Finished Jul 10 05:43:29 PM PDT 24
Peak memory 270308 kb
Host smart-b5445f19-e713-49d1-932f-a43cec4eead9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909156307 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy.2909156307
Directory /workspace/1.alert_handler_entropy/latest

Test location /workspace/coverage/default/1.alert_handler_entropy_stress.1820465024
Short name T443
Test name
Test status
Simulation time 4117600283 ps
CPU time 52.62 seconds
Started Jul 10 05:27:24 PM PDT 24
Finished Jul 10 05:28:20 PM PDT 24
Peak memory 249328 kb
Host smart-eec2da89-5452-40c9-8e18-1c7fa8ac7621
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1820465024 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy_stress.1820465024
Directory /workspace/1.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/1.alert_handler_esc_alert_accum.1977607419
Short name T357
Test name
Test status
Simulation time 779918928 ps
CPU time 35.5 seconds
Started Jul 10 05:27:20 PM PDT 24
Finished Jul 10 05:27:57 PM PDT 24
Peak memory 256652 kb
Host smart-25a203e6-4620-46c6-ba94-a82d72f6248b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19776
07419 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_alert_accum.1977607419
Directory /workspace/1.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/1.alert_handler_esc_intr_timeout.2534918876
Short name T219
Test name
Test status
Simulation time 845894135 ps
CPU time 15.45 seconds
Started Jul 10 05:27:25 PM PDT 24
Finished Jul 10 05:27:43 PM PDT 24
Peak memory 255712 kb
Host smart-975c13ef-1063-410c-9416-dd45087b287c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25349
18876 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_intr_timeout.2534918876
Directory /workspace/1.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_lpg.1576821264
Short name T488
Test name
Test status
Simulation time 51126034487 ps
CPU time 1093.73 seconds
Started Jul 10 05:27:15 PM PDT 24
Finished Jul 10 05:45:31 PM PDT 24
Peak memory 290368 kb
Host smart-d95dc33d-1fd1-4fff-91ff-be621d8bc96f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1576821264 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg.1576821264
Directory /workspace/1.alert_handler_lpg/latest

Test location /workspace/coverage/default/1.alert_handler_lpg_stub_clk.1982776457
Short name T97
Test name
Test status
Simulation time 211413671372 ps
CPU time 3299.62 seconds
Started Jul 10 05:27:25 PM PDT 24
Finished Jul 10 06:22:28 PM PDT 24
Peak memory 290280 kb
Host smart-50a13be4-0ce8-487f-98cf-d14eacc4c229
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982776457 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg_stub_clk.1982776457
Directory /workspace/1.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/1.alert_handler_random_alerts.607227423
Short name T465
Test name
Test status
Simulation time 629312421 ps
CPU time 32.46 seconds
Started Jul 10 05:27:17 PM PDT 24
Finished Jul 10 05:27:51 PM PDT 24
Peak memory 249260 kb
Host smart-28f2e12b-e2e6-44f3-8516-cccf66f55aae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60722
7423 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_alerts.607227423
Directory /workspace/1.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/1.alert_handler_random_classes.2977425983
Short name T22
Test name
Test status
Simulation time 49325115 ps
CPU time 4.66 seconds
Started Jul 10 05:27:21 PM PDT 24
Finished Jul 10 05:27:28 PM PDT 24
Peak memory 240320 kb
Host smart-cccb11a6-8e66-4c94-86de-0ddce237deb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29774
25983 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_classes.2977425983
Directory /workspace/1.alert_handler_random_classes/latest

Test location /workspace/coverage/default/1.alert_handler_smoke.3995125515
Short name T458
Test name
Test status
Simulation time 1440556030 ps
CPU time 30 seconds
Started Jul 10 05:27:17 PM PDT 24
Finished Jul 10 05:27:48 PM PDT 24
Peak memory 256560 kb
Host smart-095a1438-5cf7-4b1b-a7bf-54cb6a7f78ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39951
25515 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_smoke.3995125515
Directory /workspace/1.alert_handler_smoke/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all.3803641147
Short name T398
Test name
Test status
Simulation time 71114389646 ps
CPU time 2273.88 seconds
Started Jul 10 05:27:25 PM PDT 24
Finished Jul 10 06:05:22 PM PDT 24
Peak memory 290392 kb
Host smart-9f8a0353-dd5d-4f3b-9303-f5d7d9d38c49
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803641147 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_han
dler_stress_all.3803641147
Directory /workspace/1.alert_handler_stress_all/latest

Test location /workspace/coverage/default/10.alert_handler_alert_accum_saturation.2850238457
Short name T208
Test name
Test status
Simulation time 37393132 ps
CPU time 3.39 seconds
Started Jul 10 05:27:42 PM PDT 24
Finished Jul 10 05:27:49 PM PDT 24
Peak memory 249568 kb
Host smart-923ccfa5-4544-4fcd-a303-01c8ee926d08
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2850238457 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_alert_accum_saturation.2850238457
Directory /workspace/10.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/10.alert_handler_entropy.4019379665
Short name T491
Test name
Test status
Simulation time 44931790402 ps
CPU time 1202.58 seconds
Started Jul 10 05:27:44 PM PDT 24
Finished Jul 10 05:47:51 PM PDT 24
Peak memory 289160 kb
Host smart-f08fb30e-6317-4a10-a218-1d3d36af7454
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4019379665 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy.4019379665
Directory /workspace/10.alert_handler_entropy/latest

Test location /workspace/coverage/default/10.alert_handler_entropy_stress.2332946165
Short name T457
Test name
Test status
Simulation time 268599654 ps
CPU time 14.09 seconds
Started Jul 10 05:27:42 PM PDT 24
Finished Jul 10 05:27:59 PM PDT 24
Peak memory 249284 kb
Host smart-1356e5c3-8f7b-461d-9e89-bcf25358c7ca
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2332946165 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy_stress.2332946165
Directory /workspace/10.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/10.alert_handler_esc_alert_accum.2562624786
Short name T422
Test name
Test status
Simulation time 5071773495 ps
CPU time 69.39 seconds
Started Jul 10 05:27:44 PM PDT 24
Finished Jul 10 05:28:57 PM PDT 24
Peak memory 257580 kb
Host smart-58c8332f-8d94-4e8e-b841-bf2dd827f88d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25626
24786 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_alert_accum.2562624786
Directory /workspace/10.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/10.alert_handler_esc_intr_timeout.368002212
Short name T431
Test name
Test status
Simulation time 711798163 ps
CPU time 44.83 seconds
Started Jul 10 05:27:42 PM PDT 24
Finished Jul 10 05:28:31 PM PDT 24
Peak memory 249260 kb
Host smart-47bd0774-e22a-4433-b1e8-aafd1dad6f7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36800
2212 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_intr_timeout.368002212
Directory /workspace/10.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_lpg_stub_clk.3056742916
Short name T593
Test name
Test status
Simulation time 17487724161 ps
CPU time 1058.91 seconds
Started Jul 10 05:27:42 PM PDT 24
Finished Jul 10 05:45:24 PM PDT 24
Peak memory 285044 kb
Host smart-e5abf321-f51a-46f8-8c16-b1606d6ac5a7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056742916 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg_stub_clk.3056742916
Directory /workspace/10.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/10.alert_handler_ping_timeout.1379918987
Short name T688
Test name
Test status
Simulation time 9824533367 ps
CPU time 232.9 seconds
Started Jul 10 05:27:43 PM PDT 24
Finished Jul 10 05:31:39 PM PDT 24
Peak memory 256148 kb
Host smart-e16759d3-2d24-4b0c-8392-98c47ff3fc05
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1379918987 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_ping_timeout.1379918987
Directory /workspace/10.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_random_alerts.1785943253
Short name T619
Test name
Test status
Simulation time 649337951 ps
CPU time 21.47 seconds
Started Jul 10 05:27:44 PM PDT 24
Finished Jul 10 05:28:09 PM PDT 24
Peak memory 256204 kb
Host smart-0eb8166a-52a0-4c72-99c6-156e4566169d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17859
43253 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_alerts.1785943253
Directory /workspace/10.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/10.alert_handler_random_classes.2960901282
Short name T40
Test name
Test status
Simulation time 108532028 ps
CPU time 12.66 seconds
Started Jul 10 05:27:42 PM PDT 24
Finished Jul 10 05:27:58 PM PDT 24
Peak memory 248604 kb
Host smart-b1797fc2-0bc8-4c78-8a40-24c028acf8b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29609
01282 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_classes.2960901282
Directory /workspace/10.alert_handler_random_classes/latest

Test location /workspace/coverage/default/10.alert_handler_sig_int_fail.3478292111
Short name T48
Test name
Test status
Simulation time 1349579990 ps
CPU time 27.91 seconds
Started Jul 10 05:27:41 PM PDT 24
Finished Jul 10 05:28:12 PM PDT 24
Peak memory 249296 kb
Host smart-4ef9b8a6-75b6-44a9-86ad-658e5f4eff2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34782
92111 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_sig_int_fail.3478292111
Directory /workspace/10.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/10.alert_handler_smoke.3453394815
Short name T566
Test name
Test status
Simulation time 477685126 ps
CPU time 28.52 seconds
Started Jul 10 05:27:42 PM PDT 24
Finished Jul 10 05:28:14 PM PDT 24
Peak memory 257204 kb
Host smart-7ffe9f9a-6441-4085-9c00-5af7c9d0f82e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34533
94815 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_smoke.3453394815
Directory /workspace/10.alert_handler_smoke/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all.1749397249
Short name T28
Test name
Test status
Simulation time 152002668880 ps
CPU time 2580.3 seconds
Started Jul 10 05:27:41 PM PDT 24
Finished Jul 10 06:10:44 PM PDT 24
Peak memory 289764 kb
Host smart-48218d35-728f-4cd7-b1a2-830328a36619
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749397249 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_ha
ndler_stress_all.1749397249
Directory /workspace/10.alert_handler_stress_all/latest

Test location /workspace/coverage/default/11.alert_handler_alert_accum_saturation.304657730
Short name T199
Test name
Test status
Simulation time 350077327 ps
CPU time 3.51 seconds
Started Jul 10 05:27:44 PM PDT 24
Finished Jul 10 05:27:51 PM PDT 24
Peak memory 249512 kb
Host smart-a3f8fbca-c55b-4546-9ee4-b17f4d2b6999
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=304657730 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_alert_accum_saturation.304657730
Directory /workspace/11.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/11.alert_handler_entropy.3594517465
Short name T6
Test name
Test status
Simulation time 8332122918 ps
CPU time 1134.93 seconds
Started Jul 10 05:27:43 PM PDT 24
Finished Jul 10 05:46:41 PM PDT 24
Peak memory 283964 kb
Host smart-f48ccbaf-7f8e-4d4a-84e8-2920dad05907
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3594517465 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy.3594517465
Directory /workspace/11.alert_handler_entropy/latest

Test location /workspace/coverage/default/11.alert_handler_entropy_stress.1042572497
Short name T412
Test name
Test status
Simulation time 3924712328 ps
CPU time 38.07 seconds
Started Jul 10 05:27:43 PM PDT 24
Finished Jul 10 05:28:25 PM PDT 24
Peak memory 249584 kb
Host smart-cac8920d-ef6e-41a7-adf1-41c43e1d41fb
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1042572497 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy_stress.1042572497
Directory /workspace/11.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/11.alert_handler_esc_alert_accum.214880221
Short name T351
Test name
Test status
Simulation time 1464871966 ps
CPU time 58.85 seconds
Started Jul 10 05:27:44 PM PDT 24
Finished Jul 10 05:28:47 PM PDT 24
Peak memory 257452 kb
Host smart-ef980e5e-618e-4c81-8677-c83f3c16105c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21488
0221 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_alert_accum.214880221
Directory /workspace/11.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/11.alert_handler_esc_intr_timeout.333662859
Short name T519
Test name
Test status
Simulation time 37479421 ps
CPU time 4.95 seconds
Started Jul 10 05:27:45 PM PDT 24
Finished Jul 10 05:27:53 PM PDT 24
Peak memory 252164 kb
Host smart-6bca8bbf-11e1-4dc1-98f5-5cdd2bde2130
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33366
2859 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_intr_timeout.333662859
Directory /workspace/11.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_lpg.2198745126
Short name T587
Test name
Test status
Simulation time 42343861600 ps
CPU time 1212.2 seconds
Started Jul 10 05:27:42 PM PDT 24
Finished Jul 10 05:47:57 PM PDT 24
Peak memory 285136 kb
Host smart-23248b28-b42d-4eb3-8a6c-079c74ae8498
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198745126 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg.2198745126
Directory /workspace/11.alert_handler_lpg/latest

Test location /workspace/coverage/default/11.alert_handler_lpg_stub_clk.3985114657
Short name T522
Test name
Test status
Simulation time 234186312579 ps
CPU time 3222.2 seconds
Started Jul 10 05:27:44 PM PDT 24
Finished Jul 10 06:21:30 PM PDT 24
Peak memory 290408 kb
Host smart-631adeeb-fb26-4efb-a8b3-f9c984b58be7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985114657 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg_stub_clk.3985114657
Directory /workspace/11.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/11.alert_handler_ping_timeout.1578852180
Short name T227
Test name
Test status
Simulation time 3785775133 ps
CPU time 145.69 seconds
Started Jul 10 05:27:41 PM PDT 24
Finished Jul 10 05:30:11 PM PDT 24
Peak memory 249152 kb
Host smart-b684cf37-cc50-4632-8c8d-1f82fcfddb80
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578852180 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_ping_timeout.1578852180
Directory /workspace/11.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_random_alerts.1124422760
Short name T683
Test name
Test status
Simulation time 230481211 ps
CPU time 14.79 seconds
Started Jul 10 05:27:40 PM PDT 24
Finished Jul 10 05:27:58 PM PDT 24
Peak memory 249292 kb
Host smart-fbee4bef-d75f-48fa-9bee-408a17e8b123
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11244
22760 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_alerts.1124422760
Directory /workspace/11.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/11.alert_handler_random_classes.377113850
Short name T583
Test name
Test status
Simulation time 859528291 ps
CPU time 48.01 seconds
Started Jul 10 05:27:44 PM PDT 24
Finished Jul 10 05:28:35 PM PDT 24
Peak memory 256924 kb
Host smart-6ea5a5d8-023d-43a6-b088-ef1398038032
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37711
3850 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_classes.377113850
Directory /workspace/11.alert_handler_random_classes/latest

Test location /workspace/coverage/default/11.alert_handler_sig_int_fail.2770600195
Short name T63
Test name
Test status
Simulation time 71909611 ps
CPU time 5.3 seconds
Started Jul 10 05:27:43 PM PDT 24
Finished Jul 10 05:27:52 PM PDT 24
Peak memory 240628 kb
Host smart-3cf8f6e2-6a5a-4b92-965b-bf7d9db27df7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27706
00195 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_sig_int_fail.2770600195
Directory /workspace/11.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/11.alert_handler_smoke.1707711475
Short name T225
Test name
Test status
Simulation time 2975256680 ps
CPU time 47.13 seconds
Started Jul 10 05:27:42 PM PDT 24
Finished Jul 10 05:28:32 PM PDT 24
Peak memory 257424 kb
Host smart-72ce284e-151f-4d59-a099-8b2c8d6f77dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17077
11475 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_smoke.1707711475
Directory /workspace/11.alert_handler_smoke/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all.3497524473
Short name T525
Test name
Test status
Simulation time 3617679701 ps
CPU time 113.46 seconds
Started Jul 10 05:27:45 PM PDT 24
Finished Jul 10 05:29:42 PM PDT 24
Peak memory 257524 kb
Host smart-d13375f0-acbb-47ac-a144-78d4291b4f5a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497524473 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_ha
ndler_stress_all.3497524473
Directory /workspace/11.alert_handler_stress_all/latest

Test location /workspace/coverage/default/12.alert_handler_alert_accum_saturation.3984484468
Short name T205
Test name
Test status
Simulation time 75195231 ps
CPU time 3.52 seconds
Started Jul 10 05:27:47 PM PDT 24
Finished Jul 10 05:27:53 PM PDT 24
Peak memory 249524 kb
Host smart-71128e0e-8d44-40c6-b623-70e67387420a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3984484468 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_alert_accum_saturation.3984484468
Directory /workspace/12.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/12.alert_handler_entropy.1962807944
Short name T494
Test name
Test status
Simulation time 227487226497 ps
CPU time 2590.38 seconds
Started Jul 10 05:27:43 PM PDT 24
Finished Jul 10 06:10:57 PM PDT 24
Peak memory 290232 kb
Host smart-bc2212a8-4f6c-42d7-8818-d6631dc252d4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962807944 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy.1962807944
Directory /workspace/12.alert_handler_entropy/latest

Test location /workspace/coverage/default/12.alert_handler_entropy_stress.3592430841
Short name T705
Test name
Test status
Simulation time 651592601 ps
CPU time 28.33 seconds
Started Jul 10 05:27:49 PM PDT 24
Finished Jul 10 05:28:19 PM PDT 24
Peak memory 249252 kb
Host smart-daf8cf4c-55f3-4ab8-a09b-4ac08350592f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3592430841 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy_stress.3592430841
Directory /workspace/12.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/12.alert_handler_esc_alert_accum.2338407780
Short name T483
Test name
Test status
Simulation time 567993086 ps
CPU time 39.41 seconds
Started Jul 10 05:27:44 PM PDT 24
Finished Jul 10 05:28:27 PM PDT 24
Peak memory 256980 kb
Host smart-57efbe7c-9935-47d9-bfa7-d59e77cfab80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23384
07780 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_alert_accum.2338407780
Directory /workspace/12.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/12.alert_handler_esc_intr_timeout.3338016547
Short name T172
Test name
Test status
Simulation time 258470539 ps
CPU time 7.22 seconds
Started Jul 10 05:27:43 PM PDT 24
Finished Jul 10 05:27:54 PM PDT 24
Peak memory 253732 kb
Host smart-bf0f02c8-bcce-433c-a42e-4194948711d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33380
16547 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_intr_timeout.3338016547
Directory /workspace/12.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_lpg_stub_clk.2867464859
Short name T290
Test name
Test status
Simulation time 198460211803 ps
CPU time 1507.4 seconds
Started Jul 10 05:27:42 PM PDT 24
Finished Jul 10 05:52:54 PM PDT 24
Peak memory 282176 kb
Host smart-36d15dfd-9770-48a7-98ef-6e234e008f1e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2867464859 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg_stub_clk.2867464859
Directory /workspace/12.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/12.alert_handler_ping_timeout.2542828963
Short name T315
Test name
Test status
Simulation time 48987025551 ps
CPU time 499.02 seconds
Started Jul 10 05:27:42 PM PDT 24
Finished Jul 10 05:36:04 PM PDT 24
Peak memory 249368 kb
Host smart-bdd5d8f0-ea51-4568-8a23-2aaeb56c3dea
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542828963 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_ping_timeout.2542828963
Directory /workspace/12.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_random_alerts.4210306181
Short name T545
Test name
Test status
Simulation time 38067307 ps
CPU time 3.62 seconds
Started Jul 10 05:27:44 PM PDT 24
Finished Jul 10 05:27:51 PM PDT 24
Peak memory 240968 kb
Host smart-0f048873-7b8e-4847-8522-4580b6542c9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42103
06181 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_alerts.4210306181
Directory /workspace/12.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/12.alert_handler_sig_int_fail.4190333144
Short name T512
Test name
Test status
Simulation time 586799684 ps
CPU time 36.72 seconds
Started Jul 10 05:27:41 PM PDT 24
Finished Jul 10 05:28:21 PM PDT 24
Peak memory 249044 kb
Host smart-1c2e924b-5c1f-4461-ac03-82795e3ffee6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41903
33144 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_sig_int_fail.4190333144
Directory /workspace/12.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/12.alert_handler_smoke.1240941983
Short name T480
Test name
Test status
Simulation time 2768763069 ps
CPU time 26.02 seconds
Started Jul 10 05:27:43 PM PDT 24
Finished Jul 10 05:28:13 PM PDT 24
Peak memory 249300 kb
Host smart-233f6b8e-7b89-4aec-849b-e7e1cd5673f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12409
41983 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_smoke.1240941983
Directory /workspace/12.alert_handler_smoke/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all.1066109454
Short name T695
Test name
Test status
Simulation time 31345725383 ps
CPU time 1719.22 seconds
Started Jul 10 05:27:46 PM PDT 24
Finished Jul 10 05:56:28 PM PDT 24
Peak memory 286964 kb
Host smart-789154fc-bd7a-4639-8b08-97a092923148
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066109454 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_ha
ndler_stress_all.1066109454
Directory /workspace/12.alert_handler_stress_all/latest

Test location /workspace/coverage/default/13.alert_handler_alert_accum_saturation.1365946732
Short name T44
Test name
Test status
Simulation time 77964036 ps
CPU time 3.67 seconds
Started Jul 10 05:27:50 PM PDT 24
Finished Jul 10 05:27:55 PM PDT 24
Peak memory 249572 kb
Host smart-ffd23298-768f-440c-b146-0eae35b68483
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1365946732 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_alert_accum_saturation.1365946732
Directory /workspace/13.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/13.alert_handler_entropy.2836098159
Short name T273
Test name
Test status
Simulation time 47838245074 ps
CPU time 1458.94 seconds
Started Jul 10 05:27:49 PM PDT 24
Finished Jul 10 05:52:10 PM PDT 24
Peak memory 268796 kb
Host smart-6090de4a-5a87-495b-bf36-ab23f18dd042
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836098159 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy.2836098159
Directory /workspace/13.alert_handler_entropy/latest

Test location /workspace/coverage/default/13.alert_handler_entropy_stress.1699151395
Short name T516
Test name
Test status
Simulation time 772104891 ps
CPU time 11.08 seconds
Started Jul 10 05:27:47 PM PDT 24
Finished Jul 10 05:28:01 PM PDT 24
Peak memory 249260 kb
Host smart-070522ab-7bfc-409c-b003-8f0a755a24b6
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1699151395 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy_stress.1699151395
Directory /workspace/13.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/13.alert_handler_esc_alert_accum.1024584548
Short name T176
Test name
Test status
Simulation time 529768473 ps
CPU time 50.62 seconds
Started Jul 10 05:27:49 PM PDT 24
Finished Jul 10 05:28:41 PM PDT 24
Peak memory 256700 kb
Host smart-15651464-b49d-4796-96dd-b5c1d0280afb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10245
84548 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_alert_accum.1024584548
Directory /workspace/13.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/13.alert_handler_esc_intr_timeout.3982313932
Short name T64
Test name
Test status
Simulation time 246892643 ps
CPU time 22.49 seconds
Started Jul 10 05:27:48 PM PDT 24
Finished Jul 10 05:28:12 PM PDT 24
Peak memory 249240 kb
Host smart-77f60c19-09a9-4ab2-8cf8-2204af53911c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39823
13932 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_intr_timeout.3982313932
Directory /workspace/13.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_lpg_stub_clk.1523332456
Short name T503
Test name
Test status
Simulation time 28560694543 ps
CPU time 1630.72 seconds
Started Jul 10 05:27:46 PM PDT 24
Finished Jul 10 05:54:59 PM PDT 24
Peak memory 273580 kb
Host smart-9d776c72-120c-41f4-8759-c3d74472d817
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1523332456 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg_stub_clk.1523332456
Directory /workspace/13.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/13.alert_handler_random_alerts.1585074528
Short name T481
Test name
Test status
Simulation time 3917030018 ps
CPU time 60.01 seconds
Started Jul 10 05:27:46 PM PDT 24
Finished Jul 10 05:28:49 PM PDT 24
Peak memory 257240 kb
Host smart-44c64cf4-1ee7-4172-b913-50e134d4c4f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15850
74528 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_alerts.1585074528
Directory /workspace/13.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/13.alert_handler_random_classes.2255234368
Short name T463
Test name
Test status
Simulation time 255478169 ps
CPU time 9.47 seconds
Started Jul 10 05:27:46 PM PDT 24
Finished Jul 10 05:27:58 PM PDT 24
Peak memory 252772 kb
Host smart-28164ff9-a9db-4345-8852-de73d74aa4cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22552
34368 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_classes.2255234368
Directory /workspace/13.alert_handler_random_classes/latest

Test location /workspace/coverage/default/13.alert_handler_smoke.615324484
Short name T473
Test name
Test status
Simulation time 882806729 ps
CPU time 12.12 seconds
Started Jul 10 05:27:47 PM PDT 24
Finished Jul 10 05:28:02 PM PDT 24
Peak memory 256136 kb
Host smart-b1777ded-4ba6-4f0d-81b4-0074c6dd111b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61532
4484 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_smoke.615324484
Directory /workspace/13.alert_handler_smoke/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all.3543314330
Short name T411
Test name
Test status
Simulation time 17079000156 ps
CPU time 779.03 seconds
Started Jul 10 05:27:53 PM PDT 24
Finished Jul 10 05:40:53 PM PDT 24
Peak memory 269148 kb
Host smart-4aa97489-9b83-4d04-b723-f9caaaf56774
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543314330 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_ha
ndler_stress_all.3543314330
Directory /workspace/13.alert_handler_stress_all/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all_with_rand_reset.3331679023
Short name T84
Test name
Test status
Simulation time 60716851793 ps
CPU time 5561.06 seconds
Started Jul 10 05:27:46 PM PDT 24
Finished Jul 10 07:00:30 PM PDT 24
Peak memory 371952 kb
Host smart-c309616e-5f3a-4b26-aa1d-b0c1e56eb606
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331679023 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.alert_handler_stress_all_with_rand_reset.3331679023
Directory /workspace/13.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.alert_handler_alert_accum_saturation.1427528974
Short name T203
Test name
Test status
Simulation time 595664963 ps
CPU time 3.45 seconds
Started Jul 10 05:27:56 PM PDT 24
Finished Jul 10 05:28:00 PM PDT 24
Peak memory 249672 kb
Host smart-c207ec50-740b-419b-8253-38e0b6acf954
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1427528974 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_alert_accum_saturation.1427528974
Directory /workspace/14.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/14.alert_handler_entropy.3339832579
Short name T680
Test name
Test status
Simulation time 44875232611 ps
CPU time 1283.67 seconds
Started Jul 10 05:27:49 PM PDT 24
Finished Jul 10 05:49:15 PM PDT 24
Peak memory 290068 kb
Host smart-fb83190e-a50c-4f88-9d7a-dfab5e0c58c5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339832579 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy.3339832579
Directory /workspace/14.alert_handler_entropy/latest

Test location /workspace/coverage/default/14.alert_handler_entropy_stress.2123953910
Short name T673
Test name
Test status
Simulation time 161465747 ps
CPU time 8.76 seconds
Started Jul 10 05:27:52 PM PDT 24
Finished Jul 10 05:28:02 PM PDT 24
Peak memory 249244 kb
Host smart-fbd49156-176b-4e6d-acc7-34eb71cec9e6
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2123953910 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy_stress.2123953910
Directory /workspace/14.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/14.alert_handler_esc_alert_accum.2209003170
Short name T492
Test name
Test status
Simulation time 15818897881 ps
CPU time 225.75 seconds
Started Jul 10 05:27:49 PM PDT 24
Finished Jul 10 05:31:37 PM PDT 24
Peak memory 257524 kb
Host smart-b488b6e7-ae70-4d26-9665-7e8212d177d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22090
03170 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_alert_accum.2209003170
Directory /workspace/14.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/14.alert_handler_esc_intr_timeout.3824046240
Short name T562
Test name
Test status
Simulation time 520389781 ps
CPU time 27.68 seconds
Started Jul 10 05:27:48 PM PDT 24
Finished Jul 10 05:28:17 PM PDT 24
Peak memory 249648 kb
Host smart-9b48b371-c97d-49b4-9c69-d117a2b19307
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38240
46240 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_intr_timeout.3824046240
Directory /workspace/14.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_lpg_stub_clk.398676945
Short name T433
Test name
Test status
Simulation time 162299137779 ps
CPU time 1857.82 seconds
Started Jul 10 05:27:48 PM PDT 24
Finished Jul 10 05:58:48 PM PDT 24
Peak memory 282040 kb
Host smart-bc50131b-6446-4128-82b5-8b804fa0db78
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398676945 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg_stub_clk.398676945
Directory /workspace/14.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/14.alert_handler_random_alerts.182312481
Short name T432
Test name
Test status
Simulation time 177641106 ps
CPU time 4.31 seconds
Started Jul 10 05:27:47 PM PDT 24
Finished Jul 10 05:27:53 PM PDT 24
Peak memory 249264 kb
Host smart-52b04d51-339f-415f-ac11-f75475efcd7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18231
2481 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_alerts.182312481
Directory /workspace/14.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/14.alert_handler_random_classes.1465434811
Short name T647
Test name
Test status
Simulation time 260477018 ps
CPU time 18.32 seconds
Started Jul 10 05:27:49 PM PDT 24
Finished Jul 10 05:28:09 PM PDT 24
Peak memory 249292 kb
Host smart-9983adee-0e00-49b9-8972-d3a755223e4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14654
34811 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_classes.1465434811
Directory /workspace/14.alert_handler_random_classes/latest

Test location /workspace/coverage/default/14.alert_handler_sig_int_fail.2476919581
Short name T556
Test name
Test status
Simulation time 759410735 ps
CPU time 8.99 seconds
Started Jul 10 05:27:52 PM PDT 24
Finished Jul 10 05:28:02 PM PDT 24
Peak memory 252292 kb
Host smart-e36daac4-0aa9-429e-95db-67200b989753
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24769
19581 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_sig_int_fail.2476919581
Directory /workspace/14.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/14.alert_handler_smoke.2848055731
Short name T580
Test name
Test status
Simulation time 683417944 ps
CPU time 38.7 seconds
Started Jul 10 05:27:48 PM PDT 24
Finished Jul 10 05:28:28 PM PDT 24
Peak memory 257316 kb
Host smart-b8e8e649-e4c2-4a01-b641-efb798a0c9c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28480
55731 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_smoke.2848055731
Directory /workspace/14.alert_handler_smoke/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all_with_rand_reset.3184271976
Short name T23
Test name
Test status
Simulation time 69870734325 ps
CPU time 7316.02 seconds
Started Jul 10 05:27:52 PM PDT 24
Finished Jul 10 07:29:51 PM PDT 24
Peak memory 370712 kb
Host smart-276d73b8-5eb6-44aa-a727-4acd434f006d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184271976 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 14.alert_handler_stress_all_with_rand_reset.3184271976
Directory /workspace/14.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.alert_handler_entropy.1255992978
Short name T570
Test name
Test status
Simulation time 11665294630 ps
CPU time 1160.95 seconds
Started Jul 10 05:27:52 PM PDT 24
Finished Jul 10 05:47:15 PM PDT 24
Peak memory 286100 kb
Host smart-6b6f6a56-258b-4a34-b22e-d9f196085e35
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1255992978 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy.1255992978
Directory /workspace/15.alert_handler_entropy/latest

Test location /workspace/coverage/default/15.alert_handler_entropy_stress.2727659994
Short name T700
Test name
Test status
Simulation time 7327428681 ps
CPU time 28.61 seconds
Started Jul 10 05:27:53 PM PDT 24
Finished Jul 10 05:28:24 PM PDT 24
Peak memory 249344 kb
Host smart-f3a8791c-dbf7-4727-bd3e-c113c651deaf
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2727659994 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy_stress.2727659994
Directory /workspace/15.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/15.alert_handler_esc_alert_accum.3423465530
Short name T220
Test name
Test status
Simulation time 1141753672 ps
CPU time 64.45 seconds
Started Jul 10 05:27:53 PM PDT 24
Finished Jul 10 05:28:59 PM PDT 24
Peak memory 256984 kb
Host smart-58555c9e-b2b3-44d7-bbca-20d53bdbe37d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34234
65530 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_alert_accum.3423465530
Directory /workspace/15.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/15.alert_handler_esc_intr_timeout.2138006277
Short name T624
Test name
Test status
Simulation time 1590024933 ps
CPU time 40.73 seconds
Started Jul 10 05:27:52 PM PDT 24
Finished Jul 10 05:28:34 PM PDT 24
Peak memory 257056 kb
Host smart-6631dd95-a34e-44f9-85f0-9ffd62016903
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21380
06277 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_intr_timeout.2138006277
Directory /workspace/15.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_lpg.4242375956
Short name T295
Test name
Test status
Simulation time 107621337125 ps
CPU time 1445.16 seconds
Started Jul 10 05:27:52 PM PDT 24
Finished Jul 10 05:51:58 PM PDT 24
Peak memory 273800 kb
Host smart-a942fc54-450e-4de1-93ca-651532e3a0ea
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242375956 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg.4242375956
Directory /workspace/15.alert_handler_lpg/latest

Test location /workspace/coverage/default/15.alert_handler_lpg_stub_clk.3273541814
Short name T500
Test name
Test status
Simulation time 28643680851 ps
CPU time 1492.99 seconds
Started Jul 10 05:27:52 PM PDT 24
Finished Jul 10 05:52:47 PM PDT 24
Peak memory 290100 kb
Host smart-e30eb68a-37e2-4ee9-b6a9-22855d120b4b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273541814 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg_stub_clk.3273541814
Directory /workspace/15.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/15.alert_handler_ping_timeout.574722706
Short name T9
Test name
Test status
Simulation time 17023300436 ps
CPU time 307.19 seconds
Started Jul 10 05:27:53 PM PDT 24
Finished Jul 10 05:33:02 PM PDT 24
Peak memory 249240 kb
Host smart-2dd2040a-d734-494a-928a-cd37b1742862
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574722706 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_ping_timeout.574722706
Directory /workspace/15.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_random_alerts.3380636951
Short name T350
Test name
Test status
Simulation time 136655918 ps
CPU time 13.2 seconds
Started Jul 10 05:27:52 PM PDT 24
Finished Jul 10 05:28:07 PM PDT 24
Peak memory 249296 kb
Host smart-a878d01c-71e5-44e5-bdfb-eebcdbfca6bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33806
36951 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_alerts.3380636951
Directory /workspace/15.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/15.alert_handler_random_classes.920216100
Short name T672
Test name
Test status
Simulation time 3368367865 ps
CPU time 50.55 seconds
Started Jul 10 05:27:54 PM PDT 24
Finished Jul 10 05:28:46 PM PDT 24
Peak memory 249068 kb
Host smart-e9511092-4def-42e2-89e0-76597f7fcf36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92021
6100 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_classes.920216100
Directory /workspace/15.alert_handler_random_classes/latest

Test location /workspace/coverage/default/15.alert_handler_smoke.1186316610
Short name T681
Test name
Test status
Simulation time 2209488384 ps
CPU time 33.48 seconds
Started Jul 10 05:27:51 PM PDT 24
Finished Jul 10 05:28:26 PM PDT 24
Peak memory 257564 kb
Host smart-e25124e6-d1e6-442b-89f2-3027ee979abb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11863
16610 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_smoke.1186316610
Directory /workspace/15.alert_handler_smoke/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all.1144963853
Short name T95
Test name
Test status
Simulation time 36613204215 ps
CPU time 1044.08 seconds
Started Jul 10 05:27:52 PM PDT 24
Finished Jul 10 05:45:18 PM PDT 24
Peak memory 290040 kb
Host smart-65e0a923-bbcb-4f73-a0d8-0608d1e18b96
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144963853 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_ha
ndler_stress_all.1144963853
Directory /workspace/15.alert_handler_stress_all/latest

Test location /workspace/coverage/default/16.alert_handler_entropy.2477114875
Short name T652
Test name
Test status
Simulation time 12948065992 ps
CPU time 1022.19 seconds
Started Jul 10 05:28:07 PM PDT 24
Finished Jul 10 05:45:10 PM PDT 24
Peak memory 285280 kb
Host smart-e9721a1e-949e-4a7f-a99c-074663b3c98b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477114875 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy.2477114875
Directory /workspace/16.alert_handler_entropy/latest

Test location /workspace/coverage/default/16.alert_handler_entropy_stress.4260097341
Short name T368
Test name
Test status
Simulation time 543129871 ps
CPU time 9.04 seconds
Started Jul 10 05:28:13 PM PDT 24
Finished Jul 10 05:28:23 PM PDT 24
Peak memory 249220 kb
Host smart-2ee61975-d80b-4af9-b147-b8a8645d589c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4260097341 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy_stress.4260097341
Directory /workspace/16.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/16.alert_handler_esc_alert_accum.3956308722
Short name T345
Test name
Test status
Simulation time 5831733703 ps
CPU time 346 seconds
Started Jul 10 05:28:05 PM PDT 24
Finished Jul 10 05:33:52 PM PDT 24
Peak memory 256916 kb
Host smart-b8b4e19b-5836-4471-9be0-f64d475d8f3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39563
08722 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_alert_accum.3956308722
Directory /workspace/16.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/16.alert_handler_esc_intr_timeout.12187832
Short name T30
Test name
Test status
Simulation time 2458116737 ps
CPU time 40.87 seconds
Started Jul 10 05:27:57 PM PDT 24
Finished Jul 10 05:28:39 PM PDT 24
Peak memory 257596 kb
Host smart-cdcaa3a0-d848-46d9-8edf-fc1f5de245c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12187
832 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_intr_timeout.12187832
Directory /workspace/16.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_lpg.4044555330
Short name T278
Test name
Test status
Simulation time 234769499946 ps
CPU time 2488.61 seconds
Started Jul 10 05:28:11 PM PDT 24
Finished Jul 10 06:09:41 PM PDT 24
Peak memory 289324 kb
Host smart-85feb819-5517-4683-b2a0-7fcee67050c3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4044555330 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg.4044555330
Directory /workspace/16.alert_handler_lpg/latest

Test location /workspace/coverage/default/16.alert_handler_lpg_stub_clk.1665995693
Short name T535
Test name
Test status
Simulation time 12673868020 ps
CPU time 1093.86 seconds
Started Jul 10 05:28:11 PM PDT 24
Finished Jul 10 05:46:26 PM PDT 24
Peak memory 284844 kb
Host smart-bbdfc3c3-3205-437e-8614-a721b0189fae
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665995693 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg_stub_clk.1665995693
Directory /workspace/16.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/16.alert_handler_ping_timeout.3866220521
Short name T539
Test name
Test status
Simulation time 35647399841 ps
CPU time 391.53 seconds
Started Jul 10 05:28:05 PM PDT 24
Finished Jul 10 05:34:37 PM PDT 24
Peak memory 257284 kb
Host smart-55a0b6b9-3d3d-4c46-b23c-8e949ea8f7a3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866220521 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_ping_timeout.3866220521
Directory /workspace/16.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_random_alerts.1906328329
Short name T472
Test name
Test status
Simulation time 77882556 ps
CPU time 7.26 seconds
Started Jul 10 05:27:52 PM PDT 24
Finished Jul 10 05:28:01 PM PDT 24
Peak memory 249256 kb
Host smart-885e0be5-eb7d-464a-b687-8a0326ef3274
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19063
28329 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_alerts.1906328329
Directory /workspace/16.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/16.alert_handler_random_classes.729756455
Short name T19
Test name
Test status
Simulation time 1897585106 ps
CPU time 32.13 seconds
Started Jul 10 05:27:52 PM PDT 24
Finished Jul 10 05:28:25 PM PDT 24
Peak memory 249280 kb
Host smart-674a2c69-1929-4b41-988c-d7e48cbbc439
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72975
6455 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_classes.729756455
Directory /workspace/16.alert_handler_random_classes/latest

Test location /workspace/coverage/default/16.alert_handler_sig_int_fail.1594622542
Short name T212
Test name
Test status
Simulation time 115549900 ps
CPU time 12.14 seconds
Started Jul 10 05:28:05 PM PDT 24
Finished Jul 10 05:28:19 PM PDT 24
Peak memory 248752 kb
Host smart-20b0a9b4-6a4b-4fea-9b0d-a10ef950f156
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15946
22542 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_sig_int_fail.1594622542
Directory /workspace/16.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/16.alert_handler_smoke.300372589
Short name T409
Test name
Test status
Simulation time 230903016 ps
CPU time 22.58 seconds
Started Jul 10 05:27:53 PM PDT 24
Finished Jul 10 05:28:17 PM PDT 24
Peak memory 256396 kb
Host smart-017a5360-b692-4a9e-bcf7-df26322874c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30037
2589 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_smoke.300372589
Directory /workspace/16.alert_handler_smoke/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all.955900253
Short name T258
Test name
Test status
Simulation time 27682898284 ps
CPU time 1387.2 seconds
Started Jul 10 05:28:10 PM PDT 24
Finished Jul 10 05:51:18 PM PDT 24
Peak memory 289908 kb
Host smart-2484e505-e747-4bd0-bcaa-cff74a9a9c12
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955900253 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_han
dler_stress_all.955900253
Directory /workspace/16.alert_handler_stress_all/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all_with_rand_reset.3774688376
Short name T104
Test name
Test status
Simulation time 80733032867 ps
CPU time 1992.28 seconds
Started Jul 10 05:28:10 PM PDT 24
Finished Jul 10 06:01:24 PM PDT 24
Peak memory 302068 kb
Host smart-d496a33f-a76d-4316-8f53-10ddab2b2327
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774688376 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 16.alert_handler_stress_all_with_rand_reset.3774688376
Directory /workspace/16.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.alert_handler_alert_accum_saturation.3697203970
Short name T210
Test name
Test status
Simulation time 17993419 ps
CPU time 2.77 seconds
Started Jul 10 05:28:24 PM PDT 24
Finished Jul 10 05:28:29 PM PDT 24
Peak memory 249512 kb
Host smart-05e37ce6-31eb-4fa8-9fc4-0e34c8d67e6d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3697203970 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_alert_accum_saturation.3697203970
Directory /workspace/17.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/17.alert_handler_entropy.766764445
Short name T13
Test name
Test status
Simulation time 26033553639 ps
CPU time 1491.01 seconds
Started Jul 10 05:28:16 PM PDT 24
Finished Jul 10 05:53:08 PM PDT 24
Peak memory 273784 kb
Host smart-0c8beb6d-7632-4f65-8b5c-d0b1fe461fa3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766764445 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy.766764445
Directory /workspace/17.alert_handler_entropy/latest

Test location /workspace/coverage/default/17.alert_handler_entropy_stress.3301326924
Short name T702
Test name
Test status
Simulation time 1445741141 ps
CPU time 18.82 seconds
Started Jul 10 05:28:23 PM PDT 24
Finished Jul 10 05:28:43 PM PDT 24
Peak memory 249260 kb
Host smart-eecc4ad3-ca36-4a19-95c2-bed2c01c581d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3301326924 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy_stress.3301326924
Directory /workspace/17.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/17.alert_handler_esc_alert_accum.1372768157
Short name T548
Test name
Test status
Simulation time 7746212215 ps
CPU time 113.98 seconds
Started Jul 10 05:28:18 PM PDT 24
Finished Jul 10 05:30:13 PM PDT 24
Peak memory 257352 kb
Host smart-29deaf19-2211-4e50-94ba-1d6916829729
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13727
68157 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_alert_accum.1372768157
Directory /workspace/17.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/17.alert_handler_esc_intr_timeout.587378021
Short name T444
Test name
Test status
Simulation time 64559517 ps
CPU time 2.95 seconds
Started Jul 10 05:28:17 PM PDT 24
Finished Jul 10 05:28:21 PM PDT 24
Peak memory 249232 kb
Host smart-590be40e-bd77-4075-bab9-6be64825fc2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58737
8021 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_intr_timeout.587378021
Directory /workspace/17.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_lpg.1562217743
Short name T636
Test name
Test status
Simulation time 51549583816 ps
CPU time 2598.33 seconds
Started Jul 10 05:28:17 PM PDT 24
Finished Jul 10 06:11:36 PM PDT 24
Peak memory 289940 kb
Host smart-e88438eb-d9b8-4293-ade4-a2792ebe0263
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562217743 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg.1562217743
Directory /workspace/17.alert_handler_lpg/latest

Test location /workspace/coverage/default/17.alert_handler_lpg_stub_clk.509248788
Short name T579
Test name
Test status
Simulation time 36230447606 ps
CPU time 1840.03 seconds
Started Jul 10 05:28:16 PM PDT 24
Finished Jul 10 05:58:58 PM PDT 24
Peak memory 285736 kb
Host smart-e039088f-9ea7-47f0-b0c7-1c7d9975c3c9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=509248788 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg_stub_clk.509248788
Directory /workspace/17.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/17.alert_handler_ping_timeout.2821332821
Short name T442
Test name
Test status
Simulation time 9748013393 ps
CPU time 198.14 seconds
Started Jul 10 05:28:18 PM PDT 24
Finished Jul 10 05:31:37 PM PDT 24
Peak memory 255008 kb
Host smart-a2a09c81-ad81-490d-89b7-94de84724e0c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821332821 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_ping_timeout.2821332821
Directory /workspace/17.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_random_alerts.440300252
Short name T510
Test name
Test status
Simulation time 1177872030 ps
CPU time 16.37 seconds
Started Jul 10 05:28:12 PM PDT 24
Finished Jul 10 05:28:30 PM PDT 24
Peak memory 256516 kb
Host smart-d4b11f86-5fdd-4fd4-9318-2961b2974300
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44030
0252 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_alerts.440300252
Directory /workspace/17.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/17.alert_handler_random_classes.2138849766
Short name T54
Test name
Test status
Simulation time 1099866581 ps
CPU time 30.83 seconds
Started Jul 10 05:28:18 PM PDT 24
Finished Jul 10 05:28:50 PM PDT 24
Peak memory 248408 kb
Host smart-b88509bf-baca-4beb-82e7-642e7b824710
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21388
49766 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_classes.2138849766
Directory /workspace/17.alert_handler_random_classes/latest

Test location /workspace/coverage/default/17.alert_handler_sig_int_fail.740051026
Short name T678
Test name
Test status
Simulation time 57904540 ps
CPU time 7.52 seconds
Started Jul 10 05:28:16 PM PDT 24
Finished Jul 10 05:28:25 PM PDT 24
Peak memory 254220 kb
Host smart-15501e50-0de5-4ada-b4a0-d59580ceaa64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74005
1026 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_sig_int_fail.740051026
Directory /workspace/17.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/17.alert_handler_smoke.458180140
Short name T497
Test name
Test status
Simulation time 2262380597 ps
CPU time 31.47 seconds
Started Jul 10 05:28:12 PM PDT 24
Finished Jul 10 05:28:45 PM PDT 24
Peak memory 256632 kb
Host smart-c3b12103-36ee-4cb9-a540-7d3f41784d5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45818
0140 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_smoke.458180140
Directory /workspace/17.alert_handler_smoke/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all.1773017148
Short name T99
Test name
Test status
Simulation time 21561339731 ps
CPU time 1536 seconds
Started Jul 10 05:28:25 PM PDT 24
Finished Jul 10 05:54:02 PM PDT 24
Peak memory 305308 kb
Host smart-c09b9c0e-91c9-4647-b524-5077f68502de
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773017148 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_ha
ndler_stress_all.1773017148
Directory /workspace/17.alert_handler_stress_all/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all_with_rand_reset.2774973184
Short name T489
Test name
Test status
Simulation time 5161638338 ps
CPU time 328.19 seconds
Started Jul 10 05:28:22 PM PDT 24
Finished Jul 10 05:33:51 PM PDT 24
Peak memory 274044 kb
Host smart-4bb1a033-77f8-49b5-a799-d34cf6a159f4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774973184 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 17.alert_handler_stress_all_with_rand_reset.2774973184
Directory /workspace/17.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.alert_handler_alert_accum_saturation.1313891146
Short name T202
Test name
Test status
Simulation time 13641860 ps
CPU time 2.54 seconds
Started Jul 10 05:28:25 PM PDT 24
Finished Jul 10 05:28:29 PM PDT 24
Peak memory 249492 kb
Host smart-2135521d-9895-4bd4-a18d-5050a215ff87
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1313891146 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_alert_accum_saturation.1313891146
Directory /workspace/18.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/18.alert_handler_entropy.2956112603
Short name T609
Test name
Test status
Simulation time 87213568167 ps
CPU time 1462.11 seconds
Started Jul 10 05:28:25 PM PDT 24
Finished Jul 10 05:52:49 PM PDT 24
Peak memory 273368 kb
Host smart-aa750d20-2294-4587-a504-099b9afc1b58
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956112603 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy.2956112603
Directory /workspace/18.alert_handler_entropy/latest

Test location /workspace/coverage/default/18.alert_handler_entropy_stress.2787007963
Short name T383
Test name
Test status
Simulation time 5853277355 ps
CPU time 56.68 seconds
Started Jul 10 05:28:23 PM PDT 24
Finished Jul 10 05:29:21 PM PDT 24
Peak memory 249344 kb
Host smart-30d1cc61-fa54-4e81-8a15-cf54a3890e61
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2787007963 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy_stress.2787007963
Directory /workspace/18.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/18.alert_handler_esc_alert_accum.3061090565
Short name T477
Test name
Test status
Simulation time 16483381048 ps
CPU time 286.38 seconds
Started Jul 10 05:28:25 PM PDT 24
Finished Jul 10 05:33:13 PM PDT 24
Peak memory 257440 kb
Host smart-f690757f-d4a8-4376-b10e-3df8d6063f85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30610
90565 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_alert_accum.3061090565
Directory /workspace/18.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/18.alert_handler_esc_intr_timeout.829836087
Short name T74
Test name
Test status
Simulation time 611046940 ps
CPU time 41.39 seconds
Started Jul 10 05:28:26 PM PDT 24
Finished Jul 10 05:29:09 PM PDT 24
Peak memory 256932 kb
Host smart-e0982bdf-b2f6-4d50-bc0b-d9a0d1e60898
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82983
6087 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_intr_timeout.829836087
Directory /workspace/18.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_lpg.448550053
Short name T318
Test name
Test status
Simulation time 68849811141 ps
CPU time 1834.74 seconds
Started Jul 10 05:28:25 PM PDT 24
Finished Jul 10 05:59:02 PM PDT 24
Peak memory 273892 kb
Host smart-59536cb3-83cb-436b-ac1d-7a6c967e1b5e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448550053 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg.448550053
Directory /workspace/18.alert_handler_lpg/latest

Test location /workspace/coverage/default/18.alert_handler_lpg_stub_clk.2334674480
Short name T374
Test name
Test status
Simulation time 58816410577 ps
CPU time 1602.56 seconds
Started Jul 10 05:28:22 PM PDT 24
Finished Jul 10 05:55:06 PM PDT 24
Peak memory 289568 kb
Host smart-33eccad4-bcb0-441e-a342-e7fb0094b99f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334674480 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg_stub_clk.2334674480
Directory /workspace/18.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/18.alert_handler_ping_timeout.425689100
Short name T213
Test name
Test status
Simulation time 6254104380 ps
CPU time 258.45 seconds
Started Jul 10 05:28:25 PM PDT 24
Finished Jul 10 05:32:45 PM PDT 24
Peak memory 249404 kb
Host smart-a5642623-0914-43a7-951b-0232d8f5b8a8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=425689100 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_ping_timeout.425689100
Directory /workspace/18.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_random_alerts.256782006
Short name T413
Test name
Test status
Simulation time 865833215 ps
CPU time 56.72 seconds
Started Jul 10 05:28:23 PM PDT 24
Finished Jul 10 05:29:21 PM PDT 24
Peak memory 249220 kb
Host smart-65649b98-fe59-4ea0-9492-bec9c11383ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25678
2006 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_alerts.256782006
Directory /workspace/18.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/18.alert_handler_random_classes.1631678650
Short name T627
Test name
Test status
Simulation time 706807410 ps
CPU time 47.87 seconds
Started Jul 10 05:28:24 PM PDT 24
Finished Jul 10 05:29:14 PM PDT 24
Peak memory 256708 kb
Host smart-c4460611-eaa0-45ed-a450-fd94b433069b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16316
78650 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_classes.1631678650
Directory /workspace/18.alert_handler_random_classes/latest

Test location /workspace/coverage/default/18.alert_handler_sig_int_fail.1993890173
Short name T617
Test name
Test status
Simulation time 2257814904 ps
CPU time 12.99 seconds
Started Jul 10 05:28:23 PM PDT 24
Finished Jul 10 05:28:37 PM PDT 24
Peak memory 248916 kb
Host smart-21e36e0c-ec61-4844-a92b-33eafd8559fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19938
90173 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_sig_int_fail.1993890173
Directory /workspace/18.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/18.alert_handler_smoke.300760214
Short name T3
Test name
Test status
Simulation time 74125417 ps
CPU time 3.2 seconds
Started Jul 10 05:28:23 PM PDT 24
Finished Jul 10 05:28:27 PM PDT 24
Peak memory 251340 kb
Host smart-047c666c-1ae3-41a3-9d4b-4301e8891307
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30076
0214 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_smoke.300760214
Directory /workspace/18.alert_handler_smoke/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all.72121472
Short name T703
Test name
Test status
Simulation time 64575779307 ps
CPU time 1607.94 seconds
Started Jul 10 05:28:22 PM PDT 24
Finished Jul 10 05:55:11 PM PDT 24
Peak memory 302108 kb
Host smart-022d3bf8-55b3-4ff8-8eee-53c67150ace9
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72121472 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_hand
ler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_hand
ler_stress_all.72121472
Directory /workspace/18.alert_handler_stress_all/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all_with_rand_reset.3006372599
Short name T75
Test name
Test status
Simulation time 154966048374 ps
CPU time 1827.43 seconds
Started Jul 10 05:28:23 PM PDT 24
Finished Jul 10 05:58:52 PM PDT 24
Peak memory 290508 kb
Host smart-35bf17f5-f59d-4e17-91b2-176e389aa96d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006372599 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.alert_handler_stress_all_with_rand_reset.3006372599
Directory /workspace/18.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.alert_handler_alert_accum_saturation.2072633003
Short name T201
Test name
Test status
Simulation time 23852802 ps
CPU time 2.59 seconds
Started Jul 10 05:28:29 PM PDT 24
Finished Jul 10 05:28:34 PM PDT 24
Peak memory 249584 kb
Host smart-dc9dffd1-a510-41cd-b6a5-b2a387247a3d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2072633003 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_alert_accum_saturation.2072633003
Directory /workspace/19.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/19.alert_handler_entropy.781933531
Short name T291
Test name
Test status
Simulation time 50497719920 ps
CPU time 3224.04 seconds
Started Jul 10 05:28:30 PM PDT 24
Finished Jul 10 06:22:16 PM PDT 24
Peak memory 289136 kb
Host smart-32894cbc-f072-4715-befa-e30cf5582012
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781933531 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy.781933531
Directory /workspace/19.alert_handler_entropy/latest

Test location /workspace/coverage/default/19.alert_handler_entropy_stress.2715994427
Short name T517
Test name
Test status
Simulation time 7638390097 ps
CPU time 46.23 seconds
Started Jul 10 05:28:28 PM PDT 24
Finished Jul 10 05:29:16 PM PDT 24
Peak memory 249256 kb
Host smart-f9388a7e-fb3b-49b9-bd0c-bd761247f3a5
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2715994427 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy_stress.2715994427
Directory /workspace/19.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/19.alert_handler_esc_alert_accum.762802020
Short name T364
Test name
Test status
Simulation time 1456319133 ps
CPU time 52.04 seconds
Started Jul 10 05:28:30 PM PDT 24
Finished Jul 10 05:29:24 PM PDT 24
Peak memory 256976 kb
Host smart-f172035d-d96a-4fef-801d-103fcca3284c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76280
2020 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_alert_accum.762802020
Directory /workspace/19.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/19.alert_handler_esc_intr_timeout.1157431023
Short name T505
Test name
Test status
Simulation time 834880222 ps
CPU time 49.4 seconds
Started Jul 10 05:28:29 PM PDT 24
Finished Jul 10 05:29:20 PM PDT 24
Peak memory 256560 kb
Host smart-b7e7ac5e-31e5-47a6-aa0d-58529060d89d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11574
31023 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_intr_timeout.1157431023
Directory /workspace/19.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_lpg.533417960
Short name T89
Test name
Test status
Simulation time 441878933231 ps
CPU time 2122.64 seconds
Started Jul 10 05:28:29 PM PDT 24
Finished Jul 10 06:03:53 PM PDT 24
Peak memory 286560 kb
Host smart-579100c6-4e82-4057-8a64-0528b9a6c8fa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533417960 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg.533417960
Directory /workspace/19.alert_handler_lpg/latest

Test location /workspace/coverage/default/19.alert_handler_lpg_stub_clk.1701188903
Short name T596
Test name
Test status
Simulation time 172209457254 ps
CPU time 2369.42 seconds
Started Jul 10 05:28:28 PM PDT 24
Finished Jul 10 06:08:00 PM PDT 24
Peak memory 282160 kb
Host smart-ebfcc781-e064-4daa-9741-94a93ff1a533
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701188903 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg_stub_clk.1701188903
Directory /workspace/19.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/19.alert_handler_ping_timeout.882246812
Short name T507
Test name
Test status
Simulation time 14871365285 ps
CPU time 588.29 seconds
Started Jul 10 05:28:26 PM PDT 24
Finished Jul 10 05:38:16 PM PDT 24
Peak memory 249216 kb
Host smart-7d5c5759-02ed-4420-9a6b-f7e8a7a225cd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882246812 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_ping_timeout.882246812
Directory /workspace/19.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_random_alerts.1838718091
Short name T382
Test name
Test status
Simulation time 163719444 ps
CPU time 8.9 seconds
Started Jul 10 05:28:28 PM PDT 24
Finished Jul 10 05:28:37 PM PDT 24
Peak memory 249220 kb
Host smart-7e34bd7b-56b7-462b-bc82-bad56654efff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18387
18091 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_alerts.1838718091
Directory /workspace/19.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/19.alert_handler_random_classes.233697635
Short name T18
Test name
Test status
Simulation time 442923561 ps
CPU time 40.97 seconds
Started Jul 10 05:28:29 PM PDT 24
Finished Jul 10 05:29:12 PM PDT 24
Peak memory 248696 kb
Host smart-1f7a7e0e-ff8c-490a-bd8a-ce3e3a856032
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23369
7635 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_classes.233697635
Directory /workspace/19.alert_handler_random_classes/latest

Test location /workspace/coverage/default/19.alert_handler_sig_int_fail.3881687450
Short name T17
Test name
Test status
Simulation time 1055613266 ps
CPU time 35.22 seconds
Started Jul 10 05:28:29 PM PDT 24
Finished Jul 10 05:29:06 PM PDT 24
Peak memory 256764 kb
Host smart-036f21e6-9fa6-46b4-b371-9585c704b821
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38816
87450 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_sig_int_fail.3881687450
Directory /workspace/19.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/19.alert_handler_smoke.2191782168
Short name T502
Test name
Test status
Simulation time 3602753940 ps
CPU time 64.29 seconds
Started Jul 10 05:28:29 PM PDT 24
Finished Jul 10 05:29:35 PM PDT 24
Peak memory 257524 kb
Host smart-89ba18da-1ec1-4ef8-ae33-e47dd62d6faa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21917
82168 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_smoke.2191782168
Directory /workspace/19.alert_handler_smoke/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all.3025943562
Short name T533
Test name
Test status
Simulation time 164163202597 ps
CPU time 877.45 seconds
Started Jul 10 05:28:28 PM PDT 24
Finished Jul 10 05:43:07 PM PDT 24
Peak memory 265748 kb
Host smart-b4916ed8-92f4-476f-a46e-d28e2af8cb08
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025943562 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_ha
ndler_stress_all.3025943562
Directory /workspace/19.alert_handler_stress_all/latest

Test location /workspace/coverage/default/2.alert_handler_alert_accum_saturation.1039742549
Short name T178
Test name
Test status
Simulation time 162513077 ps
CPU time 4.26 seconds
Started Jul 10 05:27:29 PM PDT 24
Finished Jul 10 05:27:35 PM PDT 24
Peak memory 249584 kb
Host smart-92f33b33-b40f-42c9-b1cb-a2d329fda142
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1039742549 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_alert_accum_saturation.1039742549
Directory /workspace/2.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/2.alert_handler_entropy.3268755319
Short name T706
Test name
Test status
Simulation time 104972321537 ps
CPU time 2163.62 seconds
Started Jul 10 05:27:23 PM PDT 24
Finished Jul 10 06:03:29 PM PDT 24
Peak memory 286072 kb
Host smart-df6be14d-c9a9-491c-a5a3-992b75922908
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3268755319 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy.3268755319
Directory /workspace/2.alert_handler_entropy/latest

Test location /workspace/coverage/default/2.alert_handler_entropy_stress.3898250744
Short name T675
Test name
Test status
Simulation time 1883800843 ps
CPU time 23.63 seconds
Started Jul 10 05:27:25 PM PDT 24
Finished Jul 10 05:27:51 PM PDT 24
Peak memory 249296 kb
Host smart-1a1e2e03-f4b3-4211-a8ff-8f5544d96fa4
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3898250744 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy_stress.3898250744
Directory /workspace/2.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/2.alert_handler_esc_alert_accum.469260406
Short name T373
Test name
Test status
Simulation time 31668109 ps
CPU time 4.03 seconds
Started Jul 10 05:27:24 PM PDT 24
Finished Jul 10 05:27:31 PM PDT 24
Peak memory 251788 kb
Host smart-bb3052ef-0bd4-4691-a505-3939ef6c3c23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46926
0406 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_alert_accum.469260406
Directory /workspace/2.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/2.alert_handler_esc_intr_timeout.3018499220
Short name T415
Test name
Test status
Simulation time 635535628 ps
CPU time 18.73 seconds
Started Jul 10 05:27:24 PM PDT 24
Finished Jul 10 05:27:46 PM PDT 24
Peak memory 248820 kb
Host smart-82e514ed-d842-4b3d-92c8-b27cb4f77227
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30184
99220 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_intr_timeout.3018499220
Directory /workspace/2.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_lpg.1292464163
Short name T552
Test name
Test status
Simulation time 15160474864 ps
CPU time 1272.92 seconds
Started Jul 10 05:27:24 PM PDT 24
Finished Jul 10 05:48:40 PM PDT 24
Peak memory 273400 kb
Host smart-bd1c430e-cf44-4ff5-a24e-5cd91a70d62b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292464163 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg.1292464163
Directory /workspace/2.alert_handler_lpg/latest

Test location /workspace/coverage/default/2.alert_handler_lpg_stub_clk.1587396261
Short name T542
Test name
Test status
Simulation time 17362403215 ps
CPU time 829.28 seconds
Started Jul 10 05:27:26 PM PDT 24
Finished Jul 10 05:41:18 PM PDT 24
Peak memory 273348 kb
Host smart-575656e1-b785-4b56-b8cb-692163309b78
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587396261 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg_stub_clk.1587396261
Directory /workspace/2.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/2.alert_handler_ping_timeout.2038827029
Short name T312
Test name
Test status
Simulation time 11053031770 ps
CPU time 504.58 seconds
Started Jul 10 05:27:24 PM PDT 24
Finished Jul 10 05:35:51 PM PDT 24
Peak memory 249288 kb
Host smart-4823d1d2-2828-4dfb-9706-5ead1a4b5124
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038827029 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_ping_timeout.2038827029
Directory /workspace/2.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_random_alerts.1812675398
Short name T633
Test name
Test status
Simulation time 818563797 ps
CPU time 54.56 seconds
Started Jul 10 05:27:20 PM PDT 24
Finished Jul 10 05:28:17 PM PDT 24
Peak memory 256648 kb
Host smart-e3d0ce8d-a6da-4c24-bafa-0f7efdea519a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18126
75398 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_alerts.1812675398
Directory /workspace/2.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/2.alert_handler_random_classes.3439073440
Short name T262
Test name
Test status
Simulation time 3938570054 ps
CPU time 61.65 seconds
Started Jul 10 05:27:24 PM PDT 24
Finished Jul 10 05:28:28 PM PDT 24
Peak memory 257308 kb
Host smart-a7b3a5a5-e8b8-4802-84b1-c8f2d5f283f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34390
73440 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_classes.3439073440
Directory /workspace/2.alert_handler_random_classes/latest

Test location /workspace/coverage/default/2.alert_handler_sec_cm.2000071374
Short name T11
Test name
Test status
Simulation time 655370332 ps
CPU time 12.38 seconds
Started Jul 10 05:27:24 PM PDT 24
Finished Jul 10 05:27:39 PM PDT 24
Peak memory 270680 kb
Host smart-b0eed530-d70f-4bd8-8de8-f8d1b41008d0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2000071374 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sec_cm.2000071374
Directory /workspace/2.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/2.alert_handler_sig_int_fail.4068801480
Short name T603
Test name
Test status
Simulation time 1021010984 ps
CPU time 29.74 seconds
Started Jul 10 05:27:25 PM PDT 24
Finished Jul 10 05:27:58 PM PDT 24
Peak memory 256552 kb
Host smart-514b82e9-b2d1-4ecc-ac81-b8369c331366
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40688
01480 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sig_int_fail.4068801480
Directory /workspace/2.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/2.alert_handler_smoke.3231636687
Short name T380
Test name
Test status
Simulation time 1075134872 ps
CPU time 65.3 seconds
Started Jul 10 05:27:25 PM PDT 24
Finished Jul 10 05:28:34 PM PDT 24
Peak memory 256464 kb
Host smart-5a277724-9836-47b4-88ca-2125d0238810
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32316
36687 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_smoke.3231636687
Directory /workspace/2.alert_handler_smoke/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all.3173629867
Short name T365
Test name
Test status
Simulation time 288898336 ps
CPU time 12.35 seconds
Started Jul 10 05:27:24 PM PDT 24
Finished Jul 10 05:27:39 PM PDT 24
Peak memory 249140 kb
Host smart-e5bbf78d-4dd1-497f-9101-0b0869bc4b7d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173629867 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_han
dler_stress_all.3173629867
Directory /workspace/2.alert_handler_stress_all/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all_with_rand_reset.1303970422
Short name T80
Test name
Test status
Simulation time 14784856442 ps
CPU time 842.27 seconds
Started Jul 10 05:27:27 PM PDT 24
Finished Jul 10 05:41:32 PM PDT 24
Peak memory 290204 kb
Host smart-7454a5b5-ba37-41d6-8184-1b60a3b69f28
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303970422 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.alert_handler_stress_all_with_rand_reset.1303970422
Directory /workspace/2.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.alert_handler_entropy.3647113366
Short name T427
Test name
Test status
Simulation time 34560051875 ps
CPU time 1700.41 seconds
Started Jul 10 05:28:39 PM PDT 24
Finished Jul 10 05:57:00 PM PDT 24
Peak memory 290172 kb
Host smart-8931511e-5594-4741-8e83-4278a8dd8d3d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647113366 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_entropy.3647113366
Directory /workspace/20.alert_handler_entropy/latest

Test location /workspace/coverage/default/20.alert_handler_esc_alert_accum.2539777447
Short name T437
Test name
Test status
Simulation time 8641667872 ps
CPU time 303.71 seconds
Started Jul 10 05:28:30 PM PDT 24
Finished Jul 10 05:33:35 PM PDT 24
Peak memory 257020 kb
Host smart-3cad3fdd-648c-4491-82af-dfb3d605db39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25397
77447 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_alert_accum.2539777447
Directory /workspace/20.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/20.alert_handler_esc_intr_timeout.4271051093
Short name T66
Test name
Test status
Simulation time 9535757823 ps
CPU time 56.94 seconds
Started Jul 10 05:28:27 PM PDT 24
Finished Jul 10 05:29:25 PM PDT 24
Peak memory 256832 kb
Host smart-3132cb00-0f4a-4900-9bc1-e6501543fc79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42710
51093 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_intr_timeout.4271051093
Directory /workspace/20.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_lpg.4016879161
Short name T86
Test name
Test status
Simulation time 21344659573 ps
CPU time 1482.44 seconds
Started Jul 10 05:28:39 PM PDT 24
Finished Jul 10 05:53:22 PM PDT 24
Peak memory 282208 kb
Host smart-1d5fa5c0-862e-4625-af51-9fab7549e3d8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4016879161 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg.4016879161
Directory /workspace/20.alert_handler_lpg/latest

Test location /workspace/coverage/default/20.alert_handler_lpg_stub_clk.504561967
Short name T541
Test name
Test status
Simulation time 175205996634 ps
CPU time 1884 seconds
Started Jul 10 05:28:36 PM PDT 24
Finished Jul 10 06:00:01 PM PDT 24
Peak memory 273944 kb
Host smart-8a8f91b2-febe-4269-8b0b-2aa2186b7263
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504561967 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg_stub_clk.504561967
Directory /workspace/20.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/20.alert_handler_ping_timeout.2680778415
Short name T536
Test name
Test status
Simulation time 3955955746 ps
CPU time 172.72 seconds
Started Jul 10 05:28:34 PM PDT 24
Finished Jul 10 05:31:28 PM PDT 24
Peak memory 249404 kb
Host smart-5d3f8edc-7be4-4cbd-8562-cc57e35588e7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680778415 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_ping_timeout.2680778415
Directory /workspace/20.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_random_alerts.983530959
Short name T362
Test name
Test status
Simulation time 106970118 ps
CPU time 13.41 seconds
Started Jul 10 05:28:29 PM PDT 24
Finished Jul 10 05:28:45 PM PDT 24
Peak memory 249268 kb
Host smart-1b5fb20f-ec7b-4117-af9c-f1f27390f71a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98353
0959 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_alerts.983530959
Directory /workspace/20.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/20.alert_handler_random_classes.583585440
Short name T16
Test name
Test status
Simulation time 235735981 ps
CPU time 16.02 seconds
Started Jul 10 05:28:29 PM PDT 24
Finished Jul 10 05:28:47 PM PDT 24
Peak memory 254824 kb
Host smart-1444355c-c7e5-49f8-9ae7-4afbcc78abe5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58358
5440 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_classes.583585440
Directory /workspace/20.alert_handler_random_classes/latest

Test location /workspace/coverage/default/20.alert_handler_sig_int_fail.3819017309
Short name T378
Test name
Test status
Simulation time 411519258 ps
CPU time 11.61 seconds
Started Jul 10 05:28:30 PM PDT 24
Finished Jul 10 05:28:43 PM PDT 24
Peak memory 248580 kb
Host smart-4315784d-fd97-4687-a613-bb6c3e5a362d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38190
17309 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_sig_int_fail.3819017309
Directory /workspace/20.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/20.alert_handler_smoke.4044064001
Short name T434
Test name
Test status
Simulation time 86715466 ps
CPU time 7.2 seconds
Started Jul 10 05:28:28 PM PDT 24
Finished Jul 10 05:28:36 PM PDT 24
Peak memory 249188 kb
Host smart-8857fe72-62b6-4bc2-a404-8fa439a74840
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40440
64001 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_smoke.4044064001
Directory /workspace/20.alert_handler_smoke/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all.1485468127
Short name T50
Test name
Test status
Simulation time 2046968670 ps
CPU time 158.09 seconds
Started Jul 10 05:28:35 PM PDT 24
Finished Jul 10 05:31:14 PM PDT 24
Peak memory 257368 kb
Host smart-7ba23ffc-0e9b-48b9-8ef4-b6a3894a3e0f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485468127 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_ha
ndler_stress_all.1485468127
Directory /workspace/20.alert_handler_stress_all/latest

Test location /workspace/coverage/default/21.alert_handler_entropy.3033685803
Short name T366
Test name
Test status
Simulation time 65278578786 ps
CPU time 1572.1 seconds
Started Jul 10 05:28:38 PM PDT 24
Finished Jul 10 05:54:50 PM PDT 24
Peak memory 290040 kb
Host smart-11537bda-7b71-4b1f-88f4-0ff9bc7169f2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033685803 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_entropy.3033685803
Directory /workspace/21.alert_handler_entropy/latest

Test location /workspace/coverage/default/21.alert_handler_esc_alert_accum.324867148
Short name T447
Test name
Test status
Simulation time 2589652782 ps
CPU time 144.09 seconds
Started Jul 10 05:28:37 PM PDT 24
Finished Jul 10 05:31:02 PM PDT 24
Peak memory 257108 kb
Host smart-e23f6c5b-b468-48f5-befa-ead3aa961a31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32486
7148 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_alert_accum.324867148
Directory /workspace/21.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/21.alert_handler_esc_intr_timeout.3666579248
Short name T689
Test name
Test status
Simulation time 1262830258 ps
CPU time 24.94 seconds
Started Jul 10 05:28:38 PM PDT 24
Finished Jul 10 05:29:03 PM PDT 24
Peak memory 248568 kb
Host smart-d4876f26-2342-47a4-8637-6a1e121e9eb2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36665
79248 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_intr_timeout.3666579248
Directory /workspace/21.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_lpg.1335031628
Short name T297
Test name
Test status
Simulation time 87196606641 ps
CPU time 2546.16 seconds
Started Jul 10 05:28:40 PM PDT 24
Finished Jul 10 06:11:07 PM PDT 24
Peak memory 289400 kb
Host smart-b93f30f4-72c5-4dd9-9aef-f6d3e95eda9d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335031628 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg.1335031628
Directory /workspace/21.alert_handler_lpg/latest

Test location /workspace/coverage/default/21.alert_handler_lpg_stub_clk.3008080003
Short name T660
Test name
Test status
Simulation time 111050076609 ps
CPU time 3275.59 seconds
Started Jul 10 05:28:37 PM PDT 24
Finished Jul 10 06:23:13 PM PDT 24
Peak memory 289740 kb
Host smart-8e9847f0-a3bb-41ab-b114-1caaa388489c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008080003 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg_stub_clk.3008080003
Directory /workspace/21.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/21.alert_handler_random_alerts.3915283844
Short name T476
Test name
Test status
Simulation time 480012965 ps
CPU time 8.18 seconds
Started Jul 10 05:28:39 PM PDT 24
Finished Jul 10 05:28:48 PM PDT 24
Peak memory 249288 kb
Host smart-398eb7d1-5b84-4772-9cbf-72807dcafeb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39152
83844 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_alerts.3915283844
Directory /workspace/21.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/21.alert_handler_sig_int_fail.2705298551
Short name T646
Test name
Test status
Simulation time 2408912753 ps
CPU time 38.74 seconds
Started Jul 10 05:28:35 PM PDT 24
Finished Jul 10 05:29:15 PM PDT 24
Peak memory 249272 kb
Host smart-74c37667-9cb8-40f9-9265-485f33479922
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27052
98551 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_sig_int_fail.2705298551
Directory /workspace/21.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/21.alert_handler_smoke.1927064799
Short name T595
Test name
Test status
Simulation time 929755370 ps
CPU time 49.87 seconds
Started Jul 10 05:28:35 PM PDT 24
Finished Jul 10 05:29:25 PM PDT 24
Peak memory 256968 kb
Host smart-df173243-ed78-4af8-896a-b5a76b3e40f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19270
64799 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_smoke.1927064799
Directory /workspace/21.alert_handler_smoke/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all.2557496152
Short name T474
Test name
Test status
Simulation time 147546168006 ps
CPU time 4065.3 seconds
Started Jul 10 05:28:35 PM PDT 24
Finished Jul 10 06:36:21 PM PDT 24
Peak memory 302460 kb
Host smart-c78187e8-cc45-46de-b8a2-f16bf95ebac2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557496152 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_ha
ndler_stress_all.2557496152
Directory /workspace/21.alert_handler_stress_all/latest

Test location /workspace/coverage/default/22.alert_handler_entropy.4102857026
Short name T5
Test name
Test status
Simulation time 98541072632 ps
CPU time 2906.99 seconds
Started Jul 10 05:28:42 PM PDT 24
Finished Jul 10 06:17:10 PM PDT 24
Peak memory 289716 kb
Host smart-5b49f75f-6427-4eb3-8a2d-6536dc140fac
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4102857026 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_entropy.4102857026
Directory /workspace/22.alert_handler_entropy/latest

Test location /workspace/coverage/default/22.alert_handler_esc_alert_accum.2154019062
Short name T578
Test name
Test status
Simulation time 2854887787 ps
CPU time 87.88 seconds
Started Jul 10 05:28:42 PM PDT 24
Finished Jul 10 05:30:10 PM PDT 24
Peak memory 257112 kb
Host smart-d207d65e-6edb-454d-97dc-5dce6ef0c220
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21540
19062 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_alert_accum.2154019062
Directory /workspace/22.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/22.alert_handler_esc_intr_timeout.2543337952
Short name T446
Test name
Test status
Simulation time 2446766991 ps
CPU time 56.17 seconds
Started Jul 10 05:28:43 PM PDT 24
Finished Jul 10 05:29:40 PM PDT 24
Peak memory 257144 kb
Host smart-401999d6-3ed4-4457-bea8-59c6a90ceab3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25433
37952 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_intr_timeout.2543337952
Directory /workspace/22.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_lpg.614994296
Short name T299
Test name
Test status
Simulation time 26544119560 ps
CPU time 1414.42 seconds
Started Jul 10 05:28:42 PM PDT 24
Finished Jul 10 05:52:17 PM PDT 24
Peak memory 265788 kb
Host smart-47b5c2c9-9f6b-47a0-9ec2-925227085e35
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614994296 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg.614994296
Directory /workspace/22.alert_handler_lpg/latest

Test location /workspace/coverage/default/22.alert_handler_lpg_stub_clk.1496632873
Short name T62
Test name
Test status
Simulation time 11595070498 ps
CPU time 1182.94 seconds
Started Jul 10 05:28:42 PM PDT 24
Finished Jul 10 05:48:26 PM PDT 24
Peak memory 285156 kb
Host smart-864b8ac6-5b58-4556-b811-a222937c3315
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496632873 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg_stub_clk.1496632873
Directory /workspace/22.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/22.alert_handler_ping_timeout.1341403161
Short name T632
Test name
Test status
Simulation time 13438249660 ps
CPU time 575.14 seconds
Started Jul 10 05:28:42 PM PDT 24
Finished Jul 10 05:38:18 PM PDT 24
Peak memory 256172 kb
Host smart-6eafd3ce-ca6b-49dd-881d-64bde6622725
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341403161 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_ping_timeout.1341403161
Directory /workspace/22.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_random_alerts.2069314949
Short name T389
Test name
Test status
Simulation time 1410044757 ps
CPU time 32.81 seconds
Started Jul 10 05:28:36 PM PDT 24
Finished Jul 10 05:29:09 PM PDT 24
Peak memory 256972 kb
Host smart-b68cef48-dada-4a6e-b071-cf430a94ffe4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20693
14949 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_alerts.2069314949
Directory /workspace/22.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/22.alert_handler_random_classes.2542243629
Short name T445
Test name
Test status
Simulation time 4602057597 ps
CPU time 49.23 seconds
Started Jul 10 05:28:43 PM PDT 24
Finished Jul 10 05:29:33 PM PDT 24
Peak memory 257620 kb
Host smart-29f6b9c6-dbcd-4281-9f73-6546db5173fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25422
43629 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_classes.2542243629
Directory /workspace/22.alert_handler_random_classes/latest

Test location /workspace/coverage/default/22.alert_handler_sig_int_fail.3856518227
Short name T599
Test name
Test status
Simulation time 378874471 ps
CPU time 24.13 seconds
Started Jul 10 05:28:42 PM PDT 24
Finished Jul 10 05:29:07 PM PDT 24
Peak memory 249240 kb
Host smart-05a5eb84-8fc2-4f91-8725-b7c50a5c9bb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38565
18227 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_sig_int_fail.3856518227
Directory /workspace/22.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/22.alert_handler_smoke.2180902548
Short name T346
Test name
Test status
Simulation time 592145528 ps
CPU time 21.32 seconds
Started Jul 10 05:28:35 PM PDT 24
Finished Jul 10 05:28:57 PM PDT 24
Peak memory 255984 kb
Host smart-b4cd9fab-3eb8-4832-b34b-4a954ef22155
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21809
02548 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_smoke.2180902548
Directory /workspace/22.alert_handler_smoke/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all.2477647718
Short name T92
Test name
Test status
Simulation time 116292394302 ps
CPU time 2697.29 seconds
Started Jul 10 05:28:45 PM PDT 24
Finished Jul 10 06:13:43 PM PDT 24
Peak memory 290060 kb
Host smart-6dab4fe3-8607-4982-abed-b8e9046a91b8
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477647718 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_ha
ndler_stress_all.2477647718
Directory /workspace/22.alert_handler_stress_all/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all_with_rand_reset.3546344280
Short name T29
Test name
Test status
Simulation time 100793991718 ps
CPU time 3632.18 seconds
Started Jul 10 05:28:42 PM PDT 24
Finished Jul 10 06:29:15 PM PDT 24
Peak memory 322916 kb
Host smart-47bdfd65-64a1-4bd8-a9ac-127cb4adfa9d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546344280 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 22.alert_handler_stress_all_with_rand_reset.3546344280
Directory /workspace/22.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.alert_handler_entropy.1825261014
Short name T549
Test name
Test status
Simulation time 69833031985 ps
CPU time 2186.04 seconds
Started Jul 10 05:28:49 PM PDT 24
Finished Jul 10 06:05:16 PM PDT 24
Peak memory 281800 kb
Host smart-8f1b505c-c16c-4c8d-8ee4-e828681dbd69
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825261014 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_entropy.1825261014
Directory /workspace/23.alert_handler_entropy/latest

Test location /workspace/coverage/default/23.alert_handler_esc_alert_accum.80004642
Short name T682
Test name
Test status
Simulation time 6201152683 ps
CPU time 377.92 seconds
Started Jul 10 05:28:48 PM PDT 24
Finished Jul 10 05:35:07 PM PDT 24
Peak memory 257128 kb
Host smart-19895bf3-1cd9-4a38-968b-c3f5c84cce35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80004
642 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_alert_accum.80004642
Directory /workspace/23.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/23.alert_handler_esc_intr_timeout.871902935
Short name T498
Test name
Test status
Simulation time 276378744 ps
CPU time 18.23 seconds
Started Jul 10 05:28:50 PM PDT 24
Finished Jul 10 05:29:09 PM PDT 24
Peak memory 254868 kb
Host smart-a778edb9-e519-483e-9d53-ea916f172ad5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87190
2935 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_intr_timeout.871902935
Directory /workspace/23.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_lpg.4216165125
Short name T326
Test name
Test status
Simulation time 15137234806 ps
CPU time 1518.47 seconds
Started Jul 10 05:28:50 PM PDT 24
Finished Jul 10 05:54:10 PM PDT 24
Peak memory 289084 kb
Host smart-7265af0b-68f8-4159-b80d-9df616ce10e8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216165125 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg.4216165125
Directory /workspace/23.alert_handler_lpg/latest

Test location /workspace/coverage/default/23.alert_handler_lpg_stub_clk.945241457
Short name T287
Test name
Test status
Simulation time 32442755660 ps
CPU time 808.81 seconds
Started Jul 10 05:28:51 PM PDT 24
Finished Jul 10 05:42:20 PM PDT 24
Peak memory 273028 kb
Host smart-2d7f791a-80b7-44e5-80de-26490efa7a01
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945241457 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg_stub_clk.945241457
Directory /workspace/23.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/23.alert_handler_ping_timeout.2264909549
Short name T316
Test name
Test status
Simulation time 59786396974 ps
CPU time 442.26 seconds
Started Jul 10 05:28:51 PM PDT 24
Finished Jul 10 05:36:14 PM PDT 24
Peak memory 256664 kb
Host smart-01fd8cfc-b750-43d7-9aac-7487248b1b71
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264909549 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_ping_timeout.2264909549
Directory /workspace/23.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_random_alerts.1893115569
Short name T524
Test name
Test status
Simulation time 636270787 ps
CPU time 41.76 seconds
Started Jul 10 05:28:49 PM PDT 24
Finished Jul 10 05:29:32 PM PDT 24
Peak memory 256712 kb
Host smart-30f4fc5d-9330-44f1-9f86-485ba357ad59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18931
15569 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_alerts.1893115569
Directory /workspace/23.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/23.alert_handler_random_classes.1376073485
Short name T527
Test name
Test status
Simulation time 917184303 ps
CPU time 58.17 seconds
Started Jul 10 05:28:49 PM PDT 24
Finished Jul 10 05:29:48 PM PDT 24
Peak memory 250540 kb
Host smart-9c228806-0225-461a-a0aa-a8583507046b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13760
73485 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_classes.1376073485
Directory /workspace/23.alert_handler_random_classes/latest

Test location /workspace/coverage/default/23.alert_handler_sig_int_fail.4187073355
Short name T423
Test name
Test status
Simulation time 357921456 ps
CPU time 18.43 seconds
Started Jul 10 05:28:50 PM PDT 24
Finished Jul 10 05:29:09 PM PDT 24
Peak memory 249300 kb
Host smart-8ad7798e-acbe-4e03-88fd-fb3e314db555
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41870
73355 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_sig_int_fail.4187073355
Directory /workspace/23.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/23.alert_handler_smoke.3203891083
Short name T171
Test name
Test status
Simulation time 6546618345 ps
CPU time 30.71 seconds
Started Jul 10 05:28:49 PM PDT 24
Finished Jul 10 05:29:21 PM PDT 24
Peak memory 249696 kb
Host smart-ce6cda0d-3e80-4f34-ba51-5ede4b2364e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32038
91083 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_smoke.3203891083
Directory /workspace/23.alert_handler_smoke/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all.3535437599
Short name T684
Test name
Test status
Simulation time 33048443832 ps
CPU time 475.76 seconds
Started Jul 10 05:28:48 PM PDT 24
Finished Jul 10 05:36:44 PM PDT 24
Peak memory 265796 kb
Host smart-7f90b932-d147-4aed-a754-38eb7e4fb749
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535437599 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_ha
ndler_stress_all.3535437599
Directory /workspace/23.alert_handler_stress_all/latest

Test location /workspace/coverage/default/24.alert_handler_entropy.548833090
Short name T475
Test name
Test status
Simulation time 28393378378 ps
CPU time 1877.28 seconds
Started Jul 10 05:28:57 PM PDT 24
Finished Jul 10 06:00:15 PM PDT 24
Peak memory 273908 kb
Host smart-df4a8ee7-2dd4-4b19-baaf-f11dd9f31f5b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548833090 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_entropy.548833090
Directory /workspace/24.alert_handler_entropy/latest

Test location /workspace/coverage/default/24.alert_handler_esc_alert_accum.3611466142
Short name T438
Test name
Test status
Simulation time 19937108349 ps
CPU time 207.32 seconds
Started Jul 10 05:28:48 PM PDT 24
Finished Jul 10 05:32:17 PM PDT 24
Peak memory 257108 kb
Host smart-49ab21de-32ae-41fb-b21d-4612649013f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36114
66142 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_alert_accum.3611466142
Directory /workspace/24.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/24.alert_handler_esc_intr_timeout.1538433056
Short name T625
Test name
Test status
Simulation time 479628991 ps
CPU time 13.16 seconds
Started Jul 10 05:28:49 PM PDT 24
Finished Jul 10 05:29:03 PM PDT 24
Peak memory 248836 kb
Host smart-326d41a2-5dcc-462a-85ca-1d6035f88e61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15384
33056 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_intr_timeout.1538433056
Directory /workspace/24.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_lpg.1313671428
Short name T679
Test name
Test status
Simulation time 26541321100 ps
CPU time 1126.52 seconds
Started Jul 10 05:28:55 PM PDT 24
Finished Jul 10 05:47:43 PM PDT 24
Peak memory 284644 kb
Host smart-fcbcc09c-840d-438b-b86a-f606eb3bfdc9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1313671428 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg.1313671428
Directory /workspace/24.alert_handler_lpg/latest

Test location /workspace/coverage/default/24.alert_handler_lpg_stub_clk.642405462
Short name T454
Test name
Test status
Simulation time 158547986842 ps
CPU time 2617.06 seconds
Started Jul 10 05:28:55 PM PDT 24
Finished Jul 10 06:12:33 PM PDT 24
Peak memory 290148 kb
Host smart-8f3f5e48-96bc-4cc2-b0b7-f0c5538e8dc0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=642405462 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg_stub_clk.642405462
Directory /workspace/24.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/24.alert_handler_ping_timeout.2964826568
Short name T407
Test name
Test status
Simulation time 18369712503 ps
CPU time 197.52 seconds
Started Jul 10 05:28:55 PM PDT 24
Finished Jul 10 05:32:13 PM PDT 24
Peak memory 249356 kb
Host smart-29a71c63-830c-4acc-ab6c-b365426be4ba
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964826568 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_ping_timeout.2964826568
Directory /workspace/24.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_random_alerts.791692499
Short name T46
Test name
Test status
Simulation time 145191368 ps
CPU time 6.89 seconds
Started Jul 10 05:28:50 PM PDT 24
Finished Jul 10 05:28:58 PM PDT 24
Peak memory 249220 kb
Host smart-136f0528-1efa-45e5-8931-6ff8ea6f2b98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79169
2499 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_alerts.791692499
Directory /workspace/24.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/24.alert_handler_random_classes.216465228
Short name T361
Test name
Test status
Simulation time 367599316 ps
CPU time 36.67 seconds
Started Jul 10 05:28:48 PM PDT 24
Finished Jul 10 05:29:26 PM PDT 24
Peak memory 248664 kb
Host smart-0ac8cfb0-c28c-4214-b29d-153632f9ee53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21646
5228 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_classes.216465228
Directory /workspace/24.alert_handler_random_classes/latest

Test location /workspace/coverage/default/24.alert_handler_smoke.574647478
Short name T272
Test name
Test status
Simulation time 5559712069 ps
CPU time 79.31 seconds
Started Jul 10 05:28:49 PM PDT 24
Finished Jul 10 05:30:09 PM PDT 24
Peak memory 249368 kb
Host smart-55622e38-b033-4b0e-afe7-692b2c520c4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57464
7478 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_smoke.574647478
Directory /workspace/24.alert_handler_smoke/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all.2604756938
Short name T56
Test name
Test status
Simulation time 10062206187 ps
CPU time 238.38 seconds
Started Jul 10 05:28:53 PM PDT 24
Finished Jul 10 05:32:52 PM PDT 24
Peak memory 257524 kb
Host smart-08d83e22-e5ff-4f20-a8a3-1edabdad95f4
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604756938 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_ha
ndler_stress_all.2604756938
Directory /workspace/24.alert_handler_stress_all/latest

Test location /workspace/coverage/default/25.alert_handler_entropy.3562333060
Short name T568
Test name
Test status
Simulation time 5579635812 ps
CPU time 744.38 seconds
Started Jul 10 05:29:10 PM PDT 24
Finished Jul 10 05:41:36 PM PDT 24
Peak memory 273408 kb
Host smart-d7c7342b-8ea2-486c-a0fd-0ca7d895485f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562333060 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_entropy.3562333060
Directory /workspace/25.alert_handler_entropy/latest

Test location /workspace/coverage/default/25.alert_handler_esc_alert_accum.1988018757
Short name T355
Test name
Test status
Simulation time 2900509528 ps
CPU time 100.04 seconds
Started Jul 10 05:28:54 PM PDT 24
Finished Jul 10 05:30:35 PM PDT 24
Peak memory 257144 kb
Host smart-b1686b32-7d17-473f-99b4-80030fa271d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19880
18757 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_alert_accum.1988018757
Directory /workspace/25.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/25.alert_handler_esc_intr_timeout.4253347790
Short name T674
Test name
Test status
Simulation time 595879160 ps
CPU time 48.47 seconds
Started Jul 10 05:28:56 PM PDT 24
Finished Jul 10 05:29:45 PM PDT 24
Peak memory 257192 kb
Host smart-ccadde49-f01a-43c7-8a71-853f1b87afc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42533
47790 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_intr_timeout.4253347790
Directory /workspace/25.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_lpg.1252268777
Short name T332
Test name
Test status
Simulation time 52669175685 ps
CPU time 1511.24 seconds
Started Jul 10 05:29:10 PM PDT 24
Finished Jul 10 05:54:22 PM PDT 24
Peak memory 290060 kb
Host smart-fe705dc3-75ec-4761-b548-1b494719cbd4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252268777 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg.1252268777
Directory /workspace/25.alert_handler_lpg/latest

Test location /workspace/coverage/default/25.alert_handler_lpg_stub_clk.675907385
Short name T540
Test name
Test status
Simulation time 47093826522 ps
CPU time 1087.52 seconds
Started Jul 10 05:29:01 PM PDT 24
Finished Jul 10 05:47:09 PM PDT 24
Peak memory 273840 kb
Host smart-15f85a60-8863-436b-a3bb-b9691c525463
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=675907385 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg_stub_clk.675907385
Directory /workspace/25.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/25.alert_handler_ping_timeout.1629244374
Short name T314
Test name
Test status
Simulation time 18103879190 ps
CPU time 169.93 seconds
Started Jul 10 05:29:01 PM PDT 24
Finished Jul 10 05:31:51 PM PDT 24
Peak memory 249344 kb
Host smart-bc20df3b-291f-4069-81e9-262300953e64
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629244374 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_ping_timeout.1629244374
Directory /workspace/25.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_random_alerts.3162989390
Short name T656
Test name
Test status
Simulation time 1605753046 ps
CPU time 31.19 seconds
Started Jul 10 05:28:55 PM PDT 24
Finished Jul 10 05:29:26 PM PDT 24
Peak memory 249228 kb
Host smart-3bc2ec7a-43c5-4139-a940-b8caa9e2fb79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31629
89390 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_alerts.3162989390
Directory /workspace/25.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/25.alert_handler_random_classes.1688446166
Short name T529
Test name
Test status
Simulation time 1002053251 ps
CPU time 41.28 seconds
Started Jul 10 05:28:55 PM PDT 24
Finished Jul 10 05:29:36 PM PDT 24
Peak memory 249200 kb
Host smart-a866caeb-02cc-43ad-a90d-9ae71b844f5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16884
46166 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_classes.1688446166
Directory /workspace/25.alert_handler_random_classes/latest

Test location /workspace/coverage/default/25.alert_handler_sig_int_fail.3179099324
Short name T57
Test name
Test status
Simulation time 930646169 ps
CPU time 35.91 seconds
Started Jul 10 05:28:56 PM PDT 24
Finished Jul 10 05:29:32 PM PDT 24
Peak memory 257408 kb
Host smart-9c626555-be36-4ccb-aeac-feeea7cc2ed7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31790
99324 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_sig_int_fail.3179099324
Directory /workspace/25.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/25.alert_handler_smoke.2305518956
Short name T356
Test name
Test status
Simulation time 2053154752 ps
CPU time 26.68 seconds
Started Jul 10 05:28:57 PM PDT 24
Finished Jul 10 05:29:24 PM PDT 24
Peak memory 256876 kb
Host smart-5dec9b73-75a7-4dd2-abc4-7e1850ed99fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23055
18956 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_smoke.2305518956
Directory /workspace/25.alert_handler_smoke/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all_with_rand_reset.2995646180
Short name T691
Test name
Test status
Simulation time 68015194641 ps
CPU time 6930.61 seconds
Started Jul 10 05:29:03 PM PDT 24
Finished Jul 10 07:24:35 PM PDT 24
Peak memory 355436 kb
Host smart-676a8ccf-de63-4e5a-8f96-83beeaa3c9b6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995646180 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 25.alert_handler_stress_all_with_rand_reset.2995646180
Directory /workspace/25.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.alert_handler_entropy.4063106121
Short name T101
Test name
Test status
Simulation time 27256974194 ps
CPU time 640.32 seconds
Started Jul 10 05:29:01 PM PDT 24
Finished Jul 10 05:39:42 PM PDT 24
Peak memory 268808 kb
Host smart-5520d8d3-01cc-4aae-be7b-65b73a0bd492
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063106121 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_entropy.4063106121
Directory /workspace/26.alert_handler_entropy/latest

Test location /workspace/coverage/default/26.alert_handler_esc_alert_accum.566145402
Short name T642
Test name
Test status
Simulation time 34340016756 ps
CPU time 118.64 seconds
Started Jul 10 05:29:00 PM PDT 24
Finished Jul 10 05:31:00 PM PDT 24
Peak memory 257484 kb
Host smart-87ca547c-06ae-452b-beea-21c5d77cbb1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56614
5402 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_alert_accum.566145402
Directory /workspace/26.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/26.alert_handler_esc_intr_timeout.1451010322
Short name T404
Test name
Test status
Simulation time 4539368838 ps
CPU time 27 seconds
Started Jul 10 05:29:01 PM PDT 24
Finished Jul 10 05:29:29 PM PDT 24
Peak memory 257548 kb
Host smart-d73c6909-cf49-4213-a218-d8619c45d3c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14510
10322 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_intr_timeout.1451010322
Directory /workspace/26.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_lpg.118762197
Short name T336
Test name
Test status
Simulation time 559087761943 ps
CPU time 2050.99 seconds
Started Jul 10 05:29:10 PM PDT 24
Finished Jul 10 06:03:22 PM PDT 24
Peak memory 273308 kb
Host smart-9513992b-81be-4bea-9f99-0a928e81947d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118762197 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg.118762197
Directory /workspace/26.alert_handler_lpg/latest

Test location /workspace/coverage/default/26.alert_handler_lpg_stub_clk.2477553774
Short name T372
Test name
Test status
Simulation time 36920128427 ps
CPU time 722.83 seconds
Started Jul 10 05:29:11 PM PDT 24
Finished Jul 10 05:41:15 PM PDT 24
Peak memory 265756 kb
Host smart-7fbb42cf-4f00-4144-97f7-3021eb29423e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477553774 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg_stub_clk.2477553774
Directory /workspace/26.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/26.alert_handler_ping_timeout.22147962
Short name T323
Test name
Test status
Simulation time 32519108564 ps
CPU time 383.16 seconds
Started Jul 10 05:29:02 PM PDT 24
Finished Jul 10 05:35:26 PM PDT 24
Peak memory 248248 kb
Host smart-54ba6b41-d35b-4dd9-98fc-aba6e4ea75be
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22147962 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_ping_timeout.22147962
Directory /workspace/26.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_random_alerts.1575924748
Short name T397
Test name
Test status
Simulation time 1676931123 ps
CPU time 24.48 seconds
Started Jul 10 05:29:10 PM PDT 24
Finished Jul 10 05:29:36 PM PDT 24
Peak memory 256756 kb
Host smart-2333bc1b-2c76-44ae-9152-492418574073
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15759
24748 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_alerts.1575924748
Directory /workspace/26.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/26.alert_handler_random_classes.2833415146
Short name T493
Test name
Test status
Simulation time 3191114088 ps
CPU time 44.35 seconds
Started Jul 10 05:29:04 PM PDT 24
Finished Jul 10 05:29:48 PM PDT 24
Peak memory 257112 kb
Host smart-fb9f6dd7-5ab9-4571-87ef-8ae3bcb593d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28334
15146 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_classes.2833415146
Directory /workspace/26.alert_handler_random_classes/latest

Test location /workspace/coverage/default/26.alert_handler_sig_int_fail.2812619630
Short name T267
Test name
Test status
Simulation time 696717172 ps
CPU time 39.58 seconds
Started Jul 10 05:29:00 PM PDT 24
Finished Jul 10 05:29:41 PM PDT 24
Peak memory 249292 kb
Host smart-6a08d0bf-686e-4dd0-85cc-aa81bd00b186
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28126
19630 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_sig_int_fail.2812619630
Directory /workspace/26.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/26.alert_handler_smoke.582928212
Short name T417
Test name
Test status
Simulation time 2353846114 ps
CPU time 20.82 seconds
Started Jul 10 05:29:02 PM PDT 24
Finished Jul 10 05:29:23 PM PDT 24
Peak memory 250012 kb
Host smart-db53a08f-ad43-409f-9a3e-3f638f512943
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58292
8212 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_smoke.582928212
Directory /workspace/26.alert_handler_smoke/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all.1370935447
Short name T526
Test name
Test status
Simulation time 51071143844 ps
CPU time 3178.87 seconds
Started Jul 10 05:29:11 PM PDT 24
Finished Jul 10 06:22:11 PM PDT 24
Peak memory 306468 kb
Host smart-1ed5b611-762b-4576-ade9-a053ed9416a5
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370935447 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_ha
ndler_stress_all.1370935447
Directory /workspace/26.alert_handler_stress_all/latest

Test location /workspace/coverage/default/27.alert_handler_entropy.2117320203
Short name T712
Test name
Test status
Simulation time 25233902217 ps
CPU time 1768.66 seconds
Started Jul 10 05:29:08 PM PDT 24
Finished Jul 10 05:58:38 PM PDT 24
Peak memory 284200 kb
Host smart-226e5089-d7ba-4b4d-b673-d584dff5662f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117320203 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_entropy.2117320203
Directory /workspace/27.alert_handler_entropy/latest

Test location /workspace/coverage/default/27.alert_handler_esc_alert_accum.3536718244
Short name T567
Test name
Test status
Simulation time 2015594723 ps
CPU time 81.08 seconds
Started Jul 10 05:29:09 PM PDT 24
Finished Jul 10 05:30:31 PM PDT 24
Peak memory 251312 kb
Host smart-1963001f-d2bf-41f4-9ed0-9a500862efb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35367
18244 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_alert_accum.3536718244
Directory /workspace/27.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/27.alert_handler_esc_intr_timeout.3984523836
Short name T670
Test name
Test status
Simulation time 18811416 ps
CPU time 3.07 seconds
Started Jul 10 05:29:08 PM PDT 24
Finished Jul 10 05:29:12 PM PDT 24
Peak memory 241020 kb
Host smart-7a7b4a4e-4d4f-42cc-b44f-1dc44b2c4bdd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39845
23836 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_intr_timeout.3984523836
Directory /workspace/27.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_lpg_stub_clk.3501439302
Short name T298
Test name
Test status
Simulation time 73042931076 ps
CPU time 2031.78 seconds
Started Jul 10 05:29:10 PM PDT 24
Finished Jul 10 06:03:03 PM PDT 24
Peak memory 282180 kb
Host smart-ae0e7b25-6ebd-4a0e-a07b-e6ea88aedddf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501439302 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg_stub_clk.3501439302
Directory /workspace/27.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/27.alert_handler_ping_timeout.320639138
Short name T324
Test name
Test status
Simulation time 13549782702 ps
CPU time 541.54 seconds
Started Jul 10 05:29:12 PM PDT 24
Finished Jul 10 05:38:15 PM PDT 24
Peak memory 249196 kb
Host smart-d0690a3e-251d-4157-9966-89feb0e251c8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320639138 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_ping_timeout.320639138
Directory /workspace/27.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_random_alerts.2612625476
Short name T396
Test name
Test status
Simulation time 982889551 ps
CPU time 33.14 seconds
Started Jul 10 05:29:07 PM PDT 24
Finished Jul 10 05:29:41 PM PDT 24
Peak memory 257100 kb
Host smart-ceb8a132-eecd-40fe-89db-762c2244b4b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26126
25476 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_alerts.2612625476
Directory /workspace/27.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/27.alert_handler_random_classes.881602750
Short name T349
Test name
Test status
Simulation time 1056661980 ps
CPU time 63.23 seconds
Started Jul 10 05:29:08 PM PDT 24
Finished Jul 10 05:30:11 PM PDT 24
Peak memory 249112 kb
Host smart-f6b295f0-187e-402b-9a95-e69b61452de8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88160
2750 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_classes.881602750
Directory /workspace/27.alert_handler_random_classes/latest

Test location /workspace/coverage/default/27.alert_handler_smoke.1505862205
Short name T78
Test name
Test status
Simulation time 1230885860 ps
CPU time 39.55 seconds
Started Jul 10 05:29:06 PM PDT 24
Finished Jul 10 05:29:46 PM PDT 24
Peak memory 257372 kb
Host smart-55a84c2f-57cd-4a97-b2fa-9ad0846c8dde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15058
62205 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_smoke.1505862205
Directory /workspace/27.alert_handler_smoke/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all.3710581101
Short name T102
Test name
Test status
Simulation time 80420425893 ps
CPU time 1328.13 seconds
Started Jul 10 05:29:06 PM PDT 24
Finished Jul 10 05:51:15 PM PDT 24
Peak memory 289732 kb
Host smart-b298dd32-bde4-47ae-9fcc-5523607aa1d1
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710581101 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_ha
ndler_stress_all.3710581101
Directory /workspace/27.alert_handler_stress_all/latest

Test location /workspace/coverage/default/28.alert_handler_entropy.1692371140
Short name T103
Test name
Test status
Simulation time 130044618976 ps
CPU time 1057.5 seconds
Started Jul 10 05:29:12 PM PDT 24
Finished Jul 10 05:46:50 PM PDT 24
Peak memory 273924 kb
Host smart-60c76698-8934-45e7-96c0-4564bc0499a9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1692371140 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_entropy.1692371140
Directory /workspace/28.alert_handler_entropy/latest

Test location /workspace/coverage/default/28.alert_handler_esc_alert_accum.125669130
Short name T43
Test name
Test status
Simulation time 12862056492 ps
CPU time 129.8 seconds
Started Jul 10 05:29:12 PM PDT 24
Finished Jul 10 05:31:23 PM PDT 24
Peak memory 257004 kb
Host smart-c90762ce-d7df-49fd-a2ed-77889a5a8f51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12566
9130 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_alert_accum.125669130
Directory /workspace/28.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/28.alert_handler_esc_intr_timeout.53254199
Short name T487
Test name
Test status
Simulation time 741020056 ps
CPU time 49.71 seconds
Started Jul 10 05:29:22 PM PDT 24
Finished Jul 10 05:30:12 PM PDT 24
Peak memory 249216 kb
Host smart-fe1fcd0f-58d8-43a2-914a-ffd43ca207cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53254
199 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_intr_timeout.53254199
Directory /workspace/28.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_lpg.3775112014
Short name T191
Test name
Test status
Simulation time 43982823055 ps
CPU time 2589.24 seconds
Started Jul 10 05:29:12 PM PDT 24
Finished Jul 10 06:12:22 PM PDT 24
Peak memory 282184 kb
Host smart-e178a4f3-baa0-42ea-a37e-902c2b81c4b0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775112014 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg.3775112014
Directory /workspace/28.alert_handler_lpg/latest

Test location /workspace/coverage/default/28.alert_handler_lpg_stub_clk.2695590301
Short name T637
Test name
Test status
Simulation time 22475544762 ps
CPU time 1026.99 seconds
Started Jul 10 05:29:18 PM PDT 24
Finished Jul 10 05:46:25 PM PDT 24
Peak memory 273536 kb
Host smart-58dc9743-a439-4018-a003-dd22024a242b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695590301 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg_stub_clk.2695590301
Directory /workspace/28.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/28.alert_handler_random_alerts.404846655
Short name T623
Test name
Test status
Simulation time 327306344 ps
CPU time 30.22 seconds
Started Jul 10 05:29:11 PM PDT 24
Finished Jul 10 05:29:42 PM PDT 24
Peak memory 256828 kb
Host smart-8b6c8d93-0129-4966-b699-920415abc940
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40484
6655 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_alerts.404846655
Directory /workspace/28.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/28.alert_handler_random_classes.2003137845
Short name T572
Test name
Test status
Simulation time 6055277104 ps
CPU time 44.29 seconds
Started Jul 10 05:29:05 PM PDT 24
Finished Jul 10 05:29:50 PM PDT 24
Peak memory 249924 kb
Host smart-999651e2-ff22-4f50-9f91-13d8898a1541
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20031
37845 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_classes.2003137845
Directory /workspace/28.alert_handler_random_classes/latest

Test location /workspace/coverage/default/28.alert_handler_sig_int_fail.3711020413
Short name T515
Test name
Test status
Simulation time 214065925 ps
CPU time 23.08 seconds
Started Jul 10 05:29:13 PM PDT 24
Finished Jul 10 05:29:36 PM PDT 24
Peak memory 249224 kb
Host smart-a6c2d0a1-8f9a-455f-8841-d284aa998976
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37110
20413 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_sig_int_fail.3711020413
Directory /workspace/28.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/28.alert_handler_smoke.2659696267
Short name T386
Test name
Test status
Simulation time 3780083274 ps
CPU time 59.3 seconds
Started Jul 10 05:29:06 PM PDT 24
Finished Jul 10 05:30:06 PM PDT 24
Peak memory 257552 kb
Host smart-8ddd9b0e-8172-4e30-9ad0-bad8d269108f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26596
96267 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_smoke.2659696267
Directory /workspace/28.alert_handler_smoke/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all.2433036105
Short name T274
Test name
Test status
Simulation time 40606584169 ps
CPU time 2461.37 seconds
Started Jul 10 05:29:12 PM PDT 24
Finished Jul 10 06:10:15 PM PDT 24
Peak memory 290368 kb
Host smart-0fd75e89-0843-463c-940b-8844a87e7eb8
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433036105 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_ha
ndler_stress_all.2433036105
Directory /workspace/28.alert_handler_stress_all/latest

Test location /workspace/coverage/default/29.alert_handler_entropy.490086002
Short name T584
Test name
Test status
Simulation time 203154339166 ps
CPU time 3076.86 seconds
Started Jul 10 05:29:19 PM PDT 24
Finished Jul 10 06:20:37 PM PDT 24
Peak memory 289496 kb
Host smart-e9d168ec-71ad-40fa-bb14-5b4bcb092d68
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=490086002 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_entropy.490086002
Directory /workspace/29.alert_handler_entropy/latest

Test location /workspace/coverage/default/29.alert_handler_esc_alert_accum.308774869
Short name T440
Test name
Test status
Simulation time 1159922501 ps
CPU time 17.93 seconds
Started Jul 10 05:29:19 PM PDT 24
Finished Jul 10 05:29:37 PM PDT 24
Peak memory 257472 kb
Host smart-496a0fa3-0abe-455c-9712-5fcc0b7f4303
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30877
4869 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_alert_accum.308774869
Directory /workspace/29.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/29.alert_handler_esc_intr_timeout.226538096
Short name T221
Test name
Test status
Simulation time 826147778 ps
CPU time 55.45 seconds
Started Jul 10 05:29:20 PM PDT 24
Finished Jul 10 05:30:17 PM PDT 24
Peak memory 249340 kb
Host smart-e0a38a0b-d69d-4e25-8665-9cf9dcc1aeb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22653
8096 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_intr_timeout.226538096
Directory /workspace/29.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_lpg_stub_clk.2392758212
Short name T659
Test name
Test status
Simulation time 223128077908 ps
CPU time 2867.47 seconds
Started Jul 10 05:29:23 PM PDT 24
Finished Jul 10 06:17:12 PM PDT 24
Peak memory 288604 kb
Host smart-6f8ba54f-d3cf-441e-8662-352f1d33016c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392758212 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg_stub_clk.2392758212
Directory /workspace/29.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/29.alert_handler_ping_timeout.4195440192
Short name T686
Test name
Test status
Simulation time 12459184351 ps
CPU time 520.71 seconds
Started Jul 10 05:29:20 PM PDT 24
Finished Jul 10 05:38:01 PM PDT 24
Peak memory 256024 kb
Host smart-39e99904-660f-436d-868e-c41fd8403e30
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4195440192 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_ping_timeout.4195440192
Directory /workspace/29.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_random_alerts.1442018782
Short name T577
Test name
Test status
Simulation time 779252256 ps
CPU time 19.94 seconds
Started Jul 10 05:29:13 PM PDT 24
Finished Jul 10 05:29:34 PM PDT 24
Peak memory 256736 kb
Host smart-01d25039-0ed3-4c04-a161-6b3f45c04e13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14420
18782 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_alerts.1442018782
Directory /workspace/29.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/29.alert_handler_random_classes.1879843183
Short name T47
Test name
Test status
Simulation time 72375529 ps
CPU time 8.54 seconds
Started Jul 10 05:29:20 PM PDT 24
Finished Jul 10 05:29:29 PM PDT 24
Peak memory 249220 kb
Host smart-078c9293-32ab-4439-b86c-941cd790d3a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18798
43183 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_classes.1879843183
Directory /workspace/29.alert_handler_random_classes/latest

Test location /workspace/coverage/default/29.alert_handler_sig_int_fail.3411857709
Short name T55
Test name
Test status
Simulation time 1018724030 ps
CPU time 16.61 seconds
Started Jul 10 05:29:20 PM PDT 24
Finished Jul 10 05:29:38 PM PDT 24
Peak memory 248740 kb
Host smart-ea1a410e-b999-47e7-bb7d-9fd22297c686
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34118
57709 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_sig_int_fail.3411857709
Directory /workspace/29.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/29.alert_handler_smoke.1227229889
Short name T363
Test name
Test status
Simulation time 794682443 ps
CPU time 11.93 seconds
Started Jul 10 05:29:13 PM PDT 24
Finished Jul 10 05:29:25 PM PDT 24
Peak memory 255424 kb
Host smart-acc39527-a7ad-4d34-9a36-45b218743de3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12272
29889 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_smoke.1227229889
Directory /workspace/29.alert_handler_smoke/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all.312730535
Short name T506
Test name
Test status
Simulation time 72893985604 ps
CPU time 919.4 seconds
Started Jul 10 05:29:24 PM PDT 24
Finished Jul 10 05:44:45 PM PDT 24
Peak memory 265740 kb
Host smart-7fde7d4b-48ea-4dda-b837-c5e53bc4b6fe
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312730535 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_han
dler_stress_all.312730535
Directory /workspace/29.alert_handler_stress_all/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all_with_rand_reset.926397407
Short name T563
Test name
Test status
Simulation time 70810039886 ps
CPU time 3394.2 seconds
Started Jul 10 05:29:24 PM PDT 24
Finished Jul 10 06:26:00 PM PDT 24
Peak memory 336520 kb
Host smart-c3143c77-73cf-4f43-b78c-024cb0c1094a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926397407 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 29.alert_handler_stress_all_with_rand_reset.926397407
Directory /workspace/29.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.alert_handler_alert_accum_saturation.4285575447
Short name T206
Test name
Test status
Simulation time 78099475 ps
CPU time 2.48 seconds
Started Jul 10 05:27:26 PM PDT 24
Finished Jul 10 05:27:31 PM PDT 24
Peak memory 249512 kb
Host smart-84126f06-0114-4a97-9274-4c791d765726
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4285575447 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_alert_accum_saturation.4285575447
Directory /workspace/3.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/3.alert_handler_entropy.670072136
Short name T359
Test name
Test status
Simulation time 153181753120 ps
CPU time 2429.58 seconds
Started Jul 10 05:27:29 PM PDT 24
Finished Jul 10 06:08:01 PM PDT 24
Peak memory 289880 kb
Host smart-4bd725f1-e1d3-4dde-a0f0-ca3ddcad528e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670072136 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy.670072136
Directory /workspace/3.alert_handler_entropy/latest

Test location /workspace/coverage/default/3.alert_handler_entropy_stress.2625494354
Short name T8
Test name
Test status
Simulation time 874491655 ps
CPU time 37.85 seconds
Started Jul 10 05:27:26 PM PDT 24
Finished Jul 10 05:28:07 PM PDT 24
Peak memory 249292 kb
Host smart-f451e00c-92e6-4ce3-99ca-cc81c3fc0ab4
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2625494354 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy_stress.2625494354
Directory /workspace/3.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/3.alert_handler_esc_alert_accum.3761576781
Short name T467
Test name
Test status
Simulation time 8818938451 ps
CPU time 158.83 seconds
Started Jul 10 05:27:28 PM PDT 24
Finished Jul 10 05:30:09 PM PDT 24
Peak memory 256908 kb
Host smart-5ca33af6-2ca4-4c90-b6b6-61c55848bbee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37615
76781 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_alert_accum.3761576781
Directory /workspace/3.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/3.alert_handler_esc_intr_timeout.352279948
Short name T105
Test name
Test status
Simulation time 312306425 ps
CPU time 5.22 seconds
Started Jul 10 05:27:27 PM PDT 24
Finished Jul 10 05:27:35 PM PDT 24
Peak memory 240656 kb
Host smart-a7c3cc34-8c5d-4315-a261-eeeccf239cff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35227
9948 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_intr_timeout.352279948
Directory /workspace/3.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_lpg.1079683563
Short name T514
Test name
Test status
Simulation time 27193957285 ps
CPU time 994.48 seconds
Started Jul 10 05:27:25 PM PDT 24
Finished Jul 10 05:44:02 PM PDT 24
Peak memory 273908 kb
Host smart-8c84ac42-7879-40aa-9cd8-1a638e809795
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079683563 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg.1079683563
Directory /workspace/3.alert_handler_lpg/latest

Test location /workspace/coverage/default/3.alert_handler_lpg_stub_clk.87685889
Short name T281
Test name
Test status
Simulation time 169973682016 ps
CPU time 2727.76 seconds
Started Jul 10 05:27:27 PM PDT 24
Finished Jul 10 06:12:58 PM PDT 24
Peak memory 290360 kb
Host smart-58e4b354-5255-43e3-a93f-26de70a8393a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87685889 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg_stub_clk.87685889
Directory /workspace/3.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/3.alert_handler_ping_timeout.2164247861
Short name T307
Test name
Test status
Simulation time 33135418045 ps
CPU time 370.03 seconds
Started Jul 10 05:27:25 PM PDT 24
Finished Jul 10 05:33:37 PM PDT 24
Peak memory 256044 kb
Host smart-2e2eab52-116e-46c5-8350-e13ff6e64178
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164247861 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_ping_timeout.2164247861
Directory /workspace/3.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_random_alerts.581576365
Short name T419
Test name
Test status
Simulation time 125411652 ps
CPU time 8.68 seconds
Started Jul 10 05:27:27 PM PDT 24
Finished Jul 10 05:27:39 PM PDT 24
Peak memory 249212 kb
Host smart-695459cd-199f-455e-8bfd-1692f5006b19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58157
6365 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_alerts.581576365
Directory /workspace/3.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/3.alert_handler_sec_cm.1295599058
Short name T12
Test name
Test status
Simulation time 718326792 ps
CPU time 12.55 seconds
Started Jul 10 05:27:27 PM PDT 24
Finished Jul 10 05:27:42 PM PDT 24
Peak memory 278016 kb
Host smart-4b29ffa0-286a-4b44-93eb-a9bb208707ab
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1295599058 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sec_cm.1295599058
Directory /workspace/3.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/3.alert_handler_sig_int_fail.1057182739
Short name T387
Test name
Test status
Simulation time 518901447 ps
CPU time 31.1 seconds
Started Jul 10 05:27:24 PM PDT 24
Finished Jul 10 05:27:58 PM PDT 24
Peak memory 257428 kb
Host smart-a1e225d0-77ab-4ccd-bf58-97507338e488
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10571
82739 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sig_int_fail.1057182739
Directory /workspace/3.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/3.alert_handler_smoke.2086675247
Short name T348
Test name
Test status
Simulation time 4445682913 ps
CPU time 62.2 seconds
Started Jul 10 05:27:28 PM PDT 24
Finished Jul 10 05:28:32 PM PDT 24
Peak memory 257408 kb
Host smart-af700849-88d3-4cb7-9bf2-8ab5245cd7be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20866
75247 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_smoke.2086675247
Directory /workspace/3.alert_handler_smoke/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all.2574997825
Short name T555
Test name
Test status
Simulation time 549001371548 ps
CPU time 2907.25 seconds
Started Jul 10 05:27:27 PM PDT 24
Finished Jul 10 06:15:57 PM PDT 24
Peak memory 290144 kb
Host smart-e7c9d0b9-d0a1-4588-9d07-99ec68b7e87e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574997825 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_han
dler_stress_all.2574997825
Directory /workspace/3.alert_handler_stress_all/latest

Test location /workspace/coverage/default/30.alert_handler_entropy.2686782157
Short name T85
Test name
Test status
Simulation time 23088292481 ps
CPU time 1473.67 seconds
Started Jul 10 05:29:32 PM PDT 24
Finished Jul 10 05:54:06 PM PDT 24
Peak memory 290020 kb
Host smart-f92c473e-b38d-48d8-b84b-6f6bcefb9969
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2686782157 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_entropy.2686782157
Directory /workspace/30.alert_handler_entropy/latest

Test location /workspace/coverage/default/30.alert_handler_esc_alert_accum.410003363
Short name T414
Test name
Test status
Simulation time 1640049454 ps
CPU time 113.93 seconds
Started Jul 10 05:29:26 PM PDT 24
Finished Jul 10 05:31:20 PM PDT 24
Peak memory 257468 kb
Host smart-e02ced79-5665-46ff-bdf5-c20d17d67933
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41000
3363 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_alert_accum.410003363
Directory /workspace/30.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/30.alert_handler_esc_intr_timeout.358109996
Short name T217
Test name
Test status
Simulation time 1040479219 ps
CPU time 29.63 seconds
Started Jul 10 05:29:25 PM PDT 24
Finished Jul 10 05:29:55 PM PDT 24
Peak memory 249244 kb
Host smart-346c8fdb-0c37-4a2b-9c5f-14f7bdc296bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35810
9996 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_intr_timeout.358109996
Directory /workspace/30.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_lpg.2542866970
Short name T508
Test name
Test status
Simulation time 79706965328 ps
CPU time 689.65 seconds
Started Jul 10 05:29:30 PM PDT 24
Finished Jul 10 05:41:00 PM PDT 24
Peak memory 273856 kb
Host smart-be9149c4-db22-4236-baf5-a797ea99cbc4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542866970 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg.2542866970
Directory /workspace/30.alert_handler_lpg/latest

Test location /workspace/coverage/default/30.alert_handler_lpg_stub_clk.715770965
Short name T379
Test name
Test status
Simulation time 11004581038 ps
CPU time 888.38 seconds
Started Jul 10 05:29:41 PM PDT 24
Finished Jul 10 05:44:31 PM PDT 24
Peak memory 273448 kb
Host smart-623127df-d9be-46cd-94e7-52cf5fdd3d0e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715770965 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg_stub_clk.715770965
Directory /workspace/30.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/30.alert_handler_ping_timeout.71649417
Short name T277
Test name
Test status
Simulation time 75125190931 ps
CPU time 255.4 seconds
Started Jul 10 05:29:28 PM PDT 24
Finished Jul 10 05:33:45 PM PDT 24
Peak memory 249404 kb
Host smart-ac7ab1a3-0905-475f-ad27-0f910ed21a32
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71649417 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_ping_timeout.71649417
Directory /workspace/30.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_random_alerts.1064623508
Short name T352
Test name
Test status
Simulation time 96309351 ps
CPU time 5.51 seconds
Started Jul 10 05:29:24 PM PDT 24
Finished Jul 10 05:29:31 PM PDT 24
Peak memory 249264 kb
Host smart-a083ecc7-b861-4b7a-a333-0afd04a43854
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10646
23508 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_alerts.1064623508
Directory /workspace/30.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/30.alert_handler_random_classes.2871447805
Short name T403
Test name
Test status
Simulation time 672268580 ps
CPU time 13.21 seconds
Started Jul 10 05:29:23 PM PDT 24
Finished Jul 10 05:29:37 PM PDT 24
Peak memory 248600 kb
Host smart-e997e9f4-84df-4478-8be6-939756b9f4fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28714
47805 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_classes.2871447805
Directory /workspace/30.alert_handler_random_classes/latest

Test location /workspace/coverage/default/30.alert_handler_sig_int_fail.3204129716
Short name T550
Test name
Test status
Simulation time 353810278 ps
CPU time 12.55 seconds
Started Jul 10 05:29:30 PM PDT 24
Finished Jul 10 05:29:43 PM PDT 24
Peak memory 248700 kb
Host smart-f36ef0b0-0b82-4b4b-88b4-eee6d75d82ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32041
29716 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_sig_int_fail.3204129716
Directory /workspace/30.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/30.alert_handler_smoke.1447035267
Short name T644
Test name
Test status
Simulation time 3073790342 ps
CPU time 52.43 seconds
Started Jul 10 05:29:24 PM PDT 24
Finished Jul 10 05:30:17 PM PDT 24
Peak memory 256508 kb
Host smart-aee1c6c6-0249-4246-891c-7fde4263a258
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14470
35267 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_smoke.1447035267
Directory /workspace/30.alert_handler_smoke/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all.1531270926
Short name T71
Test name
Test status
Simulation time 129792280475 ps
CPU time 2069.05 seconds
Started Jul 10 05:29:39 PM PDT 24
Finished Jul 10 06:04:09 PM PDT 24
Peak memory 282180 kb
Host smart-01d05206-6461-4356-9792-b7e1bad6ff78
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531270926 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_ha
ndler_stress_all.1531270926
Directory /workspace/30.alert_handler_stress_all/latest

Test location /workspace/coverage/default/31.alert_handler_entropy.2328794161
Short name T448
Test name
Test status
Simulation time 15961360150 ps
CPU time 1574.45 seconds
Started Jul 10 05:29:43 PM PDT 24
Finished Jul 10 05:55:58 PM PDT 24
Peak memory 290068 kb
Host smart-36a05998-ebb3-40a1-9cc3-cf264bd17337
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328794161 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_entropy.2328794161
Directory /workspace/31.alert_handler_entropy/latest

Test location /workspace/coverage/default/31.alert_handler_esc_alert_accum.1625287474
Short name T582
Test name
Test status
Simulation time 7371843104 ps
CPU time 262.66 seconds
Started Jul 10 05:29:41 PM PDT 24
Finished Jul 10 05:34:04 PM PDT 24
Peak memory 257568 kb
Host smart-aa077495-84ae-477b-a293-71cc279619d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16252
87474 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_alert_accum.1625287474
Directory /workspace/31.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/31.alert_handler_esc_intr_timeout.4203499263
Short name T462
Test name
Test status
Simulation time 5594146783 ps
CPU time 23.13 seconds
Started Jul 10 05:29:37 PM PDT 24
Finished Jul 10 05:30:01 PM PDT 24
Peak memory 256560 kb
Host smart-177fc436-3958-4764-b8e0-2994ba00eb87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42034
99263 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_intr_timeout.4203499263
Directory /workspace/31.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_lpg.3873970514
Short name T564
Test name
Test status
Simulation time 24451413081 ps
CPU time 1137.25 seconds
Started Jul 10 05:29:43 PM PDT 24
Finished Jul 10 05:48:41 PM PDT 24
Peak memory 274020 kb
Host smart-ff4edbb9-99ec-47e2-b1e5-25017fa520fc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873970514 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg.3873970514
Directory /workspace/31.alert_handler_lpg/latest

Test location /workspace/coverage/default/31.alert_handler_lpg_stub_clk.3841547898
Short name T537
Test name
Test status
Simulation time 17418749070 ps
CPU time 1051.88 seconds
Started Jul 10 05:29:42 PM PDT 24
Finished Jul 10 05:47:15 PM PDT 24
Peak memory 272680 kb
Host smart-9c0db1dc-431e-4892-960b-6c4e895e10e0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841547898 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg_stub_clk.3841547898
Directory /workspace/31.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/31.alert_handler_ping_timeout.1383080563
Short name T41
Test name
Test status
Simulation time 46440093310 ps
CPU time 533.92 seconds
Started Jul 10 05:29:43 PM PDT 24
Finished Jul 10 05:38:37 PM PDT 24
Peak memory 249372 kb
Host smart-812dd11d-35cf-4b75-9b5e-044cf3750768
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1383080563 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_ping_timeout.1383080563
Directory /workspace/31.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_random_alerts.1357033218
Short name T388
Test name
Test status
Simulation time 343977406 ps
CPU time 21.93 seconds
Started Jul 10 05:29:37 PM PDT 24
Finished Jul 10 05:29:59 PM PDT 24
Peak memory 249256 kb
Host smart-e0c54355-a3ea-4732-ab6f-90a7acfa6208
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13570
33218 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_alerts.1357033218
Directory /workspace/31.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/31.alert_handler_random_classes.707678183
Short name T694
Test name
Test status
Simulation time 1052144517 ps
CPU time 25.85 seconds
Started Jul 10 05:29:36 PM PDT 24
Finished Jul 10 05:30:03 PM PDT 24
Peak memory 257008 kb
Host smart-e6ef0a40-f03e-493e-962b-1d848cd3d6ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70767
8183 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_classes.707678183
Directory /workspace/31.alert_handler_random_classes/latest

Test location /workspace/coverage/default/31.alert_handler_sig_int_fail.829803953
Short name T531
Test name
Test status
Simulation time 722067909 ps
CPU time 53.7 seconds
Started Jul 10 05:29:42 PM PDT 24
Finished Jul 10 05:30:36 PM PDT 24
Peak memory 249256 kb
Host smart-e6314a49-696d-46cc-bbee-4a4478319ac8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82980
3953 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_sig_int_fail.829803953
Directory /workspace/31.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/31.alert_handler_smoke.3556676257
Short name T634
Test name
Test status
Simulation time 359614637 ps
CPU time 32.67 seconds
Started Jul 10 05:29:38 PM PDT 24
Finished Jul 10 05:30:11 PM PDT 24
Peak memory 249632 kb
Host smart-a7116021-e2a3-471a-b95a-21df05a4916f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35566
76257 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_smoke.3556676257
Directory /workspace/31.alert_handler_smoke/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all.3059075464
Short name T630
Test name
Test status
Simulation time 120662817531 ps
CPU time 1864.66 seconds
Started Jul 10 05:29:41 PM PDT 24
Finished Jul 10 06:00:47 PM PDT 24
Peak memory 286328 kb
Host smart-d8d99203-1be5-4cc3-8271-556389442302
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059075464 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_ha
ndler_stress_all.3059075464
Directory /workspace/31.alert_handler_stress_all/latest

Test location /workspace/coverage/default/32.alert_handler_entropy.771932226
Short name T621
Test name
Test status
Simulation time 34624043568 ps
CPU time 2085.07 seconds
Started Jul 10 05:29:47 PM PDT 24
Finished Jul 10 06:04:32 PM PDT 24
Peak memory 273956 kb
Host smart-e23c902c-5f80-4114-a3da-2b1039d5fa38
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771932226 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_entropy.771932226
Directory /workspace/32.alert_handler_entropy/latest

Test location /workspace/coverage/default/32.alert_handler_esc_alert_accum.3289869919
Short name T436
Test name
Test status
Simulation time 10080549563 ps
CPU time 202.4 seconds
Started Jul 10 05:29:50 PM PDT 24
Finished Jul 10 05:33:13 PM PDT 24
Peak memory 256832 kb
Host smart-5a4c81cf-a9fe-4426-b064-82fe2308021b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32898
69919 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_alert_accum.3289869919
Directory /workspace/32.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/32.alert_handler_esc_intr_timeout.511162437
Short name T598
Test name
Test status
Simulation time 1447496423 ps
CPU time 46.42 seconds
Started Jul 10 05:29:50 PM PDT 24
Finished Jul 10 05:30:37 PM PDT 24
Peak memory 249224 kb
Host smart-f3d4f0ba-f626-4540-834b-7bf4e5216364
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51116
2437 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_intr_timeout.511162437
Directory /workspace/32.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_lpg.840571376
Short name T275
Test name
Test status
Simulation time 9744340894 ps
CPU time 744.39 seconds
Started Jul 10 05:29:48 PM PDT 24
Finished Jul 10 05:42:13 PM PDT 24
Peak memory 273940 kb
Host smart-3c2c0c57-8843-469d-8098-ce0ba31bcc1e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840571376 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg.840571376
Directory /workspace/32.alert_handler_lpg/latest

Test location /workspace/coverage/default/32.alert_handler_lpg_stub_clk.2986176420
Short name T93
Test name
Test status
Simulation time 20284439106 ps
CPU time 1211.31 seconds
Started Jul 10 05:29:55 PM PDT 24
Finished Jul 10 05:50:07 PM PDT 24
Peak memory 273972 kb
Host smart-fada766f-4548-401d-975a-130de52c32f0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986176420 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg_stub_clk.2986176420
Directory /workspace/32.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/32.alert_handler_ping_timeout.418720478
Short name T317
Test name
Test status
Simulation time 11063606156 ps
CPU time 447.59 seconds
Started Jul 10 05:29:48 PM PDT 24
Finished Jul 10 05:37:16 PM PDT 24
Peak memory 256144 kb
Host smart-37e6e1ae-d8df-4842-b845-34a643b2726c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418720478 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_ping_timeout.418720478
Directory /workspace/32.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_random_alerts.1238973311
Short name T292
Test name
Test status
Simulation time 163914949 ps
CPU time 8.61 seconds
Started Jul 10 05:29:47 PM PDT 24
Finished Jul 10 05:29:57 PM PDT 24
Peak memory 249208 kb
Host smart-0007df67-f3fa-4a2a-b7d8-585b5d9e504e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12389
73311 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_alerts.1238973311
Directory /workspace/32.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/32.alert_handler_random_classes.3185445200
Short name T370
Test name
Test status
Simulation time 1000709146 ps
CPU time 27.87 seconds
Started Jul 10 05:29:48 PM PDT 24
Finished Jul 10 05:30:16 PM PDT 24
Peak memory 256968 kb
Host smart-c8f11b23-08d1-45ff-9e6c-f82bb3b71d04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31854
45200 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_classes.3185445200
Directory /workspace/32.alert_handler_random_classes/latest

Test location /workspace/coverage/default/32.alert_handler_sig_int_fail.946895772
Short name T264
Test name
Test status
Simulation time 7048316536 ps
CPU time 22.65 seconds
Started Jul 10 05:29:47 PM PDT 24
Finished Jul 10 05:30:10 PM PDT 24
Peak memory 249348 kb
Host smart-07ee656e-e9c9-4053-8310-913fbfe38a79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94689
5772 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_sig_int_fail.946895772
Directory /workspace/32.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/32.alert_handler_smoke.1182176824
Short name T573
Test name
Test status
Simulation time 337604887 ps
CPU time 20.35 seconds
Started Jul 10 05:29:41 PM PDT 24
Finished Jul 10 05:30:02 PM PDT 24
Peak memory 256612 kb
Host smart-75911dbf-0da5-4700-b5a0-c88bdad05a46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11821
76824 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_smoke.1182176824
Directory /workspace/32.alert_handler_smoke/latest

Test location /workspace/coverage/default/33.alert_handler_entropy.3848823397
Short name T653
Test name
Test status
Simulation time 68256388341 ps
CPU time 2017.26 seconds
Started Jul 10 05:30:00 PM PDT 24
Finished Jul 10 06:03:38 PM PDT 24
Peak memory 290092 kb
Host smart-f6a6ce47-d1de-4a3d-a054-0ef45499b362
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848823397 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_entropy.3848823397
Directory /workspace/33.alert_handler_entropy/latest

Test location /workspace/coverage/default/33.alert_handler_esc_alert_accum.356101863
Short name T590
Test name
Test status
Simulation time 3943989135 ps
CPU time 245.26 seconds
Started Jul 10 05:29:59 PM PDT 24
Finished Jul 10 05:34:05 PM PDT 24
Peak memory 257080 kb
Host smart-d80a5385-5376-4761-a298-f2ac7ee25277
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35610
1863 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_alert_accum.356101863
Directory /workspace/33.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/33.alert_handler_esc_intr_timeout.3319072507
Short name T68
Test name
Test status
Simulation time 4279356759 ps
CPU time 54.84 seconds
Started Jul 10 05:29:59 PM PDT 24
Finished Jul 10 05:30:55 PM PDT 24
Peak memory 257572 kb
Host smart-783b1955-030b-4bf8-b940-302d6569c13d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33190
72507 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_intr_timeout.3319072507
Directory /workspace/33.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_lpg.1733139668
Short name T334
Test name
Test status
Simulation time 18340144977 ps
CPU time 1097.52 seconds
Started Jul 10 05:30:02 PM PDT 24
Finished Jul 10 05:48:21 PM PDT 24
Peak memory 273288 kb
Host smart-3ce1acbc-2ad7-4090-a5f8-65a2e776887f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733139668 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg.1733139668
Directory /workspace/33.alert_handler_lpg/latest

Test location /workspace/coverage/default/33.alert_handler_lpg_stub_clk.4258577920
Short name T504
Test name
Test status
Simulation time 63537650471 ps
CPU time 1596.58 seconds
Started Jul 10 05:30:02 PM PDT 24
Finished Jul 10 05:56:39 PM PDT 24
Peak memory 290148 kb
Host smart-68868b94-8eaf-48eb-b070-9dab6ab8b069
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258577920 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg_stub_clk.4258577920
Directory /workspace/33.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/33.alert_handler_ping_timeout.560242929
Short name T14
Test name
Test status
Simulation time 9855399106 ps
CPU time 397.9 seconds
Started Jul 10 05:30:00 PM PDT 24
Finished Jul 10 05:36:39 PM PDT 24
Peak memory 255748 kb
Host smart-25b233fc-9676-4393-be53-e10f6a7cb552
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560242929 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_ping_timeout.560242929
Directory /workspace/33.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_random_alerts.1591479539
Short name T439
Test name
Test status
Simulation time 1061451598 ps
CPU time 40.27 seconds
Started Jul 10 05:29:55 PM PDT 24
Finished Jul 10 05:30:35 PM PDT 24
Peak memory 256788 kb
Host smart-ccbcf3ca-8e2e-4277-b84d-b8a9f61c786e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15914
79539 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_alerts.1591479539
Directory /workspace/33.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/33.alert_handler_random_classes.201629875
Short name T90
Test name
Test status
Simulation time 95324424 ps
CPU time 14.93 seconds
Started Jul 10 05:29:54 PM PDT 24
Finished Jul 10 05:30:09 PM PDT 24
Peak memory 248524 kb
Host smart-537b8597-021c-4995-b8f3-6dc7db7a17d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20162
9875 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_classes.201629875
Directory /workspace/33.alert_handler_random_classes/latest

Test location /workspace/coverage/default/33.alert_handler_smoke.1860122903
Short name T385
Test name
Test status
Simulation time 847810166 ps
CPU time 54.88 seconds
Started Jul 10 05:29:55 PM PDT 24
Finished Jul 10 05:30:50 PM PDT 24
Peak memory 249228 kb
Host smart-eac69c20-23d3-427e-8100-d38dc5ebe482
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18601
22903 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_smoke.1860122903
Directory /workspace/33.alert_handler_smoke/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all_with_rand_reset.1282785820
Short name T486
Test name
Test status
Simulation time 45922752089 ps
CPU time 4794.17 seconds
Started Jul 10 05:30:07 PM PDT 24
Finished Jul 10 06:50:02 PM PDT 24
Peak memory 339484 kb
Host smart-48495037-d128-4d91-9dea-d30f17c9ace1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282785820 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 33.alert_handler_stress_all_with_rand_reset.1282785820
Directory /workspace/33.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.alert_handler_entropy.3019169398
Short name T600
Test name
Test status
Simulation time 16910240916 ps
CPU time 1084.62 seconds
Started Jul 10 05:30:08 PM PDT 24
Finished Jul 10 05:48:13 PM PDT 24
Peak memory 265708 kb
Host smart-9751a006-3bc7-45ab-ac72-95931b9b8a2b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3019169398 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_entropy.3019169398
Directory /workspace/34.alert_handler_entropy/latest

Test location /workspace/coverage/default/34.alert_handler_esc_alert_accum.2611741330
Short name T177
Test name
Test status
Simulation time 3758087767 ps
CPU time 163.52 seconds
Started Jul 10 05:30:05 PM PDT 24
Finished Jul 10 05:32:49 PM PDT 24
Peak memory 257596 kb
Host smart-452af924-5b5d-4756-a067-8774f7bb3477
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26117
41330 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_alert_accum.2611741330
Directory /workspace/34.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/34.alert_handler_esc_intr_timeout.2577916935
Short name T405
Test name
Test status
Simulation time 1660593599 ps
CPU time 74.4 seconds
Started Jul 10 05:30:06 PM PDT 24
Finished Jul 10 05:31:21 PM PDT 24
Peak memory 257012 kb
Host smart-a7d73e2c-4ce8-413c-a51c-4cecd03bc261
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25779
16935 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_intr_timeout.2577916935
Directory /workspace/34.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_lpg.3890554127
Short name T654
Test name
Test status
Simulation time 97535532625 ps
CPU time 1364.49 seconds
Started Jul 10 05:30:06 PM PDT 24
Finished Jul 10 05:52:52 PM PDT 24
Peak memory 273848 kb
Host smart-4d02e5a6-548a-43a6-9bce-70afb72b1e19
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3890554127 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg.3890554127
Directory /workspace/34.alert_handler_lpg/latest

Test location /workspace/coverage/default/34.alert_handler_lpg_stub_clk.3092309946
Short name T490
Test name
Test status
Simulation time 14726851594 ps
CPU time 1253.32 seconds
Started Jul 10 05:30:09 PM PDT 24
Finished Jul 10 05:51:03 PM PDT 24
Peak memory 288744 kb
Host smart-a148defa-d4a1-40a3-a7c0-c12256fd4e19
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092309946 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg_stub_clk.3092309946
Directory /workspace/34.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/34.alert_handler_ping_timeout.3370671144
Short name T569
Test name
Test status
Simulation time 5881458821 ps
CPU time 247.57 seconds
Started Jul 10 05:30:06 PM PDT 24
Finished Jul 10 05:34:14 PM PDT 24
Peak memory 249352 kb
Host smart-1f41fe4c-4e6c-4fa9-9778-1d3cc75e8ce6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3370671144 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_ping_timeout.3370671144
Directory /workspace/34.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_random_alerts.3509807359
Short name T381
Test name
Test status
Simulation time 6899180974 ps
CPU time 74.95 seconds
Started Jul 10 05:30:07 PM PDT 24
Finished Jul 10 05:31:22 PM PDT 24
Peak memory 257308 kb
Host smart-5af6a0d4-927b-4c3d-b0ce-06d93f567047
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35098
07359 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_alerts.3509807359
Directory /workspace/34.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/34.alert_handler_random_classes.1272772625
Short name T60
Test name
Test status
Simulation time 3129540186 ps
CPU time 75.35 seconds
Started Jul 10 05:30:08 PM PDT 24
Finished Jul 10 05:31:24 PM PDT 24
Peak memory 250448 kb
Host smart-bf192a9f-6dc7-47ae-ad8c-97176f187494
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12727
72625 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_classes.1272772625
Directory /workspace/34.alert_handler_random_classes/latest

Test location /workspace/coverage/default/34.alert_handler_sig_int_fail.81453957
Short name T72
Test name
Test status
Simulation time 585100179 ps
CPU time 21.35 seconds
Started Jul 10 05:30:07 PM PDT 24
Finished Jul 10 05:30:29 PM PDT 24
Peak memory 249268 kb
Host smart-596c0cd9-a0e0-4247-b14d-d4f19f9d0b8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81453
957 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_sig_int_fail.81453957
Directory /workspace/34.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/34.alert_handler_smoke.1147146643
Short name T384
Test name
Test status
Simulation time 19805996 ps
CPU time 3.54 seconds
Started Jul 10 05:30:05 PM PDT 24
Finished Jul 10 05:30:09 PM PDT 24
Peak memory 251624 kb
Host smart-bfe64668-30d9-49b9-b1ee-09e93d9c6abe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11471
46643 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_smoke.1147146643
Directory /workspace/34.alert_handler_smoke/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all.251658289
Short name T344
Test name
Test status
Simulation time 348488789 ps
CPU time 21.39 seconds
Started Jul 10 05:30:13 PM PDT 24
Finished Jul 10 05:30:35 PM PDT 24
Peak memory 256136 kb
Host smart-e3b9c32b-535f-4c54-8ba2-3169b8d6a666
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251658289 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_han
dler_stress_all.251658289
Directory /workspace/34.alert_handler_stress_all/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all_with_rand_reset.3980752752
Short name T233
Test name
Test status
Simulation time 21706503457 ps
CPU time 1372.92 seconds
Started Jul 10 05:30:13 PM PDT 24
Finished Jul 10 05:53:07 PM PDT 24
Peak memory 290328 kb
Host smart-8b7e8231-9a1b-4050-8b2e-a658a35a8ede
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980752752 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.alert_handler_stress_all_with_rand_reset.3980752752
Directory /workspace/34.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.alert_handler_esc_alert_accum.1543851474
Short name T367
Test name
Test status
Simulation time 5341882964 ps
CPU time 133.57 seconds
Started Jul 10 05:30:12 PM PDT 24
Finished Jul 10 05:32:26 PM PDT 24
Peak memory 257104 kb
Host smart-70299db2-eb8a-4e96-b9b1-8ec7b451bc39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15438
51474 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_alert_accum.1543851474
Directory /workspace/35.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/35.alert_handler_esc_intr_timeout.2928664644
Short name T416
Test name
Test status
Simulation time 536520698 ps
CPU time 10.34 seconds
Started Jul 10 05:30:13 PM PDT 24
Finished Jul 10 05:30:24 PM PDT 24
Peak memory 249732 kb
Host smart-eecd6302-0fc5-44ee-9141-85e090364963
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29286
64644 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_intr_timeout.2928664644
Directory /workspace/35.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_lpg.2537824518
Short name T42
Test name
Test status
Simulation time 102834257376 ps
CPU time 1007.95 seconds
Started Jul 10 05:30:20 PM PDT 24
Finished Jul 10 05:47:09 PM PDT 24
Peak memory 273904 kb
Host smart-0f9901f1-5e0e-4541-8ae4-de450ac9bd0d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537824518 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg.2537824518
Directory /workspace/35.alert_handler_lpg/latest

Test location /workspace/coverage/default/35.alert_handler_lpg_stub_clk.2022479161
Short name T296
Test name
Test status
Simulation time 53095508360 ps
CPU time 1023.45 seconds
Started Jul 10 05:30:20 PM PDT 24
Finished Jul 10 05:47:25 PM PDT 24
Peak memory 282644 kb
Host smart-2abd8460-c51e-4f77-b7c4-f97c5baabe41
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022479161 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg_stub_clk.2022479161
Directory /workspace/35.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/35.alert_handler_ping_timeout.1292291965
Short name T701
Test name
Test status
Simulation time 11995477685 ps
CPU time 498.88 seconds
Started Jul 10 05:30:22 PM PDT 24
Finished Jul 10 05:38:42 PM PDT 24
Peak memory 256924 kb
Host smart-efc76993-8678-4dce-8598-def0d7d9ade6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292291965 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_ping_timeout.1292291965
Directory /workspace/35.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_random_alerts.3850313437
Short name T478
Test name
Test status
Simulation time 373140438 ps
CPU time 39.78 seconds
Started Jul 10 05:30:14 PM PDT 24
Finished Jul 10 05:30:54 PM PDT 24
Peak memory 257396 kb
Host smart-9f64942e-fb11-4b8e-9595-63b930567e78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38503
13437 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_alerts.3850313437
Directory /workspace/35.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/35.alert_handler_random_classes.3459569885
Short name T543
Test name
Test status
Simulation time 360798555 ps
CPU time 19.31 seconds
Started Jul 10 05:30:12 PM PDT 24
Finished Jul 10 05:30:32 PM PDT 24
Peak memory 248620 kb
Host smart-2a531f84-ae88-4c9c-a7f6-7dfbd18e0ec3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34595
69885 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_classes.3459569885
Directory /workspace/35.alert_handler_random_classes/latest

Test location /workspace/coverage/default/35.alert_handler_sig_int_fail.2456398259
Short name T51
Test name
Test status
Simulation time 1220065714 ps
CPU time 42.17 seconds
Started Jul 10 05:30:20 PM PDT 24
Finished Jul 10 05:31:03 PM PDT 24
Peak memory 249248 kb
Host smart-c442fc28-3172-4413-9be3-62edfe6550a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24563
98259 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_sig_int_fail.2456398259
Directory /workspace/35.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/35.alert_handler_smoke.2884717871
Short name T546
Test name
Test status
Simulation time 1258953733 ps
CPU time 25.02 seconds
Started Jul 10 05:30:13 PM PDT 24
Finished Jul 10 05:30:38 PM PDT 24
Peak memory 255808 kb
Host smart-c52b4791-ef5b-4889-ad57-5365b5482066
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28847
17871 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_smoke.2884717871
Directory /workspace/35.alert_handler_smoke/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all.3763678821
Short name T662
Test name
Test status
Simulation time 35685169189 ps
CPU time 994.49 seconds
Started Jul 10 05:30:21 PM PDT 24
Finished Jul 10 05:46:56 PM PDT 24
Peak memory 283972 kb
Host smart-fbf5c9e2-3432-4f86-83af-93ff5f705e18
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763678821 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_ha
ndler_stress_all.3763678821
Directory /workspace/35.alert_handler_stress_all/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all_with_rand_reset.1627836431
Short name T100
Test name
Test status
Simulation time 316751391490 ps
CPU time 5147.84 seconds
Started Jul 10 05:30:19 PM PDT 24
Finished Jul 10 06:56:08 PM PDT 24
Peak memory 371308 kb
Host smart-6d6b54c6-afa4-4ee6-b3a0-317ea57b0d89
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627836431 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 35.alert_handler_stress_all_with_rand_reset.1627836431
Directory /workspace/35.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.alert_handler_entropy.893739290
Short name T49
Test name
Test status
Simulation time 185478189918 ps
CPU time 2703.46 seconds
Started Jul 10 05:30:26 PM PDT 24
Finished Jul 10 06:15:30 PM PDT 24
Peak memory 289688 kb
Host smart-60bf7495-91f7-45fb-850b-e91a7f6662d3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=893739290 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_entropy.893739290
Directory /workspace/36.alert_handler_entropy/latest

Test location /workspace/coverage/default/36.alert_handler_esc_alert_accum.3860971703
Short name T711
Test name
Test status
Simulation time 7193111284 ps
CPU time 85.94 seconds
Started Jul 10 05:30:20 PM PDT 24
Finished Jul 10 05:31:47 PM PDT 24
Peak memory 257576 kb
Host smart-ce752fcb-71ef-41ca-9c7d-974adad5926a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38609
71703 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_alert_accum.3860971703
Directory /workspace/36.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/36.alert_handler_esc_intr_timeout.2842533278
Short name T371
Test name
Test status
Simulation time 4419239038 ps
CPU time 31.78 seconds
Started Jul 10 05:30:20 PM PDT 24
Finished Jul 10 05:30:52 PM PDT 24
Peak memory 257356 kb
Host smart-66ff7d1c-3c30-43fd-b410-a11e585543af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28425
33278 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_intr_timeout.2842533278
Directory /workspace/36.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_lpg.996366838
Short name T327
Test name
Test status
Simulation time 27716582277 ps
CPU time 1782.19 seconds
Started Jul 10 05:30:36 PM PDT 24
Finished Jul 10 06:00:19 PM PDT 24
Peak memory 290116 kb
Host smart-df59f12d-2f50-4566-a373-0fc370cf9a1e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996366838 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg.996366838
Directory /workspace/36.alert_handler_lpg/latest

Test location /workspace/coverage/default/36.alert_handler_lpg_stub_clk.2480323452
Short name T406
Test name
Test status
Simulation time 77187771521 ps
CPU time 2378.28 seconds
Started Jul 10 05:30:27 PM PDT 24
Finished Jul 10 06:10:06 PM PDT 24
Peak memory 282100 kb
Host smart-a4b8f772-f59f-4985-aa2d-275d23101cbe
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480323452 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg_stub_clk.2480323452
Directory /workspace/36.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/36.alert_handler_ping_timeout.3351529084
Short name T591
Test name
Test status
Simulation time 4927161323 ps
CPU time 195.35 seconds
Started Jul 10 05:30:26 PM PDT 24
Finished Jul 10 05:33:42 PM PDT 24
Peak memory 249304 kb
Host smart-ef324241-ae56-413d-ab8f-42c921d6e0ba
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351529084 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_ping_timeout.3351529084
Directory /workspace/36.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_random_alerts.2078458846
Short name T392
Test name
Test status
Simulation time 96597076 ps
CPU time 6.68 seconds
Started Jul 10 05:30:22 PM PDT 24
Finished Jul 10 05:30:29 PM PDT 24
Peak memory 251400 kb
Host smart-c3890242-dc83-4de8-9c37-1ed6a10193e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20784
58846 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_alerts.2078458846
Directory /workspace/36.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/36.alert_handler_random_classes.2003974768
Short name T464
Test name
Test status
Simulation time 591593576 ps
CPU time 35.57 seconds
Started Jul 10 05:30:21 PM PDT 24
Finished Jul 10 05:30:57 PM PDT 24
Peak memory 256640 kb
Host smart-c06f053e-428b-45a3-9c10-c82d0e237413
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20039
74768 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_classes.2003974768
Directory /workspace/36.alert_handler_random_classes/latest

Test location /workspace/coverage/default/36.alert_handler_sig_int_fail.1346560791
Short name T266
Test name
Test status
Simulation time 599475102 ps
CPU time 23.14 seconds
Started Jul 10 05:30:28 PM PDT 24
Finished Jul 10 05:30:52 PM PDT 24
Peak memory 248808 kb
Host smart-5ad8caa6-84fe-419a-9b01-9572876eb738
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13465
60791 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_sig_int_fail.1346560791
Directory /workspace/36.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/36.alert_handler_smoke.1756353230
Short name T34
Test name
Test status
Simulation time 82993216 ps
CPU time 8.84 seconds
Started Jul 10 05:30:20 PM PDT 24
Finished Jul 10 05:30:30 PM PDT 24
Peak memory 255232 kb
Host smart-0d2a0e4d-5cf8-4fc0-9615-29cd3677ebad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17563
53230 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_smoke.1756353230
Directory /workspace/36.alert_handler_smoke/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all.939495518
Short name T81
Test name
Test status
Simulation time 268015666938 ps
CPU time 3431.81 seconds
Started Jul 10 05:30:27 PM PDT 24
Finished Jul 10 06:27:40 PM PDT 24
Peak memory 302384 kb
Host smart-46dbe864-6069-4f38-9d71-fb871417311a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939495518 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_han
dler_stress_all.939495518
Directory /workspace/36.alert_handler_stress_all/latest

Test location /workspace/coverage/default/37.alert_handler_entropy.1112196022
Short name T375
Test name
Test status
Simulation time 11950675909 ps
CPU time 962.14 seconds
Started Jul 10 05:30:37 PM PDT 24
Finished Jul 10 05:46:40 PM PDT 24
Peak memory 273480 kb
Host smart-7dd1e2fa-5fac-44fb-909e-97d53b64e1ba
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112196022 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_entropy.1112196022
Directory /workspace/37.alert_handler_entropy/latest

Test location /workspace/coverage/default/37.alert_handler_esc_alert_accum.2963245608
Short name T240
Test name
Test status
Simulation time 92446831369 ps
CPU time 311.62 seconds
Started Jul 10 05:30:38 PM PDT 24
Finished Jul 10 05:35:50 PM PDT 24
Peak memory 257596 kb
Host smart-8b383421-a02a-4be8-9354-0454874d70b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29632
45608 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_alert_accum.2963245608
Directory /workspace/37.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/37.alert_handler_esc_intr_timeout.3410094767
Short name T243
Test name
Test status
Simulation time 361227722 ps
CPU time 41.61 seconds
Started Jul 10 05:30:39 PM PDT 24
Finished Jul 10 05:31:21 PM PDT 24
Peak memory 249224 kb
Host smart-ae8e6f49-98e8-4447-91eb-b3aef293bf9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34100
94767 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_intr_timeout.3410094767
Directory /workspace/37.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_lpg.2242993638
Short name T501
Test name
Test status
Simulation time 36478651874 ps
CPU time 1595.49 seconds
Started Jul 10 05:30:46 PM PDT 24
Finished Jul 10 05:57:22 PM PDT 24
Peak memory 287228 kb
Host smart-cee2fd29-18c0-410a-9073-088858df6730
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242993638 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg.2242993638
Directory /workspace/37.alert_handler_lpg/latest

Test location /workspace/coverage/default/37.alert_handler_lpg_stub_clk.3078455366
Short name T36
Test name
Test status
Simulation time 31852567766 ps
CPU time 2061.51 seconds
Started Jul 10 05:30:45 PM PDT 24
Finished Jul 10 06:05:07 PM PDT 24
Peak memory 289460 kb
Host smart-65fb5263-f4aa-4efa-a63c-190b1a91da31
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3078455366 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg_stub_clk.3078455366
Directory /workspace/37.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/37.alert_handler_ping_timeout.3737646124
Short name T15
Test name
Test status
Simulation time 11582988009 ps
CPU time 466.89 seconds
Started Jul 10 05:30:45 PM PDT 24
Finished Jul 10 05:38:33 PM PDT 24
Peak memory 257004 kb
Host smart-e0141895-6bbf-4b7e-83ce-60c9c64a94d1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3737646124 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_ping_timeout.3737646124
Directory /workspace/37.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_random_alerts.421091527
Short name T435
Test name
Test status
Simulation time 82526543 ps
CPU time 12.06 seconds
Started Jul 10 05:30:30 PM PDT 24
Finished Jul 10 05:30:43 PM PDT 24
Peak memory 256380 kb
Host smart-f417540c-5829-4b46-814c-c1d0557be8aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42109
1527 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_alerts.421091527
Directory /workspace/37.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/37.alert_handler_random_classes.1747020127
Short name T561
Test name
Test status
Simulation time 847559785 ps
CPU time 58.15 seconds
Started Jul 10 05:30:37 PM PDT 24
Finished Jul 10 05:31:36 PM PDT 24
Peak memory 250280 kb
Host smart-f485619d-59d9-469c-a056-03c2837f9884
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17470
20127 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_classes.1747020127
Directory /workspace/37.alert_handler_random_classes/latest

Test location /workspace/coverage/default/37.alert_handler_sig_int_fail.2736716335
Short name T692
Test name
Test status
Simulation time 775355394 ps
CPU time 65.44 seconds
Started Jul 10 05:30:37 PM PDT 24
Finished Jul 10 05:31:44 PM PDT 24
Peak memory 256784 kb
Host smart-d7b2c233-acd1-4485-8274-b709834dc375
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27367
16335 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_sig_int_fail.2736716335
Directory /workspace/37.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/37.alert_handler_smoke.2370499082
Short name T615
Test name
Test status
Simulation time 24521960 ps
CPU time 3.21 seconds
Started Jul 10 05:30:33 PM PDT 24
Finished Jul 10 05:30:37 PM PDT 24
Peak memory 249248 kb
Host smart-186712c0-aa08-471c-bbce-56c670876c7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23704
99082 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_smoke.2370499082
Directory /workspace/37.alert_handler_smoke/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all.1750343849
Short name T558
Test name
Test status
Simulation time 108080158363 ps
CPU time 1829.73 seconds
Started Jul 10 05:30:44 PM PDT 24
Finished Jul 10 06:01:14 PM PDT 24
Peak memory 289308 kb
Host smart-4c90bdc4-38d3-4f1e-b9f3-84d68d403919
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750343849 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_ha
ndler_stress_all.1750343849
Directory /workspace/37.alert_handler_stress_all/latest

Test location /workspace/coverage/default/38.alert_handler_entropy.2549782588
Short name T669
Test name
Test status
Simulation time 72677089569 ps
CPU time 2162.5 seconds
Started Jul 10 05:30:50 PM PDT 24
Finished Jul 10 06:06:53 PM PDT 24
Peak memory 273692 kb
Host smart-edfc6300-0c90-47f4-9ef8-b046880740a8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2549782588 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_entropy.2549782588
Directory /workspace/38.alert_handler_entropy/latest

Test location /workspace/coverage/default/38.alert_handler_esc_alert_accum.234249690
Short name T565
Test name
Test status
Simulation time 812732073 ps
CPU time 64.36 seconds
Started Jul 10 05:30:53 PM PDT 24
Finished Jul 10 05:31:58 PM PDT 24
Peak memory 256540 kb
Host smart-196e9e47-052d-45ca-8d6e-e17a402f1c24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23424
9690 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_alert_accum.234249690
Directory /workspace/38.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/38.alert_handler_esc_intr_timeout.56464533
Short name T666
Test name
Test status
Simulation time 890289264 ps
CPU time 55.82 seconds
Started Jul 10 05:30:52 PM PDT 24
Finished Jul 10 05:31:49 PM PDT 24
Peak memory 256116 kb
Host smart-63634ea3-78c8-4cee-8aaa-5272bd0cd30e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56464
533 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_intr_timeout.56464533
Directory /workspace/38.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_lpg.1998103413
Short name T470
Test name
Test status
Simulation time 18352179562 ps
CPU time 874.93 seconds
Started Jul 10 05:30:53 PM PDT 24
Finished Jul 10 05:45:29 PM PDT 24
Peak memory 273964 kb
Host smart-bd353bae-c5a9-45ab-97de-90946c6939af
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1998103413 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg.1998103413
Directory /workspace/38.alert_handler_lpg/latest

Test location /workspace/coverage/default/38.alert_handler_lpg_stub_clk.268109142
Short name T408
Test name
Test status
Simulation time 29894601222 ps
CPU time 2026.09 seconds
Started Jul 10 05:30:51 PM PDT 24
Finished Jul 10 06:04:38 PM PDT 24
Peak memory 284064 kb
Host smart-4c985565-6a8a-461c-8516-1ba8c0e0d0fa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=268109142 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg_stub_clk.268109142
Directory /workspace/38.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/38.alert_handler_ping_timeout.4137047144
Short name T302
Test name
Test status
Simulation time 14000266507 ps
CPU time 297.88 seconds
Started Jul 10 05:30:52 PM PDT 24
Finished Jul 10 05:35:51 PM PDT 24
Peak memory 248264 kb
Host smart-1edc4c2f-9d6c-41d8-ae3a-a5fe76fc6a8f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137047144 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_ping_timeout.4137047144
Directory /workspace/38.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_random_alerts.2177970045
Short name T187
Test name
Test status
Simulation time 4371406929 ps
CPU time 48.76 seconds
Started Jul 10 05:30:52 PM PDT 24
Finished Jul 10 05:31:42 PM PDT 24
Peak memory 257556 kb
Host smart-0e0b6ca1-1321-4a46-a75e-068e5b4bb9ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21779
70045 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_alerts.2177970045
Directory /workspace/38.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/38.alert_handler_random_classes.1141736255
Short name T450
Test name
Test status
Simulation time 1193250510 ps
CPU time 36.94 seconds
Started Jul 10 05:30:53 PM PDT 24
Finished Jul 10 05:31:31 PM PDT 24
Peak memory 257296 kb
Host smart-8eea8876-ac2a-47f6-8afa-e1c1f6266867
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11417
36255 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_classes.1141736255
Directory /workspace/38.alert_handler_random_classes/latest

Test location /workspace/coverage/default/38.alert_handler_sig_int_fail.2177133618
Short name T59
Test name
Test status
Simulation time 313048837 ps
CPU time 19.88 seconds
Started Jul 10 05:30:52 PM PDT 24
Finished Jul 10 05:31:13 PM PDT 24
Peak memory 248680 kb
Host smart-e7bc6f62-c91b-455f-a1c5-23a2ec6d9c1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21771
33618 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_sig_int_fail.2177133618
Directory /workspace/38.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/38.alert_handler_smoke.2977869907
Short name T576
Test name
Test status
Simulation time 4054615638 ps
CPU time 24.02 seconds
Started Jul 10 05:30:52 PM PDT 24
Finished Jul 10 05:31:17 PM PDT 24
Peak memory 257544 kb
Host smart-d4ddfd8e-3109-41f0-bcc7-1cfe5a728397
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29778
69907 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_smoke.2977869907
Directory /workspace/38.alert_handler_smoke/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all.2224278671
Short name T709
Test name
Test status
Simulation time 11788588677 ps
CPU time 1120.55 seconds
Started Jul 10 05:30:53 PM PDT 24
Finished Jul 10 05:49:35 PM PDT 24
Peak memory 287112 kb
Host smart-f6bcca64-cb18-4cfc-819d-c0dfe26619b4
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224278671 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_ha
ndler_stress_all.2224278671
Directory /workspace/38.alert_handler_stress_all/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all_with_rand_reset.1331592358
Short name T245
Test name
Test status
Simulation time 129431102369 ps
CPU time 5947.68 seconds
Started Jul 10 05:30:51 PM PDT 24
Finished Jul 10 07:10:00 PM PDT 24
Peak memory 356004 kb
Host smart-31216b99-6344-4392-b6e3-c467ba52fede
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331592358 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 38.alert_handler_stress_all_with_rand_reset.1331592358
Directory /workspace/38.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.alert_handler_entropy.993560690
Short name T699
Test name
Test status
Simulation time 28613049545 ps
CPU time 1393.88 seconds
Started Jul 10 05:31:05 PM PDT 24
Finished Jul 10 05:54:20 PM PDT 24
Peak memory 289508 kb
Host smart-3ad706fa-e880-4190-a3f7-7cf25cf9099c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993560690 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_entropy.993560690
Directory /workspace/39.alert_handler_entropy/latest

Test location /workspace/coverage/default/39.alert_handler_esc_alert_accum.2805286584
Short name T425
Test name
Test status
Simulation time 17831441785 ps
CPU time 281.24 seconds
Started Jul 10 05:30:58 PM PDT 24
Finished Jul 10 05:35:40 PM PDT 24
Peak memory 256684 kb
Host smart-6a653989-baf6-4ea5-922e-99ad739d76d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28052
86584 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_alert_accum.2805286584
Directory /workspace/39.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/39.alert_handler_esc_intr_timeout.1731799179
Short name T67
Test name
Test status
Simulation time 3950378969 ps
CPU time 29.79 seconds
Started Jul 10 05:30:58 PM PDT 24
Finished Jul 10 05:31:29 PM PDT 24
Peak memory 249724 kb
Host smart-5711dab1-a92f-4e87-838b-acbc9fb53846
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17317
99179 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_intr_timeout.1731799179
Directory /workspace/39.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_lpg_stub_clk.525635992
Short name T418
Test name
Test status
Simulation time 66042200810 ps
CPU time 2246.26 seconds
Started Jul 10 05:31:04 PM PDT 24
Finished Jul 10 06:08:32 PM PDT 24
Peak memory 285804 kb
Host smart-bdcd1f3d-d867-4b9e-8662-827523532ce6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525635992 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg_stub_clk.525635992
Directory /workspace/39.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/39.alert_handler_ping_timeout.2454523632
Short name T651
Test name
Test status
Simulation time 31771514459 ps
CPU time 344.87 seconds
Started Jul 10 05:31:06 PM PDT 24
Finished Jul 10 05:36:52 PM PDT 24
Peak memory 248220 kb
Host smart-e76a49ab-cc97-4a8e-82b3-3ce6eaaf14b7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2454523632 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_ping_timeout.2454523632
Directory /workspace/39.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_random_alerts.3680090727
Short name T377
Test name
Test status
Simulation time 1239565598 ps
CPU time 25.58 seconds
Started Jul 10 05:30:58 PM PDT 24
Finished Jul 10 05:31:24 PM PDT 24
Peak memory 256768 kb
Host smart-35e6ee51-a6a6-477b-8e6f-96bcfaf63a32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36800
90727 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_alerts.3680090727
Directory /workspace/39.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/39.alert_handler_random_classes.2512733476
Short name T521
Test name
Test status
Simulation time 1381116165 ps
CPU time 29.45 seconds
Started Jul 10 05:30:58 PM PDT 24
Finished Jul 10 05:31:28 PM PDT 24
Peak memory 248724 kb
Host smart-21f9bc93-0201-4694-b856-aa1e27d82412
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25127
33476 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_classes.2512733476
Directory /workspace/39.alert_handler_random_classes/latest

Test location /workspace/coverage/default/39.alert_handler_sig_int_fail.1074732433
Short name T574
Test name
Test status
Simulation time 392104318 ps
CPU time 23.66 seconds
Started Jul 10 05:30:58 PM PDT 24
Finished Jul 10 05:31:22 PM PDT 24
Peak memory 248860 kb
Host smart-be1a1df9-2bc6-4014-a0ec-ffe530974540
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10747
32433 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_sig_int_fail.1074732433
Directory /workspace/39.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/39.alert_handler_smoke.4068502186
Short name T173
Test name
Test status
Simulation time 3061639895 ps
CPU time 48.05 seconds
Started Jul 10 05:30:57 PM PDT 24
Finished Jul 10 05:31:46 PM PDT 24
Peak memory 257608 kb
Host smart-04782233-71d3-4bf2-b320-c5a4fbc1ea58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40685
02186 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_smoke.4068502186
Directory /workspace/39.alert_handler_smoke/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all.4156278855
Short name T708
Test name
Test status
Simulation time 44202823625 ps
CPU time 2422.26 seconds
Started Jul 10 05:31:13 PM PDT 24
Finished Jul 10 06:11:36 PM PDT 24
Peak memory 287420 kb
Host smart-777b25ac-0409-4436-99ac-e5879f6a7699
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156278855 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_ha
ndler_stress_all.4156278855
Directory /workspace/39.alert_handler_stress_all/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all_with_rand_reset.2305695312
Short name T270
Test name
Test status
Simulation time 173462493457 ps
CPU time 5929.34 seconds
Started Jul 10 05:31:10 PM PDT 24
Finished Jul 10 07:10:01 PM PDT 24
Peak memory 323092 kb
Host smart-06fcf14d-4fcb-48de-b94a-21b903fe1b0b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305695312 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.alert_handler_stress_all_with_rand_reset.2305695312
Directory /workspace/39.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.alert_handler_alert_accum_saturation.1409393874
Short name T211
Test name
Test status
Simulation time 110898615 ps
CPU time 2.99 seconds
Started Jul 10 05:27:30 PM PDT 24
Finished Jul 10 05:27:34 PM PDT 24
Peak memory 249512 kb
Host smart-3ac2a3f4-fe86-4336-8987-530bdf0358c7
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1409393874 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_alert_accum_saturation.1409393874
Directory /workspace/4.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/4.alert_handler_entropy.3902685472
Short name T190
Test name
Test status
Simulation time 29522042045 ps
CPU time 867.31 seconds
Started Jul 10 05:27:35 PM PDT 24
Finished Jul 10 05:42:05 PM PDT 24
Peak memory 289992 kb
Host smart-e1b77450-55b6-4275-9391-0098a6faee35
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902685472 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy.3902685472
Directory /workspace/4.alert_handler_entropy/latest

Test location /workspace/coverage/default/4.alert_handler_entropy_stress.2913910881
Short name T611
Test name
Test status
Simulation time 323108950 ps
CPU time 15.54 seconds
Started Jul 10 05:27:29 PM PDT 24
Finished Jul 10 05:27:47 PM PDT 24
Peak memory 249200 kb
Host smart-2c711c1d-c761-40bc-8ca7-e96dd4742870
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2913910881 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy_stress.2913910881
Directory /workspace/4.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/4.alert_handler_esc_alert_accum.2966338465
Short name T242
Test name
Test status
Simulation time 7767254639 ps
CPU time 111.8 seconds
Started Jul 10 05:27:32 PM PDT 24
Finished Jul 10 05:29:25 PM PDT 24
Peak memory 250408 kb
Host smart-b3e6579e-efad-4c46-8dd6-5f7c1ae3da4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29663
38465 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_alert_accum.2966338465
Directory /workspace/4.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/4.alert_handler_esc_intr_timeout.2688526310
Short name T400
Test name
Test status
Simulation time 117530639 ps
CPU time 11.72 seconds
Started Jul 10 05:27:31 PM PDT 24
Finished Jul 10 05:27:44 PM PDT 24
Peak memory 257008 kb
Host smart-954b8a8a-f773-4d43-97d5-dcc79159f52c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26885
26310 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_intr_timeout.2688526310
Directory /workspace/4.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_lpg.241131149
Short name T228
Test name
Test status
Simulation time 64312345964 ps
CPU time 1217.8 seconds
Started Jul 10 05:27:35 PM PDT 24
Finished Jul 10 05:47:55 PM PDT 24
Peak memory 289364 kb
Host smart-ea967298-ba51-4084-9161-15fe9334460d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241131149 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg.241131149
Directory /workspace/4.alert_handler_lpg/latest

Test location /workspace/coverage/default/4.alert_handler_lpg_stub_clk.782521724
Short name T601
Test name
Test status
Simulation time 144081366858 ps
CPU time 2124.19 seconds
Started Jul 10 05:27:33 PM PDT 24
Finished Jul 10 06:02:59 PM PDT 24
Peak memory 289896 kb
Host smart-4395a4bb-f755-467b-b3d6-47b4f9630979
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782521724 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg_stub_clk.782521724
Directory /workspace/4.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/4.alert_handler_ping_timeout.855637449
Short name T321
Test name
Test status
Simulation time 12805531823 ps
CPU time 246.87 seconds
Started Jul 10 05:27:30 PM PDT 24
Finished Jul 10 05:31:39 PM PDT 24
Peak memory 255948 kb
Host smart-0bf4321b-7719-41a3-9914-9e478fb5690f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855637449 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_ping_timeout.855637449
Directory /workspace/4.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_random_alerts.2311872809
Short name T354
Test name
Test status
Simulation time 1590786349 ps
CPU time 46.63 seconds
Started Jul 10 05:27:28 PM PDT 24
Finished Jul 10 05:28:17 PM PDT 24
Peak memory 256748 kb
Host smart-9897f0b6-a446-495f-8d35-0b73b011ce84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23118
72809 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_alerts.2311872809
Directory /workspace/4.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/4.alert_handler_random_classes.306874794
Short name T459
Test name
Test status
Simulation time 222103507 ps
CPU time 9.5 seconds
Started Jul 10 05:27:34 PM PDT 24
Finished Jul 10 05:27:47 PM PDT 24
Peak memory 255224 kb
Host smart-fdfef914-91e8-41ca-a0df-7ea6180757fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30687
4794 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_classes.306874794
Directory /workspace/4.alert_handler_random_classes/latest

Test location /workspace/coverage/default/4.alert_handler_sec_cm.3221920859
Short name T33
Test name
Test status
Simulation time 466614365 ps
CPU time 26.81 seconds
Started Jul 10 05:27:31 PM PDT 24
Finished Jul 10 05:28:00 PM PDT 24
Peak memory 278156 kb
Host smart-35db361e-3072-4d83-9991-08171f6d1921
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3221920859 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sec_cm.3221920859
Directory /workspace/4.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/4.alert_handler_sig_int_fail.3955721306
Short name T253
Test name
Test status
Simulation time 224054255 ps
CPU time 16.62 seconds
Started Jul 10 05:27:35 PM PDT 24
Finished Jul 10 05:27:55 PM PDT 24
Peak memory 248800 kb
Host smart-79721ba9-8c8b-4547-ac22-c5ff62c6e159
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39557
21306 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sig_int_fail.3955721306
Directory /workspace/4.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/4.alert_handler_smoke.1572948165
Short name T534
Test name
Test status
Simulation time 154365493 ps
CPU time 12.57 seconds
Started Jul 10 05:27:28 PM PDT 24
Finished Jul 10 05:27:43 PM PDT 24
Peak memory 256888 kb
Host smart-68a4aae8-93fc-4884-a319-a3d8ba7db595
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15729
48165 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_smoke.1572948165
Directory /workspace/4.alert_handler_smoke/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all_with_rand_reset.3992701953
Short name T631
Test name
Test status
Simulation time 80899973163 ps
CPU time 3875.37 seconds
Started Jul 10 05:27:33 PM PDT 24
Finished Jul 10 06:32:10 PM PDT 24
Peak memory 322704 kb
Host smart-3c6092ae-0b8a-40b0-afd0-4fdafb87a8f7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992701953 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.alert_handler_stress_all_with_rand_reset.3992701953
Directory /workspace/4.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.alert_handler_entropy.2792049691
Short name T704
Test name
Test status
Simulation time 142080536175 ps
CPU time 1345.57 seconds
Started Jul 10 05:31:18 PM PDT 24
Finished Jul 10 05:53:44 PM PDT 24
Peak memory 286648 kb
Host smart-33752605-1df7-4a68-87fe-d320727eb098
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792049691 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_entropy.2792049691
Directory /workspace/40.alert_handler_entropy/latest

Test location /workspace/coverage/default/40.alert_handler_esc_alert_accum.614449620
Short name T426
Test name
Test status
Simulation time 6053668316 ps
CPU time 188.19 seconds
Started Jul 10 05:31:09 PM PDT 24
Finished Jul 10 05:34:18 PM PDT 24
Peak memory 256796 kb
Host smart-2caf4e9f-a633-41ec-85e6-50f219e54cd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61444
9620 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_alert_accum.614449620
Directory /workspace/40.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/40.alert_handler_esc_intr_timeout.794252301
Short name T664
Test name
Test status
Simulation time 132304939 ps
CPU time 13.6 seconds
Started Jul 10 05:31:09 PM PDT 24
Finished Jul 10 05:31:23 PM PDT 24
Peak memory 257204 kb
Host smart-6d2fb0a0-2dfa-4c04-bcad-0fda03b78855
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79425
2301 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_intr_timeout.794252301
Directory /workspace/40.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_lpg.2002997456
Short name T707
Test name
Test status
Simulation time 16847256841 ps
CPU time 1119.86 seconds
Started Jul 10 05:31:16 PM PDT 24
Finished Jul 10 05:49:56 PM PDT 24
Peak memory 273888 kb
Host smart-6c708221-ed8c-444f-b6f1-00dc4f7d9be6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002997456 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg.2002997456
Directory /workspace/40.alert_handler_lpg/latest

Test location /workspace/coverage/default/40.alert_handler_lpg_stub_clk.530395275
Short name T557
Test name
Test status
Simulation time 40475777808 ps
CPU time 2595.96 seconds
Started Jul 10 05:31:15 PM PDT 24
Finished Jul 10 06:14:32 PM PDT 24
Peak memory 273992 kb
Host smart-8aac73c9-1fac-4b64-9517-1196a8b1cc0b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530395275 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg_stub_clk.530395275
Directory /workspace/40.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/40.alert_handler_ping_timeout.1694540543
Short name T530
Test name
Test status
Simulation time 2982760523 ps
CPU time 126.19 seconds
Started Jul 10 05:31:18 PM PDT 24
Finished Jul 10 05:33:25 PM PDT 24
Peak memory 256000 kb
Host smart-3474efb6-d32f-4ad8-a258-7a12a7a8c016
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694540543 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_ping_timeout.1694540543
Directory /workspace/40.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_random_alerts.3928222267
Short name T25
Test name
Test status
Simulation time 2554031192 ps
CPU time 25.31 seconds
Started Jul 10 05:31:10 PM PDT 24
Finished Jul 10 05:31:36 PM PDT 24
Peak memory 256868 kb
Host smart-1a5dd672-070a-434e-9291-da192a030008
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39282
22267 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_alerts.3928222267
Directory /workspace/40.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/40.alert_handler_sig_int_fail.736407073
Short name T96
Test name
Test status
Simulation time 282495460 ps
CPU time 16.88 seconds
Started Jul 10 05:31:15 PM PDT 24
Finished Jul 10 05:31:33 PM PDT 24
Peak memory 249300 kb
Host smart-1eacc3d8-67d0-497e-9b86-aa62c3e97f30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73640
7073 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_sig_int_fail.736407073
Directory /workspace/40.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/40.alert_handler_smoke.1730772447
Short name T188
Test name
Test status
Simulation time 10784612453 ps
CPU time 46.12 seconds
Started Jul 10 05:31:11 PM PDT 24
Finished Jul 10 05:31:57 PM PDT 24
Peak memory 257468 kb
Host smart-23e5adfc-f8b0-40ec-b8e1-af646c326541
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17307
72447 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_smoke.1730772447
Directory /workspace/40.alert_handler_smoke/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all.4216181479
Short name T710
Test name
Test status
Simulation time 15352999926 ps
CPU time 1834.56 seconds
Started Jul 10 05:31:16 PM PDT 24
Finished Jul 10 06:01:52 PM PDT 24
Peak memory 298588 kb
Host smart-ede42713-aa6a-43ab-b6ab-6d6c70159832
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216181479 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_ha
ndler_stress_all.4216181479
Directory /workspace/40.alert_handler_stress_all/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all_with_rand_reset.4124473442
Short name T37
Test name
Test status
Simulation time 25516940786 ps
CPU time 2587.47 seconds
Started Jul 10 05:31:15 PM PDT 24
Finished Jul 10 06:14:23 PM PDT 24
Peak memory 306316 kb
Host smart-b15f7ec4-5003-487d-8c18-82dfa13c779c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124473442 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 40.alert_handler_stress_all_with_rand_reset.4124473442
Directory /workspace/40.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.alert_handler_entropy.1059205161
Short name T618
Test name
Test status
Simulation time 22026963053 ps
CPU time 648.67 seconds
Started Jul 10 05:31:26 PM PDT 24
Finished Jul 10 05:42:15 PM PDT 24
Peak memory 273184 kb
Host smart-4911ebd4-5135-492c-8da9-d63aebb95c2e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059205161 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_entropy.1059205161
Directory /workspace/41.alert_handler_entropy/latest

Test location /workspace/coverage/default/41.alert_handler_esc_alert_accum.3710278445
Short name T393
Test name
Test status
Simulation time 10242256466 ps
CPU time 160.68 seconds
Started Jul 10 05:31:21 PM PDT 24
Finished Jul 10 05:34:02 PM PDT 24
Peak memory 257264 kb
Host smart-a82d66bc-0274-4c8e-bb19-5c33d1597e2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37102
78445 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_alert_accum.3710278445
Directory /workspace/41.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/41.alert_handler_esc_intr_timeout.3367193402
Short name T612
Test name
Test status
Simulation time 2031153654 ps
CPU time 31.29 seconds
Started Jul 10 05:31:22 PM PDT 24
Finished Jul 10 05:31:54 PM PDT 24
Peak memory 256508 kb
Host smart-d5739799-1a54-425f-a5ec-552ddb10719a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33671
93402 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_intr_timeout.3367193402
Directory /workspace/41.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_lpg.2735385749
Short name T335
Test name
Test status
Simulation time 286495492131 ps
CPU time 2195.74 seconds
Started Jul 10 05:31:27 PM PDT 24
Finished Jul 10 06:08:04 PM PDT 24
Peak memory 286780 kb
Host smart-98d5b275-a2da-4dba-ac7a-dd58d8dd5ef5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735385749 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg.2735385749
Directory /workspace/41.alert_handler_lpg/latest

Test location /workspace/coverage/default/41.alert_handler_lpg_stub_clk.4250941808
Short name T553
Test name
Test status
Simulation time 121665789634 ps
CPU time 3351.78 seconds
Started Jul 10 05:31:34 PM PDT 24
Finished Jul 10 06:27:26 PM PDT 24
Peak memory 289632 kb
Host smart-9cf8e7a0-2ad7-4300-8995-7c7f55f94466
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4250941808 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg_stub_clk.4250941808
Directory /workspace/41.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/41.alert_handler_ping_timeout.4267723968
Short name T305
Test name
Test status
Simulation time 18666386507 ps
CPU time 296.29 seconds
Started Jul 10 05:31:29 PM PDT 24
Finished Jul 10 05:36:26 PM PDT 24
Peak memory 256024 kb
Host smart-be29ca34-c52c-4c5d-a72b-a160325a4130
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267723968 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_ping_timeout.4267723968
Directory /workspace/41.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_random_alerts.2941298618
Short name T496
Test name
Test status
Simulation time 1886150689 ps
CPU time 63.82 seconds
Started Jul 10 05:31:17 PM PDT 24
Finished Jul 10 05:32:21 PM PDT 24
Peak memory 256964 kb
Host smart-6a361946-2219-462f-ba68-27c63028b93d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29412
98618 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_alerts.2941298618
Directory /workspace/41.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/41.alert_handler_random_classes.4069400918
Short name T239
Test name
Test status
Simulation time 1394281061 ps
CPU time 39.66 seconds
Started Jul 10 05:31:17 PM PDT 24
Finished Jul 10 05:31:57 PM PDT 24
Peak memory 248612 kb
Host smart-ede0d586-f629-4ff1-b292-73c4c57ce5b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40694
00918 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_classes.4069400918
Directory /workspace/41.alert_handler_random_classes/latest

Test location /workspace/coverage/default/41.alert_handler_sig_int_fail.4045581545
Short name T635
Test name
Test status
Simulation time 256304723 ps
CPU time 26.85 seconds
Started Jul 10 05:31:26 PM PDT 24
Finished Jul 10 05:31:54 PM PDT 24
Peak memory 249232 kb
Host smart-8af6e4b0-42c0-425e-8641-cbab9f831f50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40455
81545 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_sig_int_fail.4045581545
Directory /workspace/41.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/41.alert_handler_smoke.4212114948
Short name T39
Test name
Test status
Simulation time 1079286749 ps
CPU time 32.84 seconds
Started Jul 10 05:31:17 PM PDT 24
Finished Jul 10 05:31:51 PM PDT 24
Peak memory 257432 kb
Host smart-84544616-ed10-4263-93a7-637243a8a4f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42121
14948 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_smoke.4212114948
Directory /workspace/41.alert_handler_smoke/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all.3147757298
Short name T685
Test name
Test status
Simulation time 3977409253 ps
CPU time 415.54 seconds
Started Jul 10 05:31:35 PM PDT 24
Finished Jul 10 05:38:31 PM PDT 24
Peak memory 265892 kb
Host smart-297a3072-b8ca-4b3f-85ce-e89e4868f71b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147757298 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_ha
ndler_stress_all.3147757298
Directory /workspace/41.alert_handler_stress_all/latest

Test location /workspace/coverage/default/42.alert_handler_entropy.2254173582
Short name T399
Test name
Test status
Simulation time 34727015662 ps
CPU time 2214.47 seconds
Started Jul 10 05:31:37 PM PDT 24
Finished Jul 10 06:08:32 PM PDT 24
Peak memory 289460 kb
Host smart-867e6588-9bfd-40e2-84ce-302fdb722b59
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254173582 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_entropy.2254173582
Directory /workspace/42.alert_handler_entropy/latest

Test location /workspace/coverage/default/42.alert_handler_esc_alert_accum.1035756741
Short name T394
Test name
Test status
Simulation time 15935784355 ps
CPU time 257.57 seconds
Started Jul 10 05:31:39 PM PDT 24
Finished Jul 10 05:35:57 PM PDT 24
Peak memory 257564 kb
Host smart-99209eaa-cf78-404c-8a79-6b217d508d1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10357
56741 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_alert_accum.1035756741
Directory /workspace/42.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/42.alert_handler_esc_intr_timeout.1578204592
Short name T551
Test name
Test status
Simulation time 1107697180 ps
CPU time 55.63 seconds
Started Jul 10 05:31:39 PM PDT 24
Finished Jul 10 05:32:35 PM PDT 24
Peak memory 257476 kb
Host smart-753e7119-00c2-4d36-9ffa-8120da4803b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15782
04592 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_intr_timeout.1578204592
Directory /workspace/42.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_lpg.3430296675
Short name T285
Test name
Test status
Simulation time 146100273697 ps
CPU time 2538.3 seconds
Started Jul 10 05:31:48 PM PDT 24
Finished Jul 10 06:14:07 PM PDT 24
Peak memory 290184 kb
Host smart-5d0b095f-a0f5-4d0b-8b24-aa31517437b5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430296675 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg.3430296675
Directory /workspace/42.alert_handler_lpg/latest

Test location /workspace/coverage/default/42.alert_handler_lpg_stub_clk.1734691392
Short name T513
Test name
Test status
Simulation time 145980815866 ps
CPU time 2372.11 seconds
Started Jul 10 05:31:50 PM PDT 24
Finished Jul 10 06:11:23 PM PDT 24
Peak memory 286340 kb
Host smart-8d8bd82c-feb4-4f17-acef-edd813c0efb7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734691392 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg_stub_clk.1734691392
Directory /workspace/42.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/42.alert_handler_ping_timeout.3846256420
Short name T322
Test name
Test status
Simulation time 2499468691 ps
CPU time 107.58 seconds
Started Jul 10 05:31:46 PM PDT 24
Finished Jul 10 05:33:34 PM PDT 24
Peak memory 253316 kb
Host smart-3bda6bdd-3d92-4096-a268-503bd3ecee26
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846256420 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_ping_timeout.3846256420
Directory /workspace/42.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_random_alerts.1584511256
Short name T687
Test name
Test status
Simulation time 194386138 ps
CPU time 13.07 seconds
Started Jul 10 05:31:33 PM PDT 24
Finished Jul 10 05:31:47 PM PDT 24
Peak memory 256788 kb
Host smart-a40a9402-4d1c-4759-bec1-c211bd1f1b06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15845
11256 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_alerts.1584511256
Directory /workspace/42.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/42.alert_handler_random_classes.997694900
Short name T663
Test name
Test status
Simulation time 1785737487 ps
CPU time 30.1 seconds
Started Jul 10 05:31:34 PM PDT 24
Finished Jul 10 05:32:05 PM PDT 24
Peak memory 248552 kb
Host smart-c970be2f-3333-4634-8302-d437b5dbc71e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99769
4900 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_classes.997694900
Directory /workspace/42.alert_handler_random_classes/latest

Test location /workspace/coverage/default/42.alert_handler_sig_int_fail.3895207730
Short name T455
Test name
Test status
Simulation time 344795232 ps
CPU time 20.65 seconds
Started Jul 10 05:31:40 PM PDT 24
Finished Jul 10 05:32:02 PM PDT 24
Peak memory 248444 kb
Host smart-95fa3771-acad-4bf2-a80c-e5d1834b62b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38952
07730 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_sig_int_fail.3895207730
Directory /workspace/42.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/42.alert_handler_smoke.3765706451
Short name T571
Test name
Test status
Simulation time 1934965161 ps
CPU time 8.59 seconds
Started Jul 10 05:31:34 PM PDT 24
Finished Jul 10 05:31:43 PM PDT 24
Peak memory 249300 kb
Host smart-d3333acf-5c55-4f41-9090-80e6d278ee08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37657
06451 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_smoke.3765706451
Directory /workspace/42.alert_handler_smoke/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all.415589272
Short name T620
Test name
Test status
Simulation time 43970963559 ps
CPU time 2053.12 seconds
Started Jul 10 05:31:50 PM PDT 24
Finished Jul 10 06:06:04 PM PDT 24
Peak memory 306700 kb
Host smart-6fa83d7d-e6fa-4ccf-a9c2-cfb4659f1c1f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415589272 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_han
dler_stress_all.415589272
Directory /workspace/42.alert_handler_stress_all/latest

Test location /workspace/coverage/default/43.alert_handler_entropy.1934826995
Short name T82
Test name
Test status
Simulation time 38420069870 ps
CPU time 2135.61 seconds
Started Jul 10 05:31:57 PM PDT 24
Finished Jul 10 06:07:34 PM PDT 24
Peak memory 273808 kb
Host smart-a2c2bbd3-e7e5-4c23-9221-ff18e05bcb17
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934826995 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_entropy.1934826995
Directory /workspace/43.alert_handler_entropy/latest

Test location /workspace/coverage/default/43.alert_handler_esc_alert_accum.43122294
Short name T495
Test name
Test status
Simulation time 3636633170 ps
CPU time 245.58 seconds
Started Jul 10 05:31:58 PM PDT 24
Finished Jul 10 05:36:05 PM PDT 24
Peak memory 256832 kb
Host smart-00433737-0919-4d56-baa4-2202e2070774
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43122
294 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_alert_accum.43122294
Directory /workspace/43.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/43.alert_handler_esc_intr_timeout.2323587588
Short name T391
Test name
Test status
Simulation time 494806483 ps
CPU time 11.83 seconds
Started Jul 10 05:31:56 PM PDT 24
Finished Jul 10 05:32:09 PM PDT 24
Peak memory 249888 kb
Host smart-6e26edf4-e34a-461b-b768-eacee18ae2c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23235
87588 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_intr_timeout.2323587588
Directory /workspace/43.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_lpg_stub_clk.690283687
Short name T230
Test name
Test status
Simulation time 48699860452 ps
CPU time 1506.42 seconds
Started Jul 10 05:31:57 PM PDT 24
Finished Jul 10 05:57:05 PM PDT 24
Peak memory 273936 kb
Host smart-83dbea2c-aab4-4908-8da1-d588360b9c9f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690283687 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg_stub_clk.690283687
Directory /workspace/43.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/43.alert_handler_ping_timeout.661925903
Short name T309
Test name
Test status
Simulation time 6041726649 ps
CPU time 122.13 seconds
Started Jul 10 05:31:59 PM PDT 24
Finished Jul 10 05:34:02 PM PDT 24
Peak memory 249420 kb
Host smart-4377d265-27a4-4fae-9fb0-2d9414368dc1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661925903 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_ping_timeout.661925903
Directory /workspace/43.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_random_alerts.956989838
Short name T358
Test name
Test status
Simulation time 491303086 ps
CPU time 9.56 seconds
Started Jul 10 05:31:50 PM PDT 24
Finished Jul 10 05:32:01 PM PDT 24
Peak memory 249264 kb
Host smart-50e60e41-c459-4684-a65b-7ce7713a70bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95698
9838 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_alerts.956989838
Directory /workspace/43.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/43.alert_handler_random_classes.2885932446
Short name T658
Test name
Test status
Simulation time 1746049723 ps
CPU time 17.22 seconds
Started Jul 10 05:31:57 PM PDT 24
Finished Jul 10 05:32:15 PM PDT 24
Peak memory 253792 kb
Host smart-d9fe4e4f-53cb-4ca1-9e2d-7d9884b16ad6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28859
32446 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_classes.2885932446
Directory /workspace/43.alert_handler_random_classes/latest

Test location /workspace/coverage/default/43.alert_handler_smoke.3616074665
Short name T468
Test name
Test status
Simulation time 4253542897 ps
CPU time 34.73 seconds
Started Jul 10 05:31:48 PM PDT 24
Finished Jul 10 05:32:23 PM PDT 24
Peak memory 257528 kb
Host smart-084af36d-3601-45e9-8ac8-1aae4495e7a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36160
74665 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_smoke.3616074665
Directory /workspace/43.alert_handler_smoke/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all.3227652690
Short name T452
Test name
Test status
Simulation time 29328590198 ps
CPU time 1876.18 seconds
Started Jul 10 05:32:02 PM PDT 24
Finished Jul 10 06:03:20 PM PDT 24
Peak memory 285700 kb
Host smart-90d78ad5-6a92-45b3-ba3e-cb4e5a2b1a02
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227652690 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_ha
ndler_stress_all.3227652690
Directory /workspace/43.alert_handler_stress_all/latest

Test location /workspace/coverage/default/44.alert_handler_entropy.3969738015
Short name T289
Test name
Test status
Simulation time 96246681693 ps
CPU time 2896.04 seconds
Started Jul 10 05:32:02 PM PDT 24
Finished Jul 10 06:20:20 PM PDT 24
Peak memory 285768 kb
Host smart-9811a2e4-5e82-4516-a186-9c069effe6f0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3969738015 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_entropy.3969738015
Directory /workspace/44.alert_handler_entropy/latest

Test location /workspace/coverage/default/44.alert_handler_esc_alert_accum.103813686
Short name T638
Test name
Test status
Simulation time 1813388329 ps
CPU time 100.27 seconds
Started Jul 10 05:32:03 PM PDT 24
Finished Jul 10 05:33:44 PM PDT 24
Peak memory 250240 kb
Host smart-54d385ed-39f3-4ef3-a71f-59012ab2e4bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10381
3686 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_alert_accum.103813686
Directory /workspace/44.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/44.alert_handler_esc_intr_timeout.669271434
Short name T693
Test name
Test status
Simulation time 164117467 ps
CPU time 14.06 seconds
Started Jul 10 05:32:04 PM PDT 24
Finished Jul 10 05:32:19 PM PDT 24
Peak memory 249220 kb
Host smart-1277ca42-1934-446f-b8a0-934213925278
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66927
1434 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_intr_timeout.669271434
Directory /workspace/44.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_lpg.4023330159
Short name T616
Test name
Test status
Simulation time 197844022684 ps
CPU time 1750.57 seconds
Started Jul 10 05:32:10 PM PDT 24
Finished Jul 10 06:01:22 PM PDT 24
Peak memory 273964 kb
Host smart-bc4c19a7-c7a4-4398-917e-3d22806e7d03
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023330159 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg.4023330159
Directory /workspace/44.alert_handler_lpg/latest

Test location /workspace/coverage/default/44.alert_handler_lpg_stub_clk.1189743078
Short name T538
Test name
Test status
Simulation time 38633303143 ps
CPU time 2155.81 seconds
Started Jul 10 05:32:09 PM PDT 24
Finished Jul 10 06:08:06 PM PDT 24
Peak memory 273944 kb
Host smart-5092ee97-de72-4393-8ec5-2162d168565e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1189743078 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg_stub_clk.1189743078
Directory /workspace/44.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/44.alert_handler_ping_timeout.1210444194
Short name T232
Test name
Test status
Simulation time 45348442564 ps
CPU time 315.78 seconds
Started Jul 10 05:32:03 PM PDT 24
Finished Jul 10 05:37:20 PM PDT 24
Peak memory 249420 kb
Host smart-2e511f22-65aa-4761-b668-e03a88302e4f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210444194 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_ping_timeout.1210444194
Directory /workspace/44.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_random_alerts.810563656
Short name T520
Test name
Test status
Simulation time 163725084 ps
CPU time 13.05 seconds
Started Jul 10 05:32:05 PM PDT 24
Finished Jul 10 05:32:18 PM PDT 24
Peak memory 257424 kb
Host smart-69ccbe9f-0239-44f1-b3af-373b22d6f90c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81056
3656 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_alerts.810563656
Directory /workspace/44.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/44.alert_handler_random_classes.3008285914
Short name T424
Test name
Test status
Simulation time 765513266 ps
CPU time 55.71 seconds
Started Jul 10 05:32:02 PM PDT 24
Finished Jul 10 05:32:59 PM PDT 24
Peak memory 256968 kb
Host smart-5bab6480-222b-435e-9f62-3812e9ee9a29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30082
85914 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_classes.3008285914
Directory /workspace/44.alert_handler_random_classes/latest

Test location /workspace/coverage/default/44.alert_handler_sig_int_fail.1676808055
Short name T303
Test name
Test status
Simulation time 349788660 ps
CPU time 32.86 seconds
Started Jul 10 05:32:02 PM PDT 24
Finished Jul 10 05:32:36 PM PDT 24
Peak memory 256724 kb
Host smart-a0d09a5f-5734-4776-8320-667635af75b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16768
08055 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_sig_int_fail.1676808055
Directory /workspace/44.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/44.alert_handler_smoke.3787045859
Short name T390
Test name
Test status
Simulation time 1976282508 ps
CPU time 63.09 seconds
Started Jul 10 05:32:04 PM PDT 24
Finished Jul 10 05:33:08 PM PDT 24
Peak memory 257404 kb
Host smart-cdc74d75-2bce-4208-b2db-f57aae47693a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37870
45859 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_smoke.3787045859
Directory /workspace/44.alert_handler_smoke/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all.2677830646
Short name T657
Test name
Test status
Simulation time 7930331818 ps
CPU time 49.24 seconds
Started Jul 10 05:32:09 PM PDT 24
Finished Jul 10 05:32:59 PM PDT 24
Peak memory 257652 kb
Host smart-09d81a31-f266-4466-b200-e6eba63a5add
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677830646 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_ha
ndler_stress_all.2677830646
Directory /workspace/44.alert_handler_stress_all/latest

Test location /workspace/coverage/default/45.alert_handler_entropy.559842434
Short name T241
Test name
Test status
Simulation time 57222010352 ps
CPU time 1409.86 seconds
Started Jul 10 05:32:20 PM PDT 24
Finished Jul 10 05:55:50 PM PDT 24
Peak memory 289040 kb
Host smart-acc7a5f4-830d-4040-bfe6-da91759f2e99
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559842434 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_entropy.559842434
Directory /workspace/45.alert_handler_entropy/latest

Test location /workspace/coverage/default/45.alert_handler_esc_alert_accum.1131512770
Short name T628
Test name
Test status
Simulation time 4995879334 ps
CPU time 158.44 seconds
Started Jul 10 05:32:17 PM PDT 24
Finished Jul 10 05:34:56 PM PDT 24
Peak memory 257596 kb
Host smart-d2d720e9-f500-4186-ab8e-c3d416d5d171
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11315
12770 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_alert_accum.1131512770
Directory /workspace/45.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/45.alert_handler_esc_intr_timeout.2955595785
Short name T677
Test name
Test status
Simulation time 540322214 ps
CPU time 6.96 seconds
Started Jul 10 05:32:17 PM PDT 24
Finished Jul 10 05:32:24 PM PDT 24
Peak memory 241096 kb
Host smart-73575535-05ae-40b6-a49f-a954d89a0705
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29555
95785 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_intr_timeout.2955595785
Directory /workspace/45.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_lpg.3991892459
Short name T605
Test name
Test status
Simulation time 30683303004 ps
CPU time 891.31 seconds
Started Jul 10 05:32:21 PM PDT 24
Finished Jul 10 05:47:13 PM PDT 24
Peak memory 273860 kb
Host smart-d17b680f-e621-4654-b92a-8f7148299a46
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991892459 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg.3991892459
Directory /workspace/45.alert_handler_lpg/latest

Test location /workspace/coverage/default/45.alert_handler_lpg_stub_clk.73659945
Short name T713
Test name
Test status
Simulation time 114476612903 ps
CPU time 838.22 seconds
Started Jul 10 05:32:21 PM PDT 24
Finished Jul 10 05:46:20 PM PDT 24
Peak memory 289328 kb
Host smart-0bf5d8ff-1a37-4398-a75b-4856fb191afa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73659945 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg_stub_clk.73659945
Directory /workspace/45.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/45.alert_handler_random_alerts.1387086664
Short name T602
Test name
Test status
Simulation time 479148839 ps
CPU time 5.83 seconds
Started Jul 10 05:32:18 PM PDT 24
Finished Jul 10 05:32:25 PM PDT 24
Peak memory 249204 kb
Host smart-2779b969-d5d7-4566-a795-07af5195835d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13870
86664 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_alerts.1387086664
Directory /workspace/45.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/45.alert_handler_random_classes.1978551707
Short name T511
Test name
Test status
Simulation time 203527241 ps
CPU time 18.53 seconds
Started Jul 10 05:32:16 PM PDT 24
Finished Jul 10 05:32:35 PM PDT 24
Peak memory 256168 kb
Host smart-9a2f8ca7-6d21-4fb6-8897-0efde0a2032c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19785
51707 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_classes.1978551707
Directory /workspace/45.alert_handler_random_classes/latest

Test location /workspace/coverage/default/45.alert_handler_sig_int_fail.3783343185
Short name T271
Test name
Test status
Simulation time 2279063100 ps
CPU time 43.59 seconds
Started Jul 10 05:32:23 PM PDT 24
Finished Jul 10 05:33:08 PM PDT 24
Peak memory 256948 kb
Host smart-26857281-b9f0-4d19-b636-65d731a892cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37833
43185 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_sig_int_fail.3783343185
Directory /workspace/45.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/45.alert_handler_smoke.2993120661
Short name T641
Test name
Test status
Simulation time 375813075 ps
CPU time 37.88 seconds
Started Jul 10 05:32:16 PM PDT 24
Finished Jul 10 05:32:55 PM PDT 24
Peak memory 257432 kb
Host smart-39488ae5-924f-48fa-83ec-e3a48ebcd07d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29931
20661 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_smoke.2993120661
Directory /workspace/45.alert_handler_smoke/latest

Test location /workspace/coverage/default/46.alert_handler_entropy.1186808008
Short name T293
Test name
Test status
Simulation time 61157586671 ps
CPU time 1419.42 seconds
Started Jul 10 05:32:33 PM PDT 24
Finished Jul 10 05:56:14 PM PDT 24
Peak memory 290116 kb
Host smart-c5f2eb23-f917-40f0-9e42-3fc800c655c1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1186808008 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_entropy.1186808008
Directory /workspace/46.alert_handler_entropy/latest

Test location /workspace/coverage/default/46.alert_handler_esc_alert_accum.3603454846
Short name T175
Test name
Test status
Simulation time 8593410747 ps
CPU time 105.36 seconds
Started Jul 10 05:32:26 PM PDT 24
Finished Jul 10 05:34:12 PM PDT 24
Peak memory 257112 kb
Host smart-30a18fab-26ec-4134-be02-fa5142f26d90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36034
54846 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_alert_accum.3603454846
Directory /workspace/46.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/46.alert_handler_esc_intr_timeout.115279238
Short name T449
Test name
Test status
Simulation time 2234344809 ps
CPU time 36.24 seconds
Started Jul 10 05:32:28 PM PDT 24
Finished Jul 10 05:33:05 PM PDT 24
Peak memory 249120 kb
Host smart-34a4646d-d767-4977-b582-35c6460e3f06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11527
9238 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_intr_timeout.115279238
Directory /workspace/46.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_lpg.691166219
Short name T330
Test name
Test status
Simulation time 272251297495 ps
CPU time 2129.23 seconds
Started Jul 10 05:32:32 PM PDT 24
Finished Jul 10 06:08:02 PM PDT 24
Peak memory 282136 kb
Host smart-92de30be-9321-4727-b7da-015bfa8886c3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691166219 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg.691166219
Directory /workspace/46.alert_handler_lpg/latest

Test location /workspace/coverage/default/46.alert_handler_lpg_stub_clk.2041976242
Short name T215
Test name
Test status
Simulation time 15571757097 ps
CPU time 1332.3 seconds
Started Jul 10 05:32:32 PM PDT 24
Finished Jul 10 05:54:46 PM PDT 24
Peak memory 289708 kb
Host smart-a8e2f207-14c1-4795-a48e-36e30e00b202
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041976242 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg_stub_clk.2041976242
Directory /workspace/46.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/46.alert_handler_ping_timeout.2902978820
Short name T665
Test name
Test status
Simulation time 22549271646 ps
CPU time 242.16 seconds
Started Jul 10 05:32:32 PM PDT 24
Finished Jul 10 05:36:36 PM PDT 24
Peak memory 249344 kb
Host smart-08ba6a7e-0192-45b6-88b1-2464cc5efac2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2902978820 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_ping_timeout.2902978820
Directory /workspace/46.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_random_alerts.139980112
Short name T608
Test name
Test status
Simulation time 264779822 ps
CPU time 27.78 seconds
Started Jul 10 05:32:27 PM PDT 24
Finished Jul 10 05:32:56 PM PDT 24
Peak memory 249328 kb
Host smart-f1e7b612-093b-4c86-b3b3-6c1798f93bcf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13998
0112 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_alerts.139980112
Directory /workspace/46.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/46.alert_handler_random_classes.1997213134
Short name T223
Test name
Test status
Simulation time 258106926 ps
CPU time 16.62 seconds
Started Jul 10 05:32:28 PM PDT 24
Finished Jul 10 05:32:46 PM PDT 24
Peak memory 249292 kb
Host smart-708079a7-cab7-4d24-9061-676ae2b1d990
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19972
13134 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_classes.1997213134
Directory /workspace/46.alert_handler_random_classes/latest

Test location /workspace/coverage/default/46.alert_handler_sig_int_fail.738429869
Short name T70
Test name
Test status
Simulation time 16652459209 ps
CPU time 61.56 seconds
Started Jul 10 05:32:29 PM PDT 24
Finished Jul 10 05:33:31 PM PDT 24
Peak memory 249312 kb
Host smart-8db5c31a-fbfe-4d4b-8d14-a86e82e494e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73842
9869 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_sig_int_fail.738429869
Directory /workspace/46.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/46.alert_handler_smoke.3926519942
Short name T460
Test name
Test status
Simulation time 667786474 ps
CPU time 41.2 seconds
Started Jul 10 05:32:27 PM PDT 24
Finished Jul 10 05:33:09 PM PDT 24
Peak memory 257064 kb
Host smart-f6ab0388-6885-4031-ac88-c0e2c3f5f7fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39265
19942 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_smoke.3926519942
Directory /workspace/46.alert_handler_smoke/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all.2824087899
Short name T247
Test name
Test status
Simulation time 10395334613 ps
CPU time 822.97 seconds
Started Jul 10 05:32:37 PM PDT 24
Finished Jul 10 05:46:21 PM PDT 24
Peak memory 273908 kb
Host smart-20f58f18-8555-4319-84a3-4645123b294f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824087899 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_ha
ndler_stress_all.2824087899
Directory /workspace/46.alert_handler_stress_all/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all_with_rand_reset.2407605017
Short name T690
Test name
Test status
Simulation time 149713025966 ps
CPU time 3680.5 seconds
Started Jul 10 05:32:39 PM PDT 24
Finished Jul 10 06:34:00 PM PDT 24
Peak memory 322240 kb
Host smart-c6bc0f80-330d-426f-9aa8-34ce3926977e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407605017 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 46.alert_handler_stress_all_with_rand_reset.2407605017
Directory /workspace/46.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.alert_handler_entropy.4186718697
Short name T588
Test name
Test status
Simulation time 18902608070 ps
CPU time 1452.13 seconds
Started Jul 10 05:32:45 PM PDT 24
Finished Jul 10 05:56:58 PM PDT 24
Peak memory 290348 kb
Host smart-b4291507-bd5b-4c7e-bf47-fbe55e2bba61
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186718697 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_entropy.4186718697
Directory /workspace/47.alert_handler_entropy/latest

Test location /workspace/coverage/default/47.alert_handler_esc_alert_accum.2528118470
Short name T650
Test name
Test status
Simulation time 19837758309 ps
CPU time 272.33 seconds
Started Jul 10 05:32:43 PM PDT 24
Finished Jul 10 05:37:16 PM PDT 24
Peak memory 252636 kb
Host smart-8558fa0f-b601-4671-8628-b3359386646b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25281
18470 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_alert_accum.2528118470
Directory /workspace/47.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/47.alert_handler_esc_intr_timeout.115324078
Short name T189
Test name
Test status
Simulation time 267661526 ps
CPU time 8.96 seconds
Started Jul 10 05:32:39 PM PDT 24
Finished Jul 10 05:32:48 PM PDT 24
Peak memory 248736 kb
Host smart-2fdf717c-a697-47c6-ac24-67f6062ffb75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11532
4078 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_intr_timeout.115324078
Directory /workspace/47.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_lpg.3974227147
Short name T331
Test name
Test status
Simulation time 17072484541 ps
CPU time 1669.8 seconds
Started Jul 10 05:32:46 PM PDT 24
Finished Jul 10 06:00:36 PM PDT 24
Peak memory 290304 kb
Host smart-6aa5dd20-fa4d-4a58-8060-0f31a35126e0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974227147 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg.3974227147
Directory /workspace/47.alert_handler_lpg/latest

Test location /workspace/coverage/default/47.alert_handler_lpg_stub_clk.1400527502
Short name T610
Test name
Test status
Simulation time 10180919398 ps
CPU time 1069.81 seconds
Started Jul 10 05:32:52 PM PDT 24
Finished Jul 10 05:50:43 PM PDT 24
Peak memory 290160 kb
Host smart-dafd5edd-454f-4377-bef1-aeed04b22bd2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1400527502 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg_stub_clk.1400527502
Directory /workspace/47.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/47.alert_handler_ping_timeout.558286664
Short name T194
Test name
Test status
Simulation time 19838562669 ps
CPU time 216.12 seconds
Started Jul 10 05:32:45 PM PDT 24
Finished Jul 10 05:36:21 PM PDT 24
Peak memory 248236 kb
Host smart-9489a437-8e05-43ee-8834-41a1157d6c78
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=558286664 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_ping_timeout.558286664
Directory /workspace/47.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_random_alerts.2884128072
Short name T698
Test name
Test status
Simulation time 740669914 ps
CPU time 35.93 seconds
Started Jul 10 05:32:38 PM PDT 24
Finished Jul 10 05:33:15 PM PDT 24
Peak memory 256644 kb
Host smart-62a04681-e1fd-48d7-b214-25da211a861e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28841
28072 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_alerts.2884128072
Directory /workspace/47.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/47.alert_handler_random_classes.2767361985
Short name T283
Test name
Test status
Simulation time 341721770 ps
CPU time 17.78 seconds
Started Jul 10 05:32:40 PM PDT 24
Finished Jul 10 05:32:58 PM PDT 24
Peak memory 249236 kb
Host smart-19aa9752-991b-46b3-ba9f-d4ed60806c62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27673
61985 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_classes.2767361985
Directory /workspace/47.alert_handler_random_classes/latest

Test location /workspace/coverage/default/47.alert_handler_sig_int_fail.681922865
Short name T456
Test name
Test status
Simulation time 492915778 ps
CPU time 18.02 seconds
Started Jul 10 05:32:45 PM PDT 24
Finished Jul 10 05:33:04 PM PDT 24
Peak memory 249232 kb
Host smart-e3094624-ac15-4f3d-82b0-75ea41a8cc7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68192
2865 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_sig_int_fail.681922865
Directory /workspace/47.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/47.alert_handler_smoke.2249541653
Short name T216
Test name
Test status
Simulation time 376015402 ps
CPU time 33.44 seconds
Started Jul 10 05:32:39 PM PDT 24
Finished Jul 10 05:33:13 PM PDT 24
Peak memory 257432 kb
Host smart-be609988-f4ee-4050-9e99-456aaa79d95b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22495
41653 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_smoke.2249541653
Directory /workspace/47.alert_handler_smoke/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all.2919232711
Short name T639
Test name
Test status
Simulation time 3128049804 ps
CPU time 167.24 seconds
Started Jul 10 05:32:55 PM PDT 24
Finished Jul 10 05:35:43 PM PDT 24
Peak memory 257516 kb
Host smart-5ffc3e6c-25fc-4252-a473-f78d79614bbb
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919232711 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_ha
ndler_stress_all.2919232711
Directory /workspace/47.alert_handler_stress_all/latest

Test location /workspace/coverage/default/48.alert_handler_entropy.2820541960
Short name T453
Test name
Test status
Simulation time 9726821600 ps
CPU time 902.67 seconds
Started Jul 10 05:33:03 PM PDT 24
Finished Jul 10 05:48:07 PM PDT 24
Peak memory 266844 kb
Host smart-ee0c90e7-c3c9-4289-b601-5d2fcd8a4f10
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2820541960 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_entropy.2820541960
Directory /workspace/48.alert_handler_entropy/latest

Test location /workspace/coverage/default/48.alert_handler_esc_alert_accum.477404952
Short name T218
Test name
Test status
Simulation time 393380662 ps
CPU time 25.12 seconds
Started Jul 10 05:33:03 PM PDT 24
Finished Jul 10 05:33:29 PM PDT 24
Peak memory 256760 kb
Host smart-6d614c31-dd5b-4fee-97af-7e002ce055f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47740
4952 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_alert_accum.477404952
Directory /workspace/48.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/48.alert_handler_esc_intr_timeout.1653554514
Short name T560
Test name
Test status
Simulation time 734022375 ps
CPU time 32.41 seconds
Started Jul 10 05:32:59 PM PDT 24
Finished Jul 10 05:33:32 PM PDT 24
Peak memory 256540 kb
Host smart-d86530da-3f43-47c6-b88b-d13d011ce18d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16535
54514 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_intr_timeout.1653554514
Directory /workspace/48.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_lpg_stub_clk.3282523389
Short name T466
Test name
Test status
Simulation time 17460473131 ps
CPU time 1065.71 seconds
Started Jul 10 05:33:04 PM PDT 24
Finished Jul 10 05:50:51 PM PDT 24
Peak memory 265788 kb
Host smart-b269df48-ed4d-4e8b-9347-acc84ba6e7b6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282523389 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg_stub_clk.3282523389
Directory /workspace/48.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/48.alert_handler_ping_timeout.2853242785
Short name T484
Test name
Test status
Simulation time 20790636628 ps
CPU time 228.72 seconds
Started Jul 10 05:32:59 PM PDT 24
Finished Jul 10 05:36:49 PM PDT 24
Peak memory 249380 kb
Host smart-83b28691-c2e8-4f17-bc51-dd443e019db0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853242785 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_ping_timeout.2853242785
Directory /workspace/48.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_random_alerts.1556603520
Short name T528
Test name
Test status
Simulation time 833317287 ps
CPU time 53.67 seconds
Started Jul 10 05:33:00 PM PDT 24
Finished Jul 10 05:33:54 PM PDT 24
Peak memory 257404 kb
Host smart-a31b1fe3-9166-4928-bcd6-ee04b330fe33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15566
03520 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_alerts.1556603520
Directory /workspace/48.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/48.alert_handler_random_classes.1395380548
Short name T369
Test name
Test status
Simulation time 56957270 ps
CPU time 6.49 seconds
Started Jul 10 05:32:59 PM PDT 24
Finished Jul 10 05:33:07 PM PDT 24
Peak memory 252900 kb
Host smart-27cc2b95-a54a-4d4f-a878-8db4e8effa51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13953
80548 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_classes.1395380548
Directory /workspace/48.alert_handler_random_classes/latest

Test location /workspace/coverage/default/48.alert_handler_sig_int_fail.2978405279
Short name T263
Test name
Test status
Simulation time 1748701042 ps
CPU time 25.12 seconds
Started Jul 10 05:32:58 PM PDT 24
Finished Jul 10 05:33:24 PM PDT 24
Peak memory 256684 kb
Host smart-8b6f1ce3-0760-4f9c-85a6-105844cd82fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29784
05279 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_sig_int_fail.2978405279
Directory /workspace/48.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/48.alert_handler_smoke.499440458
Short name T286
Test name
Test status
Simulation time 994046367 ps
CPU time 9.27 seconds
Started Jul 10 05:32:51 PM PDT 24
Finished Jul 10 05:33:01 PM PDT 24
Peak memory 256032 kb
Host smart-2b4d964f-ed28-4453-9cf8-ab614c895951
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49944
0458 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_smoke.499440458
Directory /workspace/48.alert_handler_smoke/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all_with_rand_reset.3667581166
Short name T256
Test name
Test status
Simulation time 23153491417 ps
CPU time 1475.84 seconds
Started Jul 10 05:33:06 PM PDT 24
Finished Jul 10 05:57:43 PM PDT 24
Peak memory 285956 kb
Host smart-a65b876b-fc48-435c-9c4e-ec9d4a73a065
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667581166 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 48.alert_handler_stress_all_with_rand_reset.3667581166
Directory /workspace/48.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.alert_handler_entropy.1364354162
Short name T643
Test name
Test status
Simulation time 88520585898 ps
CPU time 1138.97 seconds
Started Jul 10 05:33:18 PM PDT 24
Finished Jul 10 05:52:18 PM PDT 24
Peak memory 286052 kb
Host smart-0e3c189f-56e9-4a2d-8963-65d6a637639a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1364354162 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_entropy.1364354162
Directory /workspace/49.alert_handler_entropy/latest

Test location /workspace/coverage/default/49.alert_handler_esc_alert_accum.3880870283
Short name T544
Test name
Test status
Simulation time 184590446 ps
CPU time 19.31 seconds
Started Jul 10 05:33:12 PM PDT 24
Finished Jul 10 05:33:32 PM PDT 24
Peak memory 257404 kb
Host smart-439c4ab6-1b06-4e87-93d9-63d672eaddb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38808
70283 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_alert_accum.3880870283
Directory /workspace/49.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/49.alert_handler_esc_intr_timeout.1949791175
Short name T606
Test name
Test status
Simulation time 30256035 ps
CPU time 5.21 seconds
Started Jul 10 05:33:10 PM PDT 24
Finished Jul 10 05:33:17 PM PDT 24
Peak memory 252136 kb
Host smart-dfaa59a7-c6de-4529-90f9-2c0b30ea6516
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19497
91175 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_intr_timeout.1949791175
Directory /workspace/49.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_lpg.3046999492
Short name T697
Test name
Test status
Simulation time 87210480839 ps
CPU time 1544.77 seconds
Started Jul 10 05:33:16 PM PDT 24
Finished Jul 10 05:59:02 PM PDT 24
Peak memory 273916 kb
Host smart-0edff716-5ee1-4f68-9ea3-bf95f0be2046
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3046999492 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg.3046999492
Directory /workspace/49.alert_handler_lpg/latest

Test location /workspace/coverage/default/49.alert_handler_lpg_stub_clk.2583373836
Short name T589
Test name
Test status
Simulation time 166928944299 ps
CPU time 2393.22 seconds
Started Jul 10 05:33:24 PM PDT 24
Finished Jul 10 06:13:18 PM PDT 24
Peak memory 289872 kb
Host smart-1e9d8ff1-2408-411d-a8cd-090ec30deca4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583373836 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg_stub_clk.2583373836
Directory /workspace/49.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/49.alert_handler_random_alerts.2023846068
Short name T648
Test name
Test status
Simulation time 181832899 ps
CPU time 21.14 seconds
Started Jul 10 05:33:04 PM PDT 24
Finished Jul 10 05:33:26 PM PDT 24
Peak memory 256464 kb
Host smart-144edc60-4422-4914-860a-709003cc20ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20238
46068 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_alerts.2023846068
Directory /workspace/49.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/49.alert_handler_random_classes.1466703205
Short name T410
Test name
Test status
Simulation time 677581920 ps
CPU time 40.55 seconds
Started Jul 10 05:33:09 PM PDT 24
Finished Jul 10 05:33:50 PM PDT 24
Peak memory 256712 kb
Host smart-85db6091-2442-48d4-9da4-3ed10f45edd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14667
03205 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_classes.1466703205
Directory /workspace/49.alert_handler_random_classes/latest

Test location /workspace/coverage/default/49.alert_handler_sig_int_fail.3852297891
Short name T613
Test name
Test status
Simulation time 1275485076 ps
CPU time 15.24 seconds
Started Jul 10 05:33:12 PM PDT 24
Finished Jul 10 05:33:27 PM PDT 24
Peak memory 255428 kb
Host smart-f2f30912-38ca-4861-96a2-3168fdba7486
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38522
97891 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_sig_int_fail.3852297891
Directory /workspace/49.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/49.alert_handler_smoke.3752207427
Short name T421
Test name
Test status
Simulation time 657026601 ps
CPU time 10.51 seconds
Started Jul 10 05:33:05 PM PDT 24
Finished Jul 10 05:33:16 PM PDT 24
Peak memory 249436 kb
Host smart-4ebaba2f-1793-435f-b165-0c6bd9eb2bae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37522
07427 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_smoke.3752207427
Directory /workspace/49.alert_handler_smoke/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all.816612435
Short name T607
Test name
Test status
Simulation time 74602506698 ps
CPU time 1318.19 seconds
Started Jul 10 05:33:22 PM PDT 24
Finished Jul 10 05:55:21 PM PDT 24
Peak memory 290372 kb
Host smart-9b4811aa-0b63-40d2-8967-9d19e594098c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816612435 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_han
dler_stress_all.816612435
Directory /workspace/49.alert_handler_stress_all/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all_with_rand_reset.3590232415
Short name T629
Test name
Test status
Simulation time 31734784488 ps
CPU time 3331.72 seconds
Started Jul 10 05:33:23 PM PDT 24
Finished Jul 10 06:28:56 PM PDT 24
Peak memory 322668 kb
Host smart-3eb5c9ac-f1ff-456c-a176-8f28cd1e9ed8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590232415 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 49.alert_handler_stress_all_with_rand_reset.3590232415
Directory /workspace/49.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.alert_handler_alert_accum_saturation.1056798403
Short name T174
Test name
Test status
Simulation time 128786700 ps
CPU time 3.46 seconds
Started Jul 10 05:27:34 PM PDT 24
Finished Jul 10 05:27:40 PM PDT 24
Peak memory 249444 kb
Host smart-d47c85ac-175f-40df-98c6-3b0899b9fd25
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1056798403 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_alert_accum_saturation.1056798403
Directory /workspace/5.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/5.alert_handler_entropy.530376051
Short name T547
Test name
Test status
Simulation time 51611687146 ps
CPU time 2849.75 seconds
Started Jul 10 05:27:35 PM PDT 24
Finished Jul 10 06:15:07 PM PDT 24
Peak memory 290336 kb
Host smart-9d6ed6cd-f448-4bec-98e8-c17b2bb5eeef
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530376051 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy.530376051
Directory /workspace/5.alert_handler_entropy/latest

Test location /workspace/coverage/default/5.alert_handler_entropy_stress.1692617150
Short name T614
Test name
Test status
Simulation time 596647863 ps
CPU time 27.29 seconds
Started Jul 10 05:27:30 PM PDT 24
Finished Jul 10 05:27:59 PM PDT 24
Peak memory 249292 kb
Host smart-2e438ac4-e7c2-47a7-b2a4-a216c42f2ac7
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1692617150 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy_stress.1692617150
Directory /workspace/5.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/5.alert_handler_esc_alert_accum.3862341742
Short name T485
Test name
Test status
Simulation time 12450386394 ps
CPU time 210.97 seconds
Started Jul 10 05:27:30 PM PDT 24
Finished Jul 10 05:31:03 PM PDT 24
Peak memory 257100 kb
Host smart-dcd14082-75d9-461f-9f56-c9557e0abe96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38623
41742 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_alert_accum.3862341742
Directory /workspace/5.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/5.alert_handler_esc_intr_timeout.3750143652
Short name T581
Test name
Test status
Simulation time 3327358483 ps
CPU time 51.1 seconds
Started Jul 10 05:27:34 PM PDT 24
Finished Jul 10 05:28:27 PM PDT 24
Peak memory 256676 kb
Host smart-8e89e71c-be3f-4262-b188-cdcf05824738
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37501
43652 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_intr_timeout.3750143652
Directory /workspace/5.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_lpg.21641003
Short name T229
Test name
Test status
Simulation time 138584900091 ps
CPU time 2145.3 seconds
Started Jul 10 05:27:30 PM PDT 24
Finished Jul 10 06:03:18 PM PDT 24
Peak memory 273404 kb
Host smart-5944221c-de4d-4b36-a844-d797aa02108c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21641003 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg.21641003
Directory /workspace/5.alert_handler_lpg/latest

Test location /workspace/coverage/default/5.alert_handler_lpg_stub_clk.228015219
Short name T676
Test name
Test status
Simulation time 87729921920 ps
CPU time 2539.49 seconds
Started Jul 10 05:27:33 PM PDT 24
Finished Jul 10 06:09:55 PM PDT 24
Peak memory 289540 kb
Host smart-87739423-169e-4d32-bcd4-3659cc3bb3c0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228015219 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg_stub_clk.228015219
Directory /workspace/5.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/5.alert_handler_ping_timeout.673956176
Short name T499
Test name
Test status
Simulation time 2679522096 ps
CPU time 110.95 seconds
Started Jul 10 05:27:33 PM PDT 24
Finished Jul 10 05:29:26 PM PDT 24
Peak memory 249368 kb
Host smart-85bd92ea-bdef-4cb3-b088-63b91d506a2f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673956176 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_ping_timeout.673956176
Directory /workspace/5.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_random_alerts.2211887577
Short name T347
Test name
Test status
Simulation time 1357482761 ps
CPU time 22.68 seconds
Started Jul 10 05:27:30 PM PDT 24
Finished Jul 10 05:27:55 PM PDT 24
Peak memory 256720 kb
Host smart-10ff4dae-0565-42fd-99eb-a25bf40605d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22118
87577 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_alerts.2211887577
Directory /workspace/5.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/5.alert_handler_random_classes.2098744272
Short name T622
Test name
Test status
Simulation time 1668650557 ps
CPU time 54.41 seconds
Started Jul 10 05:27:30 PM PDT 24
Finished Jul 10 05:28:26 PM PDT 24
Peak memory 256988 kb
Host smart-8b626fe4-a649-4649-8417-12b2acb626fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20987
44272 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_classes.2098744272
Directory /workspace/5.alert_handler_random_classes/latest

Test location /workspace/coverage/default/5.alert_handler_sig_int_fail.1944658645
Short name T88
Test name
Test status
Simulation time 2559860881 ps
CPU time 47.33 seconds
Started Jul 10 05:27:33 PM PDT 24
Finished Jul 10 05:28:22 PM PDT 24
Peak memory 249328 kb
Host smart-753760b8-d7b4-4729-8100-8b67e28b0eb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19446
58645 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_sig_int_fail.1944658645
Directory /workspace/5.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/5.alert_handler_smoke.2833553451
Short name T353
Test name
Test status
Simulation time 2814341532 ps
CPU time 41.21 seconds
Started Jul 10 05:27:30 PM PDT 24
Finished Jul 10 05:28:13 PM PDT 24
Peak memory 249580 kb
Host smart-8115c353-dcaf-4fc4-a338-0a6db4b179b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28335
53451 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_smoke.2833553451
Directory /workspace/5.alert_handler_smoke/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all.1469101476
Short name T170
Test name
Test status
Simulation time 146869536315 ps
CPU time 2455.04 seconds
Started Jul 10 05:27:33 PM PDT 24
Finished Jul 10 06:08:30 PM PDT 24
Peak memory 289716 kb
Host smart-38d4a1d9-e92e-4cd4-91a1-1cc7402a31b5
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469101476 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_han
dler_stress_all.1469101476
Directory /workspace/5.alert_handler_stress_all/latest

Test location /workspace/coverage/default/6.alert_handler_alert_accum_saturation.4056011753
Short name T198
Test name
Test status
Simulation time 48957087 ps
CPU time 3.95 seconds
Started Jul 10 05:27:36 PM PDT 24
Finished Jul 10 05:27:43 PM PDT 24
Peak memory 249496 kb
Host smart-57752fb5-3612-4590-85f2-a84ac837e028
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4056011753 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_alert_accum_saturation.4056011753
Directory /workspace/6.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/6.alert_handler_entropy.3654412982
Short name T83
Test name
Test status
Simulation time 17880869361 ps
CPU time 988.87 seconds
Started Jul 10 05:27:32 PM PDT 24
Finished Jul 10 05:44:02 PM PDT 24
Peak memory 273428 kb
Host smart-74371628-8a2c-49c6-af34-618f55c96806
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654412982 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy.3654412982
Directory /workspace/6.alert_handler_entropy/latest

Test location /workspace/coverage/default/6.alert_handler_entropy_stress.3411461775
Short name T655
Test name
Test status
Simulation time 1041854978 ps
CPU time 13.5 seconds
Started Jul 10 05:27:31 PM PDT 24
Finished Jul 10 05:27:47 PM PDT 24
Peak memory 249200 kb
Host smart-5f7d18e1-e33d-4499-af6c-4e7771e1ad70
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3411461775 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy_stress.3411461775
Directory /workspace/6.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/6.alert_handler_esc_alert_accum.1564068862
Short name T518
Test name
Test status
Simulation time 3460418185 ps
CPU time 150.74 seconds
Started Jul 10 05:27:35 PM PDT 24
Finished Jul 10 05:30:10 PM PDT 24
Peak memory 257556 kb
Host smart-9d969d0b-3d81-4d04-a3f9-730059cdb1f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15640
68862 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_alert_accum.1564068862
Directory /workspace/6.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/6.alert_handler_esc_intr_timeout.3604319105
Short name T376
Test name
Test status
Simulation time 201182931 ps
CPU time 13.45 seconds
Started Jul 10 05:27:29 PM PDT 24
Finished Jul 10 05:27:45 PM PDT 24
Peak memory 248780 kb
Host smart-3f457caa-d3e7-40c9-b314-81507bacef8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36043
19105 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_intr_timeout.3604319105
Directory /workspace/6.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_lpg.600289801
Short name T319
Test name
Test status
Simulation time 133115813454 ps
CPU time 2082.98 seconds
Started Jul 10 05:27:33 PM PDT 24
Finished Jul 10 06:02:18 PM PDT 24
Peak memory 285540 kb
Host smart-e80fe8f1-8f04-467b-900f-4f19993fc73a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600289801 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg.600289801
Directory /workspace/6.alert_handler_lpg/latest

Test location /workspace/coverage/default/6.alert_handler_lpg_stub_clk.2765341952
Short name T420
Test name
Test status
Simulation time 31410354546 ps
CPU time 1847.38 seconds
Started Jul 10 05:27:34 PM PDT 24
Finished Jul 10 05:58:23 PM PDT 24
Peak memory 273900 kb
Host smart-c35307a9-19b8-4d8c-9e2b-59566cfd9b6e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765341952 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg_stub_clk.2765341952
Directory /workspace/6.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/6.alert_handler_ping_timeout.2069985206
Short name T7
Test name
Test status
Simulation time 162372314151 ps
CPU time 408.7 seconds
Started Jul 10 05:27:32 PM PDT 24
Finished Jul 10 05:34:22 PM PDT 24
Peak memory 249208 kb
Host smart-7e1e01b4-85e9-4ef4-b2f0-72f8400b056b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069985206 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_ping_timeout.2069985206
Directory /workspace/6.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_random_alerts.1039317185
Short name T604
Test name
Test status
Simulation time 603951795 ps
CPU time 26.33 seconds
Started Jul 10 05:27:30 PM PDT 24
Finished Jul 10 05:27:59 PM PDT 24
Peak memory 256540 kb
Host smart-6ddad5d6-df06-434f-adac-aa74486a900f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10393
17185 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_alerts.1039317185
Directory /workspace/6.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/6.alert_handler_random_classes.451158230
Short name T696
Test name
Test status
Simulation time 260988668 ps
CPU time 26.13 seconds
Started Jul 10 05:27:31 PM PDT 24
Finished Jul 10 05:27:59 PM PDT 24
Peak memory 256660 kb
Host smart-11921c45-961b-43ee-9e6b-750c01882526
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45115
8230 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_classes.451158230
Directory /workspace/6.alert_handler_random_classes/latest

Test location /workspace/coverage/default/6.alert_handler_sig_int_fail.4098397679
Short name T668
Test name
Test status
Simulation time 556197950 ps
CPU time 16.83 seconds
Started Jul 10 05:27:34 PM PDT 24
Finished Jul 10 05:27:53 PM PDT 24
Peak memory 249216 kb
Host smart-bbaa11d2-afe2-4ef9-9edc-61a7b17a5fc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40983
97679 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_sig_int_fail.4098397679
Directory /workspace/6.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/6.alert_handler_smoke.156950779
Short name T532
Test name
Test status
Simulation time 1562663231 ps
CPU time 34.12 seconds
Started Jul 10 05:27:31 PM PDT 24
Finished Jul 10 05:28:07 PM PDT 24
Peak memory 249320 kb
Host smart-7eb6a741-81b5-4e66-8916-c44c9e1056c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15695
0779 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_smoke.156950779
Directory /workspace/6.alert_handler_smoke/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all.503406578
Short name T401
Test name
Test status
Simulation time 1111573329 ps
CPU time 102.84 seconds
Started Jul 10 05:27:32 PM PDT 24
Finished Jul 10 05:29:16 PM PDT 24
Peak memory 257412 kb
Host smart-137d0f5f-d81d-447d-8019-014a5db7c216
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503406578 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_hand
ler_stress_all.503406578
Directory /workspace/6.alert_handler_stress_all/latest

Test location /workspace/coverage/default/7.alert_handler_alert_accum_saturation.395357219
Short name T204
Test name
Test status
Simulation time 132698383 ps
CPU time 3.46 seconds
Started Jul 10 05:27:35 PM PDT 24
Finished Jul 10 05:27:42 PM PDT 24
Peak memory 249524 kb
Host smart-59282a0a-0047-4b7e-a4f6-a45beff4cb66
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=395357219 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_alert_accum_saturation.395357219
Directory /workspace/7.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/7.alert_handler_entropy.2859136053
Short name T479
Test name
Test status
Simulation time 30270954969 ps
CPU time 1646.37 seconds
Started Jul 10 05:27:35 PM PDT 24
Finished Jul 10 05:55:04 PM PDT 24
Peak memory 273916 kb
Host smart-0ee52394-eb18-4352-bb2c-ab5ceccbb829
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859136053 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy.2859136053
Directory /workspace/7.alert_handler_entropy/latest

Test location /workspace/coverage/default/7.alert_handler_entropy_stress.2286579152
Short name T597
Test name
Test status
Simulation time 400111689 ps
CPU time 13.02 seconds
Started Jul 10 05:27:36 PM PDT 24
Finished Jul 10 05:27:52 PM PDT 24
Peak memory 249264 kb
Host smart-cb3c6550-75bb-4cbe-9fa7-0ccd7aeac2d3
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2286579152 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy_stress.2286579152
Directory /workspace/7.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/7.alert_handler_esc_alert_accum.1191198424
Short name T645
Test name
Test status
Simulation time 970089269 ps
CPU time 73.46 seconds
Started Jul 10 05:27:36 PM PDT 24
Finished Jul 10 05:28:53 PM PDT 24
Peak memory 250320 kb
Host smart-d4594682-1123-4df5-897c-74f458ba0069
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11911
98424 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_alert_accum.1191198424
Directory /workspace/7.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/7.alert_handler_esc_intr_timeout.2831542554
Short name T428
Test name
Test status
Simulation time 4043197453 ps
CPU time 61.96 seconds
Started Jul 10 05:27:34 PM PDT 24
Finished Jul 10 05:28:39 PM PDT 24
Peak memory 257596 kb
Host smart-b4a58c35-0d2f-4a7a-9923-6d01138e9ee4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28315
42554 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_intr_timeout.2831542554
Directory /workspace/7.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_lpg.2215388273
Short name T300
Test name
Test status
Simulation time 22815996339 ps
CPU time 1400.71 seconds
Started Jul 10 05:27:42 PM PDT 24
Finished Jul 10 05:51:06 PM PDT 24
Peak memory 273592 kb
Host smart-03d7915e-a154-40bc-8889-b8fefd8730aa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215388273 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg.2215388273
Directory /workspace/7.alert_handler_lpg/latest

Test location /workspace/coverage/default/7.alert_handler_lpg_stub_clk.2726031332
Short name T509
Test name
Test status
Simulation time 104126441336 ps
CPU time 1760.35 seconds
Started Jul 10 05:27:41 PM PDT 24
Finished Jul 10 05:57:04 PM PDT 24
Peak memory 273972 kb
Host smart-cd4df6d6-029e-46d6-b712-412e708768f2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726031332 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg_stub_clk.2726031332
Directory /workspace/7.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/7.alert_handler_ping_timeout.2402507507
Short name T313
Test name
Test status
Simulation time 7879043308 ps
CPU time 325.63 seconds
Started Jul 10 05:27:42 PM PDT 24
Finished Jul 10 05:33:11 PM PDT 24
Peak memory 249396 kb
Host smart-c168d099-bd34-4b3f-b37c-fbf1374ee8a7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2402507507 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_ping_timeout.2402507507
Directory /workspace/7.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_random_alerts.3594373147
Short name T214
Test name
Test status
Simulation time 317607761 ps
CPU time 7.24 seconds
Started Jul 10 05:27:35 PM PDT 24
Finished Jul 10 05:27:46 PM PDT 24
Peak memory 249204 kb
Host smart-062941e3-b3f9-429a-8a19-619ffb47f80c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35943
73147 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_alerts.3594373147
Directory /workspace/7.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/7.alert_handler_random_classes.2315096509
Short name T586
Test name
Test status
Simulation time 3447974612 ps
CPU time 46.22 seconds
Started Jul 10 05:27:35 PM PDT 24
Finished Jul 10 05:28:23 PM PDT 24
Peak memory 249388 kb
Host smart-2a982da6-febd-4880-b877-c8a66faf92e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23150
96509 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_classes.2315096509
Directory /workspace/7.alert_handler_random_classes/latest

Test location /workspace/coverage/default/7.alert_handler_sig_int_fail.1181378570
Short name T69
Test name
Test status
Simulation time 748945615 ps
CPU time 12.4 seconds
Started Jul 10 05:27:37 PM PDT 24
Finished Jul 10 05:27:53 PM PDT 24
Peak memory 249284 kb
Host smart-095a99bd-9d10-48d0-8212-603875d4606e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11813
78570 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_sig_int_fail.1181378570
Directory /workspace/7.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/7.alert_handler_smoke.22569660
Short name T430
Test name
Test status
Simulation time 252891710 ps
CPU time 26.87 seconds
Started Jul 10 05:27:32 PM PDT 24
Finished Jul 10 05:28:00 PM PDT 24
Peak memory 257252 kb
Host smart-8411aeaa-c25a-4cb4-add9-14f1081513e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22569
660 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_smoke.22569660
Directory /workspace/7.alert_handler_smoke/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all.2677482932
Short name T482
Test name
Test status
Simulation time 88410685761 ps
CPU time 2683.18 seconds
Started Jul 10 05:27:38 PM PDT 24
Finished Jul 10 06:12:24 PM PDT 24
Peak memory 288272 kb
Host smart-4170daae-5cf8-45a2-afbf-92b84c33041c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677482932 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_han
dler_stress_all.2677482932
Directory /workspace/7.alert_handler_stress_all/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all_with_rand_reset.310482095
Short name T261
Test name
Test status
Simulation time 235337332371 ps
CPU time 5031.11 seconds
Started Jul 10 05:27:35 PM PDT 24
Finished Jul 10 06:51:29 PM PDT 24
Peak memory 316440 kb
Host smart-718116fc-c4bc-4116-9e37-140a7b1e17d7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310482095 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 7.alert_handler_stress_all_with_rand_reset.310482095
Directory /workspace/7.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.alert_handler_alert_accum_saturation.1701645382
Short name T207
Test name
Test status
Simulation time 46771365 ps
CPU time 4.17 seconds
Started Jul 10 05:27:42 PM PDT 24
Finished Jul 10 05:27:49 PM PDT 24
Peak memory 249532 kb
Host smart-79fb273e-6b97-4168-9f84-e5956cbca7cc
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1701645382 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_alert_accum_saturation.1701645382
Directory /workspace/8.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/8.alert_handler_entropy.3090689791
Short name T58
Test name
Test status
Simulation time 15914808803 ps
CPU time 1572.61 seconds
Started Jul 10 05:27:34 PM PDT 24
Finished Jul 10 05:53:50 PM PDT 24
Peak memory 289936 kb
Host smart-7c0862ab-14af-447c-9abf-8ab1e2da0b02
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090689791 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy.3090689791
Directory /workspace/8.alert_handler_entropy/latest

Test location /workspace/coverage/default/8.alert_handler_entropy_stress.1201194987
Short name T429
Test name
Test status
Simulation time 756605215 ps
CPU time 30.86 seconds
Started Jul 10 05:27:35 PM PDT 24
Finished Jul 10 05:28:09 PM PDT 24
Peak memory 249208 kb
Host smart-4864fb65-2cf0-4820-a0b0-47c9d7537638
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1201194987 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy_stress.1201194987
Directory /workspace/8.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/8.alert_handler_esc_alert_accum.2989366939
Short name T523
Test name
Test status
Simulation time 6144620101 ps
CPU time 103.32 seconds
Started Jul 10 05:27:42 PM PDT 24
Finished Jul 10 05:29:29 PM PDT 24
Peak memory 256684 kb
Host smart-5540caeb-5b77-43d4-b161-acfeadfe4601
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29893
66939 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_alert_accum.2989366939
Directory /workspace/8.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/8.alert_handler_esc_intr_timeout.3925252371
Short name T192
Test name
Test status
Simulation time 413399741 ps
CPU time 24.15 seconds
Started Jul 10 05:27:38 PM PDT 24
Finished Jul 10 05:28:05 PM PDT 24
Peak memory 248740 kb
Host smart-d0a23856-7a0b-4388-89cf-5777767a9fa3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39252
52371 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_intr_timeout.3925252371
Directory /workspace/8.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_lpg.556369103
Short name T575
Test name
Test status
Simulation time 14717474906 ps
CPU time 1156.38 seconds
Started Jul 10 05:27:38 PM PDT 24
Finished Jul 10 05:46:57 PM PDT 24
Peak memory 289532 kb
Host smart-18a4da6b-ac72-4505-954f-f5333650b46b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556369103 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg.556369103
Directory /workspace/8.alert_handler_lpg/latest

Test location /workspace/coverage/default/8.alert_handler_lpg_stub_clk.2852553897
Short name T661
Test name
Test status
Simulation time 487071679442 ps
CPU time 3093.95 seconds
Started Jul 10 05:27:41 PM PDT 24
Finished Jul 10 06:19:18 PM PDT 24
Peak memory 289984 kb
Host smart-15cda5cc-6727-49aa-b593-b1a4b84ced75
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852553897 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg_stub_clk.2852553897
Directory /workspace/8.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/8.alert_handler_ping_timeout.2228750930
Short name T402
Test name
Test status
Simulation time 9060648453 ps
CPU time 369.18 seconds
Started Jul 10 05:27:37 PM PDT 24
Finished Jul 10 05:33:50 PM PDT 24
Peak memory 257540 kb
Host smart-50c9a3c0-d57a-43b9-a940-117fae7cf5fc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228750930 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_ping_timeout.2228750930
Directory /workspace/8.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_random_alerts.3171084293
Short name T671
Test name
Test status
Simulation time 583076765 ps
CPU time 23.81 seconds
Started Jul 10 05:27:35 PM PDT 24
Finished Jul 10 05:28:02 PM PDT 24
Peak memory 249264 kb
Host smart-755ed1f5-e19f-4b17-af47-29ee1a852e5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31710
84293 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_alerts.3171084293
Directory /workspace/8.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/8.alert_handler_random_classes.3282040648
Short name T441
Test name
Test status
Simulation time 4662659199 ps
CPU time 70.61 seconds
Started Jul 10 05:27:37 PM PDT 24
Finished Jul 10 05:28:51 PM PDT 24
Peak memory 250344 kb
Host smart-a9b63b2c-b70c-4214-bf6f-6e6fc00f4662
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32820
40648 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_classes.3282040648
Directory /workspace/8.alert_handler_random_classes/latest

Test location /workspace/coverage/default/8.alert_handler_sig_int_fail.433487268
Short name T649
Test name
Test status
Simulation time 314804005 ps
CPU time 21.44 seconds
Started Jul 10 05:27:40 PM PDT 24
Finished Jul 10 05:28:04 PM PDT 24
Peak memory 256964 kb
Host smart-fea67428-1aa8-403a-a559-ffa5f536bff6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43348
7268 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_sig_int_fail.433487268
Directory /workspace/8.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/8.alert_handler_smoke.3275949163
Short name T471
Test name
Test status
Simulation time 134227080 ps
CPU time 4.13 seconds
Started Jul 10 05:27:42 PM PDT 24
Finished Jul 10 05:27:50 PM PDT 24
Peak memory 257424 kb
Host smart-78b39758-f8c5-451e-863b-c6a465772fb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32759
49163 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_smoke.3275949163
Directory /workspace/8.alert_handler_smoke/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all.462964810
Short name T255
Test name
Test status
Simulation time 217395832555 ps
CPU time 3267.66 seconds
Started Jul 10 05:27:34 PM PDT 24
Finished Jul 10 06:22:04 PM PDT 24
Peak memory 290300 kb
Host smart-497aeae6-7f2c-47a1-b4b9-ad9c2176465e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462964810 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_hand
ler_stress_all.462964810
Directory /workspace/8.alert_handler_stress_all/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all_with_rand_reset.1480889312
Short name T169
Test name
Test status
Simulation time 51700463547 ps
CPU time 4776.35 seconds
Started Jul 10 05:27:37 PM PDT 24
Finished Jul 10 06:47:17 PM PDT 24
Peak memory 351576 kb
Host smart-d0bfe573-c8a8-4a90-9d73-a562b21c4379
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480889312 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 8.alert_handler_stress_all_with_rand_reset.1480889312
Directory /workspace/8.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.alert_handler_alert_accum_saturation.2420659205
Short name T209
Test name
Test status
Simulation time 51820878 ps
CPU time 2.42 seconds
Started Jul 10 05:27:36 PM PDT 24
Finished Jul 10 05:27:42 PM PDT 24
Peak memory 249528 kb
Host smart-5eaa584a-20f2-4199-96e9-88a578e3645a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2420659205 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_alert_accum_saturation.2420659205
Directory /workspace/9.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/9.alert_handler_entropy.3524093335
Short name T222
Test name
Test status
Simulation time 22582824816 ps
CPU time 1527.25 seconds
Started Jul 10 05:27:36 PM PDT 24
Finished Jul 10 05:53:07 PM PDT 24
Peak memory 273976 kb
Host smart-3b6f1254-a85f-42b5-a2e5-2a5b00c4cbc5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524093335 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy.3524093335
Directory /workspace/9.alert_handler_entropy/latest

Test location /workspace/coverage/default/9.alert_handler_entropy_stress.2823856882
Short name T395
Test name
Test status
Simulation time 355193140 ps
CPU time 16.29 seconds
Started Jul 10 05:27:41 PM PDT 24
Finished Jul 10 05:28:00 PM PDT 24
Peak memory 249260 kb
Host smart-39d2c242-54be-45ab-a462-ba9700f7c37e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2823856882 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy_stress.2823856882
Directory /workspace/9.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/9.alert_handler_esc_alert_accum.1684011084
Short name T585
Test name
Test status
Simulation time 586281156 ps
CPU time 13.06 seconds
Started Jul 10 05:27:35 PM PDT 24
Finished Jul 10 05:27:51 PM PDT 24
Peak memory 256576 kb
Host smart-f28a7abb-9b48-4a59-a8b2-52ad8244e0c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16840
11084 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_alert_accum.1684011084
Directory /workspace/9.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/9.alert_handler_esc_intr_timeout.3193158484
Short name T65
Test name
Test status
Simulation time 3173970410 ps
CPU time 56.57 seconds
Started Jul 10 05:27:37 PM PDT 24
Finished Jul 10 05:28:37 PM PDT 24
Peak memory 249344 kb
Host smart-7bd35c27-a45c-4c7e-a714-797ffa6ece30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31931
58484 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_intr_timeout.3193158484
Directory /workspace/9.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_lpg_stub_clk.2148044165
Short name T77
Test name
Test status
Simulation time 8075477936 ps
CPU time 894.84 seconds
Started Jul 10 05:27:36 PM PDT 24
Finished Jul 10 05:42:34 PM PDT 24
Peak memory 270904 kb
Host smart-e059e2d4-6c4f-4b72-b248-21aba075be12
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148044165 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg_stub_clk.2148044165
Directory /workspace/9.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/9.alert_handler_ping_timeout.3005625956
Short name T282
Test name
Test status
Simulation time 38936332749 ps
CPU time 417.14 seconds
Started Jul 10 05:27:39 PM PDT 24
Finished Jul 10 05:34:39 PM PDT 24
Peak memory 249368 kb
Host smart-afa02d78-3d51-4358-81ac-e71fdbb95e14
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3005625956 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_ping_timeout.3005625956
Directory /workspace/9.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_random_alerts.389133555
Short name T554
Test name
Test status
Simulation time 1155263873 ps
CPU time 39.62 seconds
Started Jul 10 05:27:35 PM PDT 24
Finished Jul 10 05:28:18 PM PDT 24
Peak memory 256736 kb
Host smart-62b4a739-f07d-4e48-9cb6-9f6195e6e558
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38913
3555 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_alerts.389133555
Directory /workspace/9.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/9.alert_handler_random_classes.1644255317
Short name T360
Test name
Test status
Simulation time 790916631 ps
CPU time 13.49 seconds
Started Jul 10 05:27:35 PM PDT 24
Finished Jul 10 05:27:52 PM PDT 24
Peak memory 248628 kb
Host smart-205e55ec-1582-4dde-b7d2-40a7f55b9dea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16442
55317 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_classes.1644255317
Directory /workspace/9.alert_handler_random_classes/latest

Test location /workspace/coverage/default/9.alert_handler_sig_int_fail.3116268321
Short name T269
Test name
Test status
Simulation time 467671399 ps
CPU time 28.71 seconds
Started Jul 10 05:27:36 PM PDT 24
Finished Jul 10 05:28:08 PM PDT 24
Peak memory 257344 kb
Host smart-8b915a48-efd3-44ac-bb31-67e07ba97fb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31162
68321 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_sig_int_fail.3116268321
Directory /workspace/9.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/9.alert_handler_smoke.818893709
Short name T451
Test name
Test status
Simulation time 315397570 ps
CPU time 30.14 seconds
Started Jul 10 05:27:42 PM PDT 24
Finished Jul 10 05:28:15 PM PDT 24
Peak memory 257264 kb
Host smart-88eb0e20-00ad-4b8d-9638-b358f871a965
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81889
3709 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_smoke.818893709
Directory /workspace/9.alert_handler_smoke/latest
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