Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
esc_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	8	0	8	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	82223	1			T2	1		T7	1		T9	1
class_i[0x1]	49600	1			T7	11		T19	20		T15	104
class_i[0x2]	53688	1			T7	1		T15	1		T17	800
class_i[0x3]	56221	1			T7	2		T15	239		T17	9

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Summary for Variable esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	62753	1			T7	8		T19	1		T9	1
alert[0x1]	59244	1			T19	2		T15	1288		T17	3
alert[0x2]	58204	1			T2	1		T7	7		T19	7
alert[0x3]	61531	1			T19	10		T15	1415		T17	18

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Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

esc_integrity_fail

241472

1

T2

1

T7

11

T19

20

esc_ping_fail

260

1

T7

4

T9

1

T10

8

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Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	esc_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	alert[0x0]	62676	1			T7	6		T19	1		T15	1257
esc_integrity_fail	alert[0x1]	59176	1			T19	2		T15	1288		T17	3
esc_integrity_fail	alert[0x2]	58145	1			T2	1		T7	5		T19	7
esc_integrity_fail	alert[0x3]	61475	1			T19	10		T15	1415		T17	18
esc_ping_fail	alert[0x0]	77	1			T7	2		T9	1		T10	2
esc_ping_fail	alert[0x1]	68	1			T10	2		T39	1		T62	2
esc_ping_fail	alert[0x2]	59	1			T7	2		T10	2		T62	3
esc_ping_fail	alert[0x3]	56	1			T10	2		T39	1		T62	3

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Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	class_i[0x0]	82159	1			T2	1		T15	5012		T17	20
esc_integrity_fail	class_i[0x1]	49521	1			T7	11		T19	20		T15	104
esc_integrity_fail	class_i[0x2]	53634	1			T15	1		T17	800		T28	3590
esc_integrity_fail	class_i[0x3]	56158	1			T15	239		T17	9		T21	6
esc_ping_fail	class_i[0x0]	64	1			T7	1		T9	1		T10	8
esc_ping_fail	class_i[0x1]	79	1			T39	1		T242	2		T276	2
esc_ping_fail	class_i[0x2]	54	1			T7	1		T242	1		T276	2
esc_ping_fail	class_i[0x3]	63	1			T7	2		T39	1		T62	11