Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.31	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	44	1	43	97.73

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_sig_index_cp	4	0	4	100.00	100	1	1	0
esc_sig_len_cp	11	0	11	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
len_per_esc_sig	44	1	43	97.73	100	1	1	0

Summary for Variable esc_sig_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_sig_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
index[0x0]	156	1			T15	3		T17	1		T37	1
index[0x1]	191	1			T5	1		T20	1		T16	1
index[0x2]	170	1			T38	1		T26	1		T73	1
index[0x3]	179	1			T15	3		T22	1		T40	1

---

Summary for Variable esc_sig_len_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for esc_sig_len_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
lens_less_than_1000[0]	260	1			T5	1		T20	1		T15	3
lens_less_than_1000[1]	130	1			T17	1		T26	2		T28	1
lens_less_than_1000[2]	90	1			T17	1		T31	1		T47	1
lens_less_than_1000[3]	66	1			T15	2		T17	1		T40	1
lens_less_than_1000[4]	38	1			T16	1		T27	1		T236	1
lens_less_than_1000[5]	44	1			T22	1		T40	1		T86	1
lens_less_than_1000[6]	35	1			T33	1		T76	1		T31	1
lens_less_than_1000[7]	9	1			T48	1		T237	2		T238	1
lens_less_than_1000[8]	9	1			T15	1		T47	1		T106	1
lens_less_than_1000[9]	5	1			T104	1		T239	1		T238	1
len_2	10	1			T240	3		T105	1		T241	1

---

Summary for Cross len_per_esc_sig

Samples crossed: esc_sig_index_cp esc_sig_len_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	44	1	43	97.73	1

Automatically Generated Cross Bins for len_per_esc_sig

Uncovered bins

esc_sig_index_cp	esc_sig_len_cp	COUNT	AT LEAST	NUMBER	STATUS
[index[0x0]]	[lens_less_than_1000[8]]	0	1	1

Covered bins

esc_sig_index_cp	esc_sig_len_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
index[0x0]	lens_less_than_1000[0]	46	1			T15	2		T37	1		T26	1
index[0x0]	lens_less_than_1000[1]	32	1			T28	1		T59	1		T27	1
index[0x0]	lens_less_than_1000[2]	37	1			T17	1		T47	1		T32	1
index[0x0]	lens_less_than_1000[3]	14	1			T15	1		T40	1		T242	1
index[0x0]	lens_less_than_1000[4]	4	1			T243	2		T244	1		T245	1
index[0x0]	lens_less_than_1000[5]	12	1			T86	1		T51	1		T246	1
index[0x0]	lens_less_than_1000[6]	6	1			T31	1		T247	1		T94	2
index[0x0]	lens_less_than_1000[7]	1	1			T237	1		-	-		-	-
index[0x0]	lens_less_than_1000[9]	2	1			T104	1		T248	1		-	-
index[0x0]	len_2	2	1			T248	1		T249	1		-	-
index[0x1]	lens_less_than_1000[0]	74	1			T5	1		T20	1		T22	1
index[0x1]	lens_less_than_1000[1]	26	1			T17	1		T26	1		T214	1
index[0x1]	lens_less_than_1000[2]	21	1			T31	1		T86	1		T250	1
index[0x1]	lens_less_than_1000[3]	29	1			T17	1		T47	1		T87	1
index[0x1]	lens_less_than_1000[4]	14	1			T16	1		T49	1		T53	1
index[0x1]	lens_less_than_1000[5]	9	1			T22	1		T251	1		T98	1
index[0x1]	lens_less_than_1000[6]	5	1			T94	1		T252	1		T253	1
index[0x1]	lens_less_than_1000[7]	4	1			T48	1		T237	1		T238	1
index[0x1]	lens_less_than_1000[8]	4	1			T106	1		T254	1		T255	1
index[0x1]	lens_less_than_1000[9]	1	1			T239	1		-	-		-	-
index[0x1]	len_2	4	1			T240	3		T241	1		-	-
index[0x2]	lens_less_than_1000[0]	82	1			T38	1		T63	1		T41	6
index[0x2]	lens_less_than_1000[1]	31	1			T26	1		T73	1		T22	1
index[0x2]	lens_less_than_1000[2]	15	1			T86	1		T50	1		T55	1
index[0x2]	lens_less_than_1000[3]	11	1			T86	1		T56	1		T243	1
index[0x2]	lens_less_than_1000[4]	12	1			T236	1		T256	1		T252	1
index[0x2]	lens_less_than_1000[5]	6	1			T257	1		T258	1		T259	2
index[0x2]	lens_less_than_1000[6]	7	1			T52	1		T233	1		T260	1
index[0x2]	lens_less_than_1000[7]	2	1			T261	1		T262	1		-	-
index[0x2]	lens_less_than_1000[8]	1	1			T263	1		-	-		-	-
index[0x2]	lens_less_than_1000[9]	1	1			T183	1		-	-		-	-
index[0x2]	len_2	2	1			T105	1		T264	1		-	-
index[0x3]	lens_less_than_1000[0]	58	1			T15	1		T23	1		T44	1
index[0x3]	lens_less_than_1000[1]	41	1			T22	1		T31	1		T86	1
index[0x3]	lens_less_than_1000[2]	17	1			T48	1		T265	1		T266	1
index[0x3]	lens_less_than_1000[3]	12	1			T15	1		T237	1		T267	1
index[0x3]	lens_less_than_1000[4]	8	1			T27	1		T94	1		T268	1
index[0x3]	lens_less_than_1000[5]	17	1			T40	1		T269	1		T115	1
index[0x3]	lens_less_than_1000[6]	17	1			T33	1		T76	1		T45	1
index[0x3]	lens_less_than_1000[7]	2	1			T270	1		T259	1		-	-
index[0x3]	lens_less_than_1000[8]	4	1			T15	1		T47	1		T271	1
index[0x3]	lens_less_than_1000[9]	1	1			T238	1		-	-		-	-
index[0x3]	len_2	2	1			T272	1		T273	1		-	-