Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	40	0	40	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
intr_timeout_cnt_cp	10	0	10	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	40	0	40	100.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	70	1			T15	1		T21	1		T73	1
class_index[0x1]	71	1			T15	1		T75	1		T66	1
class_index[0x2]	63	1			T17	1		T79	1		T83	1
class_index[0x3]	72	1			T19	1		T20	2		T17	2

---

Summary for Variable intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for intr_timeout_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
intr_timeout_cnt[0]	108	1			T15	1		T17	1		T73	2
intr_timeout_cnt[1]	57	1			T17	2		T21	1		T79	2
intr_timeout_cnt[2]	27	1			T20	2		T63	1		T75	1
intr_timeout_cnt[3]	9	1			T265	1		T54	1		T94	1
intr_timeout_cnt[4]	17	1			T66	1		T47	1		T51	1
intr_timeout_cnt[5]	10	1			T46	1		T86	1		T176	1
intr_timeout_cnt[6]	14	1			T19	1		T237	1		T306	1
intr_timeout_cnt[7]	13	1			T15	1		T21	1		T66	1
intr_timeout_cnt[8]	10	1			T81	1		T307	1		T271	1
intr_timeout_cnt[9]	11	1			T49	1		T265	1		T306	1

---

Summary for Cross class_cnt_cross

Samples crossed: class_index_cp intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	0	40	100.00

Automatically Generated Cross Bins for class_cnt_cross

Bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	intr_timeout_cnt[0]	30	1			T15	1		T73	1		T82	1
class_index[0x0]	intr_timeout_cnt[1]	15	1			T21	1		T83	1		T89	1
class_index[0x0]	intr_timeout_cnt[2]	8	1			T83	1		T308	1		T96	1
class_index[0x0]	intr_timeout_cnt[3]	2	1			T239	1		T273	1		-	-
class_index[0x0]	intr_timeout_cnt[4]	4	1			T66	1		T94	1		T108	1
class_index[0x0]	intr_timeout_cnt[5]	1	1			T309	1		-	-		-	-
class_index[0x0]	intr_timeout_cnt[6]	4	1			T237	1		T310	1		T311	1
class_index[0x0]	intr_timeout_cnt[7]	1	1			T312	1		-	-		-	-
class_index[0x0]	intr_timeout_cnt[8]	3	1			T271	1		T98	2		-	-
class_index[0x0]	intr_timeout_cnt[9]	2	1			T265	1		T313	1		-	-
class_index[0x1]	intr_timeout_cnt[0]	29	1			T47	1		T85	1		T94	1
class_index[0x1]	intr_timeout_cnt[1]	15	1			T79	1		T230	3		T105	1
class_index[0x1]	intr_timeout_cnt[2]	6	1			T75	1		T49	1		T89	1
class_index[0x1]	intr_timeout_cnt[3]	2	1			T98	1		T314	1		-	-
class_index[0x1]	intr_timeout_cnt[4]	6	1			T51	1		T54	1		T183	1
class_index[0x1]	intr_timeout_cnt[5]	3	1			T176	1		T315	1		T316	1
class_index[0x1]	intr_timeout_cnt[6]	1	1			T315	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[7]	4	1			T15	1		T66	1		T317	1
class_index[0x1]	intr_timeout_cnt[8]	3	1			T81	1		T318	1		T227	1
class_index[0x1]	intr_timeout_cnt[9]	2	1			T306	1		T98	1		-	-
class_index[0x2]	intr_timeout_cnt[0]	25	1			T79	1		T84	1		T48	2
class_index[0x2]	intr_timeout_cnt[1]	10	1			T17	1		T83	1		T87	1
class_index[0x2]	intr_timeout_cnt[2]	1	1			T227	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[3]	2	1			T265	1		T227	1		-	-
class_index[0x2]	intr_timeout_cnt[4]	5	1			T47	1		T94	1		T98	1
class_index[0x2]	intr_timeout_cnt[5]	2	1			T46	1		T86	1		-	-
class_index[0x2]	intr_timeout_cnt[6]	4	1			T319	1		T315	1		T249	1
class_index[0x2]	intr_timeout_cnt[7]	5	1			T86	1		T237	1		T306	1
class_index[0x2]	intr_timeout_cnt[8]	3	1			T307	1		T320	1		T321	1
class_index[0x2]	intr_timeout_cnt[9]	6	1			T49	1		T259	5		-	-
class_index[0x3]	intr_timeout_cnt[0]	24	1			T17	1		T73	1		T29	1
class_index[0x3]	intr_timeout_cnt[1]	17	1			T17	1		T79	1		T45	1
class_index[0x3]	intr_timeout_cnt[2]	12	1			T20	2		T63	1		T51	1
class_index[0x3]	intr_timeout_cnt[3]	3	1			T54	1		T94	1		T322	1
class_index[0x3]	intr_timeout_cnt[4]	2	1			T96	1		T316	1		-	-
class_index[0x3]	intr_timeout_cnt[5]	4	1			T313	3		T314	1		-	-
class_index[0x3]	intr_timeout_cnt[6]	5	1			T19	1		T306	1		T192	1
class_index[0x3]	intr_timeout_cnt[7]	3	1			T21	1		T94	1		T323	1
class_index[0x3]	intr_timeout_cnt[8]	1	1			T311	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[9]	1	1			T259	1		-	-		-	-