Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	347246	1			T2	4		T6	3		T5	1805
all_values[1]	347246	1			T2	4		T6	3		T5	1805
all_values[2]	347246	1			T2	4		T6	3		T5	1805
all_values[3]	347246	1			T2	4		T6	3		T5	1805

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

692211

1

T2

7

T5

3664

T18

69

auto[1]

696773

1

T2

9

T6

12

T5

3556

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

814420

1

T2

7

T6

8

T5

6298

auto[1]

574564

1

T2

9

T6

4

T5

922

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	99499	1			T2	2		T5	687		T18	9
all_values[0]	auto[0]	auto[1]	72901	1			T2	2		T5	231		T18	6
all_values[0]	auto[1]	auto[0]	101388	1			T6	2		T5	656		T18	7
all_values[0]	auto[1]	auto[1]	73458	1			T6	1		T5	231		T18	7
all_values[1]	auto[0]	auto[0]	100701	1			T2	1		T5	682		T18	7
all_values[1]	auto[0]	auto[1]	72315	1			T2	2		T5	231		T18	7
all_values[1]	auto[1]	auto[0]	101780	1			T2	1		T6	2		T5	668
all_values[1]	auto[1]	auto[1]	72450	1			T6	1		T5	224		T18	7
all_values[2]	auto[0]	auto[0]	102521	1			T5	922		T18	10		T8	463
all_values[2]	auto[0]	auto[1]	71051	1			T18	10		T19	3		T13	1
all_values[2]	auto[1]	auto[0]	103037	1			T2	2		T6	2		T5	881
all_values[2]	auto[1]	auto[1]	70637	1			T2	2		T6	1		T5	2
all_values[3]	auto[0]	auto[0]	102307	1			T5	910		T18	10		T8	335
all_values[3]	auto[0]	auto[1]	70916	1			T5	1		T18	10		T8	120
all_values[3]	auto[1]	auto[0]	103187	1			T2	1		T6	2		T5	892
all_values[3]	auto[1]	auto[1]	70836	1			T2	3		T6	1		T5	2