Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	4	0	4	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	347246	1			T2	4		T6	3		T5	1805
all_pins[1]	347246	1			T2	4		T6	3		T5	1805
all_pins[2]	347246	1			T2	4		T6	3		T5	1805
all_pins[3]	347246	1			T2	4		T6	3		T5	1805

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1101603	1			T2	11		T6	8		T5	6761
values[0x1]	287381	1			T2	5		T6	4		T5	459
transitions[0x0=>0x1]	189694	1			T2	3		T5	397		T18	13
transitions[0x1=>0x0]	189949	1			T2	3		T6	1		T5	397

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	273788	1			T2	4		T6	2		T5	1574
all_pins[0]	values[0x1]	73458	1			T6	1		T5	231		T18	7
all_pins[0]	transitions[0x0=>0x1]	72778	1			T5	231		T18	6		T7	8
all_pins[0]	transitions[0x1=>0x0]	70411	1			T2	3		T6	1		T5	2
all_pins[1]	values[0x0]	274796	1			T2	4		T6	2		T5	1581
all_pins[1]	values[0x1]	72450	1			T6	1		T5	224		T18	7
all_pins[1]	transitions[0x0=>0x1]	39918	1			T5	162		T18	3		T7	4
all_pins[1]	transitions[0x1=>0x0]	40926	1			T5	169		T18	3		T7	8
all_pins[2]	values[0x0]	276609	1			T2	2		T6	2		T5	1803
all_pins[2]	values[0x1]	70637	1			T2	2		T6	1		T5	2
all_pins[2]	transitions[0x0=>0x1]	38233	1			T2	2		T5	2		T18	2
all_pins[2]	transitions[0x1=>0x0]	40046	1			T5	224		T18	5		T7	4
all_pins[3]	values[0x0]	276410	1			T2	1		T6	2		T5	1803
all_pins[3]	values[0x1]	70836	1			T2	3		T6	1		T5	2
all_pins[3]	transitions[0x0=>0x1]	38765	1			T2	1		T5	2		T18	2
all_pins[3]	transitions[0x1=>0x0]	38566	1			T5	2		T18	2		T7	1