Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	290	1			T156	4		T157	4		T225	7
all_values[1]	290	1			T156	4		T157	4		T225	7
all_values[2]	290	1			T156	4		T157	4		T225	7
all_values[3]	290	1			T156	4		T157	4		T225	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

647

1

T156

4

T157

9

T225

19

auto[1]

513

1

T156

12

T157

7

T225

9

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

460

1

T156

6

T157

7

T225

19

auto[1]

700

1

T156

10

T157

9

T225

9

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

689

1

T156

9

T157

8

T225

21

auto[1]

471

1

T156

7

T157

8

T225

7

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	24	0	24	100.00
Automatically Generated Cross Bins	24	0	24	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr

cp_intr_test

cp_intr_en

cp_intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_values[0]

auto[0]

auto[0]

auto[0]

67

1

T156

1

T157

3

T225

3

all_values[0]

auto[0]

auto[0]

auto[1]

30

1

T225

1

T341

2

T342

1

all_values[0]

auto[0]

auto[1]

auto[0]

63

1

T225

1

T343

1

T344

2

all_values[0]

auto[0]

auto[1]

auto[1]

27

1

T156

1

T343

3

T341

1

all_values[0]

auto[1]

auto[0]

auto[1]

54

1

T343

1

T341

1

T344

1

all_values[0]

auto[1]

auto[1]

auto[1]

49

1

T156

2

T157

1

T225

2

all_values[1]

auto[0]

auto[0]

auto[0]

61

1

T157

1

T225

2

T343

1

all_values[1]

auto[0]

auto[0]

auto[1]

28

1

T225

1

T343

2

T341

2

all_values[1]

auto[0]

auto[1]

auto[0]

42

1

T225

1

T343

2

T344

1

all_values[1]

auto[0]

auto[1]

auto[1]

26

1

T156

1

T157

1

T345

1

all_values[1]

auto[1]

auto[0]

auto[1]

69

1

T157

1

T225

2

T343

1

all_values[1]

auto[1]

auto[1]

auto[1]

64

1

T156

3

T157

1

T225

1

all_values[2]

auto[0]

auto[0]

auto[0]

58

1

T156

2

T157

1

T225

5

all_values[2]

auto[0]

auto[0]

auto[1]

39

1

T341

3

T345

2

T344

1

all_values[2]

auto[0]

auto[1]

auto[0]

42

1

T225

1

T343

1

T346

4

all_values[2]

auto[0]

auto[1]

auto[1]

32

1

T156

1

T343

1

T347

1

all_values[2]

auto[1]

auto[0]

auto[1]

75

1

T157

2

T225

1

T343

2

all_values[2]

auto[1]

auto[1]

auto[1]

44

1

T156

1

T157

1

T343

3

all_values[3]

auto[0]

auto[0]

auto[0]

67

1

T156

1

T225

3

T343

3

all_values[3]

auto[0]

auto[0]

auto[1]

31

1

T344

1

T348

4

T347

1

all_values[3]

auto[0]

auto[1]

auto[0]

60

1

T156

2

T157

2

T225

3

all_values[3]

auto[0]

auto[1]

auto[1]

16

1

T343

1

T341

1

T346

2

all_values[3]

auto[1]

auto[0]

auto[1]

68

1

T157

1

T225

1

T341

1

all_values[3]

auto[1]

auto[1]

auto[1]

48

1

T156

1

T157

1

T343

3

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal