Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
accum_cnt_cp	6	0	6	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	24	0	24	100.00	100	1	1	0

Summary for Variable accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for accum_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
accum_cnt_2000	97104	1			T15	477		T16	122		T17	419
accum_cnt_1000	227800	1			T8	368		T15	428		T16	586
accum_cnt_100	25257	1			T8	161		T15	77		T16	33
accum_cnt_50	55103	1			T2	1		T8	114		T19	13
accum_cnt_10	178267	1			T2	7		T6	3		T5	4042
accum_cnt_0	407527	1			T2	4		T6	5		T5	1362

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Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	256948	1			T2	3		T6	2		T5	1351
class_index[0x1]	256948	1			T2	3		T6	2		T5	1351
class_index[0x2]	256948	1			T2	3		T6	2		T5	1351
class_index[0x3]	256948	1			T2	3		T6	2		T5	1351

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Summary for Cross class_cnt_cross

Samples crossed: class_index_cp accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for class_cnt_cross

Bins

class_index_cp	accum_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	accum_cnt_2000	25064	1			T17	7		T38	598		T26	533
class_index[0x0]	accum_cnt_1000	58679	1			T8	368		T17	653		T38	540
class_index[0x0]	accum_cnt_100	7900	1			T8	161		T15	12		T17	96
class_index[0x0]	accum_cnt_50	13453	1			T8	114		T20	7		T15	76
class_index[0x0]	accum_cnt_10	39660	1			T6	1		T18	14		T7	8
class_index[0x0]	accum_cnt_0	100842	1			T2	3		T6	1		T5	1351
class_index[0x1]	accum_cnt_2000	21852	1			T17	49		T37	428		T23	250
class_index[0x1]	accum_cnt_1000	55484	1			T17	619		T37	400		T23	498
class_index[0x1]	accum_cnt_100	5501	1			T15	1		T17	33		T37	22
class_index[0x1]	accum_cnt_50	12649	1			T19	7		T24	6		T15	57
class_index[0x1]	accum_cnt_10	47676	1			T2	3		T6	1		T5	1350
class_index[0x1]	accum_cnt_0	105494	1			T6	1		T5	1		T7	20
class_index[0x2]	accum_cnt_2000	21093	1			T15	477		T16	122		T17	205
class_index[0x2]	accum_cnt_1000	55319	1			T15	428		T16	586		T17	518
class_index[0x2]	accum_cnt_100	5914	1			T15	25		T16	33		T17	23
class_index[0x2]	accum_cnt_50	12992	1			T15	18		T36	9		T16	28
class_index[0x2]	accum_cnt_10	51664	1			T2	2		T6	1		T5	1349
class_index[0x2]	accum_cnt_0	103408	1			T2	1		T6	1		T5	2
class_index[0x3]	accum_cnt_2000	29095	1			T17	158		T37	71		T38	619
class_index[0x3]	accum_cnt_1000	58318	1			T17	518		T37	719		T38	649
class_index[0x3]	accum_cnt_100	5942	1			T15	39		T17	30		T37	40
class_index[0x3]	accum_cnt_50	16009	1			T2	1		T19	6		T20	14
class_index[0x3]	accum_cnt_10	39267	1			T2	2		T5	1343		T18	14
class_index[0x3]	accum_cnt_0	97783	1			T6	2		T5	8		T7	20