Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	71	0	71	100.00
Crosses	138	0	138	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
alert_index_cp	65	0	65	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	130	0	130	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for alert_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	11660	1			T15	299		T28	2		T23	77
alert[0x1]	2766	1			T20	1		T17	2		T21	1
alert[0x2]	2642	1			T21	98		T23	14		T63	1
alert[0x3]	4002	1			T9	1		T10	1		T69	2
alert[0x4]	2666	1			T17	12		T215	1		T31	1
alert[0x5]	6080	1			T15	176		T23	21		T45	8
alert[0x6]	3153	1			T21	1		T23	14		T68	1
alert[0x7]	1405	1			T62	1		T76	10		T47	21
alert[0x8]	2085	1			T15	696		T39	1		T22	2
alert[0x9]	5145	1			T76	86		T46	6		T47	33
alert[0xa]	5287	1			T7	1		T21	1		T10	1
alert[0xb]	10936	1			T15	192		T45	3		T46	2
alert[0xc]	6328	1			T23	178		T62	1		T45	1
alert[0xd]	3177	1			T17	14		T21	1		T62	1
alert[0xe]	2215	1			T15	364		T10	1		T22	10
alert[0xf]	6930	1			T20	8		T10	1		T23	10
alert[0x10]	4272	1			T23	25		T63	5		T215	1
alert[0x11]	3607	1			T21	1		T23	398		T215	1
alert[0x12]	5021	1			T21	9		T23	27		T62	1
alert[0x13]	4201	1			T7	1		T9	1		T10	1
alert[0x14]	4957	1			T2	21		T15	141		T68	1
alert[0x15]	4834	1			T15	819		T23	10		T76	15
alert[0x16]	3101	1			T19	2		T15	45		T23	23
alert[0x17]	4906	1			T15	11		T23	7		T62	1
alert[0x18]	3456	1			T15	48		T21	4		T10	2
alert[0x19]	2533	1			T9	1		T23	19		T62	1
alert[0x1a]	4890	1			T7	1		T17	1		T33	1
alert[0x1b]	10029	1			T15	28		T23	36		T69	5
alert[0x1c]	3408	1			T69	1		T65	1		T76	1640
alert[0x1d]	1195	1			T15	134		T21	19		T28	13
alert[0x1e]	6421	1			T15	419		T17	1		T21	7
alert[0x1f]	11988	1			T15	714		T17	1		T63	4
alert[0x20]	5930	1			T21	13		T66	2		T76	151
alert[0x21]	6678	1			T15	2454		T21	1		T10	1
alert[0x22]	7934	1			T7	1		T15	151		T10	1
alert[0x23]	8381	1			T15	142		T23	13		T69	1
alert[0x24]	16972	1			T15	104		T17	1		T23	268
alert[0x25]	6240	1			T23	37		T76	25		T47	1085
alert[0x26]	4099	1			T21	3		T27	1		T76	165
alert[0x27]	4627	1			T7	1		T21	5		T62	1
alert[0x28]	7171	1			T15	36		T17	1		T62	1
alert[0x29]	2863	1			T7	1		T15	6		T62	3
alert[0x2a]	3581	1			T62	1		T69	4		T76	1031
alert[0x2b]	1444	1			T23	175		T76	33		T215	2
alert[0x2c]	3634	1			T15	190		T22	2		T69	6
alert[0x2d]	1474	1			T15	163		T17	1		T39	1
alert[0x2e]	6604	1			T7	1		T15	46		T21	1
alert[0x2f]	9969	1			T9	1		T15	23		T21	4
alert[0x30]	5212	1			T23	7		T75	1		T27	9
alert[0x31]	3975	1			T22	1		T23	12		T276	1
alert[0x32]	3079	1			T69	2		T76	9		T216	4
alert[0x33]	8436	1			T7	1		T15	746		T22	4
alert[0x34]	4413	1			T23	21		T76	36		T48	256
alert[0x35]	12427	1			T15	4305		T21	1		T22	6
alert[0x36]	8132	1			T15	4837		T62	1		T31	1
alert[0x37]	10119	1			T19	3		T15	2620		T17	1
alert[0x38]	8937	1			T2	2		T15	2066		T10	1
alert[0x39]	2786	1			T19	4		T20	8		T15	76
alert[0x3a]	4784	1			T7	1		T215	1		T46	21
alert[0x3b]	4708	1			T15	8		T23	26		T47	12
alert[0x3c]	7425	1			T20	1		T23	254		T45	4
alert[0x3d]	4031	1			T19	1		T15	21		T23	54
alert[0x3e]	1593	1			T15	378		T17	3		T22	30
alert[0x3f]	15126	1			T15	1929		T21	21		T22	1
alert[0x40]	2164	1			T10	1		T75	2		T48	40

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	86069	1			T7	8		T19	7		T9	2
class_i[0x1]	132985	1			T7	1		T9	1		T20	5
class_i[0x2]	48659	1			T20	5		T15	147		T28	25
class_i[0x3]	92531	1			T2	23		T19	3		T9	1

---

Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

alert_integrity_fail

359585

1

T2

23

T19

10

T20

18

alert_ping_fail

659

1

T7

9

T9

4

T10

12

---

Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	0	130	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	alert_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	alert[0x0]	11649	1			T15	299		T28	2		T23	77
alert_integrity_fail	alert[0x1]	2751	1			T20	1		T17	2		T21	1
alert_integrity_fail	alert[0x2]	2634	1			T21	98		T23	14		T63	1
alert_integrity_fail	alert[0x3]	3990	1			T69	2		T76	294		T48	280
alert_integrity_fail	alert[0x4]	2661	1			T17	12		T31	1		T47	1637
alert_integrity_fail	alert[0x5]	6069	1			T15	176		T23	21		T45	8
alert_integrity_fail	alert[0x6]	3132	1			T21	1		T23	14		T48	32
alert_integrity_fail	alert[0x7]	1399	1			T76	10		T47	21		T277	141
alert_integrity_fail	alert[0x8]	2065	1			T15	696		T22	2		T23	8
alert_integrity_fail	alert[0x9]	5136	1			T76	86		T46	6		T47	33
alert_integrity_fail	alert[0xa]	5273	1			T21	1		T22	3		T47	24
alert_integrity_fail	alert[0xb]	10929	1			T15	192		T45	3		T46	2
alert_integrity_fail	alert[0xc]	6316	1			T23	178		T45	1		T47	267
alert_integrity_fail	alert[0xd]	3164	1			T17	14		T21	1		T88	1360
alert_integrity_fail	alert[0xe]	2207	1			T15	364		T22	10		T23	11
alert_integrity_fail	alert[0xf]	6923	1			T20	8		T23	10		T76	223
alert_integrity_fail	alert[0x10]	4263	1			T23	25		T63	5		T47	10
alert_integrity_fail	alert[0x11]	3598	1			T21	1		T23	398		T48	108
alert_integrity_fail	alert[0x12]	5011	1			T21	9		T23	27		T76	285
alert_integrity_fail	alert[0x13]	4188	1			T22	2		T23	162		T47	5
alert_integrity_fail	alert[0x14]	4944	1			T2	21		T15	141		T76	358
alert_integrity_fail	alert[0x15]	4824	1			T15	819		T23	10		T76	15
alert_integrity_fail	alert[0x16]	3087	1			T19	2		T15	45		T23	23
alert_integrity_fail	alert[0x17]	4894	1			T15	11		T23	7		T75	3
alert_integrity_fail	alert[0x18]	3446	1			T15	48		T21	4		T23	32
alert_integrity_fail	alert[0x19]	2520	1			T23	19		T27	1		T76	95
alert_integrity_fail	alert[0x1a]	4881	1			T17	1		T33	1		T76	423
alert_integrity_fail	alert[0x1b]	10024	1			T15	28		T23	36		T69	5
alert_integrity_fail	alert[0x1c]	3396	1			T69	1		T76	1640		T278	698
alert_integrity_fail	alert[0x1d]	1186	1			T15	134		T21	19		T28	13
alert_integrity_fail	alert[0x1e]	6412	1			T15	419		T17	1		T21	7
alert_integrity_fail	alert[0x1f]	11980	1			T15	714		T17	1		T63	4
alert_integrity_fail	alert[0x20]	5923	1			T21	13		T66	2		T76	151
alert_integrity_fail	alert[0x21]	6666	1			T15	2454		T21	1		T22	1
alert_integrity_fail	alert[0x22]	7910	1			T15	151		T28	1		T22	8
alert_integrity_fail	alert[0x23]	8372	1			T15	142		T23	13		T69	1
alert_integrity_fail	alert[0x24]	16962	1			T15	104		T17	1		T23	268
alert_integrity_fail	alert[0x25]	6235	1			T23	37		T76	25		T47	1085
alert_integrity_fail	alert[0x26]	4094	1			T21	3		T27	1		T76	165
alert_integrity_fail	alert[0x27]	4617	1			T21	5		T76	85		T47	163
alert_integrity_fail	alert[0x28]	7158	1			T15	36		T17	1		T33	1
alert_integrity_fail	alert[0x29]	2851	1			T15	6		T76	220		T216	17
alert_integrity_fail	alert[0x2a]	3569	1			T69	4		T76	1031		T88	36
alert_integrity_fail	alert[0x2b]	1429	1			T23	175		T76	33		T31	7
alert_integrity_fail	alert[0x2c]	3617	1			T15	190		T22	2		T69	6
alert_integrity_fail	alert[0x2d]	1460	1			T15	163		T17	1		T22	3
alert_integrity_fail	alert[0x2e]	6595	1			T15	46		T21	1		T28	10
alert_integrity_fail	alert[0x2f]	9959	1			T15	23		T21	4		T23	7
alert_integrity_fail	alert[0x30]	5204	1			T23	7		T75	1		T27	9
alert_integrity_fail	alert[0x31]	3970	1			T22	1		T23	12		T86	4
alert_integrity_fail	alert[0x32]	3066	1			T69	2		T76	9		T216	4
alert_integrity_fail	alert[0x33]	8428	1			T15	746		T22	4		T76	168
alert_integrity_fail	alert[0x34]	4410	1			T23	21		T76	36		T48	256
alert_integrity_fail	alert[0x35]	12418	1			T15	4305		T21	1		T22	6
alert_integrity_fail	alert[0x36]	8126	1			T15	4837		T31	1		T47	71
alert_integrity_fail	alert[0x37]	10109	1			T19	3		T15	2620		T17	1
alert_integrity_fail	alert[0x38]	8929	1			T2	2		T15	2066		T23	281
alert_integrity_fail	alert[0x39]	2776	1			T19	4		T20	8		T15	76
alert_integrity_fail	alert[0x3a]	4776	1			T46	21		T47	336		T88	553
alert_integrity_fail	alert[0x3b]	4702	1			T15	8		T23	26		T47	12
alert_integrity_fail	alert[0x3c]	7421	1			T20	1		T23	254		T45	4
alert_integrity_fail	alert[0x3d]	4017	1			T19	1		T15	21		T23	54
alert_integrity_fail	alert[0x3e]	1586	1			T15	378		T17	3		T22	30
alert_integrity_fail	alert[0x3f]	15122	1			T15	1929		T21	21		T22	1
alert_integrity_fail	alert[0x40]	2156	1			T75	2		T48	40		T277	213
alert_ping_fail	alert[0x0]	11	1			T276	1		T221	1		T279	1
alert_ping_fail	alert[0x1]	15	1			T215	1		T276	1		T280	2
alert_ping_fail	alert[0x2]	8	1			T276	1		T231	1		T281	1
alert_ping_fail	alert[0x3]	12	1			T9	1		T10	1		T215	1
alert_ping_fail	alert[0x4]	5	1			T215	1		T282	1		T283	1
alert_ping_fail	alert[0x5]	11	1			T284	1		T285	2		T286	1
alert_ping_fail	alert[0x6]	21	1			T68	1		T276	1		T269	1
alert_ping_fail	alert[0x7]	6	1			T62	1		T287	1		T288	1
alert_ping_fail	alert[0x8]	20	1			T39	1		T276	1		T287	1
alert_ping_fail	alert[0x9]	9	1			T276	1		T231	1		T281	2
alert_ping_fail	alert[0xa]	14	1			T7	1		T10	1		T177	1
alert_ping_fail	alert[0xb]	7	1			T247	1		T289	1		T290	1
alert_ping_fail	alert[0xc]	12	1			T62	1		T90	1		T291	1
alert_ping_fail	alert[0xd]	13	1			T62	1		T247	1		T231	1
alert_ping_fail	alert[0xe]	8	1			T10	1		T62	1		T247	1
alert_ping_fail	alert[0xf]	7	1			T10	1		T276	1		T288	1
alert_ping_fail	alert[0x10]	9	1			T215	1		T292	3		T293	1
alert_ping_fail	alert[0x11]	9	1			T215	1		T294	2		T295	1
alert_ping_fail	alert[0x12]	10	1			T62	1		T279	1		T281	1
alert_ping_fail	alert[0x13]	13	1			T7	1		T9	1		T10	1
alert_ping_fail	alert[0x14]	13	1			T68	1		T177	2		T231	1
alert_ping_fail	alert[0x15]	10	1			T222	1		T281	1		T296	1
alert_ping_fail	alert[0x16]	14	1			T269	1		T297	1		T288	1
alert_ping_fail	alert[0x17]	12	1			T62	1		T70	1		T242	1
alert_ping_fail	alert[0x18]	10	1			T10	2		T39	1		T62	1
alert_ping_fail	alert[0x19]	13	1			T9	1		T62	1		T215	1
alert_ping_fail	alert[0x1a]	9	1			T7	1		T70	1		T298	1
alert_ping_fail	alert[0x1b]	5	1			T276	1		T247	1		T291	1
alert_ping_fail	alert[0x1c]	12	1			T65	1		T90	1		T231	1
alert_ping_fail	alert[0x1d]	9	1			T276	1		T291	1		T284	1
alert_ping_fail	alert[0x1e]	9	1			T10	1		T288	1		T279	1
alert_ping_fail	alert[0x1f]	8	1			T90	1		T288	1		T291	1
alert_ping_fail	alert[0x20]	7	1			T276	1		T299	1		T300	1
alert_ping_fail	alert[0x21]	12	1			T10	1		T62	1		T276	1
alert_ping_fail	alert[0x22]	24	1			T7	1		T10	1		T62	1
alert_ping_fail	alert[0x23]	9	1			T276	1		T279	1		T284	1
alert_ping_fail	alert[0x24]	10	1			T276	1		T222	1		T291	1
alert_ping_fail	alert[0x25]	5	1			T287	1		T301	1		T302	1
alert_ping_fail	alert[0x26]	5	1			T215	1		T282	1		T293	1
alert_ping_fail	alert[0x27]	10	1			T7	1		T62	1		T215	1
alert_ping_fail	alert[0x28]	13	1			T62	1		T287	1		T231	1
alert_ping_fail	alert[0x29]	12	1			T7	1		T62	3		T215	1
alert_ping_fail	alert[0x2a]	12	1			T62	1		T215	1		T287	1
alert_ping_fail	alert[0x2b]	15	1			T215	2		T242	1		T303	2
alert_ping_fail	alert[0x2c]	17	1			T231	2		T221	2		T298	1
alert_ping_fail	alert[0x2d]	14	1			T39	1		T215	1		T247	1
alert_ping_fail	alert[0x2e]	9	1			T7	1		T215	1		T276	1
alert_ping_fail	alert[0x2f]	10	1			T9	1		T39	1		T242	3
alert_ping_fail	alert[0x30]	8	1			T247	1		T222	1		T304	2
alert_ping_fail	alert[0x31]	5	1			T276	1		T90	1		T221	1
alert_ping_fail	alert[0x32]	13	1			T231	1		T222	2		T288	1
alert_ping_fail	alert[0x33]	8	1			T7	1		T242	1		T276	1
alert_ping_fail	alert[0x34]	3	1			T222	1		T292	1		T305	1
alert_ping_fail	alert[0x35]	9	1			T279	1		T294	1		T285	1
alert_ping_fail	alert[0x36]	6	1			T62	1		T292	1		T300	1
alert_ping_fail	alert[0x37]	10	1			T288	1		T281	2		T289	1
alert_ping_fail	alert[0x38]	8	1			T10	1		T215	2		T281	1
alert_ping_fail	alert[0x39]	10	1			T247	1		T231	2		T288	1
alert_ping_fail	alert[0x3a]	8	1			T7	1		T215	1		T90	1
alert_ping_fail	alert[0x3b]	6	1			T242	1		T221	1		T294	1
alert_ping_fail	alert[0x3c]	4	1			T276	1		T222	2		T294	1
alert_ping_fail	alert[0x3d]	14	1			T242	1		T247	1		T281	1
alert_ping_fail	alert[0x3e]	7	1			T215	1		T279	1		T285	1
alert_ping_fail	alert[0x3f]	4	1			T90	1		T221	1		T222	1
alert_ping_fail	alert[0x40]	8	1			T10	1		T242	1		T287	1

---

Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	class_i[0x0]	85844	1			T19	7		T15	154		T17	38
alert_integrity_fail	class_i[0x1]	132855	1			T20	5		T15	24086		T21	4
alert_integrity_fail	class_i[0x2]	48557	1			T20	5		T15	147		T28	25
alert_integrity_fail	class_i[0x3]	92329	1			T2	23		T19	3		T20	8
alert_ping_fail	class_i[0x0]	225	1			T7	8		T9	2		T10	1
alert_ping_fail	class_i[0x1]	130	1			T7	1		T9	1		T10	1
alert_ping_fail	class_i[0x2]	102	1			T65	2		T68	3		T215	17
alert_ping_fail	class_i[0x3]	202	1			T9	1		T10	10		T39	2