Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.69 99.99 98.72 100.00 100.00 100.00 99.38 99.72


Total test records in report: 827
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T772 /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.229166090 Jul 13 05:02:15 PM PDT 24 Jul 13 05:02:28 PM PDT 24 99696107 ps
T123 /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.1037692941 Jul 13 05:02:48 PM PDT 24 Jul 13 05:06:41 PM PDT 24 2315553437 ps
T139 /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.3645401903 Jul 13 05:02:50 PM PDT 24 Jul 13 05:09:13 PM PDT 24 5201044048 ps
T773 /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.426169298 Jul 13 05:01:52 PM PDT 24 Jul 13 05:04:53 PM PDT 24 1653079930 ps
T774 /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.3738625850 Jul 13 05:03:04 PM PDT 24 Jul 13 05:03:06 PM PDT 24 9529572 ps
T775 /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.3656916749 Jul 13 05:02:57 PM PDT 24 Jul 13 05:03:10 PM PDT 24 287275513 ps
T776 /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.9015557 Jul 13 05:03:03 PM PDT 24 Jul 13 05:03:05 PM PDT 24 11825336 ps
T777 /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.912180012 Jul 13 05:03:16 PM PDT 24 Jul 13 05:03:18 PM PDT 24 18103490 ps
T144 /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.3109222308 Jul 13 05:01:59 PM PDT 24 Jul 13 05:07:46 PM PDT 24 30148760863 ps
T778 /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.2318896657 Jul 13 05:02:32 PM PDT 24 Jul 13 05:02:34 PM PDT 24 8488320 ps
T779 /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.1979911720 Jul 13 05:02:48 PM PDT 24 Jul 13 05:02:54 PM PDT 24 306632201 ps
T780 /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.1422974524 Jul 13 05:02:07 PM PDT 24 Jul 13 05:07:33 PM PDT 24 3223541080 ps
T781 /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.1578045975 Jul 13 05:02:54 PM PDT 24 Jul 13 05:02:56 PM PDT 24 7738196 ps
T782 /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.1850423115 Jul 13 05:03:05 PM PDT 24 Jul 13 05:03:07 PM PDT 24 18763636 ps
T172 /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.1959794393 Jul 13 05:02:48 PM PDT 24 Jul 13 05:03:57 PM PDT 24 3678896917 ps
T783 /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.3152796591 Jul 13 05:02:07 PM PDT 24 Jul 13 05:02:48 PM PDT 24 3179736113 ps
T784 /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.3008130096 Jul 13 05:02:39 PM PDT 24 Jul 13 05:03:16 PM PDT 24 572551887 ps
T785 /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.2876647014 Jul 13 05:01:45 PM PDT 24 Jul 13 05:01:55 PM PDT 24 693425678 ps
T786 /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.3259455213 Jul 13 05:02:06 PM PDT 24 Jul 13 05:02:10 PM PDT 24 62463310 ps
T787 /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.3480166856 Jul 13 05:02:06 PM PDT 24 Jul 13 05:02:17 PM PDT 24 238444660 ps
T788 /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.431303245 Jul 13 05:02:38 PM PDT 24 Jul 13 05:02:59 PM PDT 24 1870056283 ps
T789 /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.21262163 Jul 13 05:02:30 PM PDT 24 Jul 13 05:02:40 PM PDT 24 496084402 ps
T173 /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.625572891 Jul 13 05:01:36 PM PDT 24 Jul 13 05:02:27 PM PDT 24 1373426667 ps
T146 /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.326113300 Jul 13 05:02:38 PM PDT 24 Jul 13 05:18:42 PM PDT 24 14625785912 ps
T159 /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.1964599831 Jul 13 05:02:38 PM PDT 24 Jul 13 05:02:44 PM PDT 24 91519091 ps
T790 /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.4067602472 Jul 13 05:01:39 PM PDT 24 Jul 13 05:01:45 PM PDT 24 114217908 ps
T145 /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.941755281 Jul 13 05:01:54 PM PDT 24 Jul 13 05:04:55 PM PDT 24 5920042559 ps
T147 /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.3298859670 Jul 13 05:02:39 PM PDT 24 Jul 13 05:05:34 PM PDT 24 2319561244 ps
T235 /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.4042837977 Jul 13 05:01:52 PM PDT 24 Jul 13 05:01:58 PM PDT 24 95699700 ps
T791 /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.851133533 Jul 13 05:02:48 PM PDT 24 Jul 13 05:02:53 PM PDT 24 87144137 ps
T792 /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.2073360246 Jul 13 05:03:04 PM PDT 24 Jul 13 05:03:10 PM PDT 24 342351294 ps
T793 /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.1583705481 Jul 13 05:01:37 PM PDT 24 Jul 13 05:03:22 PM PDT 24 3270263357 ps
T353 /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.2002568305 Jul 13 05:02:56 PM PDT 24 Jul 13 05:12:01 PM PDT 24 6399320661 ps
T794 /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.3492919397 Jul 13 05:02:48 PM PDT 24 Jul 13 05:03:01 PM PDT 24 586836545 ps
T149 /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.3975907273 Jul 13 05:02:47 PM PDT 24 Jul 13 05:14:29 PM PDT 24 6353437353 ps
T167 /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.2287509300 Jul 13 05:02:15 PM PDT 24 Jul 13 05:03:44 PM PDT 24 5203919815 ps
T795 /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.1019784282 Jul 13 05:02:06 PM PDT 24 Jul 13 05:02:08 PM PDT 24 14238926 ps
T796 /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.3157024370 Jul 13 05:02:06 PM PDT 24 Jul 13 05:02:33 PM PDT 24 349280635 ps
T797 /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.2953608513 Jul 13 05:02:48 PM PDT 24 Jul 13 05:02:53 PM PDT 24 33669420 ps
T150 /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.2079331801 Jul 13 05:02:13 PM PDT 24 Jul 13 05:19:32 PM PDT 24 28548734869 ps
T798 /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.2326174556 Jul 13 05:02:01 PM PDT 24 Jul 13 05:02:04 PM PDT 24 154429423 ps
T799 /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.1811721722 Jul 13 05:02:40 PM PDT 24 Jul 13 05:03:06 PM PDT 24 2508557879 ps
T800 /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.4002282149 Jul 13 05:02:14 PM PDT 24 Jul 13 05:02:16 PM PDT 24 12381180 ps
T151 /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.2048094084 Jul 13 05:02:40 PM PDT 24 Jul 13 05:20:06 PM PDT 24 67940606390 ps
T801 /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.912335538 Jul 13 05:02:01 PM PDT 24 Jul 13 05:18:13 PM PDT 24 24590193409 ps
T141 /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.3359835960 Jul 13 05:01:52 PM PDT 24 Jul 13 05:05:07 PM PDT 24 5430713635 ps
T802 /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.969258945 Jul 13 05:03:21 PM PDT 24 Jul 13 05:03:23 PM PDT 24 9606948 ps
T803 /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.4014674894 Jul 13 05:02:01 PM PDT 24 Jul 13 05:02:24 PM PDT 24 1059617722 ps
T164 /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.2332742981 Jul 13 05:02:39 PM PDT 24 Jul 13 05:02:42 PM PDT 24 109797497 ps
T804 /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.1942127739 Jul 13 05:03:06 PM PDT 24 Jul 13 05:03:08 PM PDT 24 18747507 ps
T805 /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.2274293492 Jul 13 05:02:56 PM PDT 24 Jul 13 05:03:06 PM PDT 24 163066478 ps
T806 /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.3148700281 Jul 13 05:02:07 PM PDT 24 Jul 13 05:02:44 PM PDT 24 506761821 ps
T807 /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.1334049501 Jul 13 05:02:56 PM PDT 24 Jul 13 05:02:58 PM PDT 24 8988716 ps
T808 /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.1293664456 Jul 13 05:03:14 PM PDT 24 Jul 13 05:03:16 PM PDT 24 13365392 ps
T809 /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.2074752009 Jul 13 05:01:52 PM PDT 24 Jul 13 05:06:21 PM PDT 24 12238156655 ps
T810 /workspace/coverage/cover_reg_top/33.alert_handler_intr_test.2728539460 Jul 13 05:03:15 PM PDT 24 Jul 13 05:03:17 PM PDT 24 26973421 ps
T811 /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.1768980578 Jul 13 05:02:18 PM PDT 24 Jul 13 05:02:43 PM PDT 24 668815935 ps
T143 /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.2583370427 Jul 13 05:02:24 PM PDT 24 Jul 13 05:07:53 PM PDT 24 14122382133 ps
T812 /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.362569420 Jul 13 05:01:44 PM PDT 24 Jul 13 05:01:46 PM PDT 24 31806983 ps
T813 /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.3660294223 Jul 13 05:03:13 PM PDT 24 Jul 13 05:03:15 PM PDT 24 12411981 ps
T814 /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.1998757893 Jul 13 05:02:40 PM PDT 24 Jul 13 05:02:46 PM PDT 24 162718705 ps
T815 /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.1696899050 Jul 13 05:02:20 PM PDT 24 Jul 13 05:02:33 PM PDT 24 110958294 ps
T816 /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.2463868846 Jul 13 05:03:16 PM PDT 24 Jul 13 05:03:18 PM PDT 24 75077650 ps
T148 /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.894371447 Jul 13 05:02:15 PM PDT 24 Jul 13 05:05:25 PM PDT 24 10716063641 ps
T817 /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.3421898920 Jul 13 05:02:56 PM PDT 24 Jul 13 05:03:06 PM PDT 24 66074468 ps
T818 /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.2572384582 Jul 13 05:02:08 PM PDT 24 Jul 13 05:02:10 PM PDT 24 20946712 ps
T819 /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.472479837 Jul 13 05:01:43 PM PDT 24 Jul 13 05:05:41 PM PDT 24 16798241771 ps
T820 /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.2369947244 Jul 13 05:03:03 PM PDT 24 Jul 13 05:03:05 PM PDT 24 20876338 ps
T821 /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.1509356349 Jul 13 05:02:00 PM PDT 24 Jul 13 05:02:49 PM PDT 24 707494364 ps
T822 /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.2062846507 Jul 13 05:02:00 PM PDT 24 Jul 13 05:09:23 PM PDT 24 9338223567 ps
T168 /workspace/coverage/cover_reg_top/12.alert_handler_tl_intg_err.2616628454 Jul 13 05:02:31 PM PDT 24 Jul 13 05:03:39 PM PDT 24 3052196056 ps
T193 /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.1677853393 Jul 13 05:02:54 PM PDT 24 Jul 13 05:05:37 PM PDT 24 5412662140 ps
T823 /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.1395034174 Jul 13 05:03:05 PM PDT 24 Jul 13 05:03:07 PM PDT 24 19104458 ps
T824 /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.1106901259 Jul 13 05:03:13 PM PDT 24 Jul 13 05:03:15 PM PDT 24 25123190 ps
T825 /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.118131132 Jul 13 05:02:48 PM PDT 24 Jul 13 05:03:06 PM PDT 24 901961237 ps
T826 /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.1911837098 Jul 13 05:01:51 PM PDT 24 Jul 13 05:05:32 PM PDT 24 5284484946 ps
T827 /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.3808012355 Jul 13 05:02:00 PM PDT 24 Jul 13 05:02:08 PM PDT 24 38581599 ps

Test location /workspace/coverage/default/38.alert_handler_sig_int_fail.74569863
Short name T19
Test name
Test status
Simulation time 770382629 ps
CPU time 22.87 seconds
Started Jul 13 06:25:33 PM PDT 24
Finished Jul 13 06:25:58 PM PDT 24
Peak memory 248744 kb
Host smart-c2bdd3b2-8127-4e5b-bf70-9f5debdf61cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74569
863 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_sig_int_fail.74569863
Directory /workspace/38.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all.1702491263
Short name T15
Test name
Test status
Simulation time 116702168250 ps
CPU time 3105.21 seconds
Started Jul 13 06:25:53 PM PDT 24
Finished Jul 13 07:17:39 PM PDT 24
Peak memory 298260 kb
Host smart-501659db-9c9d-4c94-a9dd-b4125841f834
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702491263 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_ha
ndler_stress_all.1702491263
Directory /workspace/44.alert_handler_stress_all/latest

Test location /workspace/coverage/default/1.alert_handler_sec_cm.1057576899
Short name T4
Test name
Test status
Simulation time 565671448 ps
CPU time 26.42 seconds
Started Jul 13 06:24:39 PM PDT 24
Finished Jul 13 06:25:08 PM PDT 24
Peak memory 270492 kb
Host smart-143ddf20-f244-488f-b0b3-ee90f5ddef03
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1057576899 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sec_cm.1057576899
Directory /workspace/1.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all_with_rand_reset.1323175912
Short name T51
Test name
Test status
Simulation time 95212729253 ps
CPU time 6589.93 seconds
Started Jul 13 06:25:32 PM PDT 24
Finished Jul 13 08:15:24 PM PDT 24
Peak memory 315192 kb
Host smart-22fe06fe-4bd5-46be-a737-85c2d6fb581e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323175912 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 37.alert_handler_stress_all_with_rand_reset.1323175912
Directory /workspace/37.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.alert_handler_entropy.3974411933
Short name T28
Test name
Test status
Simulation time 152091467249 ps
CPU time 2141.58 seconds
Started Jul 13 06:25:13 PM PDT 24
Finished Jul 13 07:00:57 PM PDT 24
Peak memory 282172 kb
Host smart-3f12b00f-a43c-43f5-91cc-785020a74f9e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974411933 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_entropy.3974411933
Directory /workspace/24.alert_handler_entropy/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.3985743040
Short name T117
Test name
Test status
Simulation time 4765955214 ps
CPU time 762.53 seconds
Started Jul 13 05:01:52 PM PDT 24
Finished Jul 13 05:14:35 PM PDT 24
Peak memory 272952 kb
Host smart-026cb554-a2ae-4740-b74e-01d2d890502c
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985743040 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.alert_handler_shadow_reg_errors_with_csr_rw.3985743040
Directory /workspace/3.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.2137614326
Short name T166
Test name
Test status
Simulation time 610191816 ps
CPU time 27.77 seconds
Started Jul 13 05:02:15 PM PDT 24
Finished Jul 13 05:02:43 PM PDT 24
Peak memory 245788 kb
Host smart-ae7b80b5-3fa4-4f78-b87b-d4dd58daecce
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2137614326 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_intg_err.2137614326
Directory /workspace/9.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all.1619967926
Short name T17
Test name
Test status
Simulation time 566944887695 ps
CPU time 2543.4 seconds
Started Jul 13 06:25:23 PM PDT 24
Finished Jul 13 07:07:47 PM PDT 24
Peak memory 285952 kb
Host smart-123ff061-c97f-4c3d-a546-c29d08c4d076
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619967926 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_ha
ndler_stress_all.1619967926
Directory /workspace/32.alert_handler_stress_all/latest

Test location /workspace/coverage/default/40.alert_handler_lpg.3288447211
Short name T5
Test name
Test status
Simulation time 54305972704 ps
CPU time 3233.73 seconds
Started Jul 13 06:25:33 PM PDT 24
Finished Jul 13 07:19:29 PM PDT 24
Peak memory 290264 kb
Host smart-39e2fc71-23fe-427b-bc88-f86751a1f1dc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288447211 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg.3288447211
Directory /workspace/40.alert_handler_lpg/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all.4188082904
Short name T98
Test name
Test status
Simulation time 54283136394 ps
CPU time 3210.66 seconds
Started Jul 13 06:25:08 PM PDT 24
Finished Jul 13 07:18:41 PM PDT 24
Peak memory 306100 kb
Host smart-131676d4-1500-473e-8b9d-ba19c6bb2579
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188082904 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_ha
ndler_stress_all.4188082904
Directory /workspace/31.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.223527996
Short name T140
Test name
Test status
Simulation time 1588147024 ps
CPU time 180.66 seconds
Started Jul 13 05:01:45 PM PDT 24
Finished Jul 13 05:04:46 PM PDT 24
Peak memory 265344 kb
Host smart-c885f0fa-8c0a-4ec5-bb39-0173d86c2527
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=223527996 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shadow_reg_error
s.223527996
Directory /workspace/2.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all_with_rand_reset.538550435
Short name T514
Test name
Test status
Simulation time 776011453322 ps
CPU time 8195.23 seconds
Started Jul 13 06:24:40 PM PDT 24
Finished Jul 13 08:41:18 PM PDT 24
Peak memory 371796 kb
Host smart-31a6f94f-d5a3-4bc4-a687-73ba83aac8bc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538550435 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 9.alert_handler_stress_all_with_rand_reset.538550435
Directory /workspace/9.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.1032088853
Short name T118
Test name
Test status
Simulation time 3981754107 ps
CPU time 315.61 seconds
Started Jul 13 05:01:37 PM PDT 24
Finished Jul 13 05:06:53 PM PDT 24
Peak memory 265428 kb
Host smart-8cd8b896-9be4-41bd-83ea-7054d637cc48
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1032088853 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shadow_reg_erro
rs.1032088853
Directory /workspace/0.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/2.alert_handler_lpg.2318754807
Short name T68
Test name
Test status
Simulation time 80512116672 ps
CPU time 2254.13 seconds
Started Jul 13 06:24:46 PM PDT 24
Finished Jul 13 07:02:22 PM PDT 24
Peak memory 287852 kb
Host smart-bd4ae36e-9e6a-4ce1-b8f2-92e701fce31a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318754807 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg.2318754807
Directory /workspace/2.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.164910200
Short name T137
Test name
Test status
Simulation time 17421622824 ps
CPU time 1216.79 seconds
Started Jul 13 05:01:39 PM PDT 24
Finished Jul 13 05:21:57 PM PDT 24
Peak memory 273576 kb
Host smart-0c05fae8-120c-4617-9925-ba4982feaa6f
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164910200 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.alert_handler_shadow_reg_errors_with_csr_rw.164910200
Directory /workspace/1.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/21.alert_handler_entropy.2970373223
Short name T76
Test name
Test status
Simulation time 185664221997 ps
CPU time 2531.39 seconds
Started Jul 13 06:25:12 PM PDT 24
Finished Jul 13 07:07:25 PM PDT 24
Peak memory 282100 kb
Host smart-fd248bd2-7ce4-4be7-811c-cce46cf1001e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970373223 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_entropy.2970373223
Directory /workspace/21.alert_handler_entropy/latest

Test location /workspace/coverage/default/21.alert_handler_ping_timeout.2732183172
Short name T215
Test name
Test status
Simulation time 29324043737 ps
CPU time 544.96 seconds
Started Jul 13 06:25:04 PM PDT 24
Finished Jul 13 06:34:10 PM PDT 24
Peak memory 249348 kb
Host smart-5c6f3b2f-fc82-4d5b-99bd-0c8fc4063994
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2732183172 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_ping_timeout.2732183172
Directory /workspace/21.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.1259289373
Short name T124
Test name
Test status
Simulation time 2296517396 ps
CPU time 347.38 seconds
Started Jul 13 05:01:39 PM PDT 24
Finished Jul 13 05:07:27 PM PDT 24
Peak memory 268372 kb
Host smart-56d505a4-8719-4339-8f1d-673cb453c469
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259289373 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.alert_handler_shadow_reg_errors_with_csr_rw.1259289373
Directory /workspace/0.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.291532841
Short name T344
Test name
Test status
Simulation time 22950214 ps
CPU time 1.44 seconds
Started Jul 13 05:03:15 PM PDT 24
Finished Jul 13 05:03:17 PM PDT 24
Peak memory 236544 kb
Host smart-6e433ec9-65a7-49a7-8408-4ad2f9300fe1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=291532841 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.alert_handler_intr_test.291532841
Directory /workspace/32.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.3912592308
Short name T120
Test name
Test status
Simulation time 12060339624 ps
CPU time 946.76 seconds
Started Jul 13 05:01:45 PM PDT 24
Finished Jul 13 05:17:33 PM PDT 24
Peak memory 265404 kb
Host smart-b7a27121-e587-4fa8-9ea7-aa560b080d3e
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912592308 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.alert_handler_shadow_reg_errors_with_csr_rw.3912592308
Directory /workspace/2.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/25.alert_handler_ping_timeout.2928771614
Short name T276
Test name
Test status
Simulation time 12315086624 ps
CPU time 542.33 seconds
Started Jul 13 06:25:11 PM PDT 24
Finished Jul 13 06:34:15 PM PDT 24
Peak memory 255708 kb
Host smart-5b3fa77f-ed2b-42a8-b1b8-37ca9b161899
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928771614 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_ping_timeout.2928771614
Directory /workspace/25.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_lpg.2671701131
Short name T177
Test name
Test status
Simulation time 347363005292 ps
CPU time 3058.12 seconds
Started Jul 13 06:25:18 PM PDT 24
Finished Jul 13 07:16:18 PM PDT 24
Peak memory 288072 kb
Host smart-107caeb8-c50e-41f4-87d6-bf3286a7fe45
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671701131 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg.2671701131
Directory /workspace/24.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.1933980921
Short name T128
Test name
Test status
Simulation time 7257849691 ps
CPU time 203.88 seconds
Started Jul 13 05:02:08 PM PDT 24
Finished Jul 13 05:05:32 PM PDT 24
Peak memory 265412 kb
Host smart-bc4aea13-979a-499a-ad84-77ae3359aa56
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1933980921 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shadow_reg_erro
rs.1933980921
Directory /workspace/8.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all.3803029382
Short name T86
Test name
Test status
Simulation time 50461095031 ps
CPU time 2999.42 seconds
Started Jul 13 06:25:24 PM PDT 24
Finished Jul 13 07:15:25 PM PDT 24
Peak memory 289668 kb
Host smart-6275551f-9cf2-44ab-8cbe-43cb01cc0ef2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803029382 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_ha
ndler_stress_all.3803029382
Directory /workspace/29.alert_handler_stress_all/latest

Test location /workspace/coverage/default/15.alert_handler_lpg.2204127606
Short name T8
Test name
Test status
Simulation time 90935045300 ps
CPU time 1257.25 seconds
Started Jul 13 06:24:57 PM PDT 24
Finished Jul 13 06:45:55 PM PDT 24
Peak memory 272884 kb
Host smart-c07262a4-5c98-4829-b3b4-e28c10091290
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2204127606 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg.2204127606
Directory /workspace/15.alert_handler_lpg/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all.703467409
Short name T48
Test name
Test status
Simulation time 841913007808 ps
CPU time 3889.06 seconds
Started Jul 13 06:25:01 PM PDT 24
Finished Jul 13 07:29:52 PM PDT 24
Peak memory 306140 kb
Host smart-0005d443-7dba-4c5e-8610-27eb806c1e87
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703467409 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_han
dler_stress_all.703467409
Directory /workspace/18.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.161139296
Short name T125
Test name
Test status
Simulation time 5876500952 ps
CPU time 206.18 seconds
Started Jul 13 05:02:15 PM PDT 24
Finished Jul 13 05:05:42 PM PDT 24
Peak memory 272120 kb
Host smart-86c2dcf0-80b6-4ec3-a3df-dd0aa582d0da
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=161139296 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shadow_reg_erro
rs.161139296
Directory /workspace/11.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/29.alert_handler_ping_timeout.2073756153
Short name T305
Test name
Test status
Simulation time 30707741216 ps
CPU time 664.85 seconds
Started Jul 13 06:25:16 PM PDT 24
Finished Jul 13 06:36:23 PM PDT 24
Peak memory 249396 kb
Host smart-95ba959b-eab3-4130-99dc-8c36e3905159
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073756153 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_ping_timeout.2073756153
Directory /workspace/29.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.2696122043
Short name T195
Test name
Test status
Simulation time 626075170 ps
CPU time 7.53 seconds
Started Jul 13 05:02:22 PM PDT 24
Finished Jul 13 05:02:30 PM PDT 24
Peak memory 240224 kb
Host smart-4268a844-c092-46bc-8b7b-51f90d9a5a13
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696122043 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 11.alert_handler_csr_mem_rw_with_rand_reset.2696122043
Directory /workspace/11.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all.3693313259
Short name T94
Test name
Test status
Simulation time 187880195519 ps
CPU time 2665.02 seconds
Started Jul 13 06:24:57 PM PDT 24
Finished Jul 13 07:09:23 PM PDT 24
Peak memory 286560 kb
Host smart-40d440f0-615f-4334-912c-b0d0a3a538b4
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693313259 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_ha
ndler_stress_all.3693313259
Directory /workspace/16.alert_handler_stress_all/latest

Test location /workspace/coverage/default/0.alert_handler_ping_timeout.1037144510
Short name T62
Test name
Test status
Simulation time 26878963229 ps
CPU time 521.61 seconds
Started Jul 13 06:24:26 PM PDT 24
Finished Jul 13 06:33:10 PM PDT 24
Peak memory 249316 kb
Host smart-6ab6b20b-1064-4996-a18e-863ec6f405a5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037144510 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_ping_timeout.1037144510
Directory /workspace/0.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_lpg.2603294380
Short name T340
Test name
Test status
Simulation time 54088546800 ps
CPU time 2922.44 seconds
Started Jul 13 06:24:39 PM PDT 24
Finished Jul 13 07:13:24 PM PDT 24
Peak memory 290000 kb
Host smart-baf8ef1b-eee8-4342-bb0b-dea6a981c3ea
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603294380 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg.2603294380
Directory /workspace/5.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.2575791246
Short name T346
Test name
Test status
Simulation time 13067638 ps
CPU time 1.38 seconds
Started Jul 13 05:01:53 PM PDT 24
Finished Jul 13 05:01:54 PM PDT 24
Peak memory 237732 kb
Host smart-044c9899-f5dd-4ac3-9fd4-1436f8173586
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2575791246 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_intr_test.2575791246
Directory /workspace/3.alert_handler_intr_test/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all.703106941
Short name T273
Test name
Test status
Simulation time 54627388422 ps
CPU time 3381.21 seconds
Started Jul 13 06:24:46 PM PDT 24
Finished Jul 13 07:21:09 PM PDT 24
Peak memory 306556 kb
Host smart-6f1c09b2-25c7-49c4-9865-e41d07303694
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703106941 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_hand
ler_stress_all.703106941
Directory /workspace/0.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.1037692941
Short name T123
Test name
Test status
Simulation time 2315553437 ps
CPU time 231.63 seconds
Started Jul 13 05:02:48 PM PDT 24
Finished Jul 13 05:06:41 PM PDT 24
Peak memory 265248 kb
Host smart-68ef3d13-9703-4131-9ca8-7d98293c8aca
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1037692941 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shadow_reg_err
ors.1037692941
Directory /workspace/16.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/12.alert_handler_ping_timeout.662996045
Short name T627
Test name
Test status
Simulation time 31103686766 ps
CPU time 341.2 seconds
Started Jul 13 06:24:48 PM PDT 24
Finished Jul 13 06:30:30 PM PDT 24
Peak memory 248280 kb
Host smart-b946385c-21fc-4e01-a16a-0716ecb1ecdd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662996045 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_ping_timeout.662996045
Directory /workspace/12.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all_with_rand_reset.42270342
Short name T227
Test name
Test status
Simulation time 52060796040 ps
CPU time 798.18 seconds
Started Jul 13 06:25:31 PM PDT 24
Finished Jul 13 06:38:50 PM PDT 24
Peak memory 273288 kb
Host smart-4da43477-8207-4444-b873-3ebe3221a3b0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42270342 -assert nopostproc +UVM_TESTNAME=alert_
handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 26.alert_handler_stress_all_with_rand_reset.42270342
Directory /workspace/26.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.alert_handler_lpg.2582189757
Short name T326
Test name
Test status
Simulation time 123807784357 ps
CPU time 3322.87 seconds
Started Jul 13 06:25:36 PM PDT 24
Finished Jul 13 07:21:00 PM PDT 24
Peak memory 289560 kb
Host smart-ec796980-e1bb-468e-ae26-2edd0d31945f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582189757 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg.2582189757
Directory /workspace/39.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.2106678992
Short name T153
Test name
Test status
Simulation time 59015093 ps
CPU time 2.35 seconds
Started Jul 13 05:01:44 PM PDT 24
Finished Jul 13 05:01:47 PM PDT 24
Peak memory 237736 kb
Host smart-99047cab-3641-4d52-8172-be98341c40e9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2106678992 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_intg_err.2106678992
Directory /workspace/1.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.2583370427
Short name T143
Test name
Test status
Simulation time 14122382133 ps
CPU time 329.06 seconds
Started Jul 13 05:02:24 PM PDT 24
Finished Jul 13 05:07:53 PM PDT 24
Peak memory 265348 kb
Host smart-6f64bec3-3de1-4c94-b0bf-48808e807fc6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2583370427 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shadow_reg_err
ors.2583370427
Directory /workspace/12.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all.3961305659
Short name T47
Test name
Test status
Simulation time 124824379540 ps
CPU time 1545.4 seconds
Started Jul 13 06:24:32 PM PDT 24
Finished Jul 13 06:50:18 PM PDT 24
Peak memory 290368 kb
Host smart-7d578c36-ee4a-4f99-bbc8-d0c5081a5f66
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961305659 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_han
dler_stress_all.3961305659
Directory /workspace/6.alert_handler_stress_all/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all.2132280446
Short name T259
Test name
Test status
Simulation time 40396570828 ps
CPU time 2228.6 seconds
Started Jul 13 06:25:26 PM PDT 24
Finished Jul 13 07:02:36 PM PDT 24
Peak memory 306108 kb
Host smart-d8a3388b-c150-4993-8cce-601919edfc81
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132280446 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_ha
ndler_stress_all.2132280446
Directory /workspace/30.alert_handler_stress_all/latest

Test location /workspace/coverage/default/48.alert_handler_ping_timeout.1502936572
Short name T301
Test name
Test status
Simulation time 43512468676 ps
CPU time 427.06 seconds
Started Jul 13 06:26:08 PM PDT 24
Finished Jul 13 06:33:16 PM PDT 24
Peak memory 249400 kb
Host smart-bc089aa2-5ad1-426a-a290-164ae8946a78
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502936572 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_ping_timeout.1502936572
Directory /workspace/48.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.3975907273
Short name T149
Test name
Test status
Simulation time 6353437353 ps
CPU time 702.26 seconds
Started Jul 13 05:02:47 PM PDT 24
Finished Jul 13 05:14:29 PM PDT 24
Peak memory 265500 kb
Host smart-e57c16b8-78b0-40ad-9be4-0135927442c7
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975907273 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 16.alert_handler_shadow_reg_errors_with_csr_rw.3975907273
Directory /workspace/16.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/10.alert_handler_alert_accum_saturation.3448099684
Short name T3
Test name
Test status
Simulation time 223563832 ps
CPU time 3.32 seconds
Started Jul 13 06:24:39 PM PDT 24
Finished Jul 13 06:24:44 PM PDT 24
Peak memory 249580 kb
Host smart-e3fd6a6b-9773-4687-bb40-5ff47c5313c9
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3448099684 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_alert_accum_saturation.3448099684
Directory /workspace/10.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/11.alert_handler_lpg.600016738
Short name T269
Test name
Test status
Simulation time 160841030152 ps
CPU time 2307.92 seconds
Started Jul 13 06:24:39 PM PDT 24
Finished Jul 13 07:03:09 PM PDT 24
Peak memory 290264 kb
Host smart-0e401c7b-922b-45a4-970e-d04008c75e48
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600016738 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg.600016738
Directory /workspace/11.alert_handler_lpg/latest

Test location /workspace/coverage/default/32.alert_handler_lpg.359577667
Short name T65
Test name
Test status
Simulation time 47443098792 ps
CPU time 1355.61 seconds
Started Jul 13 06:25:16 PM PDT 24
Finished Jul 13 06:47:53 PM PDT 24
Peak memory 289640 kb
Host smart-0f54cf65-68ce-46a7-9e10-521a0a1d27ab
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359577667 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg.359577667
Directory /workspace/32.alert_handler_lpg/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all_with_rand_reset.570884758
Short name T248
Test name
Test status
Simulation time 155667492702 ps
CPU time 3741.75 seconds
Started Jul 13 06:25:24 PM PDT 24
Finished Jul 13 07:27:48 PM PDT 24
Peak memory 322624 kb
Host smart-e1ba8ab3-cbfb-4ec4-8593-eaa87d1a94d7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570884758 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 32.alert_handler_stress_all_with_rand_reset.570884758
Directory /workspace/32.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.alert_handler_esc_alert_accum.148312468
Short name T36
Test name
Test status
Simulation time 1658676450 ps
CPU time 37.27 seconds
Started Jul 13 06:24:29 PM PDT 24
Finished Jul 13 06:25:08 PM PDT 24
Peak memory 257472 kb
Host smart-1c420b56-d52f-48a1-8666-eaaaeec1f08d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14831
2468 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_alert_accum.148312468
Directory /workspace/2.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/11.alert_handler_alert_accum_saturation.3157904925
Short name T202
Test name
Test status
Simulation time 22872503 ps
CPU time 2.32 seconds
Started Jul 13 06:25:10 PM PDT 24
Finished Jul 13 06:25:13 PM PDT 24
Peak memory 249500 kb
Host smart-1c6118fb-c5a6-4fc9-a54a-15d3eeb79dbb
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3157904925 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_alert_accum_saturation.3157904925
Directory /workspace/11.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/17.alert_handler_alert_accum_saturation.3125197412
Short name T213
Test name
Test status
Simulation time 30962741 ps
CPU time 3.09 seconds
Started Jul 13 06:24:54 PM PDT 24
Finished Jul 13 06:24:58 PM PDT 24
Peak memory 249600 kb
Host smart-979475ef-0ff2-41b1-8483-4c01d9c8db81
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3125197412 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_alert_accum_saturation.3125197412
Directory /workspace/17.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/19.alert_handler_alert_accum_saturation.1649428828
Short name T25
Test name
Test status
Simulation time 407430935 ps
CPU time 4.3 seconds
Started Jul 13 06:25:15 PM PDT 24
Finished Jul 13 06:25:21 PM PDT 24
Peak memory 249556 kb
Host smart-ee04c080-13fe-4897-a99b-6ad05f2f75dc
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1649428828 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_alert_accum_saturation.1649428828
Directory /workspace/19.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.2272129896
Short name T225
Test name
Test status
Simulation time 14081878 ps
CPU time 1.8 seconds
Started Jul 13 05:02:15 PM PDT 24
Finished Jul 13 05:02:18 PM PDT 24
Peak memory 236576 kb
Host smart-58fdce78-29d6-4e8b-82c9-ec3e2d6db9b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2272129896 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_intr_test.2272129896
Directory /workspace/10.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.4191322835
Short name T135
Test name
Test status
Simulation time 9030212402 ps
CPU time 358.19 seconds
Started Jul 13 05:02:24 PM PDT 24
Finished Jul 13 05:08:23 PM PDT 24
Peak memory 265328 kb
Host smart-c06d58b5-abd3-434f-a48d-0677e8c08ddd
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191322835 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 12.alert_handler_shadow_reg_errors_with_csr_rw.4191322835
Directory /workspace/12.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all.1029107100
Short name T315
Test name
Test status
Simulation time 128316575775 ps
CPU time 2142.29 seconds
Started Jul 13 06:24:28 PM PDT 24
Finished Jul 13 07:00:12 PM PDT 24
Peak memory 289540 kb
Host smart-9806f6fb-946f-4ace-834c-d48c9ab2e256
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029107100 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_han
dler_stress_all.1029107100
Directory /workspace/2.alert_handler_stress_all/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all.3671440920
Short name T313
Test name
Test status
Simulation time 49308419594 ps
CPU time 2243.65 seconds
Started Jul 13 06:25:10 PM PDT 24
Finished Jul 13 07:02:36 PM PDT 24
Peak memory 289964 kb
Host smart-e2573fb3-22d5-4654-b801-90fab79a5500
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671440920 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_ha
ndler_stress_all.3671440920
Directory /workspace/20.alert_handler_stress_all/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all.351477280
Short name T309
Test name
Test status
Simulation time 72848135098 ps
CPU time 1992.38 seconds
Started Jul 13 06:25:22 PM PDT 24
Finished Jul 13 06:58:36 PM PDT 24
Peak memory 306400 kb
Host smart-769ce83c-0628-453e-8289-a4a35bcab791
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351477280 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_han
dler_stress_all.351477280
Directory /workspace/33.alert_handler_stress_all/latest

Test location /workspace/coverage/default/1.alert_handler_entropy_stress.3810299164
Short name T440
Test name
Test status
Simulation time 2030627964 ps
CPU time 12.96 seconds
Started Jul 13 06:24:33 PM PDT 24
Finished Jul 13 06:24:46 PM PDT 24
Peak memory 249200 kb
Host smart-5197bcca-99b1-4471-b049-96994331b7b4
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3810299164 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy_stress.3810299164
Directory /workspace/1.alert_handler_entropy_stress/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_intg_err.2616628454
Short name T168
Test name
Test status
Simulation time 3052196056 ps
CPU time 68.03 seconds
Started Jul 13 05:02:31 PM PDT 24
Finished Jul 13 05:03:39 PM PDT 24
Peak memory 240516 kb
Host smart-cfad06c5-1f23-49de-a550-e6aea944f878
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2616628454 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_intg_err.2616628454
Directory /workspace/12.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.326113300
Short name T146
Test name
Test status
Simulation time 14625785912 ps
CPU time 964.33 seconds
Started Jul 13 05:02:38 PM PDT 24
Finished Jul 13 05:18:42 PM PDT 24
Peak memory 265320 kb
Host smart-cf7665b0-259e-4d4c-9861-5b211aa3e1b6
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326113300 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 15.alert_handler_shadow_reg_errors_with_csr_rw.326113300
Directory /workspace/15.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.3390802904
Short name T160
Test name
Test status
Simulation time 1501898386 ps
CPU time 91.11 seconds
Started Jul 13 05:02:00 PM PDT 24
Finished Jul 13 05:03:32 PM PDT 24
Peak memory 245780 kb
Host smart-7ee73176-cf79-424b-83bc-f54dd6e68a49
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3390802904 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_intg_err.3390802904
Directory /workspace/6.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/1.alert_handler_lpg.3268436694
Short name T535
Test name
Test status
Simulation time 114692220130 ps
CPU time 2095.23 seconds
Started Jul 13 06:24:27 PM PDT 24
Finished Jul 13 06:59:25 PM PDT 24
Peak memory 289996 kb
Host smart-1626ee8a-ac7d-44dc-b7ff-b14ad741f4fd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3268436694 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg.3268436694
Directory /workspace/1.alert_handler_lpg/latest

Test location /workspace/coverage/default/1.alert_handler_lpg_stub_clk.2133243708
Short name T240
Test name
Test status
Simulation time 10100166102 ps
CPU time 837.37 seconds
Started Jul 13 06:24:27 PM PDT 24
Finished Jul 13 06:38:26 PM PDT 24
Peak memory 274080 kb
Host smart-9f2bbc70-a5f4-4304-9372-6f0a149a93d9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2133243708 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg_stub_clk.2133243708
Directory /workspace/1.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/1.alert_handler_ping_timeout.2644939594
Short name T262
Test name
Test status
Simulation time 22285229350 ps
CPU time 260.06 seconds
Started Jul 13 06:24:46 PM PDT 24
Finished Jul 13 06:29:08 PM PDT 24
Peak memory 249400 kb
Host smart-f5bb7904-edfe-40d7-ab32-196164848359
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644939594 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_ping_timeout.2644939594
Directory /workspace/1.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_ping_timeout.1835502709
Short name T499
Test name
Test status
Simulation time 10263603676 ps
CPU time 433.64 seconds
Started Jul 13 06:25:15 PM PDT 24
Finished Jul 13 06:32:31 PM PDT 24
Peak memory 256104 kb
Host smart-60185ab3-6de7-44df-abc8-7f44134e3379
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835502709 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_ping_timeout.1835502709
Directory /workspace/10.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_sig_int_fail.3401124795
Short name T320
Test name
Test status
Simulation time 925235901 ps
CPU time 52.3 seconds
Started Jul 13 06:24:52 PM PDT 24
Finished Jul 13 06:25:46 PM PDT 24
Peak memory 256388 kb
Host smart-1a89d827-801f-4ba3-9ae2-c629b06b053a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34011
24795 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_sig_int_fail.3401124795
Directory /workspace/11.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all.4151803711
Short name T22
Test name
Test status
Simulation time 265869768274 ps
CPU time 2081.89 seconds
Started Jul 13 06:24:45 PM PDT 24
Finished Jul 13 06:59:28 PM PDT 24
Peak memory 282144 kb
Host smart-e50ca508-4c4d-49e0-a049-21272d9f28be
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151803711 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_ha
ndler_stress_all.4151803711
Directory /workspace/12.alert_handler_stress_all/latest

Test location /workspace/coverage/default/16.alert_handler_entropy.1723569341
Short name T278
Test name
Test status
Simulation time 41847497140 ps
CPU time 2306.26 seconds
Started Jul 13 06:24:49 PM PDT 24
Finished Jul 13 07:03:16 PM PDT 24
Peak memory 290116 kb
Host smart-6c3b1c2b-c59a-4112-a4c4-d5141ff8cc17
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1723569341 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy.1723569341
Directory /workspace/16.alert_handler_entropy/latest

Test location /workspace/coverage/default/16.alert_handler_esc_alert_accum.4053302764
Short name T255
Test name
Test status
Simulation time 7307977209 ps
CPU time 194.89 seconds
Started Jul 13 06:24:46 PM PDT 24
Finished Jul 13 06:28:03 PM PDT 24
Peak memory 257488 kb
Host smart-026a8a38-fb68-4e8b-a66d-d39160e1fa26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40533
02764 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_alert_accum.4053302764
Directory /workspace/16.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all.2540318236
Short name T105
Test name
Test status
Simulation time 991487081304 ps
CPU time 4596.94 seconds
Started Jul 13 06:24:58 PM PDT 24
Finished Jul 13 07:41:36 PM PDT 24
Peak memory 304748 kb
Host smart-76dfd2b2-d2b1-4b0f-9aca-a8f489bfa3d9
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540318236 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_ha
ndler_stress_all.2540318236
Directory /workspace/17.alert_handler_stress_all/latest

Test location /workspace/coverage/default/21.alert_handler_smoke.1011208763
Short name T263
Test name
Test status
Simulation time 724666392 ps
CPU time 46.22 seconds
Started Jul 13 06:25:04 PM PDT 24
Finished Jul 13 06:25:51 PM PDT 24
Peak memory 257424 kb
Host smart-f85d849a-a17e-4ebf-b7ed-9c2ba436e23b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10112
08763 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_smoke.1011208763
Directory /workspace/21.alert_handler_smoke/latest

Test location /workspace/coverage/default/3.alert_handler_ping_timeout.702674292
Short name T221
Test name
Test status
Simulation time 16157824919 ps
CPU time 344.07 seconds
Started Jul 13 06:24:29 PM PDT 24
Finished Jul 13 06:30:15 PM PDT 24
Peak memory 249392 kb
Host smart-07627edb-0c94-4851-b9e3-6589114d864e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=702674292 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_ping_timeout.702674292
Directory /workspace/3.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all.217238582
Short name T244
Test name
Test status
Simulation time 13810710296 ps
CPU time 1307.5 seconds
Started Jul 13 06:25:24 PM PDT 24
Finished Jul 13 06:47:13 PM PDT 24
Peak memory 290292 kb
Host smart-0b632a8d-747d-492f-bd73-9496a1ae48cf
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217238582 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_han
dler_stress_all.217238582
Directory /workspace/34.alert_handler_stress_all/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all.3911355632
Short name T237
Test name
Test status
Simulation time 42062719293 ps
CPU time 1989.84 seconds
Started Jul 13 06:25:34 PM PDT 24
Finished Jul 13 06:58:46 PM PDT 24
Peak memory 289952 kb
Host smart-4d2ee77d-8d4c-47ec-83dd-ae16bb8f6d94
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911355632 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_ha
ndler_stress_all.3911355632
Directory /workspace/39.alert_handler_stress_all/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all_with_rand_reset.3367762190
Short name T183
Test name
Test status
Simulation time 113965431641 ps
CPU time 7702.81 seconds
Started Jul 13 06:24:39 PM PDT 24
Finished Jul 13 08:33:14 PM PDT 24
Peak memory 339036 kb
Host smart-631814ec-ae39-4dab-83f7-e63847f0f727
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367762190 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.alert_handler_stress_all_with_rand_reset.3367762190
Directory /workspace/4.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.alert_handler_sig_int_fail.3657666265
Short name T239
Test name
Test status
Simulation time 1392116337 ps
CPU time 46.75 seconds
Started Jul 13 06:25:56 PM PDT 24
Finished Jul 13 06:26:44 PM PDT 24
Peak memory 248936 kb
Host smart-7708491a-98ab-43ba-90e6-a2fb68c3cbaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36576
66265 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_sig_int_fail.3657666265
Directory /workspace/44.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all_with_rand_reset.2167409638
Short name T96
Test name
Test status
Simulation time 35857115384 ps
CPU time 3113.26 seconds
Started Jul 13 06:25:54 PM PDT 24
Finished Jul 13 07:17:48 PM PDT 24
Peak memory 305840 kb
Host smart-95c571cf-72ac-4b9b-a836-415790527880
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167409638 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 44.alert_handler_stress_all_with_rand_reset.2167409638
Directory /workspace/44.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.alert_handler_sig_int_fail.550534875
Short name T311
Test name
Test status
Simulation time 725803897 ps
CPU time 55.62 seconds
Started Jul 13 06:26:07 PM PDT 24
Finished Jul 13 06:27:03 PM PDT 24
Peak memory 256948 kb
Host smart-101fed71-cb5f-4068-adce-17fcf2335c41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55053
4875 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_sig_int_fail.550534875
Directory /workspace/49.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/5.alert_handler_lpg_stub_clk.2646249686
Short name T238
Test name
Test status
Simulation time 27177042392 ps
CPU time 719.39 seconds
Started Jul 13 06:24:44 PM PDT 24
Finished Jul 13 06:36:44 PM PDT 24
Peak memory 269800 kb
Host smart-04e1b59a-f9b4-4818-b5ea-308ee34e11df
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646249686 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg_stub_clk.2646249686
Directory /workspace/5.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/5.alert_handler_sig_int_fail.3099694054
Short name T312
Test name
Test status
Simulation time 214120248 ps
CPU time 23.43 seconds
Started Jul 13 06:25:01 PM PDT 24
Finished Jul 13 06:25:26 PM PDT 24
Peak memory 256784 kb
Host smart-c9aeb1f7-73c7-43b0-8230-61663b0c28b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30996
94054 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_sig_int_fail.3099694054
Directory /workspace/5.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.1032997206
Short name T161
Test name
Test status
Simulation time 1240537644 ps
CPU time 86.67 seconds
Started Jul 13 05:02:15 PM PDT 24
Finished Jul 13 05:03:42 PM PDT 24
Peak memory 240404 kb
Host smart-e49915bb-a3df-412f-baa6-07063c1e3cbd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1032997206 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_intg_err.1032997206
Directory /workspace/11.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.3688520498
Short name T134
Test name
Test status
Simulation time 4632163576 ps
CPU time 179.53 seconds
Started Jul 13 05:01:44 PM PDT 24
Finished Jul 13 05:04:44 PM PDT 24
Peak memory 265352 kb
Host smart-f0332bdd-7058-4636-8dc9-2bda3a9cf6fc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3688520498 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shadow_reg_erro
rs.3688520498
Directory /workspace/1.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.3359835960
Short name T141
Test name
Test status
Simulation time 5430713635 ps
CPU time 193.72 seconds
Started Jul 13 05:01:52 PM PDT 24
Finished Jul 13 05:05:07 PM PDT 24
Peak memory 265348 kb
Host smart-ff60278c-c095-47d2-b593-f164b988ca8f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3359835960 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shadow_reg_erro
rs.3359835960
Directory /workspace/4.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.1964599831
Short name T159
Test name
Test status
Simulation time 91519091 ps
CPU time 5.48 seconds
Started Jul 13 05:02:38 PM PDT 24
Finished Jul 13 05:02:44 PM PDT 24
Peak memory 237968 kb
Host smart-96f3e3c0-f5c8-460b-acb2-474a1997c055
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1964599831 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_intg_err.1964599831
Directory /workspace/14.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.2287509300
Short name T167
Test name
Test status
Simulation time 5203919815 ps
CPU time 88.8 seconds
Started Jul 13 05:02:15 PM PDT 24
Finished Jul 13 05:03:44 PM PDT 24
Peak memory 240604 kb
Host smart-325eb7d8-d106-4aa0-bf95-c0595026ad2c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2287509300 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_intg_err.2287509300
Directory /workspace/10.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.2474577009
Short name T131
Test name
Test status
Simulation time 33249018010 ps
CPU time 678.33 seconds
Started Jul 13 05:02:32 PM PDT 24
Finished Jul 13 05:13:50 PM PDT 24
Peak memory 269892 kb
Host smart-5ff5fc3d-c2da-45e4-93bf-601a71d1ffdc
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474577009 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 13.alert_handler_shadow_reg_errors_with_csr_rw.2474577009
Directory /workspace/13.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.3986056454
Short name T162
Test name
Test status
Simulation time 178281495 ps
CPU time 3.55 seconds
Started Jul 13 05:02:31 PM PDT 24
Finished Jul 13 05:02:34 PM PDT 24
Peak memory 237568 kb
Host smart-c897b45b-d3e1-4117-90be-fca22b35e591
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3986056454 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_intg_err.3986056454
Directory /workspace/13.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.2332742981
Short name T164
Test name
Test status
Simulation time 109797497 ps
CPU time 2.78 seconds
Started Jul 13 05:02:39 PM PDT 24
Finished Jul 13 05:02:42 PM PDT 24
Peak memory 237552 kb
Host smart-0310e116-ad5e-4396-80d0-2ab3d9d2b965
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2332742981 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_intg_err.2332742981
Directory /workspace/15.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.1997668764
Short name T163
Test name
Test status
Simulation time 2214553280 ps
CPU time 50.16 seconds
Started Jul 13 05:02:55 PM PDT 24
Finished Jul 13 05:03:46 PM PDT 24
Peak memory 240568 kb
Host smart-ff165c6d-db9b-42fb-9750-e5b3903daebd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1997668764 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_intg_err.1997668764
Directory /workspace/18.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.2663331765
Short name T158
Test name
Test status
Simulation time 590610940 ps
CPU time 24.55 seconds
Started Jul 13 05:02:55 PM PDT 24
Finished Jul 13 05:03:20 PM PDT 24
Peak memory 240404 kb
Host smart-35eead15-f87c-4a64-8de8-974954e8c663
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2663331765 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_intg_err.2663331765
Directory /workspace/19.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.2707135261
Short name T165
Test name
Test status
Simulation time 1781999714 ps
CPU time 72.77 seconds
Started Jul 13 05:02:00 PM PDT 24
Finished Jul 13 05:03:13 PM PDT 24
Peak memory 240432 kb
Host smart-9146cc92-61af-4540-bea0-1dde02063fde
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2707135261 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_intg_err.2707135261
Directory /workspace/4.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.625572891
Short name T173
Test name
Test status
Simulation time 1373426667 ps
CPU time 51.6 seconds
Started Jul 13 05:01:36 PM PDT 24
Finished Jul 13 05:02:27 PM PDT 24
Peak memory 237648 kb
Host smart-897e7ad6-aeab-49e2-97f7-f0c508073b33
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=625572891 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_intg_err.625572891
Directory /workspace/0.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.1959794393
Short name T172
Test name
Test status
Simulation time 3678896917 ps
CPU time 68.5 seconds
Started Jul 13 05:02:48 PM PDT 24
Finished Jul 13 05:03:57 PM PDT 24
Peak memory 240556 kb
Host smart-5d10838a-261a-4074-9132-48a04812ebc3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1959794393 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_intg_err.1959794393
Directory /workspace/17.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.3466590331
Short name T174
Test name
Test status
Simulation time 447053501 ps
CPU time 3.75 seconds
Started Jul 13 05:01:44 PM PDT 24
Finished Jul 13 05:01:49 PM PDT 24
Peak memory 237980 kb
Host smart-e8b2cef8-8683-44b6-a42d-30530189587c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3466590331 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_intg_err.3466590331
Directory /workspace/2.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.2946381120
Short name T152
Test name
Test status
Simulation time 63834623 ps
CPU time 3.12 seconds
Started Jul 13 05:02:07 PM PDT 24
Finished Jul 13 05:02:11 PM PDT 24
Peak memory 236600 kb
Host smart-7621b975-49c8-4476-80be-c66364ce6300
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2946381120 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_intg_err.2946381120
Directory /workspace/8.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.1316293098
Short name T180
Test name
Test status
Simulation time 19105554839 ps
CPU time 326.33 seconds
Started Jul 13 05:01:36 PM PDT 24
Finished Jul 13 05:07:03 PM PDT 24
Peak memory 241676 kb
Host smart-1279ca82-5b24-423b-8162-177c70fc4bc3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1316293098 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_aliasing.1316293098
Directory /workspace/0.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.1583705481
Short name T793
Test name
Test status
Simulation time 3270263357 ps
CPU time 104.55 seconds
Started Jul 13 05:01:37 PM PDT 24
Finished Jul 13 05:03:22 PM PDT 24
Peak memory 237544 kb
Host smart-b099976a-f15d-45d7-82e7-f144d9df1bac
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1583705481 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_bit_bash.1583705481
Directory /workspace/0.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.1652194484
Short name T196
Test name
Test status
Simulation time 447964928 ps
CPU time 10.59 seconds
Started Jul 13 05:01:38 PM PDT 24
Finished Jul 13 05:01:49 PM PDT 24
Peak memory 249060 kb
Host smart-82f38116-c3ee-4ce6-acfa-68f0c7297e77
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1652194484 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_hw_reset.1652194484
Directory /workspace/0.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.4067602472
Short name T790
Test name
Test status
Simulation time 114217908 ps
CPU time 5.58 seconds
Started Jul 13 05:01:39 PM PDT 24
Finished Jul 13 05:01:45 PM PDT 24
Peak memory 256540 kb
Host smart-4fd2bd6a-d63b-4c0f-8732-8acd5ad8b2b0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067602472 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 0.alert_handler_csr_mem_rw_with_rand_reset.4067602472
Directory /workspace/0.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.2860157149
Short name T181
Test name
Test status
Simulation time 39694067 ps
CPU time 5.72 seconds
Started Jul 13 05:01:38 PM PDT 24
Finished Jul 13 05:01:44 PM PDT 24
Peak memory 237516 kb
Host smart-5b26b304-8e33-4bfc-a85c-fa8d40d1059e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2860157149 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_rw.2860157149
Directory /workspace/0.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.435666735
Short name T756
Test name
Test status
Simulation time 14902136 ps
CPU time 1.51 seconds
Started Jul 13 05:01:38 PM PDT 24
Finished Jul 13 05:01:40 PM PDT 24
Peak memory 237588 kb
Host smart-41a83c41-c19c-4848-aea5-e890a664ca17
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=435666735 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_intr_test.435666735
Directory /workspace/0.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.2978375470
Short name T171
Test name
Test status
Simulation time 275024173 ps
CPU time 24.44 seconds
Started Jul 13 05:01:38 PM PDT 24
Finished Jul 13 05:02:03 PM PDT 24
Peak memory 245776 kb
Host smart-804ffc8f-b97c-484c-b6d7-6b74771682c5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2978375470 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_same_csr_out
standing.2978375470
Directory /workspace/0.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.1385256151
Short name T726
Test name
Test status
Simulation time 131312836 ps
CPU time 6.02 seconds
Started Jul 13 05:01:36 PM PDT 24
Finished Jul 13 05:01:43 PM PDT 24
Peak memory 251680 kb
Host smart-af788889-9fd0-4c33-934e-28295775729c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1385256151 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_errors.1385256151
Directory /workspace/0.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.4037651483
Short name T754
Test name
Test status
Simulation time 3479161149 ps
CPU time 241.04 seconds
Started Jul 13 05:01:44 PM PDT 24
Finished Jul 13 05:05:46 PM PDT 24
Peak memory 240292 kb
Host smart-f203d03f-7d7e-4dc5-b28a-70aabb7e5c27
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4037651483 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_aliasing.4037651483
Directory /workspace/1.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.472479837
Short name T819
Test name
Test status
Simulation time 16798241771 ps
CPU time 237.63 seconds
Started Jul 13 05:01:43 PM PDT 24
Finished Jul 13 05:05:41 PM PDT 24
Peak memory 240580 kb
Host smart-c6f46ae3-a805-48b3-b121-64073611d1c1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=472479837 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_bit_bash.472479837
Directory /workspace/1.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.1271267503
Short name T720
Test name
Test status
Simulation time 439081027 ps
CPU time 5.39 seconds
Started Jul 13 05:01:46 PM PDT 24
Finished Jul 13 05:01:51 PM PDT 24
Peak memory 248696 kb
Host smart-378a03c0-de76-4827-8b65-9a09d500765c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1271267503 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_hw_reset.1271267503
Directory /workspace/1.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.4235224064
Short name T351
Test name
Test status
Simulation time 145535115 ps
CPU time 6.13 seconds
Started Jul 13 05:01:44 PM PDT 24
Finished Jul 13 05:01:51 PM PDT 24
Peak memory 239676 kb
Host smart-d5c0ed08-5137-43ca-ab18-4da52f36c773
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235224064 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 1.alert_handler_csr_mem_rw_with_rand_reset.4235224064
Directory /workspace/1.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.2876647014
Short name T785
Test name
Test status
Simulation time 693425678 ps
CPU time 9.1 seconds
Started Jul 13 05:01:45 PM PDT 24
Finished Jul 13 05:01:55 PM PDT 24
Peak memory 236532 kb
Host smart-c6db371b-6279-41a7-8f39-e76a0a7fae67
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2876647014 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_rw.2876647014
Directory /workspace/1.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.362569420
Short name T812
Test name
Test status
Simulation time 31806983 ps
CPU time 1.3 seconds
Started Jul 13 05:01:44 PM PDT 24
Finished Jul 13 05:01:46 PM PDT 24
Peak memory 237360 kb
Host smart-5fe9a1f5-d582-41ba-a491-108882520c04
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=362569420 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_intr_test.362569420
Directory /workspace/1.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.1442504046
Short name T750
Test name
Test status
Simulation time 511009674 ps
CPU time 41.74 seconds
Started Jul 13 05:01:44 PM PDT 24
Finished Jul 13 05:02:27 PM PDT 24
Peak memory 244736 kb
Host smart-d1070460-5eb9-43aa-8cbb-b5e4d3e0e9fa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1442504046 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_same_csr_out
standing.1442504046
Directory /workspace/1.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.2289483843
Short name T766
Test name
Test status
Simulation time 2405909479 ps
CPU time 14.97 seconds
Started Jul 13 05:01:44 PM PDT 24
Finished Jul 13 05:01:59 PM PDT 24
Peak memory 248756 kb
Host smart-a09cafba-a4fa-4df9-b1ba-c42959c613ad
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2289483843 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_errors.2289483843
Directory /workspace/1.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.2692748514
Short name T354
Test name
Test status
Simulation time 66836035 ps
CPU time 9.74 seconds
Started Jul 13 05:02:14 PM PDT 24
Finished Jul 13 05:02:24 PM PDT 24
Peak memory 256456 kb
Host smart-506c059b-eb0b-4fa7-b2f8-4373f7351caf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692748514 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 10.alert_handler_csr_mem_rw_with_rand_reset.2692748514
Directory /workspace/10.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.442740174
Short name T352
Test name
Test status
Simulation time 35352952 ps
CPU time 5.42 seconds
Started Jul 13 05:02:18 PM PDT 24
Finished Jul 13 05:02:23 PM PDT 24
Peak memory 237476 kb
Host smart-d74680c9-130a-4556-9440-db6b3bfbbc0b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=442740174 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_csr_rw.442740174
Directory /workspace/10.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.3365432395
Short name T717
Test name
Test status
Simulation time 695523782 ps
CPU time 22.25 seconds
Started Jul 13 05:02:15 PM PDT 24
Finished Jul 13 05:02:38 PM PDT 24
Peak memory 248716 kb
Host smart-bc5fe89e-38f7-4080-b413-be683f9d7a01
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3365432395 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_same_csr_ou
tstanding.3365432395
Directory /workspace/10.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.43234165
Short name T129
Test name
Test status
Simulation time 7802737136 ps
CPU time 158.16 seconds
Started Jul 13 05:02:14 PM PDT 24
Finished Jul 13 05:04:53 PM PDT 24
Peak memory 265336 kb
Host smart-c342a71d-5d23-4b90-a492-1ded5d000e3e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=43234165 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shadow_reg_error
s.43234165
Directory /workspace/10.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.3931111342
Short name T133
Test name
Test status
Simulation time 4252183905 ps
CPU time 550.97 seconds
Started Jul 13 05:02:14 PM PDT 24
Finished Jul 13 05:11:26 PM PDT 24
Peak memory 271200 kb
Host smart-2d5679ca-759d-4595-a637-b8d8f6724a7a
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931111342 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 10.alert_handler_shadow_reg_errors_with_csr_rw.3931111342
Directory /workspace/10.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.4130700698
Short name T735
Test name
Test status
Simulation time 72255784 ps
CPU time 10.99 seconds
Started Jul 13 05:02:13 PM PDT 24
Finished Jul 13 05:02:25 PM PDT 24
Peak memory 246940 kb
Host smart-f72351e1-6a45-42c9-98ac-5bfb9c2f420b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4130700698 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_errors.4130700698
Directory /workspace/10.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.4063821338
Short name T771
Test name
Test status
Simulation time 124036610 ps
CPU time 8.5 seconds
Started Jul 13 05:02:25 PM PDT 24
Finished Jul 13 05:02:33 PM PDT 24
Peak memory 236612 kb
Host smart-68853699-df60-446f-b797-93905fc9dab6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4063821338 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_csr_rw.4063821338
Directory /workspace/11.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.1799377033
Short name T721
Test name
Test status
Simulation time 9061302 ps
CPU time 1.56 seconds
Started Jul 13 05:02:23 PM PDT 24
Finished Jul 13 05:02:25 PM PDT 24
Peak memory 237576 kb
Host smart-18fb8b83-362b-45cf-b535-551c0396a1f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1799377033 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_intr_test.1799377033
Directory /workspace/11.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.1696899050
Short name T815
Test name
Test status
Simulation time 110958294 ps
CPU time 12.13 seconds
Started Jul 13 05:02:20 PM PDT 24
Finished Jul 13 05:02:33 PM PDT 24
Peak memory 244808 kb
Host smart-642fa31c-7f15-4f7e-8437-6972c5196d06
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1696899050 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_same_csr_ou
tstanding.1696899050
Directory /workspace/11.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.3281291353
Short name T116
Test name
Test status
Simulation time 30582126519 ps
CPU time 459.48 seconds
Started Jul 13 05:02:14 PM PDT 24
Finished Jul 13 05:09:54 PM PDT 24
Peak memory 265380 kb
Host smart-c2cd8549-86c6-42f2-be75-0669f6381bfa
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281291353 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 11.alert_handler_shadow_reg_errors_with_csr_rw.3281291353
Directory /workspace/11.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.229166090
Short name T772
Test name
Test status
Simulation time 99696107 ps
CPU time 11.88 seconds
Started Jul 13 05:02:15 PM PDT 24
Finished Jul 13 05:02:28 PM PDT 24
Peak memory 256860 kb
Host smart-b06a90db-b256-40de-8592-3cdd5cd3ac6b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=229166090 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_errors.229166090
Directory /workspace/11.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.171153092
Short name T169
Test name
Test status
Simulation time 253890572 ps
CPU time 7.06 seconds
Started Jul 13 05:02:41 PM PDT 24
Finished Jul 13 05:02:48 PM PDT 24
Peak memory 239668 kb
Host smart-9a33ef28-7a9e-4e97-b79f-d02cb229c6d3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171153092 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 12.alert_handler_csr_mem_rw_with_rand_reset.171153092
Directory /workspace/12.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.2992386054
Short name T733
Test name
Test status
Simulation time 115236456 ps
CPU time 4.42 seconds
Started Jul 13 05:02:31 PM PDT 24
Finished Jul 13 05:02:35 PM PDT 24
Peak memory 236448 kb
Host smart-2e1d1dfa-e0fb-47d5-9bdd-b13bfd75e43d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2992386054 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_csr_rw.2992386054
Directory /workspace/12.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.283989865
Short name T757
Test name
Test status
Simulation time 8774083 ps
CPU time 1.38 seconds
Started Jul 13 05:02:39 PM PDT 24
Finished Jul 13 05:02:41 PM PDT 24
Peak memory 236632 kb
Host smart-020f954c-9d11-4b57-8a94-a66056fb37a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=283989865 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_intr_test.283989865
Directory /workspace/12.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.3008130096
Short name T784
Test name
Test status
Simulation time 572551887 ps
CPU time 36.1 seconds
Started Jul 13 05:02:39 PM PDT 24
Finished Jul 13 05:03:16 PM PDT 24
Peak memory 244808 kb
Host smart-7bcce4e5-9e75-4022-993a-e760e15107b6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3008130096 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_same_csr_ou
tstanding.3008130096
Directory /workspace/12.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.4177293995
Short name T727
Test name
Test status
Simulation time 1075154736 ps
CPU time 16.18 seconds
Started Jul 13 05:02:33 PM PDT 24
Finished Jul 13 05:02:49 PM PDT 24
Peak memory 248344 kb
Host smart-ad705495-1ad0-4eef-9dba-d2e1831671e2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4177293995 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_errors.4177293995
Directory /workspace/12.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.2123245933
Short name T349
Test name
Test status
Simulation time 1086181422 ps
CPU time 8.96 seconds
Started Jul 13 05:02:30 PM PDT 24
Finished Jul 13 05:02:39 PM PDT 24
Peak memory 239572 kb
Host smart-a27849cd-696d-45f5-9043-8b5b40c17361
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123245933 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 13.alert_handler_csr_mem_rw_with_rand_reset.2123245933
Directory /workspace/13.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.21262163
Short name T789
Test name
Test status
Simulation time 496084402 ps
CPU time 9.73 seconds
Started Jul 13 05:02:30 PM PDT 24
Finished Jul 13 05:02:40 PM PDT 24
Peak memory 237472 kb
Host smart-c1e7aaa0-1609-492d-94d7-00a86c66711e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=21262163 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_csr_rw.21262163
Directory /workspace/13.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.2318896657
Short name T778
Test name
Test status
Simulation time 8488320 ps
CPU time 1.58 seconds
Started Jul 13 05:02:32 PM PDT 24
Finished Jul 13 05:02:34 PM PDT 24
Peak memory 237488 kb
Host smart-c0a6c097-efe3-45b9-aead-723ab4643d20
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2318896657 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_intr_test.2318896657
Directory /workspace/13.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.2741946488
Short name T762
Test name
Test status
Simulation time 2068663871 ps
CPU time 43.13 seconds
Started Jul 13 05:02:40 PM PDT 24
Finished Jul 13 05:03:24 PM PDT 24
Peak memory 248712 kb
Host smart-a96a86d8-9493-4348-a2ab-14297b807afc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2741946488 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_same_csr_ou
tstanding.2741946488
Directory /workspace/13.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.258059036
Short name T122
Test name
Test status
Simulation time 843774798 ps
CPU time 113.88 seconds
Started Jul 13 05:02:35 PM PDT 24
Finished Jul 13 05:04:29 PM PDT 24
Peak memory 265500 kb
Host smart-0b4df265-334d-45d7-b23e-858777305c8b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=258059036 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shadow_reg_erro
rs.258059036
Directory /workspace/13.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.1811721722
Short name T799
Test name
Test status
Simulation time 2508557879 ps
CPU time 26.1 seconds
Started Jul 13 05:02:40 PM PDT 24
Finished Jul 13 05:03:06 PM PDT 24
Peak memory 248856 kb
Host smart-1938d498-d1cf-4c15-b1c7-c3fb002994b8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1811721722 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_errors.1811721722
Directory /workspace/13.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.3644811497
Short name T767
Test name
Test status
Simulation time 291228026 ps
CPU time 5.15 seconds
Started Jul 13 05:02:37 PM PDT 24
Finished Jul 13 05:02:42 PM PDT 24
Peak memory 240880 kb
Host smart-b9e64364-6e70-442f-99e8-48c25d87d593
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644811497 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 14.alert_handler_csr_mem_rw_with_rand_reset.3644811497
Directory /workspace/14.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.1998757893
Short name T814
Test name
Test status
Simulation time 162718705 ps
CPU time 5.75 seconds
Started Jul 13 05:02:40 PM PDT 24
Finished Jul 13 05:02:46 PM PDT 24
Peak memory 237760 kb
Host smart-74043abe-03de-486b-ab85-02c465697281
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1998757893 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_csr_rw.1998757893
Directory /workspace/14.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.1216586481
Short name T760
Test name
Test status
Simulation time 10343457 ps
CPU time 1.39 seconds
Started Jul 13 05:02:40 PM PDT 24
Finished Jul 13 05:02:42 PM PDT 24
Peak memory 237596 kb
Host smart-9c6f487b-d777-40cb-8e59-56e0800b16bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1216586481 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_intr_test.1216586481
Directory /workspace/14.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.431303245
Short name T788
Test name
Test status
Simulation time 1870056283 ps
CPU time 20.3 seconds
Started Jul 13 05:02:38 PM PDT 24
Finished Jul 13 05:02:59 PM PDT 24
Peak memory 245776 kb
Host smart-5d5fa2e3-c953-4d8e-890e-1e46ef9e096e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=431303245 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_same_csr_out
standing.431303245
Directory /workspace/14.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.3298859670
Short name T147
Test name
Test status
Simulation time 2319561244 ps
CPU time 174.02 seconds
Started Jul 13 05:02:39 PM PDT 24
Finished Jul 13 05:05:34 PM PDT 24
Peak memory 265472 kb
Host smart-d8e61de3-6966-4777-91d0-d6e09483c3ec
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3298859670 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shadow_reg_err
ors.3298859670
Directory /workspace/14.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.2048094084
Short name T151
Test name
Test status
Simulation time 67940606390 ps
CPU time 1045.32 seconds
Started Jul 13 05:02:40 PM PDT 24
Finished Jul 13 05:20:06 PM PDT 24
Peak memory 265400 kb
Host smart-d72b8626-27bc-4602-8165-9365b0f717ae
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048094084 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 14.alert_handler_shadow_reg_errors_with_csr_rw.2048094084
Directory /workspace/14.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.421997029
Short name T713
Test name
Test status
Simulation time 28070199 ps
CPU time 4.24 seconds
Started Jul 13 05:02:38 PM PDT 24
Finished Jul 13 05:02:42 PM PDT 24
Peak memory 250436 kb
Host smart-97181de5-94df-498c-9857-cea015a70abb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=421997029 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_errors.421997029
Directory /workspace/14.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.56515630
Short name T755
Test name
Test status
Simulation time 208689313 ps
CPU time 14.15 seconds
Started Jul 13 05:02:47 PM PDT 24
Finished Jul 13 05:03:02 PM PDT 24
Peak memory 243552 kb
Host smart-555e6473-7dd8-455c-a285-55c6ab782703
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56515630 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 15.alert_handler_csr_mem_rw_with_rand_reset.56515630
Directory /workspace/15.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.2953608513
Short name T797
Test name
Test status
Simulation time 33669420 ps
CPU time 4.32 seconds
Started Jul 13 05:02:48 PM PDT 24
Finished Jul 13 05:02:53 PM PDT 24
Peak memory 236452 kb
Host smart-f2c806a9-55ab-4dca-a576-620cc0e7f342
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2953608513 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_csr_rw.2953608513
Directory /workspace/15.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.2309264570
Short name T738
Test name
Test status
Simulation time 11238069 ps
CPU time 1.7 seconds
Started Jul 13 05:02:48 PM PDT 24
Finished Jul 13 05:02:50 PM PDT 24
Peak memory 237568 kb
Host smart-444ac460-f935-4943-999f-91ea8196f620
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2309264570 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_intr_test.2309264570
Directory /workspace/15.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.3492919397
Short name T794
Test name
Test status
Simulation time 586836545 ps
CPU time 12.33 seconds
Started Jul 13 05:02:48 PM PDT 24
Finished Jul 13 05:03:01 PM PDT 24
Peak memory 240464 kb
Host smart-e40df74d-b65c-4178-b97a-a32a11b186e5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3492919397 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_same_csr_ou
tstanding.3492919397
Directory /workspace/15.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.2963109684
Short name T121
Test name
Test status
Simulation time 7966880912 ps
CPU time 166.48 seconds
Started Jul 13 05:02:39 PM PDT 24
Finished Jul 13 05:05:25 PM PDT 24
Peak memory 265488 kb
Host smart-dc013f47-3f54-4aef-bbdf-e8a35ac5bda0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2963109684 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shadow_reg_err
ors.2963109684
Directory /workspace/15.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.4290065035
Short name T707
Test name
Test status
Simulation time 63885785 ps
CPU time 10.07 seconds
Started Jul 13 05:02:39 PM PDT 24
Finished Jul 13 05:02:50 PM PDT 24
Peak memory 248784 kb
Host smart-4e9bba75-8685-4cad-b19b-fcba125dd749
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4290065035 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_errors.4290065035
Directory /workspace/15.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.4144548241
Short name T715
Test name
Test status
Simulation time 51328973 ps
CPU time 5.27 seconds
Started Jul 13 05:02:49 PM PDT 24
Finished Jul 13 05:02:54 PM PDT 24
Peak memory 237544 kb
Host smart-7c5bbcdf-7e35-4571-8899-d97ca40c078a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144548241 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 16.alert_handler_csr_mem_rw_with_rand_reset.4144548241
Directory /workspace/16.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.1979911720
Short name T779
Test name
Test status
Simulation time 306632201 ps
CPU time 5.27 seconds
Started Jul 13 05:02:48 PM PDT 24
Finished Jul 13 05:02:54 PM PDT 24
Peak memory 237552 kb
Host smart-2f61ef67-ba50-421d-9abb-ef5afa44fe09
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1979911720 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_csr_rw.1979911720
Directory /workspace/16.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.3998871699
Short name T745
Test name
Test status
Simulation time 12273426 ps
CPU time 1.38 seconds
Started Jul 13 05:02:50 PM PDT 24
Finished Jul 13 05:02:52 PM PDT 24
Peak memory 236788 kb
Host smart-ea2018cd-9356-4fe5-875e-2e02e718d4c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3998871699 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_intr_test.3998871699
Directory /workspace/16.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.3654260636
Short name T170
Test name
Test status
Simulation time 1486211591 ps
CPU time 26.59 seconds
Started Jul 13 05:02:47 PM PDT 24
Finished Jul 13 05:03:15 PM PDT 24
Peak memory 245680 kb
Host smart-443e0869-e363-4502-a87a-4885c0d4cf3a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3654260636 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_same_csr_ou
tstanding.3654260636
Directory /workspace/16.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.118131132
Short name T825
Test name
Test status
Simulation time 901961237 ps
CPU time 17.46 seconds
Started Jul 13 05:02:48 PM PDT 24
Finished Jul 13 05:03:06 PM PDT 24
Peak memory 248496 kb
Host smart-2e52f2e6-a61e-41ee-88d0-67d27c0d75a9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=118131132 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_errors.118131132
Directory /workspace/16.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.2722508750
Short name T154
Test name
Test status
Simulation time 98301014 ps
CPU time 2.77 seconds
Started Jul 13 05:02:47 PM PDT 24
Finished Jul 13 05:02:50 PM PDT 24
Peak memory 237928 kb
Host smart-83bafa84-b28e-4dc4-912c-656d7f71fe0a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2722508750 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_intg_err.2722508750
Directory /workspace/16.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.1614511973
Short name T751
Test name
Test status
Simulation time 60294628 ps
CPU time 5.14 seconds
Started Jul 13 05:02:50 PM PDT 24
Finished Jul 13 05:02:56 PM PDT 24
Peak memory 242036 kb
Host smart-cca818ef-a6d4-4362-9530-a07837c7cd2b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614511973 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 17.alert_handler_csr_mem_rw_with_rand_reset.1614511973
Directory /workspace/17.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.3383567611
Short name T736
Test name
Test status
Simulation time 96611597 ps
CPU time 7.69 seconds
Started Jul 13 05:02:47 PM PDT 24
Finished Jul 13 05:02:55 PM PDT 24
Peak memory 240300 kb
Host smart-0f7d11c5-aba7-4c8a-830a-4badcd01f94f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3383567611 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_csr_rw.3383567611
Directory /workspace/17.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.1323320035
Short name T763
Test name
Test status
Simulation time 31486452 ps
CPU time 1.55 seconds
Started Jul 13 05:02:47 PM PDT 24
Finished Jul 13 05:02:49 PM PDT 24
Peak memory 237508 kb
Host smart-6c7bda21-c46a-42f8-957e-c16f6934b278
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1323320035 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_intr_test.1323320035
Directory /workspace/17.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.1197967348
Short name T182
Test name
Test status
Simulation time 356406446 ps
CPU time 12.52 seconds
Started Jul 13 05:02:50 PM PDT 24
Finished Jul 13 05:03:03 PM PDT 24
Peak memory 244728 kb
Host smart-b51fedd1-cad5-41b3-8e78-0dfaa0306849
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1197967348 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_same_csr_ou
tstanding.1197967348
Directory /workspace/17.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.3645401903
Short name T139
Test name
Test status
Simulation time 5201044048 ps
CPU time 382.47 seconds
Started Jul 13 05:02:50 PM PDT 24
Finished Jul 13 05:09:13 PM PDT 24
Peak memory 265344 kb
Host smart-f62f9bdf-f2db-42d9-8efa-5e20450bef1b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3645401903 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shadow_reg_err
ors.3645401903
Directory /workspace/17.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.6933048
Short name T138
Test name
Test status
Simulation time 23956672947 ps
CPU time 445.05 seconds
Started Jul 13 05:02:46 PM PDT 24
Finished Jul 13 05:10:11 PM PDT 24
Peak memory 265336 kb
Host smart-f5dbd479-b62e-416b-b130-d1de5752260e
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6933048 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 17.alert_handler_shadow_reg_errors_with_csr_rw.6933048
Directory /workspace/17.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.851133533
Short name T791
Test name
Test status
Simulation time 87144137 ps
CPU time 4.3 seconds
Started Jul 13 05:02:48 PM PDT 24
Finished Jul 13 05:02:53 PM PDT 24
Peak memory 252220 kb
Host smart-80519378-cd4e-416b-8226-1716213fc561
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=851133533 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_errors.851133533
Directory /workspace/17.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.3421898920
Short name T817
Test name
Test status
Simulation time 66074468 ps
CPU time 10.4 seconds
Started Jul 13 05:02:56 PM PDT 24
Finished Jul 13 05:03:06 PM PDT 24
Peak memory 253108 kb
Host smart-16fe3cf9-e1a2-458f-a8d4-92cac2280b8e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421898920 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 18.alert_handler_csr_mem_rw_with_rand_reset.3421898920
Directory /workspace/18.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.1330568099
Short name T759
Test name
Test status
Simulation time 93840737 ps
CPU time 8.11 seconds
Started Jul 13 05:02:54 PM PDT 24
Finished Jul 13 05:03:03 PM PDT 24
Peak memory 236608 kb
Host smart-7be47b2d-8e0a-4d01-a80d-57898ab10cf2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1330568099 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_csr_rw.1330568099
Directory /workspace/18.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.1578045975
Short name T781
Test name
Test status
Simulation time 7738196 ps
CPU time 1.47 seconds
Started Jul 13 05:02:54 PM PDT 24
Finished Jul 13 05:02:56 PM PDT 24
Peak memory 237488 kb
Host smart-62be77f5-feb5-41e3-ad63-518882a5d669
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1578045975 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_intr_test.1578045975
Directory /workspace/18.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.2174139201
Short name T748
Test name
Test status
Simulation time 172518435 ps
CPU time 11.45 seconds
Started Jul 13 05:02:55 PM PDT 24
Finished Jul 13 05:03:07 PM PDT 24
Peak memory 244728 kb
Host smart-9a6bd941-20f2-47a7-9ba4-6df52c8ec550
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2174139201 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_same_csr_ou
tstanding.2174139201
Directory /workspace/18.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.1238151962
Short name T136
Test name
Test status
Simulation time 8954301249 ps
CPU time 112.46 seconds
Started Jul 13 05:02:54 PM PDT 24
Finished Jul 13 05:04:47 PM PDT 24
Peak memory 266636 kb
Host smart-dc559341-1811-4d51-b543-a947c694eb2c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1238151962 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shadow_reg_err
ors.1238151962
Directory /workspace/18.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.1046456645
Short name T127
Test name
Test status
Simulation time 7650572613 ps
CPU time 317.13 seconds
Started Jul 13 05:02:55 PM PDT 24
Finished Jul 13 05:08:12 PM PDT 24
Peak memory 265380 kb
Host smart-729b4d43-3231-47b7-99e8-b70b7f000c29
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046456645 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 18.alert_handler_shadow_reg_errors_with_csr_rw.1046456645
Directory /workspace/18.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.1082648764
Short name T714
Test name
Test status
Simulation time 883103185 ps
CPU time 18.91 seconds
Started Jul 13 05:02:57 PM PDT 24
Finished Jul 13 05:03:16 PM PDT 24
Peak memory 255456 kb
Host smart-700ae98e-29fe-42cc-a4e1-8e2251f8619d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1082648764 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_errors.1082648764
Directory /workspace/18.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.2073360246
Short name T792
Test name
Test status
Simulation time 342351294 ps
CPU time 5.24 seconds
Started Jul 13 05:03:04 PM PDT 24
Finished Jul 13 05:03:10 PM PDT 24
Peak memory 248740 kb
Host smart-bef26439-03f5-4eff-b216-dd4becac2fd3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073360246 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 19.alert_handler_csr_mem_rw_with_rand_reset.2073360246
Directory /workspace/19.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.2274293492
Short name T805
Test name
Test status
Simulation time 163066478 ps
CPU time 9.77 seconds
Started Jul 13 05:02:56 PM PDT 24
Finished Jul 13 05:03:06 PM PDT 24
Peak memory 237556 kb
Host smart-d8ce8f3d-31a1-498a-91c4-16925929da55
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2274293492 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_csr_rw.2274293492
Directory /workspace/19.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.1334049501
Short name T807
Test name
Test status
Simulation time 8988716 ps
CPU time 1.58 seconds
Started Jul 13 05:02:56 PM PDT 24
Finished Jul 13 05:02:58 PM PDT 24
Peak memory 237588 kb
Host smart-921a9841-b6d6-45e1-ad97-0ed716d79e72
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1334049501 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_intr_test.1334049501
Directory /workspace/19.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.1369013634
Short name T179
Test name
Test status
Simulation time 354415261 ps
CPU time 24.24 seconds
Started Jul 13 05:02:55 PM PDT 24
Finished Jul 13 05:03:19 PM PDT 24
Peak memory 245776 kb
Host smart-8510b6f9-4e3c-401f-8b15-9db541c5513e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1369013634 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_same_csr_ou
tstanding.1369013634
Directory /workspace/19.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.1677853393
Short name T193
Test name
Test status
Simulation time 5412662140 ps
CPU time 161.79 seconds
Started Jul 13 05:02:54 PM PDT 24
Finished Jul 13 05:05:37 PM PDT 24
Peak memory 265344 kb
Host smart-60c5e0b5-8be8-46c9-adde-1fb491ccbaa0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1677853393 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shadow_reg_err
ors.1677853393
Directory /workspace/19.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.2002568305
Short name T353
Test name
Test status
Simulation time 6399320661 ps
CPU time 544.45 seconds
Started Jul 13 05:02:56 PM PDT 24
Finished Jul 13 05:12:01 PM PDT 24
Peak memory 265408 kb
Host smart-a3a0e52b-721a-48e2-ba08-0470727400fe
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002568305 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 19.alert_handler_shadow_reg_errors_with_csr_rw.2002568305
Directory /workspace/19.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.3656916749
Short name T775
Test name
Test status
Simulation time 287275513 ps
CPU time 12.22 seconds
Started Jul 13 05:02:57 PM PDT 24
Finished Jul 13 05:03:10 PM PDT 24
Peak memory 254744 kb
Host smart-7c46df34-c0d7-40e4-a08d-96cb8f702d94
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3656916749 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_errors.3656916749
Directory /workspace/19.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.2074752009
Short name T809
Test name
Test status
Simulation time 12238156655 ps
CPU time 268.01 seconds
Started Jul 13 05:01:52 PM PDT 24
Finished Jul 13 05:06:21 PM PDT 24
Peak memory 241504 kb
Host smart-071bf434-37af-4504-bdc9-cd0696b7f83f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2074752009 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_aliasing.2074752009
Directory /workspace/2.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.426169298
Short name T773
Test name
Test status
Simulation time 1653079930 ps
CPU time 179.93 seconds
Started Jul 13 05:01:52 PM PDT 24
Finished Jul 13 05:04:53 PM PDT 24
Peak memory 240432 kb
Host smart-45e4cc95-906f-4d5a-a817-711a492fa3be
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=426169298 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_bit_bash.426169298
Directory /workspace/2.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.1276496539
Short name T155
Test name
Test status
Simulation time 87751644 ps
CPU time 3.68 seconds
Started Jul 13 05:01:54 PM PDT 24
Finished Jul 13 05:01:58 PM PDT 24
Peak memory 248616 kb
Host smart-a5cf5cff-5cff-4e10-9245-68f2de0bc0a2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1276496539 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_hw_reset.1276496539
Directory /workspace/2.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.623969085
Short name T731
Test name
Test status
Simulation time 46240511 ps
CPU time 5.55 seconds
Started Jul 13 05:01:52 PM PDT 24
Finished Jul 13 05:01:58 PM PDT 24
Peak memory 248884 kb
Host smart-500dcc68-464d-4fee-8ce1-9e10d98215d8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623969085 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 2.alert_handler_csr_mem_rw_with_rand_reset.623969085
Directory /workspace/2.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.3020895082
Short name T712
Test name
Test status
Simulation time 125497559 ps
CPU time 5.92 seconds
Started Jul 13 05:01:51 PM PDT 24
Finished Jul 13 05:01:58 PM PDT 24
Peak memory 240516 kb
Host smart-8aec5b08-39bd-4a0c-900c-6964e457971f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3020895082 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_rw.3020895082
Directory /workspace/2.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.2744953036
Short name T729
Test name
Test status
Simulation time 11522369 ps
CPU time 1.29 seconds
Started Jul 13 05:01:53 PM PDT 24
Finished Jul 13 05:01:55 PM PDT 24
Peak memory 235688 kb
Host smart-2ea33065-c604-4994-ba98-67333414d93d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2744953036 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_intr_test.2744953036
Directory /workspace/2.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.1211535017
Short name T734
Test name
Test status
Simulation time 390394628 ps
CPU time 11.57 seconds
Started Jul 13 05:01:51 PM PDT 24
Finished Jul 13 05:02:03 PM PDT 24
Peak memory 240520 kb
Host smart-d515674a-3afd-406f-878f-10c49616cfe3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1211535017 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_same_csr_out
standing.1211535017
Directory /workspace/2.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.433955597
Short name T724
Test name
Test status
Simulation time 801757176 ps
CPU time 18.88 seconds
Started Jul 13 05:01:43 PM PDT 24
Finished Jul 13 05:02:03 PM PDT 24
Peak memory 248712 kb
Host smart-e64c689b-ed6a-4622-9991-1f86665861a9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=433955597 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_errors.433955597
Directory /workspace/2.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.2596522625
Short name T347
Test name
Test status
Simulation time 6454807 ps
CPU time 1.43 seconds
Started Jul 13 05:03:04 PM PDT 24
Finished Jul 13 05:03:05 PM PDT 24
Peak memory 237576 kb
Host smart-47ec0f46-32e1-4458-b26b-e10f913891e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2596522625 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.alert_handler_intr_test.2596522625
Directory /workspace/20.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.9015557
Short name T776
Test name
Test status
Simulation time 11825336 ps
CPU time 1.71 seconds
Started Jul 13 05:03:03 PM PDT 24
Finished Jul 13 05:03:05 PM PDT 24
Peak memory 237496 kb
Host smart-3c079de0-da3d-451a-9ccd-79eb0e073bb0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=9015557 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.alert_handler_intr_test.9015557
Directory /workspace/21.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.667799035
Short name T740
Test name
Test status
Simulation time 69944056 ps
CPU time 1.5 seconds
Started Jul 13 05:03:04 PM PDT 24
Finished Jul 13 05:03:06 PM PDT 24
Peak memory 237336 kb
Host smart-920dcd80-87ee-49f8-a1f8-f30b7d39c0e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=667799035 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.alert_handler_intr_test.667799035
Directory /workspace/22.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.2369947244
Short name T820
Test name
Test status
Simulation time 20876338 ps
CPU time 1.7 seconds
Started Jul 13 05:03:03 PM PDT 24
Finished Jul 13 05:03:05 PM PDT 24
Peak memory 237588 kb
Host smart-a1a2fe32-1c83-4341-961c-03ca8f33e81a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2369947244 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.alert_handler_intr_test.2369947244
Directory /workspace/23.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.1395034174
Short name T823
Test name
Test status
Simulation time 19104458 ps
CPU time 1.97 seconds
Started Jul 13 05:03:05 PM PDT 24
Finished Jul 13 05:03:07 PM PDT 24
Peak memory 237488 kb
Host smart-498a146a-ad7f-4e4e-ad5f-376e4b843a26
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1395034174 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.alert_handler_intr_test.1395034174
Directory /workspace/24.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.2366554657
Short name T716
Test name
Test status
Simulation time 18767404 ps
CPU time 1.56 seconds
Started Jul 13 05:03:05 PM PDT 24
Finished Jul 13 05:03:07 PM PDT 24
Peak memory 235620 kb
Host smart-d447ad94-29b2-42a0-b9a6-b50b58ae0252
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2366554657 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.alert_handler_intr_test.2366554657
Directory /workspace/25.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.3933320634
Short name T345
Test name
Test status
Simulation time 6317144 ps
CPU time 1.44 seconds
Started Jul 13 05:03:05 PM PDT 24
Finished Jul 13 05:03:06 PM PDT 24
Peak memory 237568 kb
Host smart-9606d36c-c2de-445d-9006-588e50802bb3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3933320634 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.alert_handler_intr_test.3933320634
Directory /workspace/26.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.1942127739
Short name T804
Test name
Test status
Simulation time 18747507 ps
CPU time 1.51 seconds
Started Jul 13 05:03:06 PM PDT 24
Finished Jul 13 05:03:08 PM PDT 24
Peak memory 236860 kb
Host smart-fa288ae2-ef67-4aa4-989f-8dcc31a89fba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1942127739 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.alert_handler_intr_test.1942127739
Directory /workspace/27.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.1850423115
Short name T782
Test name
Test status
Simulation time 18763636 ps
CPU time 1.58 seconds
Started Jul 13 05:03:05 PM PDT 24
Finished Jul 13 05:03:07 PM PDT 24
Peak memory 236636 kb
Host smart-23ff7b78-da54-4ace-98ed-03cfe7647107
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1850423115 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.alert_handler_intr_test.1850423115
Directory /workspace/28.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.2416334540
Short name T341
Test name
Test status
Simulation time 28622777 ps
CPU time 1.23 seconds
Started Jul 13 05:03:05 PM PDT 24
Finished Jul 13 05:03:07 PM PDT 24
Peak memory 236528 kb
Host smart-65bcec85-b8d1-4c7e-a185-51b2151ca832
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2416334540 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.alert_handler_intr_test.2416334540
Directory /workspace/29.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.1541010231
Short name T728
Test name
Test status
Simulation time 570339082 ps
CPU time 62.54 seconds
Started Jul 13 05:01:54 PM PDT 24
Finished Jul 13 05:02:57 PM PDT 24
Peak memory 237652 kb
Host smart-a6bb6cda-6509-415e-a2d5-3883afb1fadf
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1541010231 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_aliasing.1541010231
Directory /workspace/3.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.1911837098
Short name T826
Test name
Test status
Simulation time 5284484946 ps
CPU time 220.23 seconds
Started Jul 13 05:01:51 PM PDT 24
Finished Jul 13 05:05:32 PM PDT 24
Peak memory 236668 kb
Host smart-6fe5ccee-48bf-442c-9da3-f5a843798fc0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1911837098 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_bit_bash.1911837098
Directory /workspace/3.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.4228552917
Short name T730
Test name
Test status
Simulation time 70872598 ps
CPU time 6.11 seconds
Started Jul 13 05:01:52 PM PDT 24
Finished Jul 13 05:01:59 PM PDT 24
Peak memory 240720 kb
Host smart-c5167d3b-ae0f-4770-b3b1-d16304b87f5d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4228552917 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_hw_reset.4228552917
Directory /workspace/3.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.2836415671
Short name T194
Test name
Test status
Simulation time 263186700 ps
CPU time 11.35 seconds
Started Jul 13 05:01:54 PM PDT 24
Finished Jul 13 05:02:06 PM PDT 24
Peak memory 243572 kb
Host smart-fca7c8c2-ac47-4431-abc0-2509e9b23d5b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836415671 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 3.alert_handler_csr_mem_rw_with_rand_reset.2836415671
Directory /workspace/3.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.972358443
Short name T758
Test name
Test status
Simulation time 131472883 ps
CPU time 9.53 seconds
Started Jul 13 05:01:53 PM PDT 24
Finished Jul 13 05:02:03 PM PDT 24
Peak memory 237476 kb
Host smart-29ce549b-95a5-4083-b1f7-b09968b58de1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=972358443 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_rw.972358443
Directory /workspace/3.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.1362736849
Short name T753
Test name
Test status
Simulation time 243980279 ps
CPU time 16.88 seconds
Started Jul 13 05:01:51 PM PDT 24
Finished Jul 13 05:02:08 PM PDT 24
Peak memory 240500 kb
Host smart-26530a2a-b615-497b-8e35-ed1c95f0c460
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1362736849 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_same_csr_out
standing.1362736849
Directory /workspace/3.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.941755281
Short name T145
Test name
Test status
Simulation time 5920042559 ps
CPU time 181.02 seconds
Started Jul 13 05:01:54 PM PDT 24
Finished Jul 13 05:04:55 PM PDT 24
Peak memory 265348 kb
Host smart-c048b23b-23e4-40b0-b4a0-54023a08ab22
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=941755281 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shadow_reg_error
s.941755281
Directory /workspace/3.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.1396369465
Short name T765
Test name
Test status
Simulation time 1080474658 ps
CPU time 21.19 seconds
Started Jul 13 05:01:53 PM PDT 24
Finished Jul 13 05:02:15 PM PDT 24
Peak memory 248716 kb
Host smart-8f2572f8-29f1-43e4-90f5-3e3a05d3bf05
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1396369465 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_errors.1396369465
Directory /workspace/3.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.4042837977
Short name T235
Test name
Test status
Simulation time 95699700 ps
CPU time 5.43 seconds
Started Jul 13 05:01:52 PM PDT 24
Finished Jul 13 05:01:58 PM PDT 24
Peak memory 238432 kb
Host smart-62ecb551-d8d8-4ae2-88e3-a6585707fb9f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4042837977 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_intg_err.4042837977
Directory /workspace/3.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.3738625850
Short name T774
Test name
Test status
Simulation time 9529572 ps
CPU time 1.33 seconds
Started Jul 13 05:03:04 PM PDT 24
Finished Jul 13 05:03:06 PM PDT 24
Peak memory 237584 kb
Host smart-9d9de668-d812-400a-b85c-6872724fe0f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3738625850 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.alert_handler_intr_test.3738625850
Directory /workspace/30.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.2615980155
Short name T342
Test name
Test status
Simulation time 13390778 ps
CPU time 1.4 seconds
Started Jul 13 05:03:05 PM PDT 24
Finished Jul 13 05:03:06 PM PDT 24
Peak memory 237508 kb
Host smart-9847e7b6-500e-4a11-ac11-bfae4b9baa41
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2615980155 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.alert_handler_intr_test.2615980155
Directory /workspace/31.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.alert_handler_intr_test.2728539460
Short name T810
Test name
Test status
Simulation time 26973421 ps
CPU time 1.39 seconds
Started Jul 13 05:03:15 PM PDT 24
Finished Jul 13 05:03:17 PM PDT 24
Peak memory 237488 kb
Host smart-120e2540-f30f-412e-a416-6b1999e2f403
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2728539460 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.alert_handler_intr_test.2728539460
Directory /workspace/33.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.1106901259
Short name T824
Test name
Test status
Simulation time 25123190 ps
CPU time 1.56 seconds
Started Jul 13 05:03:13 PM PDT 24
Finished Jul 13 05:03:15 PM PDT 24
Peak memory 237472 kb
Host smart-c24ca9d2-894f-469d-ba8c-da7d11e3f3da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1106901259 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.alert_handler_intr_test.1106901259
Directory /workspace/34.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.2463868846
Short name T816
Test name
Test status
Simulation time 75077650 ps
CPU time 1.48 seconds
Started Jul 13 05:03:16 PM PDT 24
Finished Jul 13 05:03:18 PM PDT 24
Peak memory 237508 kb
Host smart-ced5f6ff-ee24-46b6-9e44-e7c3d160c828
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2463868846 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.alert_handler_intr_test.2463868846
Directory /workspace/35.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.1293664456
Short name T808
Test name
Test status
Simulation time 13365392 ps
CPU time 1.47 seconds
Started Jul 13 05:03:14 PM PDT 24
Finished Jul 13 05:03:16 PM PDT 24
Peak memory 237584 kb
Host smart-12231c55-1d55-499a-b92d-e803fe143141
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1293664456 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.alert_handler_intr_test.1293664456
Directory /workspace/36.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.2219384960
Short name T157
Test name
Test status
Simulation time 8900259 ps
CPU time 1.55 seconds
Started Jul 13 05:03:14 PM PDT 24
Finished Jul 13 05:03:16 PM PDT 24
Peak memory 235580 kb
Host smart-408cef8a-17c8-40b5-805d-68d3b92289e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2219384960 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.alert_handler_intr_test.2219384960
Directory /workspace/37.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.785005620
Short name T725
Test name
Test status
Simulation time 18736234 ps
CPU time 1.44 seconds
Started Jul 13 05:03:14 PM PDT 24
Finished Jul 13 05:03:16 PM PDT 24
Peak memory 237576 kb
Host smart-3b994dac-4b52-4a19-80d4-50434a3c8aca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=785005620 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.alert_handler_intr_test.785005620
Directory /workspace/38.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.3647510810
Short name T747
Test name
Test status
Simulation time 24839244 ps
CPU time 1.34 seconds
Started Jul 13 05:03:14 PM PDT 24
Finished Jul 13 05:03:16 PM PDT 24
Peak memory 236660 kb
Host smart-9b835327-a600-4cfd-8de2-06fb5cbd3e61
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3647510810 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.alert_handler_intr_test.3647510810
Directory /workspace/39.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.2806991448
Short name T710
Test name
Test status
Simulation time 1052134791 ps
CPU time 162.03 seconds
Started Jul 13 05:02:00 PM PDT 24
Finished Jul 13 05:04:43 PM PDT 24
Peak memory 240484 kb
Host smart-0b0c1108-2a87-475e-b58a-fca863f36a85
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2806991448 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_aliasing.2806991448
Directory /workspace/4.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.2062846507
Short name T822
Test name
Test status
Simulation time 9338223567 ps
CPU time 441.79 seconds
Started Jul 13 05:02:00 PM PDT 24
Finished Jul 13 05:09:23 PM PDT 24
Peak memory 240604 kb
Host smart-3a9f7e47-60d3-40d1-b46e-7e0648b68e1d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2062846507 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_bit_bash.2062846507
Directory /workspace/4.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.1230277006
Short name T711
Test name
Test status
Simulation time 72262882 ps
CPU time 4.02 seconds
Started Jul 13 05:02:00 PM PDT 24
Finished Jul 13 05:02:05 PM PDT 24
Peak memory 248636 kb
Host smart-f478e856-7cb5-4eeb-a8e9-3e27a557fe9d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1230277006 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_hw_reset.1230277006
Directory /workspace/4.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.4194714872
Short name T722
Test name
Test status
Simulation time 1339042404 ps
CPU time 9.98 seconds
Started Jul 13 05:02:02 PM PDT 24
Finished Jul 13 05:02:13 PM PDT 24
Peak memory 240300 kb
Host smart-6f246169-8a0f-483d-a451-8e287dc23e14
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194714872 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 4.alert_handler_csr_mem_rw_with_rand_reset.4194714872
Directory /workspace/4.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.2898594480
Short name T350
Test name
Test status
Simulation time 55136608 ps
CPU time 4.94 seconds
Started Jul 13 05:01:59 PM PDT 24
Finished Jul 13 05:02:05 PM PDT 24
Peak memory 240504 kb
Host smart-a4433bef-f0da-4df9-80a5-53d06047b41b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2898594480 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_rw.2898594480
Directory /workspace/4.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.2746260509
Short name T343
Test name
Test status
Simulation time 16524297 ps
CPU time 1.82 seconds
Started Jul 13 05:02:04 PM PDT 24
Finished Jul 13 05:02:06 PM PDT 24
Peak memory 236556 kb
Host smart-d1b36e35-469b-4f36-9cf6-c75d9b842287
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2746260509 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_intr_test.2746260509
Directory /workspace/4.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.3186200855
Short name T742
Test name
Test status
Simulation time 168521038 ps
CPU time 12.68 seconds
Started Jul 13 05:02:00 PM PDT 24
Finished Jul 13 05:02:14 PM PDT 24
Peak memory 245712 kb
Host smart-7027e6a9-9952-4bfb-a9f7-fd496bff6473
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3186200855 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_same_csr_out
standing.3186200855
Directory /workspace/4.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.219122460
Short name T119
Test name
Test status
Simulation time 14512658165 ps
CPU time 1141.46 seconds
Started Jul 13 05:01:51 PM PDT 24
Finished Jul 13 05:20:53 PM PDT 24
Peak memory 265524 kb
Host smart-bc025e3b-618c-4ba3-b7ec-ba68ffa82d92
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219122460 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.alert_handler_shadow_reg_errors_with_csr_rw.219122460
Directory /workspace/4.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.2884162152
Short name T768
Test name
Test status
Simulation time 97564105 ps
CPU time 10.37 seconds
Started Jul 13 05:02:02 PM PDT 24
Finished Jul 13 05:02:13 PM PDT 24
Peak memory 246692 kb
Host smart-5937d5aa-f23c-4790-a1ce-c4a931332e01
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2884162152 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_errors.2884162152
Directory /workspace/4.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.912180012
Short name T777
Test name
Test status
Simulation time 18103490 ps
CPU time 1.36 seconds
Started Jul 13 05:03:16 PM PDT 24
Finished Jul 13 05:03:18 PM PDT 24
Peak memory 236564 kb
Host smart-2c6f1a61-1c67-498f-90c7-ba7a00b43307
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=912180012 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.alert_handler_intr_test.912180012
Directory /workspace/40.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.4152470859
Short name T739
Test name
Test status
Simulation time 19800210 ps
CPU time 1.57 seconds
Started Jul 13 05:03:13 PM PDT 24
Finished Jul 13 05:03:14 PM PDT 24
Peak memory 237568 kb
Host smart-b3db514a-102e-4701-886f-414c0a8e1342
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4152470859 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.alert_handler_intr_test.4152470859
Directory /workspace/41.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.3660294223
Short name T813
Test name
Test status
Simulation time 12411981 ps
CPU time 1.34 seconds
Started Jul 13 05:03:13 PM PDT 24
Finished Jul 13 05:03:15 PM PDT 24
Peak memory 236564 kb
Host smart-a7cf3266-d797-4ba3-be30-a7e4ceda930b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3660294223 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.alert_handler_intr_test.3660294223
Directory /workspace/42.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.1492626205
Short name T741
Test name
Test status
Simulation time 25442711 ps
CPU time 1.49 seconds
Started Jul 13 05:03:14 PM PDT 24
Finished Jul 13 05:03:16 PM PDT 24
Peak memory 237584 kb
Host smart-d74e77eb-e360-4526-aabf-c90ab20005a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1492626205 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.alert_handler_intr_test.1492626205
Directory /workspace/43.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.1373005906
Short name T737
Test name
Test status
Simulation time 11726108 ps
CPU time 1.33 seconds
Started Jul 13 05:03:22 PM PDT 24
Finished Jul 13 05:03:24 PM PDT 24
Peak memory 237532 kb
Host smart-346f85ff-a06b-466c-9cd1-c5caf47ab2c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1373005906 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.alert_handler_intr_test.1373005906
Directory /workspace/44.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.2540647242
Short name T156
Test name
Test status
Simulation time 9956614 ps
CPU time 1.35 seconds
Started Jul 13 05:03:22 PM PDT 24
Finished Jul 13 05:03:23 PM PDT 24
Peak memory 237584 kb
Host smart-5af9988f-1209-49ca-8334-bcf0466a64fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2540647242 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.alert_handler_intr_test.2540647242
Directory /workspace/45.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.3084812989
Short name T746
Test name
Test status
Simulation time 7447244 ps
CPU time 1.39 seconds
Started Jul 13 05:03:23 PM PDT 24
Finished Jul 13 05:03:25 PM PDT 24
Peak memory 236788 kb
Host smart-caee6adc-b5a9-4b6f-8506-40f0a8e2e407
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3084812989 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.alert_handler_intr_test.3084812989
Directory /workspace/46.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.1156540277
Short name T348
Test name
Test status
Simulation time 6786086 ps
CPU time 1.53 seconds
Started Jul 13 05:03:19 PM PDT 24
Finished Jul 13 05:03:21 PM PDT 24
Peak memory 237420 kb
Host smart-cea42e57-a16f-4e1b-a37e-e4f999af2050
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1156540277 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.alert_handler_intr_test.1156540277
Directory /workspace/47.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.969258945
Short name T802
Test name
Test status
Simulation time 9606948 ps
CPU time 1.58 seconds
Started Jul 13 05:03:21 PM PDT 24
Finished Jul 13 05:03:23 PM PDT 24
Peak memory 237588 kb
Host smart-4554ed67-0913-4610-bad7-49c1a64aa286
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=969258945 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.alert_handler_intr_test.969258945
Directory /workspace/48.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.4065102949
Short name T770
Test name
Test status
Simulation time 12935792 ps
CPU time 1.81 seconds
Started Jul 13 05:03:24 PM PDT 24
Finished Jul 13 05:03:26 PM PDT 24
Peak memory 237776 kb
Host smart-61ceee7d-246a-4b45-bc6e-f9f6ce63dd69
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4065102949 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.alert_handler_intr_test.4065102949
Directory /workspace/49.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.526683037
Short name T709
Test name
Test status
Simulation time 125468168 ps
CPU time 5.96 seconds
Started Jul 13 05:02:01 PM PDT 24
Finished Jul 13 05:02:08 PM PDT 24
Peak memory 243516 kb
Host smart-ba060001-93bb-40bb-90f7-f5dc6b2b57ba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526683037 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 5.alert_handler_csr_mem_rw_with_rand_reset.526683037
Directory /workspace/5.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.3252881686
Short name T744
Test name
Test status
Simulation time 124867369 ps
CPU time 5.37 seconds
Started Jul 13 05:01:59 PM PDT 24
Finished Jul 13 05:02:05 PM PDT 24
Peak memory 237568 kb
Host smart-0c94a57a-7660-4a82-b6ad-e2b9fd52d3a6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3252881686 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_csr_rw.3252881686
Directory /workspace/5.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.2034290426
Short name T761
Test name
Test status
Simulation time 6405023 ps
CPU time 1.58 seconds
Started Jul 13 05:02:02 PM PDT 24
Finished Jul 13 05:02:04 PM PDT 24
Peak memory 237732 kb
Host smart-8db57258-ea2b-4b10-8b06-2e55a7629bf9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2034290426 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_intr_test.2034290426
Directory /workspace/5.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.1509356349
Short name T821
Test name
Test status
Simulation time 707494364 ps
CPU time 48.36 seconds
Started Jul 13 05:02:00 PM PDT 24
Finished Jul 13 05:02:49 PM PDT 24
Peak memory 248636 kb
Host smart-618deaf2-3bb7-4f7d-9b79-3e7122cf546f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1509356349 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_same_csr_out
standing.1509356349
Directory /workspace/5.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.3109222308
Short name T144
Test name
Test status
Simulation time 30148760863 ps
CPU time 345.9 seconds
Started Jul 13 05:01:59 PM PDT 24
Finished Jul 13 05:07:46 PM PDT 24
Peak memory 265376 kb
Host smart-fd894979-c730-4b4b-9b0e-f06aabf17886
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3109222308 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shadow_reg_erro
rs.3109222308
Directory /workspace/5.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.912335538
Short name T801
Test name
Test status
Simulation time 24590193409 ps
CPU time 971.86 seconds
Started Jul 13 05:02:01 PM PDT 24
Finished Jul 13 05:18:13 PM PDT 24
Peak memory 265504 kb
Host smart-9b2ed0bb-0ebc-42be-a8cd-79e88217545a
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912335538 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.alert_handler_shadow_reg_errors_with_csr_rw.912335538
Directory /workspace/5.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.3808012355
Short name T827
Test name
Test status
Simulation time 38581599 ps
CPU time 6.37 seconds
Started Jul 13 05:02:00 PM PDT 24
Finished Jul 13 05:02:08 PM PDT 24
Peak memory 248768 kb
Host smart-cce539fb-db98-4238-849b-53358559822b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3808012355 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_errors.3808012355
Directory /workspace/5.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.2326174556
Short name T798
Test name
Test status
Simulation time 154429423 ps
CPU time 2.6 seconds
Started Jul 13 05:02:01 PM PDT 24
Finished Jul 13 05:02:04 PM PDT 24
Peak memory 237912 kb
Host smart-5873e0d4-bba3-41bf-8d4b-b3d54bcf2664
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2326174556 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_intg_err.2326174556
Directory /workspace/5.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.3480166856
Short name T787
Test name
Test status
Simulation time 238444660 ps
CPU time 10.07 seconds
Started Jul 13 05:02:06 PM PDT 24
Finished Jul 13 05:02:17 PM PDT 24
Peak memory 239872 kb
Host smart-2855d618-783a-4bd2-a1dd-357fff2f8c0d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480166856 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 6.alert_handler_csr_mem_rw_with_rand_reset.3480166856
Directory /workspace/6.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.3794096770
Short name T743
Test name
Test status
Simulation time 179036613 ps
CPU time 7.97 seconds
Started Jul 13 05:02:07 PM PDT 24
Finished Jul 13 05:02:16 PM PDT 24
Peak memory 237484 kb
Host smart-50d84cd9-974f-470b-a0f8-6904acfb4894
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3794096770 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_csr_rw.3794096770
Directory /workspace/6.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.2572384582
Short name T818
Test name
Test status
Simulation time 20946712 ps
CPU time 1.41 seconds
Started Jul 13 05:02:08 PM PDT 24
Finished Jul 13 05:02:10 PM PDT 24
Peak memory 237488 kb
Host smart-cd56d42c-cd5c-4da4-b792-a98c5658e7af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2572384582 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_intr_test.2572384582
Directory /workspace/6.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.3148700281
Short name T806
Test name
Test status
Simulation time 506761821 ps
CPU time 36.18 seconds
Started Jul 13 05:02:07 PM PDT 24
Finished Jul 13 05:02:44 PM PDT 24
Peak memory 244792 kb
Host smart-2cef4430-3ff6-47fb-8e3b-8eb2881e0648
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3148700281 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_same_csr_out
standing.3148700281
Directory /workspace/6.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.3724956682
Short name T132
Test name
Test status
Simulation time 926996094 ps
CPU time 117.34 seconds
Started Jul 13 05:01:59 PM PDT 24
Finished Jul 13 05:03:57 PM PDT 24
Peak memory 265268 kb
Host smart-5894f2e4-a809-44fc-acfd-c41cb3d8f7c0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3724956682 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shadow_reg_erro
rs.3724956682
Directory /workspace/6.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.2794426971
Short name T130
Test name
Test status
Simulation time 9145793075 ps
CPU time 391.89 seconds
Started Jul 13 05:02:00 PM PDT 24
Finished Jul 13 05:08:32 PM PDT 24
Peak memory 265384 kb
Host smart-20de3686-873f-42d8-81b8-af68b6eaeb71
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794426971 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.alert_handler_shadow_reg_errors_with_csr_rw.2794426971
Directory /workspace/6.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.4014674894
Short name T803
Test name
Test status
Simulation time 1059617722 ps
CPU time 22.48 seconds
Started Jul 13 05:02:01 PM PDT 24
Finished Jul 13 05:02:24 PM PDT 24
Peak memory 255580 kb
Host smart-7457cd17-485e-4bd9-bf0f-75bf47cf37c4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4014674894 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_errors.4014674894
Directory /workspace/6.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.318333575
Short name T718
Test name
Test status
Simulation time 216228844 ps
CPU time 12.22 seconds
Started Jul 13 05:02:07 PM PDT 24
Finished Jul 13 05:02:20 PM PDT 24
Peak memory 256748 kb
Host smart-3154145b-e578-44e4-883d-e0faf5b7b004
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318333575 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 7.alert_handler_csr_mem_rw_with_rand_reset.318333575
Directory /workspace/7.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.2530588620
Short name T732
Test name
Test status
Simulation time 52093553 ps
CPU time 4.69 seconds
Started Jul 13 05:02:07 PM PDT 24
Finished Jul 13 05:02:12 PM PDT 24
Peak memory 237516 kb
Host smart-9fd5f069-e3bc-4b3e-bf13-b6d5d91798b6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2530588620 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_csr_rw.2530588620
Directory /workspace/7.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.1019784282
Short name T795
Test name
Test status
Simulation time 14238926 ps
CPU time 1.58 seconds
Started Jul 13 05:02:06 PM PDT 24
Finished Jul 13 05:02:08 PM PDT 24
Peak memory 237592 kb
Host smart-6a30a68f-7de6-4a89-9b28-2d6629e2b44f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1019784282 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_intr_test.1019784282
Directory /workspace/7.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.3152796591
Short name T783
Test name
Test status
Simulation time 3179736113 ps
CPU time 40.13 seconds
Started Jul 13 05:02:07 PM PDT 24
Finished Jul 13 05:02:48 PM PDT 24
Peak memory 244808 kb
Host smart-abf94a08-6e75-4a75-b10e-b2b2eaad6dde
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3152796591 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_same_csr_out
standing.3152796591
Directory /workspace/7.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.3193424579
Short name T126
Test name
Test status
Simulation time 1058777679 ps
CPU time 134.29 seconds
Started Jul 13 05:02:06 PM PDT 24
Finished Jul 13 05:04:21 PM PDT 24
Peak memory 265364 kb
Host smart-8ca0f460-2087-4dfd-8d9d-cb8c5818ac03
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3193424579 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shadow_reg_erro
rs.3193424579
Directory /workspace/7.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.1422974524
Short name T780
Test name
Test status
Simulation time 3223541080 ps
CPU time 325.44 seconds
Started Jul 13 05:02:07 PM PDT 24
Finished Jul 13 05:07:33 PM PDT 24
Peak memory 265340 kb
Host smart-4ef63f6a-833e-439c-a4e3-68150e5b68f3
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422974524 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.alert_handler_shadow_reg_errors_with_csr_rw.1422974524
Directory /workspace/7.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.579815430
Short name T708
Test name
Test status
Simulation time 151985443 ps
CPU time 4.5 seconds
Started Jul 13 05:02:08 PM PDT 24
Finished Jul 13 05:02:13 PM PDT 24
Peak memory 249712 kb
Host smart-59792d18-8ef2-4826-8ddb-5dae2f239284
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=579815430 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_errors.579815430
Directory /workspace/7.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.3259455213
Short name T786
Test name
Test status
Simulation time 62463310 ps
CPU time 3.08 seconds
Started Jul 13 05:02:06 PM PDT 24
Finished Jul 13 05:02:10 PM PDT 24
Peak memory 237712 kb
Host smart-2035c5c7-5c57-41a9-a7c6-84b9e969eff8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3259455213 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_intg_err.3259455213
Directory /workspace/7.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.3253159582
Short name T723
Test name
Test status
Simulation time 121817767 ps
CPU time 11.24 seconds
Started Jul 13 05:02:07 PM PDT 24
Finished Jul 13 05:02:19 PM PDT 24
Peak memory 251960 kb
Host smart-edec4abc-fcba-4c50-8ee0-3a6637eeb17b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253159582 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 8.alert_handler_csr_mem_rw_with_rand_reset.3253159582
Directory /workspace/8.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.1402153482
Short name T749
Test name
Test status
Simulation time 406515799 ps
CPU time 4.66 seconds
Started Jul 13 05:02:07 PM PDT 24
Finished Jul 13 05:02:13 PM PDT 24
Peak memory 236380 kb
Host smart-d558dbca-f883-4fcf-9576-ce6295bc9ce4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1402153482 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_csr_rw.1402153482
Directory /workspace/8.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.1502973590
Short name T719
Test name
Test status
Simulation time 8358323 ps
CPU time 1.55 seconds
Started Jul 13 05:02:07 PM PDT 24
Finished Jul 13 05:02:09 PM PDT 24
Peak memory 237600 kb
Host smart-d83e1f61-5354-461b-a1ab-fd129c539d56
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1502973590 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_intr_test.1502973590
Directory /workspace/8.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.3157024370
Short name T796
Test name
Test status
Simulation time 349280635 ps
CPU time 26.03 seconds
Started Jul 13 05:02:06 PM PDT 24
Finished Jul 13 05:02:33 PM PDT 24
Peak memory 240500 kb
Host smart-c60e80a9-e167-4a22-b4f9-7d517d30c377
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3157024370 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_same_csr_out
standing.3157024370
Directory /workspace/8.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.1565282853
Short name T142
Test name
Test status
Simulation time 2515023987 ps
CPU time 287.22 seconds
Started Jul 13 05:02:08 PM PDT 24
Finished Jul 13 05:06:56 PM PDT 24
Peak memory 269472 kb
Host smart-020ad360-f01d-40a4-9687-04186d457b62
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565282853 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.alert_handler_shadow_reg_errors_with_csr_rw.1565282853
Directory /workspace/8.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.603536414
Short name T764
Test name
Test status
Simulation time 188915202 ps
CPU time 14.96 seconds
Started Jul 13 05:02:07 PM PDT 24
Finished Jul 13 05:02:22 PM PDT 24
Peak memory 248768 kb
Host smart-71fe522c-8f20-477c-9e89-eb3e9b0668ea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=603536414 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_errors.603536414
Directory /workspace/8.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.1078508514
Short name T228
Test name
Test status
Simulation time 200470130 ps
CPU time 13.54 seconds
Started Jul 13 05:02:14 PM PDT 24
Finished Jul 13 05:02:28 PM PDT 24
Peak memory 249804 kb
Host smart-0c09a845-c736-47ba-a7e8-b7e54c557e73
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078508514 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 9.alert_handler_csr_mem_rw_with_rand_reset.1078508514
Directory /workspace/9.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.1489794897
Short name T769
Test name
Test status
Simulation time 67387685 ps
CPU time 3.49 seconds
Started Jul 13 05:02:17 PM PDT 24
Finished Jul 13 05:02:20 PM PDT 24
Peak memory 237760 kb
Host smart-db206c35-3e47-4eec-af12-1cc9ca8408fb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1489794897 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_csr_rw.1489794897
Directory /workspace/9.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.4002282149
Short name T800
Test name
Test status
Simulation time 12381180 ps
CPU time 1.36 seconds
Started Jul 13 05:02:14 PM PDT 24
Finished Jul 13 05:02:16 PM PDT 24
Peak memory 236492 kb
Host smart-16085262-6fb7-4e4d-a047-1dfa5b821b5b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4002282149 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_intr_test.4002282149
Directory /workspace/9.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.1768980578
Short name T811
Test name
Test status
Simulation time 668815935 ps
CPU time 25.06 seconds
Started Jul 13 05:02:18 PM PDT 24
Finished Jul 13 05:02:43 PM PDT 24
Peak memory 248636 kb
Host smart-5f5c0355-bbf8-43c7-a713-22250d478524
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1768980578 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_same_csr_out
standing.1768980578
Directory /workspace/9.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.894371447
Short name T148
Test name
Test status
Simulation time 10716063641 ps
CPU time 189.92 seconds
Started Jul 13 05:02:15 PM PDT 24
Finished Jul 13 05:05:25 PM PDT 24
Peak memory 265420 kb
Host smart-50b8fe57-a499-4d8d-ab62-98e6c0ae9f1f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=894371447 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shadow_reg_error
s.894371447
Directory /workspace/9.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.2079331801
Short name T150
Test name
Test status
Simulation time 28548734869 ps
CPU time 1038.61 seconds
Started Jul 13 05:02:13 PM PDT 24
Finished Jul 13 05:19:32 PM PDT 24
Peak memory 265424 kb
Host smart-fdefa53a-79d2-49fc-8710-7e382a544815
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079331801 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.alert_handler_shadow_reg_errors_with_csr_rw.2079331801
Directory /workspace/9.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.3140595014
Short name T752
Test name
Test status
Simulation time 423163269 ps
CPU time 8.8 seconds
Started Jul 13 05:02:14 PM PDT 24
Finished Jul 13 05:02:23 PM PDT 24
Peak memory 250824 kb
Host smart-7110e619-1276-4fcb-beaa-450c5eb78509
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3140595014 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_errors.3140595014
Directory /workspace/9.alert_handler_tl_errors/latest

Test location /workspace/coverage/default/0.alert_handler_alert_accum_saturation.2918338606
Short name T201
Test name
Test status
Simulation time 79769537 ps
CPU time 3.52 seconds
Started Jul 13 06:24:35 PM PDT 24
Finished Jul 13 06:24:40 PM PDT 24
Peak memory 249520 kb
Host smart-68425375-6d91-43ac-a3ea-9d5605cdef4d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2918338606 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_alert_accum_saturation.2918338606
Directory /workspace/0.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/0.alert_handler_entropy.1244831461
Short name T426
Test name
Test status
Simulation time 8251093476 ps
CPU time 895.89 seconds
Started Jul 13 06:24:50 PM PDT 24
Finished Jul 13 06:39:47 PM PDT 24
Peak memory 273896 kb
Host smart-27752492-ec8e-42de-834d-1942a6967538
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1244831461 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy.1244831461
Directory /workspace/0.alert_handler_entropy/latest

Test location /workspace/coverage/default/0.alert_handler_entropy_stress.348461768
Short name T682
Test name
Test status
Simulation time 1066958247 ps
CPU time 13.96 seconds
Started Jul 13 06:24:25 PM PDT 24
Finished Jul 13 06:24:42 PM PDT 24
Peak memory 249220 kb
Host smart-9de79f15-972b-4596-bcd3-36f10e8cd688
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=348461768 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy_stress.348461768
Directory /workspace/0.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/0.alert_handler_esc_alert_accum.2237208890
Short name T408
Test name
Test status
Simulation time 3054523031 ps
CPU time 165.67 seconds
Started Jul 13 06:24:54 PM PDT 24
Finished Jul 13 06:27:40 PM PDT 24
Peak memory 257124 kb
Host smart-e1bbe92d-ca73-48c1-a7ec-2c4a3ea3a265
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22372
08890 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_alert_accum.2237208890
Directory /workspace/0.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/0.alert_handler_esc_intr_timeout.3164479493
Short name T403
Test name
Test status
Simulation time 1766715749 ps
CPU time 47.02 seconds
Started Jul 13 06:24:36 PM PDT 24
Finished Jul 13 06:25:30 PM PDT 24
Peak memory 249856 kb
Host smart-52692d19-2a2d-4112-9179-9882641367f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31644
79493 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_intr_timeout.3164479493
Directory /workspace/0.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_lpg.2888163078
Short name T569
Test name
Test status
Simulation time 13848722996 ps
CPU time 1255.55 seconds
Started Jul 13 06:24:43 PM PDT 24
Finished Jul 13 06:45:40 PM PDT 24
Peak memory 273240 kb
Host smart-e7585e24-a274-4164-a845-ba61ec980aec
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888163078 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg.2888163078
Directory /workspace/0.alert_handler_lpg/latest

Test location /workspace/coverage/default/0.alert_handler_lpg_stub_clk.3943449445
Short name T359
Test name
Test status
Simulation time 54147702721 ps
CPU time 3077.16 seconds
Started Jul 13 06:24:25 PM PDT 24
Finished Jul 13 07:15:45 PM PDT 24
Peak memory 290268 kb
Host smart-3b6e6ca5-7e73-42f2-ac21-3d90fc4bf0f7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943449445 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg_stub_clk.3943449445
Directory /workspace/0.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/0.alert_handler_random_alerts.2622543877
Short name T554
Test name
Test status
Simulation time 901521903 ps
CPU time 13.38 seconds
Started Jul 13 06:24:29 PM PDT 24
Finished Jul 13 06:24:43 PM PDT 24
Peak memory 249204 kb
Host smart-b439725b-cafb-4880-ae6b-7c41f95ff135
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26225
43877 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_alerts.2622543877
Directory /workspace/0.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/0.alert_handler_random_classes.2137740099
Short name T642
Test name
Test status
Simulation time 951792434 ps
CPU time 55.13 seconds
Started Jul 13 06:24:26 PM PDT 24
Finished Jul 13 06:25:24 PM PDT 24
Peak memory 248912 kb
Host smart-7d105ba0-f224-4ab6-962c-6f367d310e7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21377
40099 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_classes.2137740099
Directory /workspace/0.alert_handler_random_classes/latest

Test location /workspace/coverage/default/0.alert_handler_sec_cm.2182786471
Short name T35
Test name
Test status
Simulation time 1958459250 ps
CPU time 81.56 seconds
Started Jul 13 06:24:37 PM PDT 24
Finished Jul 13 06:26:00 PM PDT 24
Peak memory 270736 kb
Host smart-2707f2a7-bf6c-461a-9622-c2914b5a24c8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2182786471 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sec_cm.2182786471
Directory /workspace/0.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/0.alert_handler_sig_int_fail.1792644845
Short name T108
Test name
Test status
Simulation time 167149418 ps
CPU time 18.54 seconds
Started Jul 13 06:24:45 PM PDT 24
Finished Jul 13 06:25:05 PM PDT 24
Peak memory 257312 kb
Host smart-6c699050-8058-4835-adbe-381402a03e20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17926
44845 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sig_int_fail.1792644845
Directory /workspace/0.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/0.alert_handler_smoke.3163958245
Short name T616
Test name
Test status
Simulation time 3456325721 ps
CPU time 51.62 seconds
Started Jul 13 06:24:30 PM PDT 24
Finished Jul 13 06:25:22 PM PDT 24
Peak memory 257488 kb
Host smart-cbc3e7b4-cd9f-4a5b-94f2-fe6a36ba000f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31639
58245 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_smoke.3163958245
Directory /workspace/0.alert_handler_smoke/latest

Test location /workspace/coverage/default/1.alert_handler_alert_accum_saturation.1342717426
Short name T200
Test name
Test status
Simulation time 34393336 ps
CPU time 2.69 seconds
Started Jul 13 06:24:28 PM PDT 24
Finished Jul 13 06:24:32 PM PDT 24
Peak memory 249544 kb
Host smart-698e7814-113a-4eec-a82e-74c975c4783c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1342717426 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_alert_accum_saturation.1342717426
Directory /workspace/1.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/1.alert_handler_entropy.3485720651
Short name T414
Test name
Test status
Simulation time 50598477901 ps
CPU time 2885.48 seconds
Started Jul 13 06:24:30 PM PDT 24
Finished Jul 13 07:12:37 PM PDT 24
Peak memory 288700 kb
Host smart-3009545c-59ee-43cd-8ea1-2b12ac3fbc00
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3485720651 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy.3485720651
Directory /workspace/1.alert_handler_entropy/latest

Test location /workspace/coverage/default/1.alert_handler_esc_alert_accum.698933594
Short name T699
Test name
Test status
Simulation time 2383651655 ps
CPU time 130.98 seconds
Started Jul 13 06:24:30 PM PDT 24
Finished Jul 13 06:26:42 PM PDT 24
Peak memory 257072 kb
Host smart-58fe9ae4-ceb2-4c9f-89a0-f16cf93f7de8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69893
3594 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_alert_accum.698933594
Directory /workspace/1.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/1.alert_handler_esc_intr_timeout.3439068109
Short name T423
Test name
Test status
Simulation time 832406840 ps
CPU time 48.57 seconds
Started Jul 13 06:24:28 PM PDT 24
Finished Jul 13 06:25:18 PM PDT 24
Peak memory 256920 kb
Host smart-5b131d14-a4e0-4796-85b6-10e7fa784751
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34390
68109 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_intr_timeout.3439068109
Directory /workspace/1.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_random_alerts.3519426930
Short name T187
Test name
Test status
Simulation time 340479852 ps
CPU time 20.04 seconds
Started Jul 13 06:24:32 PM PDT 24
Finished Jul 13 06:24:53 PM PDT 24
Peak memory 249312 kb
Host smart-3ca6b60f-b93a-4f4e-87a5-db0873c3fbc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35194
26930 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_alerts.3519426930
Directory /workspace/1.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/1.alert_handler_random_classes.1589378641
Short name T438
Test name
Test status
Simulation time 818609068 ps
CPU time 18.91 seconds
Started Jul 13 06:24:20 PM PDT 24
Finished Jul 13 06:24:42 PM PDT 24
Peak memory 256780 kb
Host smart-ae551b7a-3056-4f42-82e9-58d8fe21cb9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15893
78641 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_classes.1589378641
Directory /workspace/1.alert_handler_random_classes/latest

Test location /workspace/coverage/default/1.alert_handler_sig_int_fail.1756018046
Short name T689
Test name
Test status
Simulation time 345400298 ps
CPU time 21.35 seconds
Started Jul 13 06:24:36 PM PDT 24
Finished Jul 13 06:24:59 PM PDT 24
Peak memory 248972 kb
Host smart-7a510253-5150-421f-b5f2-8027e9063f53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17560
18046 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sig_int_fail.1756018046
Directory /workspace/1.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/1.alert_handler_smoke.1967100085
Short name T72
Test name
Test status
Simulation time 680900785 ps
CPU time 26.92 seconds
Started Jul 13 06:24:33 PM PDT 24
Finished Jul 13 06:25:01 PM PDT 24
Peak memory 257416 kb
Host smart-f4efe73d-ea89-4745-8284-e0587cc0b652
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19671
00085 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_smoke.1967100085
Directory /workspace/1.alert_handler_smoke/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all.2644111304
Short name T378
Test name
Test status
Simulation time 849779131 ps
CPU time 78.61 seconds
Started Jul 13 06:24:32 PM PDT 24
Finished Jul 13 06:25:51 PM PDT 24
Peak memory 250540 kb
Host smart-4557c0c9-bd05-416d-82e3-991ff61841f6
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644111304 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_han
dler_stress_all.2644111304
Directory /workspace/1.alert_handler_stress_all/latest

Test location /workspace/coverage/default/10.alert_handler_entropy.2069912869
Short name T662
Test name
Test status
Simulation time 31304260220 ps
CPU time 901.78 seconds
Started Jul 13 06:24:38 PM PDT 24
Finished Jul 13 06:39:41 PM PDT 24
Peak memory 273176 kb
Host smart-1853d28c-fc26-4ed7-b1a1-c089be6e16bd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069912869 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy.2069912869
Directory /workspace/10.alert_handler_entropy/latest

Test location /workspace/coverage/default/10.alert_handler_entropy_stress.2185832995
Short name T1
Test name
Test status
Simulation time 1106211218 ps
CPU time 14.05 seconds
Started Jul 13 06:24:46 PM PDT 24
Finished Jul 13 06:25:02 PM PDT 24
Peak memory 249248 kb
Host smart-593e2030-1d45-49e5-8b6a-4ed8b1163edd
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2185832995 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy_stress.2185832995
Directory /workspace/10.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/10.alert_handler_esc_alert_accum.3098414202
Short name T448
Test name
Test status
Simulation time 1902011943 ps
CPU time 120.69 seconds
Started Jul 13 06:24:43 PM PDT 24
Finished Jul 13 06:26:45 PM PDT 24
Peak memory 257488 kb
Host smart-7d27e620-16ea-4688-b6c7-5c8ff05e2df1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30984
14202 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_alert_accum.3098414202
Directory /workspace/10.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/10.alert_handler_esc_intr_timeout.60830623
Short name T482
Test name
Test status
Simulation time 858197260 ps
CPU time 52.71 seconds
Started Jul 13 06:24:39 PM PDT 24
Finished Jul 13 06:25:33 PM PDT 24
Peak memory 248844 kb
Host smart-f1914227-c25b-4ef3-8c59-94f9ea9bb311
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60830
623 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_intr_timeout.60830623
Directory /workspace/10.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_lpg.4226274905
Short name T649
Test name
Test status
Simulation time 149150278683 ps
CPU time 2255.51 seconds
Started Jul 13 06:24:57 PM PDT 24
Finished Jul 13 07:02:34 PM PDT 24
Peak memory 283176 kb
Host smart-66b6d2e8-9ae8-49a1-923c-20920ccdf9be
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226274905 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg.4226274905
Directory /workspace/10.alert_handler_lpg/latest

Test location /workspace/coverage/default/10.alert_handler_lpg_stub_clk.610740343
Short name T516
Test name
Test status
Simulation time 13128511317 ps
CPU time 1216.88 seconds
Started Jul 13 06:24:48 PM PDT 24
Finished Jul 13 06:45:06 PM PDT 24
Peak memory 289520 kb
Host smart-fc9eb624-9839-4f88-9c8c-73f23e7a97a6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610740343 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg_stub_clk.610740343
Directory /workspace/10.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/10.alert_handler_random_alerts.469860430
Short name T564
Test name
Test status
Simulation time 2522476012 ps
CPU time 38.26 seconds
Started Jul 13 06:24:53 PM PDT 24
Finished Jul 13 06:25:33 PM PDT 24
Peak memory 249404 kb
Host smart-cc523402-52fe-4896-89a0-1971490addd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46986
0430 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_alerts.469860430
Directory /workspace/10.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/10.alert_handler_random_classes.896352829
Short name T567
Test name
Test status
Simulation time 2764470721 ps
CPU time 38.26 seconds
Started Jul 13 06:24:55 PM PDT 24
Finished Jul 13 06:25:34 PM PDT 24
Peak memory 249176 kb
Host smart-5e208c38-7602-4487-ab06-32be3b7e5b69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89635
2829 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_classes.896352829
Directory /workspace/10.alert_handler_random_classes/latest

Test location /workspace/coverage/default/10.alert_handler_sig_int_fail.2866304437
Short name T192
Test name
Test status
Simulation time 185113183 ps
CPU time 22.76 seconds
Started Jul 13 06:24:48 PM PDT 24
Finished Jul 13 06:25:12 PM PDT 24
Peak memory 256796 kb
Host smart-1182b495-8dd3-4d12-8cfb-4808ab2d8038
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28663
04437 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_sig_int_fail.2866304437
Directory /workspace/10.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/10.alert_handler_smoke.205764675
Short name T411
Test name
Test status
Simulation time 397184429 ps
CPU time 25.11 seconds
Started Jul 13 06:24:45 PM PDT 24
Finished Jul 13 06:25:11 PM PDT 24
Peak memory 249204 kb
Host smart-8e455f1f-c2e2-43e6-9d86-a8fa0c7095f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20576
4675 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_smoke.205764675
Directory /workspace/10.alert_handler_smoke/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all.1655891855
Short name T306
Test name
Test status
Simulation time 249368350982 ps
CPU time 3799.25 seconds
Started Jul 13 06:24:36 PM PDT 24
Finished Jul 13 07:27:57 PM PDT 24
Peak memory 298464 kb
Host smart-55edf590-165e-40bd-afec-5b5bab76dc0e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655891855 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_ha
ndler_stress_all.1655891855
Directory /workspace/10.alert_handler_stress_all/latest

Test location /workspace/coverage/default/11.alert_handler_entropy.1462868135
Short name T608
Test name
Test status
Simulation time 125951070658 ps
CPU time 1457.96 seconds
Started Jul 13 06:25:05 PM PDT 24
Finished Jul 13 06:49:24 PM PDT 24
Peak memory 289976 kb
Host smart-f3bc1082-fc4d-4c04-8838-c90974896046
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462868135 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy.1462868135
Directory /workspace/11.alert_handler_entropy/latest

Test location /workspace/coverage/default/11.alert_handler_entropy_stress.2116075034
Short name T658
Test name
Test status
Simulation time 280011726 ps
CPU time 13.3 seconds
Started Jul 13 06:24:45 PM PDT 24
Finished Jul 13 06:25:00 PM PDT 24
Peak memory 249304 kb
Host smart-9f153553-0ee1-4455-bc25-27878bf1e0c0
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2116075034 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy_stress.2116075034
Directory /workspace/11.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/11.alert_handler_esc_alert_accum.233102935
Short name T434
Test name
Test status
Simulation time 4996606351 ps
CPU time 279.18 seconds
Started Jul 13 06:25:13 PM PDT 24
Finished Jul 13 06:29:55 PM PDT 24
Peak memory 257584 kb
Host smart-533ee59b-786c-4b66-a319-bf569386fbd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23310
2935 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_alert_accum.233102935
Directory /workspace/11.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/11.alert_handler_esc_intr_timeout.2994907504
Short name T635
Test name
Test status
Simulation time 91175156 ps
CPU time 3.27 seconds
Started Jul 13 06:24:38 PM PDT 24
Finished Jul 13 06:24:43 PM PDT 24
Peak memory 240220 kb
Host smart-032a3f7e-3de1-47e4-9383-516418af7c88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29949
07504 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_intr_timeout.2994907504
Directory /workspace/11.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_lpg_stub_clk.4171962824
Short name T38
Test name
Test status
Simulation time 55666300717 ps
CPU time 2646.57 seconds
Started Jul 13 06:25:08 PM PDT 24
Finished Jul 13 07:09:16 PM PDT 24
Peak memory 290144 kb
Host smart-49784238-d5dc-43b0-bfc2-bfdc151aae9d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4171962824 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg_stub_clk.4171962824
Directory /workspace/11.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/11.alert_handler_ping_timeout.1575554437
Short name T242
Test name
Test status
Simulation time 30598838236 ps
CPU time 320.02 seconds
Started Jul 13 06:24:36 PM PDT 24
Finished Jul 13 06:29:57 PM PDT 24
Peak memory 249392 kb
Host smart-a8820ce0-755f-4fc5-a835-df0270e933ff
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575554437 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_ping_timeout.1575554437
Directory /workspace/11.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_random_alerts.774352782
Short name T460
Test name
Test status
Simulation time 2096397526 ps
CPU time 36.43 seconds
Started Jul 13 06:24:35 PM PDT 24
Finished Jul 13 06:25:12 PM PDT 24
Peak memory 249268 kb
Host smart-8964e7f7-2f84-4b5f-a484-4cafc600b4a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77435
2782 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_alerts.774352782
Directory /workspace/11.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/11.alert_handler_random_classes.1205918646
Short name T463
Test name
Test status
Simulation time 752127178 ps
CPU time 39.59 seconds
Started Jul 13 06:24:55 PM PDT 24
Finished Jul 13 06:25:35 PM PDT 24
Peak memory 249208 kb
Host smart-5a76419d-50b2-45dc-8fb1-695cf63c2da7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12059
18646 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_classes.1205918646
Directory /workspace/11.alert_handler_random_classes/latest

Test location /workspace/coverage/default/11.alert_handler_smoke.1868674768
Short name T377
Test name
Test status
Simulation time 888588591 ps
CPU time 14.65 seconds
Started Jul 13 06:24:46 PM PDT 24
Finished Jul 13 06:25:02 PM PDT 24
Peak memory 249716 kb
Host smart-bded1062-a633-4026-9d7d-56d00fcd8446
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18686
74768 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_smoke.1868674768
Directory /workspace/11.alert_handler_smoke/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all.1517955323
Short name T233
Test name
Test status
Simulation time 109211241912 ps
CPU time 2311.57 seconds
Started Jul 13 06:24:55 PM PDT 24
Finished Jul 13 07:03:27 PM PDT 24
Peak memory 305692 kb
Host smart-3dcef3f1-05bd-4a9d-9361-47c50c2b4140
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517955323 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_ha
ndler_stress_all.1517955323
Directory /workspace/11.alert_handler_stress_all/latest

Test location /workspace/coverage/default/12.alert_handler_alert_accum_saturation.814406207
Short name T209
Test name
Test status
Simulation time 41789902 ps
CPU time 3.71 seconds
Started Jul 13 06:25:05 PM PDT 24
Finished Jul 13 06:25:09 PM PDT 24
Peak memory 249608 kb
Host smart-dfe11c6c-5b08-4100-b624-e73e92d2fcb8
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=814406207 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_alert_accum_saturation.814406207
Directory /workspace/12.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/12.alert_handler_entropy.3087035162
Short name T422
Test name
Test status
Simulation time 19655050525 ps
CPU time 1225.76 seconds
Started Jul 13 06:24:51 PM PDT 24
Finished Jul 13 06:45:17 PM PDT 24
Peak memory 283120 kb
Host smart-fd8f7b81-932c-495e-b43e-685795310127
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087035162 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy.3087035162
Directory /workspace/12.alert_handler_entropy/latest

Test location /workspace/coverage/default/12.alert_handler_entropy_stress.637328927
Short name T365
Test name
Test status
Simulation time 424647642 ps
CPU time 11.77 seconds
Started Jul 13 06:24:47 PM PDT 24
Finished Jul 13 06:25:00 PM PDT 24
Peak memory 249276 kb
Host smart-7174e5ca-f9bd-4b74-8ae4-e7e63ea0be5f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=637328927 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy_stress.637328927
Directory /workspace/12.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/12.alert_handler_esc_alert_accum.3837601990
Short name T528
Test name
Test status
Simulation time 7029150200 ps
CPU time 106.27 seconds
Started Jul 13 06:24:57 PM PDT 24
Finished Jul 13 06:26:44 PM PDT 24
Peak memory 257048 kb
Host smart-518973bb-2cea-4b48-990f-d11c99dffe3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38376
01990 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_alert_accum.3837601990
Directory /workspace/12.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/12.alert_handler_esc_intr_timeout.3045158783
Short name T503
Test name
Test status
Simulation time 1820271796 ps
CPU time 51.22 seconds
Started Jul 13 06:24:57 PM PDT 24
Finished Jul 13 06:25:49 PM PDT 24
Peak memory 249660 kb
Host smart-2a0a4a3a-8073-45c2-8138-63e4d98e6051
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30451
58783 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_intr_timeout.3045158783
Directory /workspace/12.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_lpg.3358629016
Short name T297
Test name
Test status
Simulation time 33056834853 ps
CPU time 1988.98 seconds
Started Jul 13 06:24:45 PM PDT 24
Finished Jul 13 06:57:54 PM PDT 24
Peak memory 289732 kb
Host smart-2fa7bfff-c7c1-4dc7-b409-230a4634dcd0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3358629016 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg.3358629016
Directory /workspace/12.alert_handler_lpg/latest

Test location /workspace/coverage/default/12.alert_handler_lpg_stub_clk.141928380
Short name T576
Test name
Test status
Simulation time 13614065960 ps
CPU time 1206.79 seconds
Started Jul 13 06:25:02 PM PDT 24
Finished Jul 13 06:45:10 PM PDT 24
Peak memory 288528 kb
Host smart-d17afd2a-32de-42ee-82b1-13b2d4423117
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141928380 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg_stub_clk.141928380
Directory /workspace/12.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/12.alert_handler_random_alerts.2268657408
Short name T398
Test name
Test status
Simulation time 2719958561 ps
CPU time 41.8 seconds
Started Jul 13 06:25:10 PM PDT 24
Finished Jul 13 06:25:54 PM PDT 24
Peak memory 257388 kb
Host smart-3e33d6cc-4d1e-4ef5-9bb0-beab2d62d332
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22686
57408 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_alerts.2268657408
Directory /workspace/12.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/12.alert_handler_random_classes.3851600613
Short name T703
Test name
Test status
Simulation time 426075928 ps
CPU time 21.49 seconds
Started Jul 13 06:24:47 PM PDT 24
Finished Jul 13 06:25:10 PM PDT 24
Peak memory 248664 kb
Host smart-26feea59-ea7b-452b-8bca-a6f48cef616f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38516
00613 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_classes.3851600613
Directory /workspace/12.alert_handler_random_classes/latest

Test location /workspace/coverage/default/12.alert_handler_sig_int_fail.3749933466
Short name T583
Test name
Test status
Simulation time 869993668 ps
CPU time 46.63 seconds
Started Jul 13 06:24:39 PM PDT 24
Finished Jul 13 06:25:28 PM PDT 24
Peak memory 249300 kb
Host smart-dbb345ed-9a63-4c71-aca4-a3063b3ac0a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37499
33466 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_sig_int_fail.3749933466
Directory /workspace/12.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/12.alert_handler_smoke.3231397894
Short name T526
Test name
Test status
Simulation time 4679580595 ps
CPU time 59.81 seconds
Started Jul 13 06:24:57 PM PDT 24
Finished Jul 13 06:25:58 PM PDT 24
Peak memory 257556 kb
Host smart-6c00dea7-bf21-4abc-bfaf-51dadf502712
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32313
97894 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_smoke.3231397894
Directory /workspace/12.alert_handler_smoke/latest

Test location /workspace/coverage/default/13.alert_handler_alert_accum_saturation.1311138762
Short name T203
Test name
Test status
Simulation time 44937564 ps
CPU time 3.65 seconds
Started Jul 13 06:24:42 PM PDT 24
Finished Jul 13 06:24:48 PM PDT 24
Peak memory 249528 kb
Host smart-cd7578de-9fcf-4a6f-bdfd-9af5b94a8ccd
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1311138762 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_alert_accum_saturation.1311138762
Directory /workspace/13.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/13.alert_handler_entropy.4048631388
Short name T110
Test name
Test status
Simulation time 393246499974 ps
CPU time 2449.73 seconds
Started Jul 13 06:24:41 PM PDT 24
Finished Jul 13 07:05:33 PM PDT 24
Peak memory 284192 kb
Host smart-8be9f146-1a8e-407d-b97e-352f562cbac6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048631388 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy.4048631388
Directory /workspace/13.alert_handler_entropy/latest

Test location /workspace/coverage/default/13.alert_handler_entropy_stress.2735302854
Short name T592
Test name
Test status
Simulation time 165158291 ps
CPU time 9.38 seconds
Started Jul 13 06:24:42 PM PDT 24
Finished Jul 13 06:24:53 PM PDT 24
Peak memory 249196 kb
Host smart-09633624-be3c-4466-b1a5-8e0496d46ae4
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2735302854 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy_stress.2735302854
Directory /workspace/13.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/13.alert_handler_esc_alert_accum.2946240655
Short name T432
Test name
Test status
Simulation time 979491487 ps
CPU time 107.44 seconds
Started Jul 13 06:24:45 PM PDT 24
Finished Jul 13 06:26:34 PM PDT 24
Peak memory 256932 kb
Host smart-87c21e39-0bfb-4e17-ad6a-73d2fd42d76d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29462
40655 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_alert_accum.2946240655
Directory /workspace/13.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/13.alert_handler_esc_intr_timeout.3652350057
Short name T73
Test name
Test status
Simulation time 488102594 ps
CPU time 32.07 seconds
Started Jul 13 06:25:02 PM PDT 24
Finished Jul 13 06:25:35 PM PDT 24
Peak memory 249224 kb
Host smart-4c0465df-ce5f-4fed-8157-568d5bc10236
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36523
50057 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_intr_timeout.3652350057
Directory /workspace/13.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_lpg.717514660
Short name T286
Test name
Test status
Simulation time 177066142689 ps
CPU time 2435.29 seconds
Started Jul 13 06:24:59 PM PDT 24
Finished Jul 13 07:05:35 PM PDT 24
Peak memory 287988 kb
Host smart-a7e006a7-6fcc-437a-94dd-f96712ebb1cd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717514660 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg.717514660
Directory /workspace/13.alert_handler_lpg/latest

Test location /workspace/coverage/default/13.alert_handler_lpg_stub_clk.701612314
Short name T533
Test name
Test status
Simulation time 69081721054 ps
CPU time 1120.08 seconds
Started Jul 13 06:24:48 PM PDT 24
Finished Jul 13 06:43:29 PM PDT 24
Peak memory 273904 kb
Host smart-bdfa4080-13cf-40f9-99ff-c9c2f67f4ba3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=701612314 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg_stub_clk.701612314
Directory /workspace/13.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/13.alert_handler_ping_timeout.147240899
Short name T600
Test name
Test status
Simulation time 7088978981 ps
CPU time 284.02 seconds
Started Jul 13 06:25:03 PM PDT 24
Finished Jul 13 06:29:48 PM PDT 24
Peak memory 249564 kb
Host smart-505d2478-7414-4419-b5e5-6fd31e92e04d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=147240899 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_ping_timeout.147240899
Directory /workspace/13.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_random_alerts.3515259345
Short name T471
Test name
Test status
Simulation time 102247162 ps
CPU time 7.29 seconds
Started Jul 13 06:24:58 PM PDT 24
Finished Jul 13 06:25:06 PM PDT 24
Peak memory 251840 kb
Host smart-3f44d1f7-dfbd-4ea1-92a4-a2cb8f62e26b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35152
59345 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_alerts.3515259345
Directory /workspace/13.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/13.alert_handler_random_classes.4202066492
Short name T469
Test name
Test status
Simulation time 89940406 ps
CPU time 4.16 seconds
Started Jul 13 06:24:57 PM PDT 24
Finished Jul 13 06:25:02 PM PDT 24
Peak memory 240384 kb
Host smart-6d341fc8-ec23-4a74-89a3-8e9be413870f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42020
66492 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_classes.4202066492
Directory /workspace/13.alert_handler_random_classes/latest

Test location /workspace/coverage/default/13.alert_handler_sig_int_fail.4193869176
Short name T679
Test name
Test status
Simulation time 1184262885 ps
CPU time 34.11 seconds
Started Jul 13 06:25:07 PM PDT 24
Finished Jul 13 06:25:42 PM PDT 24
Peak memory 256516 kb
Host smart-59ab7348-b78c-422b-a1a1-4db2158897d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41938
69176 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_sig_int_fail.4193869176
Directory /workspace/13.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/13.alert_handler_smoke.3479136118
Short name T475
Test name
Test status
Simulation time 339709251 ps
CPU time 31.2 seconds
Started Jul 13 06:24:45 PM PDT 24
Finished Jul 13 06:25:17 PM PDT 24
Peak memory 256396 kb
Host smart-d5760c5e-55e2-48d3-b8f0-9743985e5dec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34791
36118 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_smoke.3479136118
Directory /workspace/13.alert_handler_smoke/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all.4213479148
Short name T653
Test name
Test status
Simulation time 14101222451 ps
CPU time 853.24 seconds
Started Jul 13 06:25:06 PM PDT 24
Finished Jul 13 06:39:20 PM PDT 24
Peak memory 273996 kb
Host smart-ff4504f9-3ffb-43fc-ac13-fefe668eada1
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213479148 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_ha
ndler_stress_all.4213479148
Directory /workspace/13.alert_handler_stress_all/latest

Test location /workspace/coverage/default/14.alert_handler_alert_accum_saturation.4287717244
Short name T212
Test name
Test status
Simulation time 45015874 ps
CPU time 2.34 seconds
Started Jul 13 06:24:44 PM PDT 24
Finished Jul 13 06:24:47 PM PDT 24
Peak memory 249460 kb
Host smart-476b728d-77ee-4d98-912b-dbbce4d44379
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4287717244 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_alert_accum_saturation.4287717244
Directory /workspace/14.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/14.alert_handler_entropy.2805794419
Short name T565
Test name
Test status
Simulation time 18097055514 ps
CPU time 1247.49 seconds
Started Jul 13 06:25:06 PM PDT 24
Finished Jul 13 06:45:55 PM PDT 24
Peak memory 273500 kb
Host smart-4026cd2c-2229-45d6-9384-abd426d19887
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805794419 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy.2805794419
Directory /workspace/14.alert_handler_entropy/latest

Test location /workspace/coverage/default/14.alert_handler_entropy_stress.2933117439
Short name T470
Test name
Test status
Simulation time 2737374237 ps
CPU time 29.06 seconds
Started Jul 13 06:25:02 PM PDT 24
Finished Jul 13 06:25:33 PM PDT 24
Peak memory 249372 kb
Host smart-07c56b0f-60a8-4922-8bc0-ffc6d58d2e70
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2933117439 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy_stress.2933117439
Directory /workspace/14.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/14.alert_handler_esc_alert_accum.286299118
Short name T443
Test name
Test status
Simulation time 1400579342 ps
CPU time 70.09 seconds
Started Jul 13 06:24:47 PM PDT 24
Finished Jul 13 06:25:58 PM PDT 24
Peak memory 256832 kb
Host smart-9a366f11-6945-41d5-879f-ceac1c803be1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28629
9118 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_alert_accum.286299118
Directory /workspace/14.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/14.alert_handler_esc_intr_timeout.397091533
Short name T625
Test name
Test status
Simulation time 373535676 ps
CPU time 23.81 seconds
Started Jul 13 06:25:03 PM PDT 24
Finished Jul 13 06:25:28 PM PDT 24
Peak memory 256940 kb
Host smart-571d60dd-bb2e-4578-9296-3399100616da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39709
1533 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_intr_timeout.397091533
Directory /workspace/14.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_lpg.1814972192
Short name T676
Test name
Test status
Simulation time 100364515775 ps
CPU time 1650.18 seconds
Started Jul 13 06:24:59 PM PDT 24
Finished Jul 13 06:52:30 PM PDT 24
Peak memory 273340 kb
Host smart-ba9689ad-ffd5-4c52-b371-83c87d3bc652
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1814972192 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg.1814972192
Directory /workspace/14.alert_handler_lpg/latest

Test location /workspace/coverage/default/14.alert_handler_lpg_stub_clk.1466566015
Short name T626
Test name
Test status
Simulation time 35729158525 ps
CPU time 1752.78 seconds
Started Jul 13 06:24:56 PM PDT 24
Finished Jul 13 06:54:10 PM PDT 24
Peak memory 273776 kb
Host smart-79856d6a-c876-43f5-bb61-3afd36b2955b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1466566015 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg_stub_clk.1466566015
Directory /workspace/14.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/14.alert_handler_ping_timeout.3884455518
Short name T280
Test name
Test status
Simulation time 4623193136 ps
CPU time 186.29 seconds
Started Jul 13 06:25:13 PM PDT 24
Finished Jul 13 06:28:21 PM PDT 24
Peak memory 249376 kb
Host smart-57fa1b7c-d2a3-4675-a530-6a79b5394fc2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884455518 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_ping_timeout.3884455518
Directory /workspace/14.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_random_alerts.1686505568
Short name T628
Test name
Test status
Simulation time 15236159479 ps
CPU time 70.52 seconds
Started Jul 13 06:24:36 PM PDT 24
Finished Jul 13 06:25:48 PM PDT 24
Peak memory 257596 kb
Host smart-07cc565b-f68e-4865-80b6-dac60bbd2df9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16865
05568 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_alerts.1686505568
Directory /workspace/14.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/14.alert_handler_random_classes.2701221538
Short name T424
Test name
Test status
Simulation time 394994057 ps
CPU time 27.63 seconds
Started Jul 13 06:24:48 PM PDT 24
Finished Jul 13 06:25:17 PM PDT 24
Peak memory 248736 kb
Host smart-4b988770-928e-46c7-a268-c7daa3432ed8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27012
21538 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_classes.2701221538
Directory /workspace/14.alert_handler_random_classes/latest

Test location /workspace/coverage/default/14.alert_handler_sig_int_fail.1249323650
Short name T437
Test name
Test status
Simulation time 435382602 ps
CPU time 28.4 seconds
Started Jul 13 06:25:19 PM PDT 24
Finished Jul 13 06:25:48 PM PDT 24
Peak memory 248592 kb
Host smart-d5cc81ef-fa9d-42bb-8553-558d8723d048
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12493
23650 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_sig_int_fail.1249323650
Directory /workspace/14.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/14.alert_handler_smoke.798450641
Short name T191
Test name
Test status
Simulation time 1267625529 ps
CPU time 20.89 seconds
Started Jul 13 06:24:53 PM PDT 24
Finished Jul 13 06:25:15 PM PDT 24
Peak memory 256012 kb
Host smart-4512b867-488b-4230-8de1-6b38896c71ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79845
0641 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_smoke.798450641
Directory /workspace/14.alert_handler_smoke/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all.3887044791
Short name T613
Test name
Test status
Simulation time 14899318333 ps
CPU time 1536.35 seconds
Started Jul 13 06:24:52 PM PDT 24
Finished Jul 13 06:50:29 PM PDT 24
Peak memory 290140 kb
Host smart-86bb29be-96e8-4cf1-8759-6495b4660bbf
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887044791 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_ha
ndler_stress_all.3887044791
Directory /workspace/14.alert_handler_stress_all/latest

Test location /workspace/coverage/default/15.alert_handler_alert_accum_saturation.3552290258
Short name T198
Test name
Test status
Simulation time 31845304 ps
CPU time 3.6 seconds
Started Jul 13 06:24:49 PM PDT 24
Finished Jul 13 06:24:54 PM PDT 24
Peak memory 249564 kb
Host smart-d743bf10-f2e2-476a-9b90-069147fe9645
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3552290258 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_alert_accum_saturation.3552290258
Directory /workspace/15.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/15.alert_handler_entropy.3313577467
Short name T57
Test name
Test status
Simulation time 14914577376 ps
CPU time 741.71 seconds
Started Jul 13 06:24:46 PM PDT 24
Finished Jul 13 06:37:09 PM PDT 24
Peak memory 272960 kb
Host smart-f94401b2-e062-4a82-afbb-72315da6fb8d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313577467 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy.3313577467
Directory /workspace/15.alert_handler_entropy/latest

Test location /workspace/coverage/default/15.alert_handler_entropy_stress.2752299641
Short name T67
Test name
Test status
Simulation time 3339713765 ps
CPU time 39.41 seconds
Started Jul 13 06:25:00 PM PDT 24
Finished Jul 13 06:25:40 PM PDT 24
Peak memory 249380 kb
Host smart-4f1c89cd-7dc8-4c20-8a29-3202e81f8334
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2752299641 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy_stress.2752299641
Directory /workspace/15.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/15.alert_handler_esc_alert_accum.221034072
Short name T386
Test name
Test status
Simulation time 3100655398 ps
CPU time 54.03 seconds
Started Jul 13 06:25:01 PM PDT 24
Finished Jul 13 06:25:55 PM PDT 24
Peak memory 257136 kb
Host smart-bd0efa3a-fa9a-4c3f-a384-6b49a4de3f08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22103
4072 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_alert_accum.221034072
Directory /workspace/15.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/15.alert_handler_esc_intr_timeout.3023956797
Short name T77
Test name
Test status
Simulation time 3560300380 ps
CPU time 55.67 seconds
Started Jul 13 06:24:51 PM PDT 24
Finished Jul 13 06:25:47 PM PDT 24
Peak memory 249992 kb
Host smart-f09b4c1b-5c93-4ce7-882f-025897bda197
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30239
56797 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_intr_timeout.3023956797
Directory /workspace/15.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_lpg_stub_clk.1926667026
Short name T685
Test name
Test status
Simulation time 49003637750 ps
CPU time 1085.44 seconds
Started Jul 13 06:25:08 PM PDT 24
Finished Jul 13 06:43:15 PM PDT 24
Peak memory 271900 kb
Host smart-ecd84210-45bb-4945-84af-38ca7aa3c04e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926667026 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg_stub_clk.1926667026
Directory /workspace/15.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/15.alert_handler_ping_timeout.1500288862
Short name T495
Test name
Test status
Simulation time 26366894144 ps
CPU time 277.04 seconds
Started Jul 13 06:25:08 PM PDT 24
Finished Jul 13 06:29:47 PM PDT 24
Peak memory 256036 kb
Host smart-47c240d7-9d7b-4b1b-9ecf-6b1d87a2e47e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500288862 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_ping_timeout.1500288862
Directory /workspace/15.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_random_alerts.1603490372
Short name T664
Test name
Test status
Simulation time 147775317 ps
CPU time 5.9 seconds
Started Jul 13 06:24:39 PM PDT 24
Finished Jul 13 06:24:47 PM PDT 24
Peak memory 249144 kb
Host smart-b9947add-641a-4715-808a-e937fcadb6aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16034
90372 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_alerts.1603490372
Directory /workspace/15.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/15.alert_handler_random_classes.1928923639
Short name T465
Test name
Test status
Simulation time 1268122899 ps
CPU time 69.28 seconds
Started Jul 13 06:24:45 PM PDT 24
Finished Jul 13 06:25:55 PM PDT 24
Peak memory 256200 kb
Host smart-1ba690cb-077c-40b1-935d-3231735e6782
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19289
23639 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_classes.1928923639
Directory /workspace/15.alert_handler_random_classes/latest

Test location /workspace/coverage/default/15.alert_handler_sig_int_fail.966755431
Short name T54
Test name
Test status
Simulation time 703707291 ps
CPU time 48.06 seconds
Started Jul 13 06:25:10 PM PDT 24
Finished Jul 13 06:26:00 PM PDT 24
Peak memory 256736 kb
Host smart-52d818dd-fc86-42d5-a914-61a1a0212dd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96675
5431 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_sig_int_fail.966755431
Directory /workspace/15.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/15.alert_handler_smoke.3933000176
Short name T615
Test name
Test status
Simulation time 149855204 ps
CPU time 15.85 seconds
Started Jul 13 06:24:58 PM PDT 24
Finished Jul 13 06:25:15 PM PDT 24
Peak memory 256208 kb
Host smart-18054d0f-d3d8-406b-8125-011bb25c2d53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39330
00176 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_smoke.3933000176
Directory /workspace/15.alert_handler_smoke/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all.33769518
Short name T588
Test name
Test status
Simulation time 99926714370 ps
CPU time 1568.59 seconds
Started Jul 13 06:24:55 PM PDT 24
Finished Jul 13 06:51:04 PM PDT 24
Peak memory 306028 kb
Host smart-c96e9155-caa6-4643-9813-8d2ff166ed7d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33769518 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_hand
ler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_hand
ler_stress_all.33769518
Directory /workspace/15.alert_handler_stress_all/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all_with_rand_reset.2236817712
Short name T568
Test name
Test status
Simulation time 31416429958 ps
CPU time 3231.45 seconds
Started Jul 13 06:24:53 PM PDT 24
Finished Jul 13 07:18:46 PM PDT 24
Peak memory 331300 kb
Host smart-1adc7ec6-88ee-4648-b47c-d77229c04c9c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236817712 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 15.alert_handler_stress_all_with_rand_reset.2236817712
Directory /workspace/15.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.alert_handler_alert_accum_saturation.1563360543
Short name T197
Test name
Test status
Simulation time 53256439 ps
CPU time 3.2 seconds
Started Jul 13 06:25:02 PM PDT 24
Finished Jul 13 06:25:06 PM PDT 24
Peak memory 249508 kb
Host smart-50dfd1cf-fded-4b49-b76a-d6ff6a68ce39
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1563360543 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_alert_accum_saturation.1563360543
Directory /workspace/16.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/16.alert_handler_entropy_stress.1735850836
Short name T488
Test name
Test status
Simulation time 254553548 ps
CPU time 8.39 seconds
Started Jul 13 06:24:48 PM PDT 24
Finished Jul 13 06:25:03 PM PDT 24
Peak memory 249132 kb
Host smart-dfd9128d-2dd1-4920-8988-1f4565ebe778
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1735850836 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy_stress.1735850836
Directory /workspace/16.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/16.alert_handler_esc_intr_timeout.296871746
Short name T596
Test name
Test status
Simulation time 3014968789 ps
CPU time 35.37 seconds
Started Jul 13 06:24:58 PM PDT 24
Finished Jul 13 06:25:35 PM PDT 24
Peak memory 249792 kb
Host smart-b58d8f54-e31b-43f1-89cb-6179bb0152d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29687
1746 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_intr_timeout.296871746
Directory /workspace/16.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_lpg.981775797
Short name T275
Test name
Test status
Simulation time 49614660226 ps
CPU time 1082.12 seconds
Started Jul 13 06:24:45 PM PDT 24
Finished Jul 13 06:42:49 PM PDT 24
Peak memory 273648 kb
Host smart-32bf16bf-5466-433b-9774-8bde16793b2a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981775797 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg.981775797
Directory /workspace/16.alert_handler_lpg/latest

Test location /workspace/coverage/default/16.alert_handler_lpg_stub_clk.162170501
Short name T100
Test name
Test status
Simulation time 23563638108 ps
CPU time 1531.08 seconds
Started Jul 13 06:25:08 PM PDT 24
Finished Jul 13 06:50:41 PM PDT 24
Peak memory 273844 kb
Host smart-737ca098-f465-4320-a175-0720da0bbe4b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162170501 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg_stub_clk.162170501
Directory /workspace/16.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/16.alert_handler_ping_timeout.1772366621
Short name T515
Test name
Test status
Simulation time 14595141234 ps
CPU time 232.78 seconds
Started Jul 13 06:24:56 PM PDT 24
Finished Jul 13 06:28:49 PM PDT 24
Peak memory 249352 kb
Host smart-62504e4b-4b9f-48d9-9994-1935d705f079
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772366621 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_ping_timeout.1772366621
Directory /workspace/16.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_random_alerts.1726858680
Short name T419
Test name
Test status
Simulation time 1955872183 ps
CPU time 21.87 seconds
Started Jul 13 06:25:06 PM PDT 24
Finished Jul 13 06:25:29 PM PDT 24
Peak memory 249264 kb
Host smart-85e95c34-50cb-4cf7-b7a0-9c67fafcc9e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17268
58680 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_alerts.1726858680
Directory /workspace/16.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/16.alert_handler_random_classes.1177587722
Short name T671
Test name
Test status
Simulation time 120475183 ps
CPU time 4.76 seconds
Started Jul 13 06:24:49 PM PDT 24
Finished Jul 13 06:24:54 PM PDT 24
Peak memory 241084 kb
Host smart-a5a327b1-c665-493b-9c36-430b8480e4ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11775
87722 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_classes.1177587722
Directory /workspace/16.alert_handler_random_classes/latest

Test location /workspace/coverage/default/16.alert_handler_sig_int_fail.789678227
Short name T318
Test name
Test status
Simulation time 205916710 ps
CPU time 24.85 seconds
Started Jul 13 06:24:51 PM PDT 24
Finished Jul 13 06:25:17 PM PDT 24
Peak memory 248984 kb
Host smart-204c1a2e-779f-4a43-a2de-84e90f86d6d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78967
8227 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_sig_int_fail.789678227
Directory /workspace/16.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/16.alert_handler_smoke.2835247615
Short name T521
Test name
Test status
Simulation time 242916707 ps
CPU time 25.3 seconds
Started Jul 13 06:24:50 PM PDT 24
Finished Jul 13 06:25:16 PM PDT 24
Peak memory 257416 kb
Host smart-b2b6ae73-148d-43ce-9941-16f2199b1cba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28352
47615 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_smoke.2835247615
Directory /workspace/16.alert_handler_smoke/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all_with_rand_reset.177734142
Short name T175
Test name
Test status
Simulation time 16053370389 ps
CPU time 1603.69 seconds
Started Jul 13 06:25:11 PM PDT 24
Finished Jul 13 06:51:57 PM PDT 24
Peak memory 290076 kb
Host smart-7fa49278-d144-4ef7-bb7a-59811df9d18d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177734142 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 16.alert_handler_stress_all_with_rand_reset.177734142
Directory /workspace/16.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.alert_handler_entropy.1958828355
Short name T593
Test name
Test status
Simulation time 13824456893 ps
CPU time 704.39 seconds
Started Jul 13 06:25:10 PM PDT 24
Finished Jul 13 06:36:56 PM PDT 24
Peak memory 265744 kb
Host smart-2312de38-619c-4f7b-8567-670bb1290baf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1958828355 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy.1958828355
Directory /workspace/17.alert_handler_entropy/latest

Test location /workspace/coverage/default/17.alert_handler_entropy_stress.4214387819
Short name T683
Test name
Test status
Simulation time 596567994 ps
CPU time 28.34 seconds
Started Jul 13 06:25:03 PM PDT 24
Finished Jul 13 06:25:33 PM PDT 24
Peak memory 249188 kb
Host smart-081f51b6-e466-416d-b276-b28615d1661d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4214387819 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy_stress.4214387819
Directory /workspace/17.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/17.alert_handler_esc_alert_accum.2229922011
Short name T257
Test name
Test status
Simulation time 3383786479 ps
CPU time 94.62 seconds
Started Jul 13 06:25:14 PM PDT 24
Finished Jul 13 06:26:50 PM PDT 24
Peak memory 256868 kb
Host smart-603f5dab-3987-48d3-b281-bfcd76d59d1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22299
22011 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_alert_accum.2229922011
Directory /workspace/17.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/17.alert_handler_esc_intr_timeout.355047887
Short name T439
Test name
Test status
Simulation time 337254831 ps
CPU time 28.59 seconds
Started Jul 13 06:25:11 PM PDT 24
Finished Jul 13 06:25:41 PM PDT 24
Peak memory 248972 kb
Host smart-d90b5f58-a83e-41df-b93d-666500f4da7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35504
7887 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_intr_timeout.355047887
Directory /workspace/17.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_lpg.2109003280
Short name T442
Test name
Test status
Simulation time 133277585449 ps
CPU time 2146.88 seconds
Started Jul 13 06:25:12 PM PDT 24
Finished Jul 13 07:01:01 PM PDT 24
Peak memory 283592 kb
Host smart-4a9b4af3-429d-4e9a-a7d5-3c393ada357c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109003280 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg.2109003280
Directory /workspace/17.alert_handler_lpg/latest

Test location /workspace/coverage/default/17.alert_handler_lpg_stub_clk.3465869742
Short name T581
Test name
Test status
Simulation time 28147905249 ps
CPU time 866.38 seconds
Started Jul 13 06:24:45 PM PDT 24
Finished Jul 13 06:39:12 PM PDT 24
Peak memory 272160 kb
Host smart-0d75f120-af8f-45b1-8f40-3dfacd6e91a9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465869742 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg_stub_clk.3465869742
Directory /workspace/17.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/17.alert_handler_ping_timeout.108546737
Short name T282
Test name
Test status
Simulation time 6613408738 ps
CPU time 300.36 seconds
Started Jul 13 06:25:12 PM PDT 24
Finished Jul 13 06:30:14 PM PDT 24
Peak memory 248300 kb
Host smart-248f2199-85f1-4a13-9764-dbeb1567eaa1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108546737 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_ping_timeout.108546737
Directory /workspace/17.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_random_alerts.1129787575
Short name T668
Test name
Test status
Simulation time 1764693103 ps
CPU time 29.77 seconds
Started Jul 13 06:25:04 PM PDT 24
Finished Jul 13 06:25:34 PM PDT 24
Peak memory 256716 kb
Host smart-aa6200cd-0498-417a-a2b2-963d6c060c1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11297
87575 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_alerts.1129787575
Directory /workspace/17.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/17.alert_handler_random_classes.2994936258
Short name T561
Test name
Test status
Simulation time 1923048352 ps
CPU time 28.65 seconds
Started Jul 13 06:25:02 PM PDT 24
Finished Jul 13 06:25:32 PM PDT 24
Peak memory 249288 kb
Host smart-7c2d398c-75b7-4f86-9da5-7ca1b1d8301f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29949
36258 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_classes.2994936258
Directory /workspace/17.alert_handler_random_classes/latest

Test location /workspace/coverage/default/17.alert_handler_sig_int_fail.196493599
Short name T226
Test name
Test status
Simulation time 118996384 ps
CPU time 9.09 seconds
Started Jul 13 06:25:15 PM PDT 24
Finished Jul 13 06:25:26 PM PDT 24
Peak memory 252048 kb
Host smart-aba516f5-282a-4978-9360-41f8fc8b618c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19649
3599 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_sig_int_fail.196493599
Directory /workspace/17.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/17.alert_handler_smoke.2560791659
Short name T486
Test name
Test status
Simulation time 987843125 ps
CPU time 25.02 seconds
Started Jul 13 06:24:52 PM PDT 24
Finished Jul 13 06:25:17 PM PDT 24
Peak memory 257408 kb
Host smart-0b754781-2ef1-40a2-bea1-eca8618fdf08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25607
91659 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_smoke.2560791659
Directory /workspace/17.alert_handler_smoke/latest

Test location /workspace/coverage/default/18.alert_handler_alert_accum_saturation.2193083264
Short name T204
Test name
Test status
Simulation time 29047648 ps
CPU time 3.17 seconds
Started Jul 13 06:24:57 PM PDT 24
Finished Jul 13 06:25:01 PM PDT 24
Peak memory 249360 kb
Host smart-a833d19a-b131-4600-acfc-7a1c8093e13e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2193083264 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_alert_accum_saturation.2193083264
Directory /workspace/18.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/18.alert_handler_entropy.2080689292
Short name T575
Test name
Test status
Simulation time 72137141563 ps
CPU time 1974.97 seconds
Started Jul 13 06:25:06 PM PDT 24
Finished Jul 13 06:58:03 PM PDT 24
Peak memory 273348 kb
Host smart-cef6c1da-7f22-486b-aa42-7b0c0a866cae
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080689292 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy.2080689292
Directory /workspace/18.alert_handler_entropy/latest

Test location /workspace/coverage/default/18.alert_handler_entropy_stress.2195988724
Short name T510
Test name
Test status
Simulation time 327137733 ps
CPU time 9.94 seconds
Started Jul 13 06:25:07 PM PDT 24
Finished Jul 13 06:25:18 PM PDT 24
Peak memory 249188 kb
Host smart-4e53d11a-033b-4226-9375-d9f396d0e2c1
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2195988724 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy_stress.2195988724
Directory /workspace/18.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/18.alert_handler_esc_alert_accum.4271558795
Short name T527
Test name
Test status
Simulation time 13646710945 ps
CPU time 241.97 seconds
Started Jul 13 06:25:02 PM PDT 24
Finished Jul 13 06:29:05 PM PDT 24
Peak memory 257588 kb
Host smart-1882dfe8-5f1a-4756-b9fb-1862d9002d87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42715
58795 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_alert_accum.4271558795
Directory /workspace/18.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/18.alert_handler_esc_intr_timeout.2296664332
Short name T661
Test name
Test status
Simulation time 735623117 ps
CPU time 50.57 seconds
Started Jul 13 06:24:54 PM PDT 24
Finished Jul 13 06:25:45 PM PDT 24
Peak memory 249180 kb
Host smart-dc44d061-877f-4ba7-8986-6d39ff4d8fa5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22966
64332 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_intr_timeout.2296664332
Directory /workspace/18.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_lpg.3045288471
Short name T331
Test name
Test status
Simulation time 15710469860 ps
CPU time 866.06 seconds
Started Jul 13 06:24:59 PM PDT 24
Finished Jul 13 06:39:26 PM PDT 24
Peak memory 273856 kb
Host smart-35697bbc-9d9b-4b3c-809c-04b061e55077
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045288471 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg.3045288471
Directory /workspace/18.alert_handler_lpg/latest

Test location /workspace/coverage/default/18.alert_handler_lpg_stub_clk.4237358558
Short name T64
Test name
Test status
Simulation time 11278121818 ps
CPU time 966.2 seconds
Started Jul 13 06:24:53 PM PDT 24
Finished Jul 13 06:41:01 PM PDT 24
Peak memory 272892 kb
Host smart-5b142ef5-b403-4d1c-875e-3ede31682b3b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237358558 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg_stub_clk.4237358558
Directory /workspace/18.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/18.alert_handler_ping_timeout.1806719715
Short name T285
Test name
Test status
Simulation time 25935611511 ps
CPU time 275.83 seconds
Started Jul 13 06:24:59 PM PDT 24
Finished Jul 13 06:29:36 PM PDT 24
Peak memory 255860 kb
Host smart-c8bc763b-cd71-49b2-9d25-47529804cc28
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806719715 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_ping_timeout.1806719715
Directory /workspace/18.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_random_alerts.826444671
Short name T609
Test name
Test status
Simulation time 1209049274 ps
CPU time 71.12 seconds
Started Jul 13 06:25:03 PM PDT 24
Finished Jul 13 06:26:15 PM PDT 24
Peak memory 256704 kb
Host smart-127bc3d0-67c0-4042-b773-ee9f5e2e5774
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82644
4671 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_alerts.826444671
Directory /workspace/18.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/18.alert_handler_random_classes.4177109358
Short name T41
Test name
Test status
Simulation time 1692100105 ps
CPU time 53.35 seconds
Started Jul 13 06:24:48 PM PDT 24
Finished Jul 13 06:25:42 PM PDT 24
Peak memory 256944 kb
Host smart-6deecc65-c5ae-4a36-a958-9456e51e3b5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41771
09358 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_classes.4177109358
Directory /workspace/18.alert_handler_random_classes/latest

Test location /workspace/coverage/default/18.alert_handler_sig_int_fail.2499516677
Short name T691
Test name
Test status
Simulation time 905647740 ps
CPU time 34.48 seconds
Started Jul 13 06:25:12 PM PDT 24
Finished Jul 13 06:25:48 PM PDT 24
Peak memory 257404 kb
Host smart-238a8a3c-bc7b-40a0-a200-98de3262e35f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24995
16677 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_sig_int_fail.2499516677
Directory /workspace/18.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/18.alert_handler_smoke.1761182012
Short name T512
Test name
Test status
Simulation time 613825068 ps
CPU time 39.43 seconds
Started Jul 13 06:24:48 PM PDT 24
Finished Jul 13 06:25:29 PM PDT 24
Peak memory 249144 kb
Host smart-af363e3d-901e-4725-93cc-23964d2813ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17611
82012 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_smoke.1761182012
Directory /workspace/18.alert_handler_smoke/latest

Test location /workspace/coverage/default/19.alert_handler_entropy.2256006060
Short name T504
Test name
Test status
Simulation time 36924977906 ps
CPU time 2418.62 seconds
Started Jul 13 06:25:09 PM PDT 24
Finished Jul 13 07:05:29 PM PDT 24
Peak memory 289456 kb
Host smart-94538ca7-7a13-4405-b0f5-414e9b3aa851
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256006060 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy.2256006060
Directory /workspace/19.alert_handler_entropy/latest

Test location /workspace/coverage/default/19.alert_handler_entropy_stress.559945699
Short name T477
Test name
Test status
Simulation time 464937315 ps
CPU time 8.09 seconds
Started Jul 13 06:25:10 PM PDT 24
Finished Jul 13 06:25:19 PM PDT 24
Peak memory 249192 kb
Host smart-47729aec-a443-4a44-9598-8ea06d71cd81
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=559945699 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy_stress.559945699
Directory /workspace/19.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/19.alert_handler_esc_alert_accum.1475366869
Short name T40
Test name
Test status
Simulation time 661368342 ps
CPU time 14.33 seconds
Started Jul 13 06:25:07 PM PDT 24
Finished Jul 13 06:25:23 PM PDT 24
Peak memory 256744 kb
Host smart-e30af444-125a-46a8-8894-b6d079f211fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14753
66869 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_alert_accum.1475366869
Directory /workspace/19.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/19.alert_handler_esc_intr_timeout.3427833205
Short name T372
Test name
Test status
Simulation time 2203184757 ps
CPU time 61.19 seconds
Started Jul 13 06:25:12 PM PDT 24
Finished Jul 13 06:26:15 PM PDT 24
Peak memory 256648 kb
Host smart-39fbbebc-d928-4224-8c61-00a7b7afa057
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34278
33205 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_intr_timeout.3427833205
Directory /workspace/19.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_lpg.1063337314
Short name T681
Test name
Test status
Simulation time 17750095541 ps
CPU time 768.17 seconds
Started Jul 13 06:25:18 PM PDT 24
Finished Jul 13 06:38:08 PM PDT 24
Peak memory 273664 kb
Host smart-7d6a91b8-16bf-4e89-b384-5334f4ca08b6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1063337314 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg.1063337314
Directory /workspace/19.alert_handler_lpg/latest

Test location /workspace/coverage/default/19.alert_handler_lpg_stub_clk.2308160479
Short name T111
Test name
Test status
Simulation time 42039782175 ps
CPU time 2618 seconds
Started Jul 13 06:25:09 PM PDT 24
Finished Jul 13 07:08:49 PM PDT 24
Peak memory 289424 kb
Host smart-f9a73dfb-379e-4778-81be-f33165337108
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2308160479 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg_stub_clk.2308160479
Directory /workspace/19.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/19.alert_handler_ping_timeout.2348269825
Short name T288
Test name
Test status
Simulation time 7777154283 ps
CPU time 295.92 seconds
Started Jul 13 06:25:12 PM PDT 24
Finished Jul 13 06:30:10 PM PDT 24
Peak memory 249260 kb
Host smart-82d68600-51c7-4a14-ac92-e2943b071beb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348269825 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_ping_timeout.2348269825
Directory /workspace/19.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_random_alerts.3910054104
Short name T402
Test name
Test status
Simulation time 820595226 ps
CPU time 37.04 seconds
Started Jul 13 06:25:03 PM PDT 24
Finished Jul 13 06:25:41 PM PDT 24
Peak memory 256484 kb
Host smart-e3dcd720-0601-4f50-87a5-84d13f3bd976
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39100
54104 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_alerts.3910054104
Directory /workspace/19.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/19.alert_handler_random_classes.141370629
Short name T391
Test name
Test status
Simulation time 91862181 ps
CPU time 14.37 seconds
Started Jul 13 06:25:15 PM PDT 24
Finished Jul 13 06:25:31 PM PDT 24
Peak memory 248808 kb
Host smart-a7616f86-ac46-4b4d-9e50-cd38f471faf7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14137
0629 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_classes.141370629
Directory /workspace/19.alert_handler_random_classes/latest

Test location /workspace/coverage/default/19.alert_handler_sig_int_fail.191357314
Short name T321
Test name
Test status
Simulation time 737939245 ps
CPU time 52.66 seconds
Started Jul 13 06:24:59 PM PDT 24
Finished Jul 13 06:25:53 PM PDT 24
Peak memory 249176 kb
Host smart-c1a2253a-0311-4c3f-8411-a661d9ee0638
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19135
7314 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_sig_int_fail.191357314
Directory /workspace/19.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/19.alert_handler_smoke.2914154815
Short name T374
Test name
Test status
Simulation time 1225722659 ps
CPU time 43.55 seconds
Started Jul 13 06:25:09 PM PDT 24
Finished Jul 13 06:25:54 PM PDT 24
Peak memory 257424 kb
Host smart-e7951d38-55e8-43b4-ab28-f7862037f388
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29141
54815 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_smoke.2914154815
Directory /workspace/19.alert_handler_smoke/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all.1060467037
Short name T525
Test name
Test status
Simulation time 15305997965 ps
CPU time 1395.58 seconds
Started Jul 13 06:24:56 PM PDT 24
Finished Jul 13 06:48:12 PM PDT 24
Peak memory 290032 kb
Host smart-3186f5c1-7805-46b3-b8cd-1af65ec7eb5a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060467037 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_ha
ndler_stress_all.1060467037
Directory /workspace/19.alert_handler_stress_all/latest

Test location /workspace/coverage/default/2.alert_handler_alert_accum_saturation.2257445968
Short name T199
Test name
Test status
Simulation time 34708543 ps
CPU time 3.37 seconds
Started Jul 13 06:24:37 PM PDT 24
Finished Jul 13 06:24:45 PM PDT 24
Peak memory 249556 kb
Host smart-caccee5a-bb60-49a5-8a1f-a68bd827d867
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2257445968 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_alert_accum_saturation.2257445968
Directory /workspace/2.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/2.alert_handler_entropy.2954158227
Short name T594
Test name
Test status
Simulation time 35348857020 ps
CPU time 2139.12 seconds
Started Jul 13 06:24:35 PM PDT 24
Finished Jul 13 07:00:15 PM PDT 24
Peak memory 290284 kb
Host smart-ddc7242c-2b50-43e5-b4a0-9d7fadf54a2b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954158227 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy.2954158227
Directory /workspace/2.alert_handler_entropy/latest

Test location /workspace/coverage/default/2.alert_handler_entropy_stress.394951260
Short name T14
Test name
Test status
Simulation time 451650319 ps
CPU time 20.86 seconds
Started Jul 13 06:24:40 PM PDT 24
Finished Jul 13 06:25:03 PM PDT 24
Peak memory 249212 kb
Host smart-5f16f3b6-57ad-4a9d-8a68-be1aa471f531
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=394951260 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy_stress.394951260
Directory /workspace/2.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/2.alert_handler_esc_intr_timeout.2666364532
Short name T79
Test name
Test status
Simulation time 5284184305 ps
CPU time 61.06 seconds
Started Jul 13 06:24:34 PM PDT 24
Finished Jul 13 06:25:36 PM PDT 24
Peak memory 257000 kb
Host smart-220503d8-f213-438b-8782-36a0b10b6cb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26663
64532 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_intr_timeout.2666364532
Directory /workspace/2.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_lpg_stub_clk.1552313957
Short name T258
Test name
Test status
Simulation time 169552753658 ps
CPU time 2147.37 seconds
Started Jul 13 06:24:38 PM PDT 24
Finished Jul 13 07:00:28 PM PDT 24
Peak memory 285080 kb
Host smart-57b26a34-2381-4cdf-8b19-2b9d60860da6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552313957 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg_stub_clk.1552313957
Directory /workspace/2.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/2.alert_handler_ping_timeout.1282772286
Short name T690
Test name
Test status
Simulation time 17596369340 ps
CPU time 655.79 seconds
Started Jul 13 06:24:40 PM PDT 24
Finished Jul 13 06:35:37 PM PDT 24
Peak memory 249236 kb
Host smart-9409a226-8c00-4b3b-bc50-3cd3d10e08a5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282772286 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_ping_timeout.1282772286
Directory /workspace/2.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_random_alerts.2125949890
Short name T544
Test name
Test status
Simulation time 1907223234 ps
CPU time 26.01 seconds
Started Jul 13 06:24:27 PM PDT 24
Finished Jul 13 06:24:55 PM PDT 24
Peak memory 257112 kb
Host smart-ce7e00a3-a53f-426e-82fc-31f826940de6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21259
49890 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_alerts.2125949890
Directory /workspace/2.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/2.alert_handler_random_classes.2097302626
Short name T29
Test name
Test status
Simulation time 494873882 ps
CPU time 38.2 seconds
Started Jul 13 06:24:35 PM PDT 24
Finished Jul 13 06:25:14 PM PDT 24
Peak memory 249312 kb
Host smart-c70540ae-31a5-49af-8624-af814e21ee91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20973
02626 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_classes.2097302626
Directory /workspace/2.alert_handler_random_classes/latest

Test location /workspace/coverage/default/2.alert_handler_sec_cm.706564229
Short name T11
Test name
Test status
Simulation time 490778981 ps
CPU time 25.75 seconds
Started Jul 13 06:24:26 PM PDT 24
Finished Jul 13 06:24:54 PM PDT 24
Peak memory 270612 kb
Host smart-c5c83d07-b8ae-4d1c-a306-7076a9c18cdc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=706564229 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sec_cm.706564229
Directory /workspace/2.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/2.alert_handler_sig_int_fail.1775192489
Short name T319
Test name
Test status
Simulation time 124298961 ps
CPU time 7.86 seconds
Started Jul 13 06:24:36 PM PDT 24
Finished Jul 13 06:24:45 PM PDT 24
Peak memory 248732 kb
Host smart-64e5ae81-28a9-421a-a94b-e94d455c7ab2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17751
92489 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sig_int_fail.1775192489
Directory /workspace/2.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/2.alert_handler_smoke.1848266963
Short name T571
Test name
Test status
Simulation time 294339198 ps
CPU time 20.01 seconds
Started Jul 13 06:24:47 PM PDT 24
Finished Jul 13 06:25:09 PM PDT 24
Peak memory 257276 kb
Host smart-afd59fce-2971-4bb6-ace8-1f1e3abef03a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18482
66963 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_smoke.1848266963
Directory /workspace/2.alert_handler_smoke/latest

Test location /workspace/coverage/default/20.alert_handler_entropy.25789629
Short name T687
Test name
Test status
Simulation time 17895313643 ps
CPU time 1529.29 seconds
Started Jul 13 06:25:12 PM PDT 24
Finished Jul 13 06:50:43 PM PDT 24
Peak memory 289540 kb
Host smart-6cbe29a7-1ffb-45fc-aa03-36c215b9f20c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25789629 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_entropy.25789629
Directory /workspace/20.alert_handler_entropy/latest

Test location /workspace/coverage/default/20.alert_handler_esc_alert_accum.3174586701
Short name T406
Test name
Test status
Simulation time 3667400998 ps
CPU time 170.24 seconds
Started Jul 13 06:25:11 PM PDT 24
Finished Jul 13 06:28:03 PM PDT 24
Peak memory 257524 kb
Host smart-b701cb44-523b-4693-b6a1-b44a3a84e1c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31745
86701 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_alert_accum.3174586701
Directory /workspace/20.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/20.alert_handler_esc_intr_timeout.2242850330
Short name T375
Test name
Test status
Simulation time 44238747 ps
CPU time 5.02 seconds
Started Jul 13 06:25:15 PM PDT 24
Finished Jul 13 06:25:22 PM PDT 24
Peak memory 241012 kb
Host smart-4308df90-bc73-4cd9-a24d-d04147d618f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22428
50330 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_intr_timeout.2242850330
Directory /workspace/20.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_lpg.3018482178
Short name T274
Test name
Test status
Simulation time 74549158109 ps
CPU time 1084.35 seconds
Started Jul 13 06:25:12 PM PDT 24
Finished Jul 13 06:43:18 PM PDT 24
Peak memory 273960 kb
Host smart-f5c2c16e-5c4b-45b0-84c7-660f8a7bace9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3018482178 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg.3018482178
Directory /workspace/20.alert_handler_lpg/latest

Test location /workspace/coverage/default/20.alert_handler_lpg_stub_clk.3525028812
Short name T364
Test name
Test status
Simulation time 556218208258 ps
CPU time 2376.18 seconds
Started Jul 13 06:25:02 PM PDT 24
Finished Jul 13 07:04:40 PM PDT 24
Peak memory 289620 kb
Host smart-ee106451-77b2-4f2a-84be-81ad531af7a1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525028812 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg_stub_clk.3525028812
Directory /workspace/20.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/20.alert_handler_ping_timeout.694561550
Short name T247
Test name
Test status
Simulation time 22069675665 ps
CPU time 260.92 seconds
Started Jul 13 06:25:05 PM PDT 24
Finished Jul 13 06:29:27 PM PDT 24
Peak memory 249232 kb
Host smart-043750e0-e9ce-46ed-84ec-437da27e16f7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694561550 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_ping_timeout.694561550
Directory /workspace/20.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_random_alerts.2965663147
Short name T219
Test name
Test status
Simulation time 186271509 ps
CPU time 17.43 seconds
Started Jul 13 06:24:57 PM PDT 24
Finished Jul 13 06:25:16 PM PDT 24
Peak memory 249284 kb
Host smart-113932e4-8aaa-419f-a661-cd9d1c6f0ff8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29656
63147 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_alerts.2965663147
Directory /workspace/20.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/20.alert_handler_random_classes.3773827020
Short name T643
Test name
Test status
Simulation time 338099899 ps
CPU time 6.7 seconds
Started Jul 13 06:24:55 PM PDT 24
Finished Jul 13 06:25:02 PM PDT 24
Peak memory 241096 kb
Host smart-2130fd81-700e-461e-b6e7-70ee3a1a6426
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37738
27020 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_classes.3773827020
Directory /workspace/20.alert_handler_random_classes/latest

Test location /workspace/coverage/default/20.alert_handler_sig_int_fail.3041084037
Short name T435
Test name
Test status
Simulation time 1679363404 ps
CPU time 26.64 seconds
Started Jul 13 06:25:05 PM PDT 24
Finished Jul 13 06:25:32 PM PDT 24
Peak memory 256792 kb
Host smart-5257098f-a7e9-48f9-904d-3f46529951e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30410
84037 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_sig_int_fail.3041084037
Directory /workspace/20.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/20.alert_handler_smoke.1609889719
Short name T483
Test name
Test status
Simulation time 425498046 ps
CPU time 26.67 seconds
Started Jul 13 06:25:08 PM PDT 24
Finished Jul 13 06:25:36 PM PDT 24
Peak memory 249236 kb
Host smart-f44041c9-edef-4a20-9b2c-7b5a49b44d56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16098
89719 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_smoke.1609889719
Directory /workspace/20.alert_handler_smoke/latest

Test location /workspace/coverage/default/21.alert_handler_esc_alert_accum.4082335203
Short name T531
Test name
Test status
Simulation time 21107927589 ps
CPU time 347.11 seconds
Started Jul 13 06:25:14 PM PDT 24
Finished Jul 13 06:31:03 PM PDT 24
Peak memory 257564 kb
Host smart-6ecd9824-4ca7-4c76-a2ca-9487b1fdd6f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40823
35203 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_alert_accum.4082335203
Directory /workspace/21.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/21.alert_handler_esc_intr_timeout.1573010913
Short name T368
Test name
Test status
Simulation time 237484905 ps
CPU time 11.79 seconds
Started Jul 13 06:25:16 PM PDT 24
Finished Jul 13 06:25:30 PM PDT 24
Peak memory 249212 kb
Host smart-af7d8427-d804-4836-b935-3755ede0cd01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15730
10913 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_intr_timeout.1573010913
Directory /workspace/21.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_lpg.1264621101
Short name T355
Test name
Test status
Simulation time 29895439554 ps
CPU time 686.98 seconds
Started Jul 13 06:25:10 PM PDT 24
Finished Jul 13 06:36:39 PM PDT 24
Peak memory 273272 kb
Host smart-308cc370-cd1a-47e1-ae83-6bab8faa2000
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264621101 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg.1264621101
Directory /workspace/21.alert_handler_lpg/latest

Test location /workspace/coverage/default/21.alert_handler_lpg_stub_clk.4237213479
Short name T618
Test name
Test status
Simulation time 59261668155 ps
CPU time 1480.69 seconds
Started Jul 13 06:25:14 PM PDT 24
Finished Jul 13 06:49:57 PM PDT 24
Peak memory 273732 kb
Host smart-35bf2777-4b4e-4855-b595-40a4465b0fb0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237213479 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg_stub_clk.4237213479
Directory /workspace/21.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/21.alert_handler_random_alerts.1685114564
Short name T418
Test name
Test status
Simulation time 4898107833 ps
CPU time 32.76 seconds
Started Jul 13 06:25:04 PM PDT 24
Finished Jul 13 06:25:37 PM PDT 24
Peak memory 256772 kb
Host smart-42522697-ca9e-4ba2-bdd2-45664f6ea1c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16851
14564 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_alerts.1685114564
Directory /workspace/21.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/21.alert_handler_random_classes.90649145
Short name T612
Test name
Test status
Simulation time 178693949 ps
CPU time 12.38 seconds
Started Jul 13 06:25:05 PM PDT 24
Finished Jul 13 06:25:18 PM PDT 24
Peak memory 248728 kb
Host smart-2afc04f6-9f15-43a6-b2be-ec356522cbbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90649
145 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_classes.90649145
Directory /workspace/21.alert_handler_random_classes/latest

Test location /workspace/coverage/default/21.alert_handler_sig_int_fail.18235959
Short name T574
Test name
Test status
Simulation time 5618431507 ps
CPU time 49.96 seconds
Started Jul 13 06:24:59 PM PDT 24
Finished Jul 13 06:25:49 PM PDT 24
Peak memory 249272 kb
Host smart-d50459b5-ca9e-4479-b1c5-184cf60a18aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18235
959 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_sig_int_fail.18235959
Directory /workspace/21.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all.2716387209
Short name T88
Test name
Test status
Simulation time 282984545266 ps
CPU time 1983.8 seconds
Started Jul 13 06:25:03 PM PDT 24
Finished Jul 13 06:58:08 PM PDT 24
Peak memory 306396 kb
Host smart-f40f38b0-9a90-4b54-b864-64b08be4fcba
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716387209 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_ha
ndler_stress_all.2716387209
Directory /workspace/21.alert_handler_stress_all/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all_with_rand_reset.1714112015
Short name T698
Test name
Test status
Simulation time 83676517144 ps
CPU time 7716.78 seconds
Started Jul 13 06:25:10 PM PDT 24
Finished Jul 13 08:33:50 PM PDT 24
Peak memory 372116 kb
Host smart-61788ca5-2bbb-4148-b8b6-2e83d7b872ef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714112015 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.alert_handler_stress_all_with_rand_reset.1714112015
Directory /workspace/21.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.alert_handler_entropy.785849639
Short name T23
Test name
Test status
Simulation time 24668828701 ps
CPU time 1478.99 seconds
Started Jul 13 06:25:12 PM PDT 24
Finished Jul 13 06:49:53 PM PDT 24
Peak memory 273844 kb
Host smart-a05c92ea-03bf-4fa1-adb6-f70d948fdcea
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785849639 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_entropy.785849639
Directory /workspace/22.alert_handler_entropy/latest

Test location /workspace/coverage/default/22.alert_handler_esc_alert_accum.4237820609
Short name T371
Test name
Test status
Simulation time 444865939 ps
CPU time 15.15 seconds
Started Jul 13 06:25:15 PM PDT 24
Finished Jul 13 06:25:32 PM PDT 24
Peak memory 249020 kb
Host smart-420dbfae-1aa2-4bbf-8ce3-0f66b74d27de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42378
20609 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_alert_accum.4237820609
Directory /workspace/22.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/22.alert_handler_esc_intr_timeout.2848281994
Short name T431
Test name
Test status
Simulation time 378133889 ps
CPU time 21.36 seconds
Started Jul 13 06:25:10 PM PDT 24
Finished Jul 13 06:25:33 PM PDT 24
Peak memory 248756 kb
Host smart-8db682f2-00fb-4526-9ea8-38b854f22697
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28482
81994 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_intr_timeout.2848281994
Directory /workspace/22.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_lpg.3140555505
Short name T339
Test name
Test status
Simulation time 72525337894 ps
CPU time 2648.95 seconds
Started Jul 13 06:25:07 PM PDT 24
Finished Jul 13 07:09:18 PM PDT 24
Peak memory 282144 kb
Host smart-d3e0e68c-ec41-4780-9106-b11d5dc60895
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3140555505 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg.3140555505
Directory /workspace/22.alert_handler_lpg/latest

Test location /workspace/coverage/default/22.alert_handler_lpg_stub_clk.2920476773
Short name T260
Test name
Test status
Simulation time 16331708921 ps
CPU time 1229.6 seconds
Started Jul 13 06:25:06 PM PDT 24
Finished Jul 13 06:45:36 PM PDT 24
Peak memory 273720 kb
Host smart-b8046f85-cc1a-4849-b57e-041fb1dd6583
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920476773 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg_stub_clk.2920476773
Directory /workspace/22.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/22.alert_handler_ping_timeout.3450409450
Short name T606
Test name
Test status
Simulation time 71541513630 ps
CPU time 179.58 seconds
Started Jul 13 06:25:10 PM PDT 24
Finished Jul 13 06:28:11 PM PDT 24
Peak memory 248904 kb
Host smart-9bedadf3-b670-4f03-9047-053244a93629
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450409450 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_ping_timeout.3450409450
Directory /workspace/22.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_random_alerts.2535502375
Short name T667
Test name
Test status
Simulation time 1587023081 ps
CPU time 47.59 seconds
Started Jul 13 06:25:15 PM PDT 24
Finished Jul 13 06:26:04 PM PDT 24
Peak memory 249212 kb
Host smart-4488d7dd-fc59-4854-b959-5e5fce4cb3a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25355
02375 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_alerts.2535502375
Directory /workspace/22.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/22.alert_handler_random_classes.1600965937
Short name T638
Test name
Test status
Simulation time 306448026 ps
CPU time 29.81 seconds
Started Jul 13 06:25:14 PM PDT 24
Finished Jul 13 06:25:46 PM PDT 24
Peak memory 248684 kb
Host smart-4ecf55e8-0514-4d0c-ba16-3af509f770ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16009
65937 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_classes.1600965937
Directory /workspace/22.alert_handler_random_classes/latest

Test location /workspace/coverage/default/22.alert_handler_sig_int_fail.3410466147
Short name T540
Test name
Test status
Simulation time 264123486 ps
CPU time 30.81 seconds
Started Jul 13 06:25:09 PM PDT 24
Finished Jul 13 06:25:41 PM PDT 24
Peak memory 257144 kb
Host smart-91cf4b2a-57fb-4e21-8715-c405708ef9e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34104
66147 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_sig_int_fail.3410466147
Directory /workspace/22.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/22.alert_handler_smoke.3065560785
Short name T550
Test name
Test status
Simulation time 718930351 ps
CPU time 47.33 seconds
Started Jul 13 06:25:11 PM PDT 24
Finished Jul 13 06:26:00 PM PDT 24
Peak memory 257356 kb
Host smart-14affb28-ad09-44d4-8ee7-e4891697067f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30655
60785 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_smoke.3065560785
Directory /workspace/22.alert_handler_smoke/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all.2621230448
Short name T107
Test name
Test status
Simulation time 12931854375 ps
CPU time 149.88 seconds
Started Jul 13 06:25:09 PM PDT 24
Finished Jul 13 06:27:40 PM PDT 24
Peak memory 254684 kb
Host smart-dae66217-cd96-4d18-b7a1-92fb20022f29
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621230448 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_ha
ndler_stress_all.2621230448
Directory /workspace/22.alert_handler_stress_all/latest

Test location /workspace/coverage/default/23.alert_handler_entropy.840175560
Short name T684
Test name
Test status
Simulation time 45294727329 ps
CPU time 2545.43 seconds
Started Jul 13 06:25:12 PM PDT 24
Finished Jul 13 07:07:40 PM PDT 24
Peak memory 281984 kb
Host smart-7878a484-a173-4a2a-917e-c0fd72cc0b19
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840175560 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_entropy.840175560
Directory /workspace/23.alert_handler_entropy/latest

Test location /workspace/coverage/default/23.alert_handler_esc_alert_accum.591126740
Short name T692
Test name
Test status
Simulation time 1132730978 ps
CPU time 65.49 seconds
Started Jul 13 06:25:05 PM PDT 24
Finished Jul 13 06:26:11 PM PDT 24
Peak memory 250328 kb
Host smart-9c59f934-8a6b-4492-942b-80a21e1daead
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59112
6740 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_alert_accum.591126740
Directory /workspace/23.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/23.alert_handler_esc_intr_timeout.1761817550
Short name T404
Test name
Test status
Simulation time 737834738 ps
CPU time 48.1 seconds
Started Jul 13 06:25:10 PM PDT 24
Finished Jul 13 06:25:59 PM PDT 24
Peak memory 256880 kb
Host smart-879ebd0a-c140-4c5f-8161-0b46b12921e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17618
17550 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_intr_timeout.1761817550
Directory /workspace/23.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_lpg.1865632185
Short name T335
Test name
Test status
Simulation time 153571005627 ps
CPU time 2606.12 seconds
Started Jul 13 06:25:18 PM PDT 24
Finished Jul 13 07:08:46 PM PDT 24
Peak memory 290176 kb
Host smart-3195fc5b-fc15-4dc8-8f0e-e947d9c720a2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865632185 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg.1865632185
Directory /workspace/23.alert_handler_lpg/latest

Test location /workspace/coverage/default/23.alert_handler_lpg_stub_clk.529412758
Short name T602
Test name
Test status
Simulation time 80923576443 ps
CPU time 2280.18 seconds
Started Jul 13 06:25:12 PM PDT 24
Finished Jul 13 07:03:14 PM PDT 24
Peak memory 273980 kb
Host smart-148395ab-8f3a-4800-99dc-a0fe3caafca1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=529412758 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg_stub_clk.529412758
Directory /workspace/23.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/23.alert_handler_ping_timeout.1517364872
Short name T39
Test name
Test status
Simulation time 9732541898 ps
CPU time 105.98 seconds
Started Jul 13 06:25:06 PM PDT 24
Finished Jul 13 06:26:53 PM PDT 24
Peak memory 248220 kb
Host smart-d7abe51c-94f9-40fc-be25-a7c43f5195b7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517364872 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_ping_timeout.1517364872
Directory /workspace/23.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_random_alerts.268849276
Short name T620
Test name
Test status
Simulation time 2721884842 ps
CPU time 42.38 seconds
Started Jul 13 06:25:08 PM PDT 24
Finished Jul 13 06:25:51 PM PDT 24
Peak memory 256676 kb
Host smart-721dac88-2385-4c3e-bb20-a9942d9eab40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26884
9276 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_alerts.268849276
Directory /workspace/23.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/23.alert_handler_random_classes.3809802902
Short name T387
Test name
Test status
Simulation time 256607324 ps
CPU time 13.49 seconds
Started Jul 13 06:25:01 PM PDT 24
Finished Jul 13 06:25:15 PM PDT 24
Peak memory 254784 kb
Host smart-5ec0b3c7-e5c0-458b-af3c-afa077e37510
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38098
02902 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_classes.3809802902
Directory /workspace/23.alert_handler_random_classes/latest

Test location /workspace/coverage/default/23.alert_handler_sig_int_fail.3518279327
Short name T75
Test name
Test status
Simulation time 2331720992 ps
CPU time 51.57 seconds
Started Jul 13 06:25:15 PM PDT 24
Finished Jul 13 06:26:09 PM PDT 24
Peak memory 257124 kb
Host smart-84c6c014-7c8f-4ab8-a327-5807ee8784ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35182
79327 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_sig_int_fail.3518279327
Directory /workspace/23.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/23.alert_handler_smoke.294479126
Short name T383
Test name
Test status
Simulation time 786113121 ps
CPU time 52.5 seconds
Started Jul 13 06:25:08 PM PDT 24
Finished Jul 13 06:26:02 PM PDT 24
Peak memory 249252 kb
Host smart-bcd5ab24-2cb1-4fa2-b7ed-46a09e7954e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29447
9126 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_smoke.294479126
Directory /workspace/23.alert_handler_smoke/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all.2404060259
Short name T589
Test name
Test status
Simulation time 184150853492 ps
CPU time 3577.72 seconds
Started Jul 13 06:25:16 PM PDT 24
Finished Jul 13 07:24:56 PM PDT 24
Peak memory 298564 kb
Host smart-5c349788-3658-48a4-83a2-078ee10a22be
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404060259 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_ha
ndler_stress_all.2404060259
Directory /workspace/23.alert_handler_stress_all/latest

Test location /workspace/coverage/default/24.alert_handler_esc_alert_accum.3970689580
Short name T392
Test name
Test status
Simulation time 8642734373 ps
CPU time 128.81 seconds
Started Jul 13 06:25:14 PM PDT 24
Finished Jul 13 06:27:25 PM PDT 24
Peak memory 257604 kb
Host smart-b1bbd0f7-de5c-41c4-9d56-0911f854cf7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39706
89580 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_alert_accum.3970689580
Directory /workspace/24.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/24.alert_handler_esc_intr_timeout.3633203262
Short name T232
Test name
Test status
Simulation time 719382104 ps
CPU time 13.68 seconds
Started Jul 13 06:25:22 PM PDT 24
Finished Jul 13 06:25:36 PM PDT 24
Peak memory 248724 kb
Host smart-9da0e807-499b-4a05-8e70-446fa8865747
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36332
03262 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_intr_timeout.3633203262
Directory /workspace/24.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_lpg_stub_clk.3726043409
Short name T190
Test name
Test status
Simulation time 101299416939 ps
CPU time 1562.01 seconds
Started Jul 13 06:25:26 PM PDT 24
Finished Jul 13 06:51:29 PM PDT 24
Peak memory 283332 kb
Host smart-1002558f-2c64-445c-bbec-5d7b14120272
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726043409 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg_stub_clk.3726043409
Directory /workspace/24.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/24.alert_handler_ping_timeout.3738535703
Short name T9
Test name
Test status
Simulation time 9168513881 ps
CPU time 86.22 seconds
Started Jul 13 06:25:24 PM PDT 24
Finished Jul 13 06:26:51 PM PDT 24
Peak memory 249260 kb
Host smart-53f1d1f2-1fd4-4283-878f-1f9c304b26cc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738535703 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_ping_timeout.3738535703
Directory /workspace/24.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_random_alerts.2547306940
Short name T453
Test name
Test status
Simulation time 428931686 ps
CPU time 24.66 seconds
Started Jul 13 06:25:17 PM PDT 24
Finished Jul 13 06:25:43 PM PDT 24
Peak memory 256916 kb
Host smart-73f00eeb-2a67-4dee-9aca-001ebb9fede0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25473
06940 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_alerts.2547306940
Directory /workspace/24.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/24.alert_handler_random_classes.2803690766
Short name T87
Test name
Test status
Simulation time 536733977 ps
CPU time 21.52 seconds
Started Jul 13 06:25:05 PM PDT 24
Finished Jul 13 06:25:28 PM PDT 24
Peak memory 255820 kb
Host smart-b9e3b1f0-1859-4f78-a961-57323e6f2304
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28036
90766 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_classes.2803690766
Directory /workspace/24.alert_handler_random_classes/latest

Test location /workspace/coverage/default/24.alert_handler_sig_int_fail.4214607495
Short name T81
Test name
Test status
Simulation time 477259207 ps
CPU time 18.6 seconds
Started Jul 13 06:25:07 PM PDT 24
Finished Jul 13 06:25:26 PM PDT 24
Peak memory 249284 kb
Host smart-90b50958-96ae-45fd-b78c-f5a41db4edae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42146
07495 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_sig_int_fail.4214607495
Directory /workspace/24.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/24.alert_handler_smoke.4247084777
Short name T633
Test name
Test status
Simulation time 118976155 ps
CPU time 6.61 seconds
Started Jul 13 06:25:12 PM PDT 24
Finished Jul 13 06:25:21 PM PDT 24
Peak memory 254344 kb
Host smart-38e6df86-f4ff-4216-8616-e610e267447d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42470
84777 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_smoke.4247084777
Directory /workspace/24.alert_handler_smoke/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all.1987715768
Short name T497
Test name
Test status
Simulation time 34435303668 ps
CPU time 617.31 seconds
Started Jul 13 06:25:13 PM PDT 24
Finished Jul 13 06:35:32 PM PDT 24
Peak memory 268900 kb
Host smart-9046fbd1-cb3a-4147-9df7-074e53f84189
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987715768 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_ha
ndler_stress_all.1987715768
Directory /workspace/24.alert_handler_stress_all/latest

Test location /workspace/coverage/default/25.alert_handler_entropy.534340600
Short name T44
Test name
Test status
Simulation time 42282792907 ps
CPU time 1259.03 seconds
Started Jul 13 06:25:27 PM PDT 24
Finished Jul 13 06:46:26 PM PDT 24
Peak memory 289936 kb
Host smart-d927cd9c-62a0-464b-a377-71cdd31f8aa5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534340600 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_entropy.534340600
Directory /workspace/25.alert_handler_entropy/latest

Test location /workspace/coverage/default/25.alert_handler_esc_alert_accum.1070211206
Short name T223
Test name
Test status
Simulation time 8757908048 ps
CPU time 215.59 seconds
Started Jul 13 06:25:14 PM PDT 24
Finished Jul 13 06:28:51 PM PDT 24
Peak memory 252416 kb
Host smart-ad6bf2ce-2650-4ff8-81bf-a2d97792cbba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10702
11206 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_alert_accum.1070211206
Directory /workspace/25.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/25.alert_handler_esc_intr_timeout.4291939961
Short name T322
Test name
Test status
Simulation time 5888799312 ps
CPU time 53.06 seconds
Started Jul 13 06:25:11 PM PDT 24
Finished Jul 13 06:26:06 PM PDT 24
Peak memory 248936 kb
Host smart-37b4172a-6da7-496f-a90a-f165f80179a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42919
39961 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_intr_timeout.4291939961
Directory /workspace/25.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_lpg.1114796318
Short name T330
Test name
Test status
Simulation time 208414287605 ps
CPU time 1958.82 seconds
Started Jul 13 06:25:18 PM PDT 24
Finished Jul 13 06:57:59 PM PDT 24
Peak memory 273324 kb
Host smart-8dd56bcd-467c-410f-8482-9f549475ce7b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114796318 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg.1114796318
Directory /workspace/25.alert_handler_lpg/latest

Test location /workspace/coverage/default/25.alert_handler_lpg_stub_clk.19452424
Short name T489
Test name
Test status
Simulation time 170470155662 ps
CPU time 2419.7 seconds
Started Jul 13 06:25:14 PM PDT 24
Finished Jul 13 07:05:35 PM PDT 24
Peak memory 289828 kb
Host smart-420795cb-da01-4bff-bd54-055a44bb312a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19452424 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg_stub_clk.19452424
Directory /workspace/25.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/25.alert_handler_random_alerts.2611234954
Short name T376
Test name
Test status
Simulation time 4191940450 ps
CPU time 74.85 seconds
Started Jul 13 06:25:27 PM PDT 24
Finished Jul 13 06:26:42 PM PDT 24
Peak memory 257032 kb
Host smart-40649d4e-eb72-450d-aea6-0efda135224f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26112
34954 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_alerts.2611234954
Directory /workspace/25.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/25.alert_handler_random_classes.1886144195
Short name T93
Test name
Test status
Simulation time 162809978 ps
CPU time 12.08 seconds
Started Jul 13 06:25:12 PM PDT 24
Finished Jul 13 06:25:26 PM PDT 24
Peak memory 255060 kb
Host smart-72eb7ebc-acf5-4658-a5e6-218db10108c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18861
44195 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_classes.1886144195
Directory /workspace/25.alert_handler_random_classes/latest

Test location /workspace/coverage/default/25.alert_handler_sig_int_fail.868583911
Short name T660
Test name
Test status
Simulation time 147734667 ps
CPU time 5.84 seconds
Started Jul 13 06:25:13 PM PDT 24
Finished Jul 13 06:25:21 PM PDT 24
Peak memory 249216 kb
Host smart-98cd82bf-063c-457a-8919-1d890552aed8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86858
3911 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_sig_int_fail.868583911
Directory /workspace/25.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/25.alert_handler_smoke.1823611033
Short name T559
Test name
Test status
Simulation time 1087917477 ps
CPU time 27.3 seconds
Started Jul 13 06:25:13 PM PDT 24
Finished Jul 13 06:25:42 PM PDT 24
Peak memory 249276 kb
Host smart-09a3810f-cd15-45f8-a646-8e24223acfc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18236
11033 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_smoke.1823611033
Directory /workspace/25.alert_handler_smoke/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all.2921978182
Short name T500
Test name
Test status
Simulation time 148749618773 ps
CPU time 2123.51 seconds
Started Jul 13 06:25:09 PM PDT 24
Finished Jul 13 07:00:34 PM PDT 24
Peak memory 290024 kb
Host smart-3defc07e-b111-4260-8c1a-cf2bddceba74
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921978182 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_ha
ndler_stress_all.2921978182
Directory /workspace/25.alert_handler_stress_all/latest

Test location /workspace/coverage/default/26.alert_handler_entropy.3849024046
Short name T701
Test name
Test status
Simulation time 149700880839 ps
CPU time 2296.24 seconds
Started Jul 13 06:25:15 PM PDT 24
Finished Jul 13 07:03:33 PM PDT 24
Peak memory 282156 kb
Host smart-056bf37b-c357-4ec3-958a-2d048cb9f814
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849024046 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_entropy.3849024046
Directory /workspace/26.alert_handler_entropy/latest

Test location /workspace/coverage/default/26.alert_handler_esc_alert_accum.3495688508
Short name T545
Test name
Test status
Simulation time 5749091799 ps
CPU time 140.14 seconds
Started Jul 13 06:25:15 PM PDT 24
Finished Jul 13 06:27:37 PM PDT 24
Peak memory 257540 kb
Host smart-60b00e09-0b83-4d21-b107-35cef5086d88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34956
88508 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_alert_accum.3495688508
Directory /workspace/26.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/26.alert_handler_esc_intr_timeout.555548396
Short name T657
Test name
Test status
Simulation time 3505717497 ps
CPU time 51.71 seconds
Started Jul 13 06:25:23 PM PDT 24
Finished Jul 13 06:26:16 PM PDT 24
Peak memory 257056 kb
Host smart-f065fffc-0eda-49cf-a730-14ea15e10ba4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55554
8396 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_intr_timeout.555548396
Directory /workspace/26.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_lpg.303562657
Short name T13
Test name
Test status
Simulation time 15978516797 ps
CPU time 1099.74 seconds
Started Jul 13 06:25:16 PM PDT 24
Finished Jul 13 06:43:38 PM PDT 24
Peak memory 273212 kb
Host smart-d098cd8c-aab0-4a6b-bf4c-94f8cbff539e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303562657 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg.303562657
Directory /workspace/26.alert_handler_lpg/latest

Test location /workspace/coverage/default/26.alert_handler_lpg_stub_clk.1604649553
Short name T101
Test name
Test status
Simulation time 31428434778 ps
CPU time 1970.84 seconds
Started Jul 13 06:25:13 PM PDT 24
Finished Jul 13 06:58:06 PM PDT 24
Peak memory 285308 kb
Host smart-aea73cbc-c4df-409f-95d1-27aa424109fb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604649553 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg_stub_clk.1604649553
Directory /workspace/26.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/26.alert_handler_ping_timeout.2473112467
Short name T300
Test name
Test status
Simulation time 3864914676 ps
CPU time 153.06 seconds
Started Jul 13 06:25:19 PM PDT 24
Finished Jul 13 06:27:53 PM PDT 24
Peak memory 255744 kb
Host smart-b31fb2e4-5fb4-42e4-a196-4a1c6c702310
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473112467 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_ping_timeout.2473112467
Directory /workspace/26.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_random_alerts.2837847008
Short name T524
Test name
Test status
Simulation time 196630738 ps
CPU time 6.98 seconds
Started Jul 13 06:25:12 PM PDT 24
Finished Jul 13 06:25:20 PM PDT 24
Peak memory 251572 kb
Host smart-6e9e7cc5-beeb-4ce1-aa47-e540c9dd2aba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28378
47008 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_alerts.2837847008
Directory /workspace/26.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/26.alert_handler_random_classes.2701695855
Short name T445
Test name
Test status
Simulation time 1416438823 ps
CPU time 47.17 seconds
Started Jul 13 06:25:02 PM PDT 24
Finished Jul 13 06:25:50 PM PDT 24
Peak memory 248864 kb
Host smart-fa948bd2-bf78-4a2d-b7e2-0bc69b5f41a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27016
95855 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_classes.2701695855
Directory /workspace/26.alert_handler_random_classes/latest

Test location /workspace/coverage/default/26.alert_handler_sig_int_fail.984513851
Short name T678
Test name
Test status
Simulation time 60909660 ps
CPU time 9.2 seconds
Started Jul 13 06:25:06 PM PDT 24
Finished Jul 13 06:25:16 PM PDT 24
Peak memory 249304 kb
Host smart-78c49215-2b45-485b-b9ec-aa1d756593da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98451
3851 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_sig_int_fail.984513851
Directory /workspace/26.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/26.alert_handler_smoke.4209034039
Short name T622
Test name
Test status
Simulation time 1150115568 ps
CPU time 69.5 seconds
Started Jul 13 06:25:34 PM PDT 24
Finished Jul 13 06:26:45 PM PDT 24
Peak memory 257364 kb
Host smart-c2973efa-b5ec-4904-a53a-db80d7223ee8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42090
34039 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_smoke.4209034039
Directory /workspace/26.alert_handler_smoke/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all.627292045
Short name T572
Test name
Test status
Simulation time 47014415569 ps
CPU time 994.29 seconds
Started Jul 13 06:25:07 PM PDT 24
Finished Jul 13 06:41:42 PM PDT 24
Peak memory 272060 kb
Host smart-867850ed-e81b-4afc-b394-615d7d485edf
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627292045 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_han
dler_stress_all.627292045
Directory /workspace/26.alert_handler_stress_all/latest

Test location /workspace/coverage/default/27.alert_handler_entropy.924223394
Short name T534
Test name
Test status
Simulation time 177637536361 ps
CPU time 2747.71 seconds
Started Jul 13 06:25:18 PM PDT 24
Finished Jul 13 07:11:08 PM PDT 24
Peak memory 290180 kb
Host smart-0807f857-4085-4abe-8354-730e3884184e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=924223394 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_entropy.924223394
Directory /workspace/27.alert_handler_entropy/latest

Test location /workspace/coverage/default/27.alert_handler_esc_alert_accum.3825302602
Short name T650
Test name
Test status
Simulation time 8038120445 ps
CPU time 241.59 seconds
Started Jul 13 06:25:02 PM PDT 24
Finished Jul 13 06:29:05 PM PDT 24
Peak memory 257588 kb
Host smart-1c4b8952-ebbe-4c6e-8993-a87c54d17193
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38253
02602 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_alert_accum.3825302602
Directory /workspace/27.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/27.alert_handler_esc_intr_timeout.106525811
Short name T74
Test name
Test status
Simulation time 690296338 ps
CPU time 22 seconds
Started Jul 13 06:25:15 PM PDT 24
Finished Jul 13 06:25:39 PM PDT 24
Peak memory 256984 kb
Host smart-923de390-6438-49ec-9806-1ca7c8cabe61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10652
5811 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_intr_timeout.106525811
Directory /workspace/27.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_lpg.2949933119
Short name T697
Test name
Test status
Simulation time 121412258656 ps
CPU time 1605.78 seconds
Started Jul 13 06:25:32 PM PDT 24
Finished Jul 13 06:52:19 PM PDT 24
Peak memory 273852 kb
Host smart-52ac7729-a56b-4f86-ba70-7f73753eab5b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949933119 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg.2949933119
Directory /workspace/27.alert_handler_lpg/latest

Test location /workspace/coverage/default/27.alert_handler_lpg_stub_clk.4078221631
Short name T16
Test name
Test status
Simulation time 19993655412 ps
CPU time 790.98 seconds
Started Jul 13 06:25:08 PM PDT 24
Finished Jul 13 06:38:20 PM PDT 24
Peak memory 273940 kb
Host smart-1f1040b1-52d8-47f3-b109-24bd921821d5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078221631 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg_stub_clk.4078221631
Directory /workspace/27.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/27.alert_handler_ping_timeout.1433501710
Short name T591
Test name
Test status
Simulation time 10368741572 ps
CPU time 172.19 seconds
Started Jul 13 06:25:07 PM PDT 24
Finished Jul 13 06:28:00 PM PDT 24
Peak memory 249224 kb
Host smart-e059f0db-2699-4f83-92eb-667bbfee4b5a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433501710 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_ping_timeout.1433501710
Directory /workspace/27.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_random_alerts.2652224412
Short name T480
Test name
Test status
Simulation time 601441915 ps
CPU time 41.96 seconds
Started Jul 13 06:25:14 PM PDT 24
Finished Jul 13 06:25:58 PM PDT 24
Peak memory 256636 kb
Host smart-adeba340-2953-4e40-8b36-d91c94f598a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26522
24412 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_alerts.2652224412
Directory /workspace/27.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/27.alert_handler_random_classes.1350961477
Short name T30
Test name
Test status
Simulation time 1053185835 ps
CPU time 7.24 seconds
Started Jul 13 06:25:22 PM PDT 24
Finished Jul 13 06:25:30 PM PDT 24
Peak memory 251720 kb
Host smart-5c67ead9-1e9c-4c51-8614-c30b31bfe18c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13509
61477 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_classes.1350961477
Directory /workspace/27.alert_handler_random_classes/latest

Test location /workspace/coverage/default/27.alert_handler_sig_int_fail.3403604390
Short name T307
Test name
Test status
Simulation time 323711912 ps
CPU time 21.9 seconds
Started Jul 13 06:25:11 PM PDT 24
Finished Jul 13 06:25:34 PM PDT 24
Peak memory 249272 kb
Host smart-ec05e6fe-a316-49ff-ace6-df382c188d74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34036
04390 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_sig_int_fail.3403604390
Directory /workspace/27.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/27.alert_handler_smoke.2595768300
Short name T217
Test name
Test status
Simulation time 10180966148 ps
CPU time 47.56 seconds
Started Jul 13 06:25:11 PM PDT 24
Finished Jul 13 06:26:00 PM PDT 24
Peak memory 249780 kb
Host smart-70f20eee-ff85-47d8-9b88-bf6f02d7bc5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25957
68300 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_smoke.2595768300
Directory /workspace/27.alert_handler_smoke/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all.1127845129
Short name T644
Test name
Test status
Simulation time 38999577544 ps
CPU time 2425.26 seconds
Started Jul 13 06:25:18 PM PDT 24
Finished Jul 13 07:05:45 PM PDT 24
Peak memory 290120 kb
Host smart-f429ac6c-4a14-4e7e-963d-ca1bcf8a0f5a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127845129 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_ha
ndler_stress_all.1127845129
Directory /workspace/27.alert_handler_stress_all/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all_with_rand_reset.1552779590
Short name T176
Test name
Test status
Simulation time 12447566428 ps
CPU time 1255.66 seconds
Started Jul 13 06:25:31 PM PDT 24
Finished Jul 13 06:46:28 PM PDT 24
Peak memory 289284 kb
Host smart-8815c63c-0b3f-4ad3-b1f5-1ffa617b4f27
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552779590 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.alert_handler_stress_all_with_rand_reset.1552779590
Directory /workspace/27.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.alert_handler_entropy.1462626132
Short name T520
Test name
Test status
Simulation time 23029168320 ps
CPU time 1393.68 seconds
Started Jul 13 06:25:14 PM PDT 24
Finished Jul 13 06:48:29 PM PDT 24
Peak memory 269864 kb
Host smart-c864e20a-a337-4d46-b0a3-7b0818931d93
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462626132 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_entropy.1462626132
Directory /workspace/28.alert_handler_entropy/latest

Test location /workspace/coverage/default/28.alert_handler_esc_alert_accum.1418723913
Short name T61
Test name
Test status
Simulation time 3689799611 ps
CPU time 171.13 seconds
Started Jul 13 06:25:32 PM PDT 24
Finished Jul 13 06:28:24 PM PDT 24
Peak memory 257588 kb
Host smart-d780b684-ae18-4d3e-80a4-d564c4504dd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14187
23913 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_alert_accum.1418723913
Directory /workspace/28.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/28.alert_handler_esc_intr_timeout.2333319084
Short name T373
Test name
Test status
Simulation time 128035073 ps
CPU time 5.91 seconds
Started Jul 13 06:25:23 PM PDT 24
Finished Jul 13 06:25:29 PM PDT 24
Peak memory 249152 kb
Host smart-725e0141-8c05-4df4-9e9b-07b70f42119f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23333
19084 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_intr_timeout.2333319084
Directory /workspace/28.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_lpg.367384108
Short name T296
Test name
Test status
Simulation time 56005220835 ps
CPU time 2289.09 seconds
Started Jul 13 06:25:17 PM PDT 24
Finished Jul 13 07:03:28 PM PDT 24
Peak memory 290200 kb
Host smart-0e9ec437-9e8c-4c21-a516-224e744e2b74
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367384108 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg.367384108
Directory /workspace/28.alert_handler_lpg/latest

Test location /workspace/coverage/default/28.alert_handler_lpg_stub_clk.761902379
Short name T496
Test name
Test status
Simulation time 19133718026 ps
CPU time 504.75 seconds
Started Jul 13 06:25:30 PM PDT 24
Finished Jul 13 06:33:56 PM PDT 24
Peak memory 273312 kb
Host smart-d91bd0a1-9b84-4f73-ba9b-0d8cab64aa64
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761902379 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg_stub_clk.761902379
Directory /workspace/28.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/28.alert_handler_ping_timeout.781789042
Short name T302
Test name
Test status
Simulation time 18061053517 ps
CPU time 388.48 seconds
Started Jul 13 06:25:16 PM PDT 24
Finished Jul 13 06:31:47 PM PDT 24
Peak memory 249044 kb
Host smart-61089667-a8dc-4c64-8444-d65a5efb35aa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781789042 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_ping_timeout.781789042
Directory /workspace/28.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_random_alerts.641738715
Short name T188
Test name
Test status
Simulation time 329502034 ps
CPU time 29.63 seconds
Started Jul 13 06:25:16 PM PDT 24
Finished Jul 13 06:25:48 PM PDT 24
Peak memory 256720 kb
Host smart-835e41fe-7e40-43ee-bc6d-18144b5f5b57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64173
8715 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_alerts.641738715
Directory /workspace/28.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/28.alert_handler_random_classes.2622252823
Short name T610
Test name
Test status
Simulation time 225620514 ps
CPU time 14.37 seconds
Started Jul 13 06:25:33 PM PDT 24
Finished Jul 13 06:25:48 PM PDT 24
Peak memory 248796 kb
Host smart-959b5217-a9c9-44c5-8d2f-9e0c24226c0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26222
52823 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_classes.2622252823
Directory /workspace/28.alert_handler_random_classes/latest

Test location /workspace/coverage/default/28.alert_handler_sig_int_fail.2372387190
Short name T21
Test name
Test status
Simulation time 2193236598 ps
CPU time 68.49 seconds
Started Jul 13 06:25:12 PM PDT 24
Finished Jul 13 06:26:22 PM PDT 24
Peak memory 256776 kb
Host smart-e2bbc341-f3ad-472d-8cde-99b4fe8a9fbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23723
87190 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_sig_int_fail.2372387190
Directory /workspace/28.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/28.alert_handler_smoke.3921666943
Short name T405
Test name
Test status
Simulation time 3487460034 ps
CPU time 61.85 seconds
Started Jul 13 06:25:17 PM PDT 24
Finished Jul 13 06:26:20 PM PDT 24
Peak memory 257560 kb
Host smart-9d974915-9f9b-4920-86a8-d085916349b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39216
66943 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_smoke.3921666943
Directory /workspace/28.alert_handler_smoke/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all.352446507
Short name T267
Test name
Test status
Simulation time 106660763313 ps
CPU time 4517.83 seconds
Started Jul 13 06:25:19 PM PDT 24
Finished Jul 13 07:40:39 PM PDT 24
Peak memory 302456 kb
Host smart-8536b430-ec7f-4585-8788-3343464eafdc
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352446507 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_han
dler_stress_all.352446507
Directory /workspace/28.alert_handler_stress_all/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all_with_rand_reset.2077807067
Short name T688
Test name
Test status
Simulation time 56556618553 ps
CPU time 5181.22 seconds
Started Jul 13 06:25:29 PM PDT 24
Finished Jul 13 07:51:52 PM PDT 24
Peak memory 331156 kb
Host smart-9487c8a6-ccef-415d-aa1b-344b8a4f2f7e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077807067 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.alert_handler_stress_all_with_rand_reset.2077807067
Directory /workspace/28.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.alert_handler_entropy.858590327
Short name T416
Test name
Test status
Simulation time 7033774556 ps
CPU time 796.41 seconds
Started Jul 13 06:25:29 PM PDT 24
Finished Jul 13 06:38:47 PM PDT 24
Peak memory 273628 kb
Host smart-a655f869-010c-4325-8211-c5f2fa8c06e8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858590327 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_entropy.858590327
Directory /workspace/29.alert_handler_entropy/latest

Test location /workspace/coverage/default/29.alert_handler_esc_alert_accum.202316158
Short name T441
Test name
Test status
Simulation time 921485255 ps
CPU time 21.76 seconds
Started Jul 13 06:25:31 PM PDT 24
Finished Jul 13 06:25:55 PM PDT 24
Peak memory 256708 kb
Host smart-8d29db3b-0494-434c-a375-00500970b901
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20231
6158 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_alert_accum.202316158
Directory /workspace/29.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/29.alert_handler_esc_intr_timeout.530099054
Short name T369
Test name
Test status
Simulation time 80902622 ps
CPU time 11.08 seconds
Started Jul 13 06:25:18 PM PDT 24
Finished Jul 13 06:25:30 PM PDT 24
Peak memory 249148 kb
Host smart-71786719-d4eb-4fc6-a1c4-e072ce3d2c57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53009
9054 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_intr_timeout.530099054
Directory /workspace/29.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_lpg.2830396479
Short name T332
Test name
Test status
Simulation time 32241213979 ps
CPU time 1094.56 seconds
Started Jul 13 06:25:20 PM PDT 24
Finished Jul 13 06:43:36 PM PDT 24
Peak memory 284712 kb
Host smart-f6352532-17fb-4ed0-9fb0-9bb9dc569178
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830396479 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg.2830396479
Directory /workspace/29.alert_handler_lpg/latest

Test location /workspace/coverage/default/29.alert_handler_lpg_stub_clk.3959532207
Short name T112
Test name
Test status
Simulation time 23407101285 ps
CPU time 1774.32 seconds
Started Jul 13 06:25:20 PM PDT 24
Finished Jul 13 06:54:55 PM PDT 24
Peak memory 273888 kb
Host smart-5852238d-22ea-4b85-8144-ead72b84c782
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959532207 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg_stub_clk.3959532207
Directory /workspace/29.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/29.alert_handler_random_alerts.1904179478
Short name T563
Test name
Test status
Simulation time 2443264891 ps
CPU time 41.22 seconds
Started Jul 13 06:25:31 PM PDT 24
Finished Jul 13 06:26:14 PM PDT 24
Peak memory 256892 kb
Host smart-57da00ae-ffc1-44ee-b8c2-0dc4e9c4b7ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19041
79478 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_alerts.1904179478
Directory /workspace/29.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/29.alert_handler_random_classes.2753285238
Short name T607
Test name
Test status
Simulation time 2691591017 ps
CPU time 43.79 seconds
Started Jul 13 06:25:32 PM PDT 24
Finished Jul 13 06:26:17 PM PDT 24
Peak memory 249128 kb
Host smart-03c1ce37-daf8-42e9-89f9-b719ef622546
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27532
85238 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_classes.2753285238
Directory /workspace/29.alert_handler_random_classes/latest

Test location /workspace/coverage/default/29.alert_handler_sig_int_fail.4266653430
Short name T323
Test name
Test status
Simulation time 324243511 ps
CPU time 24.99 seconds
Started Jul 13 06:25:09 PM PDT 24
Finished Jul 13 06:25:35 PM PDT 24
Peak memory 256164 kb
Host smart-3a980c55-0488-48be-aa9d-5f3bf1962215
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42666
53430 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_sig_int_fail.4266653430
Directory /workspace/29.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/29.alert_handler_smoke.1697583550
Short name T696
Test name
Test status
Simulation time 94135533 ps
CPU time 4.76 seconds
Started Jul 13 06:25:18 PM PDT 24
Finished Jul 13 06:25:25 PM PDT 24
Peak memory 252100 kb
Host smart-8f2a4b89-55b0-410a-a1ef-6c87c158973b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16975
83550 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_smoke.1697583550
Directory /workspace/29.alert_handler_smoke/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all_with_rand_reset.3919771230
Short name T106
Test name
Test status
Simulation time 65117387188 ps
CPU time 1885.25 seconds
Started Jul 13 06:25:12 PM PDT 24
Finished Jul 13 06:56:39 PM PDT 24
Peak memory 305592 kb
Host smart-724b5f2c-a018-4c49-bf55-d1b140d20c5e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919771230 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 29.alert_handler_stress_all_with_rand_reset.3919771230
Directory /workspace/29.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.alert_handler_alert_accum_saturation.4024682866
Short name T178
Test name
Test status
Simulation time 81863902 ps
CPU time 3.67 seconds
Started Jul 13 06:24:38 PM PDT 24
Finished Jul 13 06:24:43 PM PDT 24
Peak memory 249556 kb
Host smart-aab51edb-8cdc-4dcc-a583-802c9bc11f3d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4024682866 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_alert_accum_saturation.4024682866
Directory /workspace/3.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/3.alert_handler_entropy.3697093717
Short name T380
Test name
Test status
Simulation time 15751980595 ps
CPU time 1107.12 seconds
Started Jul 13 06:24:47 PM PDT 24
Finished Jul 13 06:43:15 PM PDT 24
Peak memory 265724 kb
Host smart-73aefb58-ff54-41c9-a46e-92c77900e14c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697093717 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy.3697093717
Directory /workspace/3.alert_handler_entropy/latest

Test location /workspace/coverage/default/3.alert_handler_entropy_stress.4105455983
Short name T652
Test name
Test status
Simulation time 10723086804 ps
CPU time 107.74 seconds
Started Jul 13 06:24:40 PM PDT 24
Finished Jul 13 06:26:30 PM PDT 24
Peak memory 249412 kb
Host smart-e677c4aa-7fd4-4311-a161-468c7c750f8f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4105455983 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy_stress.4105455983
Directory /workspace/3.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/3.alert_handler_esc_alert_accum.772305238
Short name T18
Test name
Test status
Simulation time 603706923 ps
CPU time 37.85 seconds
Started Jul 13 06:24:41 PM PDT 24
Finished Jul 13 06:25:21 PM PDT 24
Peak memory 256548 kb
Host smart-4ff4cc2a-770c-4bdc-a332-f8a0a484ee55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77230
5238 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_alert_accum.772305238
Directory /workspace/3.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/3.alert_handler_esc_intr_timeout.2556108609
Short name T459
Test name
Test status
Simulation time 1592737105 ps
CPU time 43.47 seconds
Started Jul 13 06:24:38 PM PDT 24
Finished Jul 13 06:25:23 PM PDT 24
Peak memory 249272 kb
Host smart-de36ef1d-b9a6-43ed-bad3-588ac6f12391
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25561
08609 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_intr_timeout.2556108609
Directory /workspace/3.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_lpg.1564185617
Short name T324
Test name
Test status
Simulation time 53333477466 ps
CPU time 2676.24 seconds
Started Jul 13 06:24:50 PM PDT 24
Finished Jul 13 07:09:27 PM PDT 24
Peak memory 287272 kb
Host smart-3c930253-8f8c-45bd-b5dc-b6917a8dca3c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1564185617 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg.1564185617
Directory /workspace/3.alert_handler_lpg/latest

Test location /workspace/coverage/default/3.alert_handler_lpg_stub_clk.430282023
Short name T91
Test name
Test status
Simulation time 170114815898 ps
CPU time 2665.51 seconds
Started Jul 13 06:24:41 PM PDT 24
Finished Jul 13 07:09:08 PM PDT 24
Peak memory 285076 kb
Host smart-3e3b114b-fb36-4ea4-86d3-79d5519df61b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430282023 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg_stub_clk.430282023
Directory /workspace/3.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/3.alert_handler_random_alerts.1967522238
Short name T357
Test name
Test status
Simulation time 1785941296 ps
CPU time 55.23 seconds
Started Jul 13 06:24:31 PM PDT 24
Finished Jul 13 06:25:27 PM PDT 24
Peak memory 256752 kb
Host smart-f210b5cf-70ac-405e-a0ec-8e4211c1f48b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19675
22238 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_alerts.1967522238
Directory /workspace/3.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/3.alert_handler_random_classes.2266032844
Short name T647
Test name
Test status
Simulation time 43058574 ps
CPU time 3.32 seconds
Started Jul 13 06:24:25 PM PDT 24
Finished Jul 13 06:24:31 PM PDT 24
Peak memory 241084 kb
Host smart-dc1b09a2-cd04-4ef0-a841-5edce9cecf53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22660
32844 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_classes.2266032844
Directory /workspace/3.alert_handler_random_classes/latest

Test location /workspace/coverage/default/3.alert_handler_sec_cm.1665989218
Short name T34
Test name
Test status
Simulation time 176981610 ps
CPU time 12.65 seconds
Started Jul 13 06:25:03 PM PDT 24
Finished Jul 13 06:25:17 PM PDT 24
Peak memory 271596 kb
Host smart-39362970-f5bb-43d2-b240-794e6ddb69e6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1665989218 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sec_cm.1665989218
Directory /workspace/3.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/3.alert_handler_sig_int_fail.2325195348
Short name T2
Test name
Test status
Simulation time 165791406 ps
CPU time 11.38 seconds
Started Jul 13 06:24:45 PM PDT 24
Finished Jul 13 06:25:02 PM PDT 24
Peak memory 249236 kb
Host smart-4ad11817-5c1f-4731-8173-aef9d1a8cbe2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23251
95348 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sig_int_fail.2325195348
Directory /workspace/3.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/3.alert_handler_smoke.4171084511
Short name T640
Test name
Test status
Simulation time 648590245 ps
CPU time 20.77 seconds
Started Jul 13 06:24:25 PM PDT 24
Finished Jul 13 06:24:48 PM PDT 24
Peak memory 256840 kb
Host smart-11d55f86-b095-4105-b30b-cae0f6609dc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41710
84511 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_smoke.4171084511
Directory /workspace/3.alert_handler_smoke/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all.3345037641
Short name T46
Test name
Test status
Simulation time 13884081137 ps
CPU time 1152.01 seconds
Started Jul 13 06:24:41 PM PDT 24
Finished Jul 13 06:43:55 PM PDT 24
Peak memory 288348 kb
Host smart-628ad028-0727-4abb-899a-f91842b151c2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345037641 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_han
dler_stress_all.3345037641
Directory /workspace/3.alert_handler_stress_all/latest

Test location /workspace/coverage/default/30.alert_handler_entropy.2855666862
Short name T467
Test name
Test status
Simulation time 26554231023 ps
CPU time 1478.82 seconds
Started Jul 13 06:25:26 PM PDT 24
Finished Jul 13 06:50:06 PM PDT 24
Peak memory 290360 kb
Host smart-8d888e59-ebd2-4eaa-933f-a90c195cd5a4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855666862 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_entropy.2855666862
Directory /workspace/30.alert_handler_entropy/latest

Test location /workspace/coverage/default/30.alert_handler_esc_alert_accum.3939303457
Short name T412
Test name
Test status
Simulation time 2111812798 ps
CPU time 33.28 seconds
Started Jul 13 06:25:34 PM PDT 24
Finished Jul 13 06:26:08 PM PDT 24
Peak memory 256792 kb
Host smart-a0fd62ab-2549-4016-b810-ef70f0bb4d68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39393
03457 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_alert_accum.3939303457
Directory /workspace/30.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/30.alert_handler_esc_intr_timeout.2946949594
Short name T452
Test name
Test status
Simulation time 58526581 ps
CPU time 5.24 seconds
Started Jul 13 06:25:29 PM PDT 24
Finished Jul 13 06:25:35 PM PDT 24
Peak memory 249776 kb
Host smart-48ec365a-3441-4b55-81d4-3154e97a19e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29469
49594 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_intr_timeout.2946949594
Directory /workspace/30.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_lpg.2054974296
Short name T304
Test name
Test status
Simulation time 138304797414 ps
CPU time 3313.55 seconds
Started Jul 13 06:25:30 PM PDT 24
Finished Jul 13 07:20:45 PM PDT 24
Peak memory 289808 kb
Host smart-683a0e1a-7985-480d-b183-e8d5e5e62e82
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054974296 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg.2054974296
Directory /workspace/30.alert_handler_lpg/latest

Test location /workspace/coverage/default/30.alert_handler_lpg_stub_clk.2436493189
Short name T548
Test name
Test status
Simulation time 49586251779 ps
CPU time 1372.31 seconds
Started Jul 13 06:25:24 PM PDT 24
Finished Jul 13 06:48:17 PM PDT 24
Peak memory 270920 kb
Host smart-9d35e098-aaf9-4236-b8ca-b14e7f4901c2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436493189 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg_stub_clk.2436493189
Directory /workspace/30.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/30.alert_handler_ping_timeout.1707767026
Short name T279
Test name
Test status
Simulation time 45080103594 ps
CPU time 459.24 seconds
Started Jul 13 06:25:29 PM PDT 24
Finished Jul 13 06:33:10 PM PDT 24
Peak memory 249404 kb
Host smart-85eb45d2-c3aa-45d8-8c0f-72c70fe72e85
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707767026 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_ping_timeout.1707767026
Directory /workspace/30.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_random_alerts.3789595166
Short name T680
Test name
Test status
Simulation time 540448333 ps
CPU time 16.44 seconds
Started Jul 13 06:25:15 PM PDT 24
Finished Jul 13 06:25:34 PM PDT 24
Peak memory 256608 kb
Host smart-05d50879-58e9-40e0-8129-9cb81f36a8b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37895
95166 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_alerts.3789595166
Directory /workspace/30.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/30.alert_handler_random_classes.157333885
Short name T669
Test name
Test status
Simulation time 851800413 ps
CPU time 37.63 seconds
Started Jul 13 06:25:11 PM PDT 24
Finished Jul 13 06:25:51 PM PDT 24
Peak memory 249228 kb
Host smart-0b703f2b-ae84-4e64-a682-a485c7ad841f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15733
3885 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_classes.157333885
Directory /workspace/30.alert_handler_random_classes/latest

Test location /workspace/coverage/default/30.alert_handler_sig_int_fail.1532669936
Short name T603
Test name
Test status
Simulation time 578573236 ps
CPU time 51.27 seconds
Started Jul 13 06:25:23 PM PDT 24
Finished Jul 13 06:26:15 PM PDT 24
Peak memory 256996 kb
Host smart-fa7caa25-7c97-440a-8fae-8a32b26a291c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15326
69936 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_sig_int_fail.1532669936
Directory /workspace/30.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/30.alert_handler_smoke.1329590197
Short name T189
Test name
Test status
Simulation time 295171883 ps
CPU time 10.49 seconds
Started Jul 13 06:25:15 PM PDT 24
Finished Jul 13 06:25:28 PM PDT 24
Peak memory 255684 kb
Host smart-08e29dda-f667-4738-a4d5-9e5e00025c6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13295
90197 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_smoke.1329590197
Directory /workspace/30.alert_handler_smoke/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all_with_rand_reset.2121808938
Short name T32
Test name
Test status
Simulation time 55066053568 ps
CPU time 3538.93 seconds
Started Jul 13 06:25:14 PM PDT 24
Finished Jul 13 07:24:15 PM PDT 24
Peak memory 306484 kb
Host smart-f74c8a23-088f-4693-8838-af5c26d6a2e4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121808938 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.alert_handler_stress_all_with_rand_reset.2121808938
Directory /workspace/30.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.alert_handler_entropy.265222373
Short name T601
Test name
Test status
Simulation time 18864450685 ps
CPU time 1063.89 seconds
Started Jul 13 06:25:06 PM PDT 24
Finished Jul 13 06:42:51 PM PDT 24
Peak memory 273888 kb
Host smart-ca297de8-2d17-4f3b-8c92-f43eda503ea0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=265222373 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_entropy.265222373
Directory /workspace/31.alert_handler_entropy/latest

Test location /workspace/coverage/default/31.alert_handler_esc_alert_accum.3958398333
Short name T229
Test name
Test status
Simulation time 31895546410 ps
CPU time 290.7 seconds
Started Jul 13 06:25:35 PM PDT 24
Finished Jul 13 06:30:27 PM PDT 24
Peak memory 256872 kb
Host smart-13ce69b6-1606-462b-8b45-9e1e81139b2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39583
98333 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_alert_accum.3958398333
Directory /workspace/31.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/31.alert_handler_esc_intr_timeout.3120015080
Short name T85
Test name
Test status
Simulation time 493757428 ps
CPU time 12.08 seconds
Started Jul 13 06:25:13 PM PDT 24
Finished Jul 13 06:25:26 PM PDT 24
Peak memory 256888 kb
Host smart-cd43d3a5-3746-4e2c-91fe-6ba903989d7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31200
15080 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_intr_timeout.3120015080
Directory /workspace/31.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_lpg.271315435
Short name T268
Test name
Test status
Simulation time 79220860883 ps
CPU time 1348.3 seconds
Started Jul 13 06:25:28 PM PDT 24
Finished Jul 13 06:47:58 PM PDT 24
Peak memory 273672 kb
Host smart-8edb2709-2292-4765-b019-be01694f96ed
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271315435 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg.271315435
Directory /workspace/31.alert_handler_lpg/latest

Test location /workspace/coverage/default/31.alert_handler_lpg_stub_clk.2424005689
Short name T26
Test name
Test status
Simulation time 8529851907 ps
CPU time 1017.96 seconds
Started Jul 13 06:25:36 PM PDT 24
Finished Jul 13 06:42:34 PM PDT 24
Peak memory 283728 kb
Host smart-1a8aaedb-f0d0-411d-8ff0-6024c8685f8b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424005689 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg_stub_clk.2424005689
Directory /workspace/31.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/31.alert_handler_ping_timeout.586615324
Short name T281
Test name
Test status
Simulation time 108460353211 ps
CPU time 611.03 seconds
Started Jul 13 06:25:28 PM PDT 24
Finished Jul 13 06:35:40 PM PDT 24
Peak memory 249376 kb
Host smart-96cef317-9781-4e8b-8550-d78108e5daf5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=586615324 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_ping_timeout.586615324
Directory /workspace/31.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_random_alerts.2067225853
Short name T360
Test name
Test status
Simulation time 4857007948 ps
CPU time 23.78 seconds
Started Jul 13 06:25:30 PM PDT 24
Finished Jul 13 06:25:55 PM PDT 24
Peak memory 256700 kb
Host smart-1e046c1a-853c-4fca-a961-f818f3b2f1c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20672
25853 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_alerts.2067225853
Directory /workspace/31.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/31.alert_handler_random_classes.1985341291
Short name T82
Test name
Test status
Simulation time 1825552183 ps
CPU time 52.01 seconds
Started Jul 13 06:25:17 PM PDT 24
Finished Jul 13 06:26:11 PM PDT 24
Peak memory 249280 kb
Host smart-99780b91-2f2a-43c8-8780-bb047ebdd1e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19853
41291 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_classes.1985341291
Directory /workspace/31.alert_handler_random_classes/latest

Test location /workspace/coverage/default/31.alert_handler_sig_int_fail.3577799687
Short name T474
Test name
Test status
Simulation time 201819376 ps
CPU time 20.54 seconds
Started Jul 13 06:25:24 PM PDT 24
Finished Jul 13 06:25:46 PM PDT 24
Peak memory 249228 kb
Host smart-175692f1-edb9-4428-8e17-1e62bff730ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35777
99687 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_sig_int_fail.3577799687
Directory /workspace/31.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/31.alert_handler_smoke.1399412087
Short name T577
Test name
Test status
Simulation time 266765608 ps
CPU time 33.11 seconds
Started Jul 13 06:25:19 PM PDT 24
Finished Jul 13 06:25:53 PM PDT 24
Peak memory 249272 kb
Host smart-6148108b-1ba5-41e8-8094-00fc7ceca170
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13994
12087 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_smoke.1399412087
Directory /workspace/31.alert_handler_smoke/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all_with_rand_reset.704560496
Short name T272
Test name
Test status
Simulation time 146912658493 ps
CPU time 3726.47 seconds
Started Jul 13 06:25:32 PM PDT 24
Finished Jul 13 07:27:41 PM PDT 24
Peak memory 323152 kb
Host smart-7e859e4a-64e0-47d9-9e4b-0f7bac9aa339
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704560496 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 31.alert_handler_stress_all_with_rand_reset.704560496
Directory /workspace/31.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.alert_handler_entropy.2031837941
Short name T605
Test name
Test status
Simulation time 84694773714 ps
CPU time 1512.33 seconds
Started Jul 13 06:25:24 PM PDT 24
Finished Jul 13 06:50:37 PM PDT 24
Peak memory 290072 kb
Host smart-827db074-c24e-423e-8b8b-852617e6abae
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031837941 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_entropy.2031837941
Directory /workspace/32.alert_handler_entropy/latest

Test location /workspace/coverage/default/32.alert_handler_esc_alert_accum.3783378297
Short name T494
Test name
Test status
Simulation time 7782374593 ps
CPU time 204.79 seconds
Started Jul 13 06:25:31 PM PDT 24
Finished Jul 13 06:28:57 PM PDT 24
Peak memory 257068 kb
Host smart-1ae923bc-037b-4c3b-8ec7-7a6a37c77b0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37833
78297 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_alert_accum.3783378297
Directory /workspace/32.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/32.alert_handler_esc_intr_timeout.1717787742
Short name T595
Test name
Test status
Simulation time 293385144 ps
CPU time 22.64 seconds
Started Jul 13 06:25:29 PM PDT 24
Finished Jul 13 06:25:53 PM PDT 24
Peak memory 256892 kb
Host smart-7c3faf36-0b61-4821-bb6d-ba0e636a7670
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17177
87742 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_intr_timeout.1717787742
Directory /workspace/32.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_lpg_stub_clk.458316235
Short name T336
Test name
Test status
Simulation time 30541046916 ps
CPU time 2058.38 seconds
Started Jul 13 06:25:31 PM PDT 24
Finished Jul 13 06:59:51 PM PDT 24
Peak memory 289644 kb
Host smart-de6a3a6b-9190-4ee8-a2da-fea3650d38f2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458316235 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg_stub_clk.458316235
Directory /workspace/32.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/32.alert_handler_ping_timeout.4138438188
Short name T287
Test name
Test status
Simulation time 26056249680 ps
CPU time 196.18 seconds
Started Jul 13 06:25:17 PM PDT 24
Finished Jul 13 06:28:35 PM PDT 24
Peak memory 249380 kb
Host smart-80e5efb9-b02c-4844-80a2-92b7c19de26f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138438188 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_ping_timeout.4138438188
Directory /workspace/32.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_random_alerts.4233221170
Short name T43
Test name
Test status
Simulation time 2604218394 ps
CPU time 40.96 seconds
Started Jul 13 06:25:25 PM PDT 24
Finished Jul 13 06:26:07 PM PDT 24
Peak memory 256916 kb
Host smart-b0d93b07-beb0-4201-a9bb-404712b73473
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42332
21170 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_alerts.4233221170
Directory /workspace/32.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/32.alert_handler_random_classes.3178489415
Short name T519
Test name
Test status
Simulation time 1979865058 ps
CPU time 21.58 seconds
Started Jul 13 06:25:29 PM PDT 24
Finished Jul 13 06:25:52 PM PDT 24
Peak memory 255980 kb
Host smart-04d43eb8-299b-48df-a733-c85ee6d76c4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31784
89415 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_classes.3178489415
Directory /workspace/32.alert_handler_random_classes/latest

Test location /workspace/coverage/default/32.alert_handler_sig_int_fail.2032998233
Short name T542
Test name
Test status
Simulation time 128637685 ps
CPU time 9.98 seconds
Started Jul 13 06:25:29 PM PDT 24
Finished Jul 13 06:25:41 PM PDT 24
Peak memory 253200 kb
Host smart-8ca9d068-e307-4074-b304-e628e0a6b307
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20329
98233 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_sig_int_fail.2032998233
Directory /workspace/32.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/32.alert_handler_smoke.3477790612
Short name T555
Test name
Test status
Simulation time 9540053463 ps
CPU time 72.19 seconds
Started Jul 13 06:25:15 PM PDT 24
Finished Jul 13 06:26:29 PM PDT 24
Peak memory 257568 kb
Host smart-64f858cc-e045-4265-bc14-990d504489d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34777
90612 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_smoke.3477790612
Directory /workspace/32.alert_handler_smoke/latest

Test location /workspace/coverage/default/33.alert_handler_entropy.1263930738
Short name T518
Test name
Test status
Simulation time 25634858960 ps
CPU time 1514.91 seconds
Started Jul 13 06:25:32 PM PDT 24
Finished Jul 13 06:50:48 PM PDT 24
Peak memory 273820 kb
Host smart-d2b68249-e4a0-4b9d-b745-906e636a840f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1263930738 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_entropy.1263930738
Directory /workspace/33.alert_handler_entropy/latest

Test location /workspace/coverage/default/33.alert_handler_esc_alert_accum.1360587181
Short name T590
Test name
Test status
Simulation time 5043041775 ps
CPU time 199.5 seconds
Started Jul 13 06:25:25 PM PDT 24
Finished Jul 13 06:28:46 PM PDT 24
Peak memory 257528 kb
Host smart-112da360-b74f-4dd6-95b6-ae83d466b55f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13605
87181 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_alert_accum.1360587181
Directory /workspace/33.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/33.alert_handler_esc_intr_timeout.4009932619
Short name T553
Test name
Test status
Simulation time 133774081 ps
CPU time 9.46 seconds
Started Jul 13 06:25:16 PM PDT 24
Finished Jul 13 06:25:27 PM PDT 24
Peak memory 256980 kb
Host smart-ec8676e2-87eb-487b-8491-45bdd30f9d29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40099
32619 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_intr_timeout.4009932619
Directory /workspace/33.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_lpg.491893088
Short name T587
Test name
Test status
Simulation time 29587848510 ps
CPU time 1586.81 seconds
Started Jul 13 06:25:27 PM PDT 24
Finished Jul 13 06:51:55 PM PDT 24
Peak memory 273228 kb
Host smart-5363cf5f-edd5-48b3-b4c9-e9aa51a39c47
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=491893088 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg.491893088
Directory /workspace/33.alert_handler_lpg/latest

Test location /workspace/coverage/default/33.alert_handler_lpg_stub_clk.3556887894
Short name T395
Test name
Test status
Simulation time 26514955513 ps
CPU time 681.51 seconds
Started Jul 13 06:25:30 PM PDT 24
Finished Jul 13 06:36:53 PM PDT 24
Peak memory 273908 kb
Host smart-de765cba-5bf8-4d71-849b-de0ce48cbf65
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556887894 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg_stub_clk.3556887894
Directory /workspace/33.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/33.alert_handler_ping_timeout.4248532728
Short name T283
Test name
Test status
Simulation time 14128480731 ps
CPU time 154.16 seconds
Started Jul 13 06:25:28 PM PDT 24
Finished Jul 13 06:28:04 PM PDT 24
Peak memory 249376 kb
Host smart-a5a328b0-e2e5-49cf-9b42-ff347e1a1f97
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248532728 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_ping_timeout.4248532728
Directory /workspace/33.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_random_alerts.564491704
Short name T492
Test name
Test status
Simulation time 669601241 ps
CPU time 44.69 seconds
Started Jul 13 06:25:22 PM PDT 24
Finished Jul 13 06:26:07 PM PDT 24
Peak memory 256808 kb
Host smart-ed043f86-3988-4dbc-9059-8871357406da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56449
1704 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_alerts.564491704
Directory /workspace/33.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/33.alert_handler_random_classes.3792987326
Short name T253
Test name
Test status
Simulation time 142492903 ps
CPU time 11.37 seconds
Started Jul 13 06:25:23 PM PDT 24
Finished Jul 13 06:25:35 PM PDT 24
Peak memory 255016 kb
Host smart-edcca978-6015-446c-a60c-ab612e7c6420
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37929
87326 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_classes.3792987326
Directory /workspace/33.alert_handler_random_classes/latest

Test location /workspace/coverage/default/33.alert_handler_sig_int_fail.393949344
Short name T317
Test name
Test status
Simulation time 318551681 ps
CPU time 21.18 seconds
Started Jul 13 06:25:17 PM PDT 24
Finished Jul 13 06:25:40 PM PDT 24
Peak memory 249160 kb
Host smart-663e80a3-da35-40bf-ba5c-66871a7d2ca4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39394
9344 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_sig_int_fail.393949344
Directory /workspace/33.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/33.alert_handler_smoke.4005934836
Short name T363
Test name
Test status
Simulation time 16782426 ps
CPU time 3.26 seconds
Started Jul 13 06:25:30 PM PDT 24
Finished Jul 13 06:25:35 PM PDT 24
Peak memory 251456 kb
Host smart-777dae1f-b0c6-4c00-bcfd-909b3e0861b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40059
34836 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_smoke.4005934836
Directory /workspace/33.alert_handler_smoke/latest

Test location /workspace/coverage/default/34.alert_handler_entropy.2576486095
Short name T251
Test name
Test status
Simulation time 15341287864 ps
CPU time 919.29 seconds
Started Jul 13 06:25:21 PM PDT 24
Finished Jul 13 06:40:40 PM PDT 24
Peak memory 273880 kb
Host smart-2717e403-3525-4bfa-adaa-25bc7d3ecdc2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576486095 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_entropy.2576486095
Directory /workspace/34.alert_handler_entropy/latest

Test location /workspace/coverage/default/34.alert_handler_esc_alert_accum.3081146381
Short name T362
Test name
Test status
Simulation time 1498994934 ps
CPU time 104.8 seconds
Started Jul 13 06:25:32 PM PDT 24
Finished Jul 13 06:27:18 PM PDT 24
Peak memory 256708 kb
Host smart-a14ae35f-19a1-4d5c-b5d8-683d9b2f5eeb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30811
46381 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_alert_accum.3081146381
Directory /workspace/34.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/34.alert_handler_esc_intr_timeout.3494856063
Short name T584
Test name
Test status
Simulation time 1413201719 ps
CPU time 32.05 seconds
Started Jul 13 06:25:14 PM PDT 24
Finished Jul 13 06:25:48 PM PDT 24
Peak memory 249164 kb
Host smart-9110c21b-df42-4deb-9bb1-14f20b70211d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34948
56063 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_intr_timeout.3494856063
Directory /workspace/34.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_lpg.2273172124
Short name T639
Test name
Test status
Simulation time 25399886405 ps
CPU time 1422.49 seconds
Started Jul 13 06:25:31 PM PDT 24
Finished Jul 13 06:49:15 PM PDT 24
Peak memory 273952 kb
Host smart-a67faed1-e3b0-4334-bb55-841ef0ffaffc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273172124 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg.2273172124
Directory /workspace/34.alert_handler_lpg/latest

Test location /workspace/coverage/default/34.alert_handler_lpg_stub_clk.1996369691
Short name T389
Test name
Test status
Simulation time 20994183923 ps
CPU time 1189.63 seconds
Started Jul 13 06:25:23 PM PDT 24
Finished Jul 13 06:45:14 PM PDT 24
Peak memory 272748 kb
Host smart-bcf3bc1a-815c-4527-9f7a-e058c0ddc103
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996369691 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg_stub_clk.1996369691
Directory /workspace/34.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/34.alert_handler_ping_timeout.891544126
Short name T295
Test name
Test status
Simulation time 34724357877 ps
CPU time 442.02 seconds
Started Jul 13 06:25:19 PM PDT 24
Finished Jul 13 06:32:42 PM PDT 24
Peak memory 249312 kb
Host smart-0dc8c373-3a84-427d-9a44-42adf2886823
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891544126 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_ping_timeout.891544126
Directory /workspace/34.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_random_alerts.2926865674
Short name T224
Test name
Test status
Simulation time 3602100901 ps
CPU time 58.42 seconds
Started Jul 13 06:25:27 PM PDT 24
Finished Jul 13 06:26:26 PM PDT 24
Peak memory 256520 kb
Host smart-684fc598-b0b0-403c-9f95-322e52c2c791
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29268
65674 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_alerts.2926865674
Directory /workspace/34.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/34.alert_handler_random_classes.823634152
Short name T508
Test name
Test status
Simulation time 391672486 ps
CPU time 35.25 seconds
Started Jul 13 06:25:19 PM PDT 24
Finished Jul 13 06:25:55 PM PDT 24
Peak memory 249224 kb
Host smart-3312a1f6-86e4-437a-87cd-4c797904a32d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82363
4152 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_classes.823634152
Directory /workspace/34.alert_handler_random_classes/latest

Test location /workspace/coverage/default/34.alert_handler_sig_int_fail.901599979
Short name T428
Test name
Test status
Simulation time 1007188733 ps
CPU time 30.26 seconds
Started Jul 13 06:25:18 PM PDT 24
Finished Jul 13 06:25:49 PM PDT 24
Peak memory 256988 kb
Host smart-3694518b-f793-49e1-a211-10c1a0d263f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90159
9979 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_sig_int_fail.901599979
Directory /workspace/34.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/34.alert_handler_smoke.3585210840
Short name T655
Test name
Test status
Simulation time 612688070 ps
CPU time 38.72 seconds
Started Jul 13 06:25:19 PM PDT 24
Finished Jul 13 06:25:59 PM PDT 24
Peak memory 256924 kb
Host smart-d3a3ef5f-9051-4019-9608-24c27ac5cc94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35852
10840 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_smoke.3585210840
Directory /workspace/34.alert_handler_smoke/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all_with_rand_reset.3205741015
Short name T113
Test name
Test status
Simulation time 43231537013 ps
CPU time 1326.32 seconds
Started Jul 13 06:25:18 PM PDT 24
Finished Jul 13 06:47:26 PM PDT 24
Peak memory 284036 kb
Host smart-9046d62d-289c-4f1c-bceb-0de3b765277d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205741015 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.alert_handler_stress_all_with_rand_reset.3205741015
Directory /workspace/34.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.alert_handler_entropy.2006954347
Short name T619
Test name
Test status
Simulation time 245607515149 ps
CPU time 2716.83 seconds
Started Jul 13 06:25:31 PM PDT 24
Finished Jul 13 07:10:49 PM PDT 24
Peak memory 282088 kb
Host smart-a001c2b0-5685-4c31-b084-d7be50c73ed9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2006954347 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_entropy.2006954347
Directory /workspace/35.alert_handler_entropy/latest

Test location /workspace/coverage/default/35.alert_handler_esc_alert_accum.1897116280
Short name T490
Test name
Test status
Simulation time 3472234993 ps
CPU time 51.15 seconds
Started Jul 13 06:25:31 PM PDT 24
Finished Jul 13 06:26:23 PM PDT 24
Peak memory 256728 kb
Host smart-09a7cc00-6c55-4260-879a-f890f8b9314b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18971
16280 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_alert_accum.1897116280
Directory /workspace/35.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/35.alert_handler_esc_intr_timeout.2473777955
Short name T457
Test name
Test status
Simulation time 653740357 ps
CPU time 26.66 seconds
Started Jul 13 06:25:29 PM PDT 24
Finished Jul 13 06:25:57 PM PDT 24
Peak memory 256624 kb
Host smart-9034174b-be6d-4610-887c-3d5f0385272f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24737
77955 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_intr_timeout.2473777955
Directory /workspace/35.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_lpg.3678468019
Short name T686
Test name
Test status
Simulation time 136329970002 ps
CPU time 3139.47 seconds
Started Jul 13 06:25:21 PM PDT 24
Finished Jul 13 07:17:41 PM PDT 24
Peak memory 290312 kb
Host smart-bc293f40-cafa-4946-8ec0-d945ba5a83e6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678468019 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg.3678468019
Directory /workspace/35.alert_handler_lpg/latest

Test location /workspace/coverage/default/35.alert_handler_lpg_stub_clk.3036799562
Short name T59
Test name
Test status
Simulation time 114898258285 ps
CPU time 1699.05 seconds
Started Jul 13 06:25:20 PM PDT 24
Finished Jul 13 06:53:40 PM PDT 24
Peak memory 273336 kb
Host smart-fc2ab762-bf48-4c38-b297-928dd09fcc79
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036799562 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg_stub_clk.3036799562
Directory /workspace/35.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/35.alert_handler_ping_timeout.2930272879
Short name T551
Test name
Test status
Simulation time 38849675811 ps
CPU time 121.02 seconds
Started Jul 13 06:25:22 PM PDT 24
Finished Jul 13 06:27:24 PM PDT 24
Peak memory 249340 kb
Host smart-31cfbd08-bdf0-4ba2-b397-8380d4e5a809
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930272879 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_ping_timeout.2930272879
Directory /workspace/35.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_random_alerts.2631776751
Short name T436
Test name
Test status
Simulation time 412746307 ps
CPU time 36.2 seconds
Started Jul 13 06:25:28 PM PDT 24
Finished Jul 13 06:26:05 PM PDT 24
Peak memory 257332 kb
Host smart-a1a6d1fd-8815-486f-ab3c-b346362781a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26317
76751 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_alerts.2631776751
Directory /workspace/35.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/35.alert_handler_random_classes.1948740131
Short name T498
Test name
Test status
Simulation time 1371716794 ps
CPU time 40 seconds
Started Jul 13 06:25:22 PM PDT 24
Finished Jul 13 06:26:02 PM PDT 24
Peak memory 249288 kb
Host smart-227ec7fe-5ecb-413e-b96a-a49b12f0d4a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19487
40131 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_classes.1948740131
Directory /workspace/35.alert_handler_random_classes/latest

Test location /workspace/coverage/default/35.alert_handler_sig_int_fail.4288411172
Short name T566
Test name
Test status
Simulation time 2058230937 ps
CPU time 31.97 seconds
Started Jul 13 06:25:29 PM PDT 24
Finished Jul 13 06:26:02 PM PDT 24
Peak memory 249284 kb
Host smart-f4afebaf-d08a-46b1-bfe0-b45152cbf456
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42884
11172 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_sig_int_fail.4288411172
Directory /workspace/35.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/35.alert_handler_smoke.3353193041
Short name T702
Test name
Test status
Simulation time 290268945 ps
CPU time 23.61 seconds
Started Jul 13 06:25:18 PM PDT 24
Finished Jul 13 06:25:43 PM PDT 24
Peak memory 256484 kb
Host smart-e823901c-c126-4068-b3ca-c727234b1ce2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33531
93041 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_smoke.3353193041
Directory /workspace/35.alert_handler_smoke/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all.321110040
Short name T308
Test name
Test status
Simulation time 14548503105 ps
CPU time 792.61 seconds
Started Jul 13 06:25:31 PM PDT 24
Finished Jul 13 06:38:45 PM PDT 24
Peak memory 265716 kb
Host smart-78ee0af2-b14e-4775-987c-d9a145c0fbce
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321110040 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_han
dler_stress_all.321110040
Directory /workspace/35.alert_handler_stress_all/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all_with_rand_reset.3640014794
Short name T245
Test name
Test status
Simulation time 302744110761 ps
CPU time 4572.11 seconds
Started Jul 13 06:25:34 PM PDT 24
Finished Jul 13 07:41:48 PM PDT 24
Peak memory 300752 kb
Host smart-5543dfc1-a0b4-4296-9532-f905da2ff8d2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640014794 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 35.alert_handler_stress_all_with_rand_reset.3640014794
Directory /workspace/35.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.alert_handler_entropy.3104877153
Short name T546
Test name
Test status
Simulation time 512863086412 ps
CPU time 3467.62 seconds
Started Jul 13 06:25:20 PM PDT 24
Finished Jul 13 07:23:09 PM PDT 24
Peak memory 290332 kb
Host smart-674ee5eb-e77b-4f60-a150-e1eb9c6d4a63
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104877153 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_entropy.3104877153
Directory /workspace/36.alert_handler_entropy/latest

Test location /workspace/coverage/default/36.alert_handler_esc_alert_accum.1798648425
Short name T455
Test name
Test status
Simulation time 28613938939 ps
CPU time 168.21 seconds
Started Jul 13 06:25:29 PM PDT 24
Finished Jul 13 06:28:18 PM PDT 24
Peak memory 256700 kb
Host smart-7aa8989d-763b-4dda-90ab-a119a1c3ff33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17986
48425 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_alert_accum.1798648425
Directory /workspace/36.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/36.alert_handler_esc_intr_timeout.3290605554
Short name T410
Test name
Test status
Simulation time 693480159 ps
CPU time 20.11 seconds
Started Jul 13 06:25:33 PM PDT 24
Finished Jul 13 06:25:54 PM PDT 24
Peak memory 249048 kb
Host smart-e9dd1683-fc23-417f-92ec-f3bf0c8a737c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32906
05554 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_intr_timeout.3290605554
Directory /workspace/36.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_lpg.3340101469
Short name T327
Test name
Test status
Simulation time 267033851550 ps
CPU time 2313.59 seconds
Started Jul 13 06:25:18 PM PDT 24
Finished Jul 13 07:03:53 PM PDT 24
Peak memory 288272 kb
Host smart-8a2498e1-1998-42c3-bb5e-25ab63d15c39
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340101469 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg.3340101469
Directory /workspace/36.alert_handler_lpg/latest

Test location /workspace/coverage/default/36.alert_handler_lpg_stub_clk.3759961369
Short name T485
Test name
Test status
Simulation time 19326455550 ps
CPU time 1321.67 seconds
Started Jul 13 06:25:28 PM PDT 24
Finished Jul 13 06:47:31 PM PDT 24
Peak memory 282176 kb
Host smart-5ee6b9d3-3e37-4274-a93a-1d2a00c50705
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759961369 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg_stub_clk.3759961369
Directory /workspace/36.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/36.alert_handler_ping_timeout.4199327716
Short name T10
Test name
Test status
Simulation time 7935360378 ps
CPU time 345.23 seconds
Started Jul 13 06:25:34 PM PDT 24
Finished Jul 13 06:31:21 PM PDT 24
Peak memory 249376 kb
Host smart-d05bfc88-c292-4733-8499-ef09a09c21fd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199327716 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_ping_timeout.4199327716
Directory /workspace/36.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_random_alerts.3669516707
Short name T417
Test name
Test status
Simulation time 883866738 ps
CPU time 34.47 seconds
Started Jul 13 06:25:25 PM PDT 24
Finished Jul 13 06:26:00 PM PDT 24
Peak memory 249136 kb
Host smart-c439e6d4-9c00-45df-a92b-cce0d9e3aba1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36695
16707 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_alerts.3669516707
Directory /workspace/36.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/36.alert_handler_random_classes.1888504268
Short name T634
Test name
Test status
Simulation time 2377966970 ps
CPU time 37.71 seconds
Started Jul 13 06:25:30 PM PDT 24
Finished Jul 13 06:26:09 PM PDT 24
Peak memory 249352 kb
Host smart-66b9f1f2-799b-422d-8873-aa20abe09d92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18885
04268 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_classes.1888504268
Directory /workspace/36.alert_handler_random_classes/latest

Test location /workspace/coverage/default/36.alert_handler_sig_int_fail.2550581087
Short name T487
Test name
Test status
Simulation time 911080244 ps
CPU time 14.69 seconds
Started Jul 13 06:25:28 PM PDT 24
Finished Jul 13 06:25:43 PM PDT 24
Peak memory 255160 kb
Host smart-c6eeb068-56ed-45f6-b967-72b3dc714488
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25505
81087 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_sig_int_fail.2550581087
Directory /workspace/36.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/36.alert_handler_smoke.2133730402
Short name T501
Test name
Test status
Simulation time 94520264 ps
CPU time 10.72 seconds
Started Jul 13 06:25:28 PM PDT 24
Finished Jul 13 06:25:40 PM PDT 24
Peak memory 255668 kb
Host smart-a5aa681d-e625-48c2-9221-72c0bc39bfdd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21337
30402 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_smoke.2133730402
Directory /workspace/36.alert_handler_smoke/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all.590628842
Short name T186
Test name
Test status
Simulation time 245556818 ps
CPU time 16.12 seconds
Started Jul 13 06:25:25 PM PDT 24
Finished Jul 13 06:25:42 PM PDT 24
Peak memory 249216 kb
Host smart-f2d41347-adfb-415d-9b81-a1bda4c9d997
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590628842 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_han
dler_stress_all.590628842
Directory /workspace/36.alert_handler_stress_all/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all_with_rand_reset.3178553595
Short name T66
Test name
Test status
Simulation time 38321717604 ps
CPU time 2310.91 seconds
Started Jul 13 06:25:36 PM PDT 24
Finished Jul 13 07:04:07 PM PDT 24
Peak memory 290256 kb
Host smart-55483d32-cfa1-4982-9d52-6173a1ef6569
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178553595 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 36.alert_handler_stress_all_with_rand_reset.3178553595
Directory /workspace/36.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.alert_handler_entropy.4049591935
Short name T502
Test name
Test status
Simulation time 149721405604 ps
CPU time 2336.01 seconds
Started Jul 13 06:25:34 PM PDT 24
Finished Jul 13 07:04:32 PM PDT 24
Peak memory 289392 kb
Host smart-1aa2df93-7185-494f-b93e-4e48565af1c6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049591935 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_entropy.4049591935
Directory /workspace/37.alert_handler_entropy/latest

Test location /workspace/coverage/default/37.alert_handler_esc_alert_accum.2416717495
Short name T472
Test name
Test status
Simulation time 373438860 ps
CPU time 15.61 seconds
Started Jul 13 06:25:34 PM PDT 24
Finished Jul 13 06:25:51 PM PDT 24
Peak memory 256824 kb
Host smart-bf9b5ddb-2b54-42d5-a5ce-69382eb33ee1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24167
17495 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_alert_accum.2416717495
Directory /workspace/37.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/37.alert_handler_esc_intr_timeout.2687646771
Short name T543
Test name
Test status
Simulation time 1142446622 ps
CPU time 21.66 seconds
Started Jul 13 06:25:22 PM PDT 24
Finished Jul 13 06:25:45 PM PDT 24
Peak memory 248780 kb
Host smart-1464186b-ad9e-4c82-a2bf-92bb1286b456
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26876
46771 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_intr_timeout.2687646771
Directory /workspace/37.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_lpg.121048188
Short name T303
Test name
Test status
Simulation time 445252274158 ps
CPU time 3104.86 seconds
Started Jul 13 06:25:40 PM PDT 24
Finished Jul 13 07:17:26 PM PDT 24
Peak memory 288904 kb
Host smart-7aaf96f8-46bd-4c81-81c6-c3c5f96915a2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121048188 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg.121048188
Directory /workspace/37.alert_handler_lpg/latest

Test location /workspace/coverage/default/37.alert_handler_lpg_stub_clk.1737854960
Short name T367
Test name
Test status
Simulation time 294130745887 ps
CPU time 2677.73 seconds
Started Jul 13 06:25:35 PM PDT 24
Finished Jul 13 07:10:14 PM PDT 24
Peak memory 290016 kb
Host smart-8844a3b1-0f74-4a85-8a31-5c4a5aff7f73
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737854960 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg_stub_clk.1737854960
Directory /workspace/37.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/37.alert_handler_ping_timeout.640908302
Short name T231
Test name
Test status
Simulation time 35783029044 ps
CPU time 390.11 seconds
Started Jul 13 06:25:31 PM PDT 24
Finished Jul 13 06:32:02 PM PDT 24
Peak memory 249368 kb
Host smart-2ef69cab-7b52-40cf-a39b-eff2fd23b371
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640908302 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_ping_timeout.640908302
Directory /workspace/37.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_random_alerts.2815064183
Short name T547
Test name
Test status
Simulation time 1344058624 ps
CPU time 43.9 seconds
Started Jul 13 06:25:24 PM PDT 24
Finished Jul 13 06:26:09 PM PDT 24
Peak memory 257156 kb
Host smart-ed86dda3-704f-44c5-a6d0-8ac40e5edc3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28150
64183 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_alerts.2815064183
Directory /workspace/37.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/37.alert_handler_random_classes.3017476508
Short name T491
Test name
Test status
Simulation time 301112264 ps
CPU time 28.84 seconds
Started Jul 13 06:25:25 PM PDT 24
Finished Jul 13 06:25:55 PM PDT 24
Peak memory 249204 kb
Host smart-32a08d0d-c1cf-4102-b3f1-d0f93c90b8f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30174
76508 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_classes.3017476508
Directory /workspace/37.alert_handler_random_classes/latest

Test location /workspace/coverage/default/37.alert_handler_sig_int_fail.3197848881
Short name T92
Test name
Test status
Simulation time 1374699705 ps
CPU time 39.89 seconds
Started Jul 13 06:25:36 PM PDT 24
Finished Jul 13 06:26:17 PM PDT 24
Peak memory 256960 kb
Host smart-57fb54b8-c5f1-46b6-b615-c717af8b584c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31978
48881 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_sig_int_fail.3197848881
Directory /workspace/37.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/37.alert_handler_smoke.1434353209
Short name T381
Test name
Test status
Simulation time 199029553 ps
CPU time 9.2 seconds
Started Jul 13 06:25:31 PM PDT 24
Finished Jul 13 06:25:42 PM PDT 24
Peak memory 249212 kb
Host smart-b92c211c-9e03-4ce4-b0f0-0ae9bc0df2cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14343
53209 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_smoke.1434353209
Directory /workspace/37.alert_handler_smoke/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all.2639293223
Short name T53
Test name
Test status
Simulation time 2924390332 ps
CPU time 159.15 seconds
Started Jul 13 06:25:37 PM PDT 24
Finished Jul 13 06:28:16 PM PDT 24
Peak memory 257584 kb
Host smart-4f4c712b-72a4-492b-9342-e3c5c0365c37
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639293223 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_ha
ndler_stress_all.2639293223
Directory /workspace/37.alert_handler_stress_all/latest

Test location /workspace/coverage/default/38.alert_handler_entropy.692151509
Short name T621
Test name
Test status
Simulation time 25054957269 ps
CPU time 620.14 seconds
Started Jul 13 06:25:30 PM PDT 24
Finished Jul 13 06:35:52 PM PDT 24
Peak memory 273472 kb
Host smart-c780ac4c-9acc-4571-8a7e-732d2e28e576
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692151509 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_entropy.692151509
Directory /workspace/38.alert_handler_entropy/latest

Test location /workspace/coverage/default/38.alert_handler_esc_alert_accum.3099773664
Short name T461
Test name
Test status
Simulation time 5226859739 ps
CPU time 200.43 seconds
Started Jul 13 06:25:25 PM PDT 24
Finished Jul 13 06:28:46 PM PDT 24
Peak memory 257620 kb
Host smart-2a9c60c1-1172-4727-b337-0bc890c1b4ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30997
73664 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_alert_accum.3099773664
Directory /workspace/38.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/38.alert_handler_esc_intr_timeout.3439098118
Short name T507
Test name
Test status
Simulation time 1450717872 ps
CPU time 22.48 seconds
Started Jul 13 06:25:31 PM PDT 24
Finished Jul 13 06:25:54 PM PDT 24
Peak memory 255644 kb
Host smart-259c588b-e90d-4fc2-9b0a-8fc258a72189
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34390
98118 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_intr_timeout.3439098118
Directory /workspace/38.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_lpg.3941057722
Short name T329
Test name
Test status
Simulation time 92627027718 ps
CPU time 2568.87 seconds
Started Jul 13 06:25:27 PM PDT 24
Finished Jul 13 07:08:17 PM PDT 24
Peak memory 283856 kb
Host smart-86523964-70a2-49f4-9df4-dd75a747565b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941057722 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg.3941057722
Directory /workspace/38.alert_handler_lpg/latest

Test location /workspace/coverage/default/38.alert_handler_lpg_stub_clk.2750767208
Short name T254
Test name
Test status
Simulation time 48052306108 ps
CPU time 1390.78 seconds
Started Jul 13 06:25:38 PM PDT 24
Finished Jul 13 06:48:50 PM PDT 24
Peak memory 288940 kb
Host smart-3b3071ae-0437-4bad-a90e-f2e4c1f296ea
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2750767208 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg_stub_clk.2750767208
Directory /workspace/38.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/38.alert_handler_ping_timeout.3859886205
Short name T291
Test name
Test status
Simulation time 11101070586 ps
CPU time 447.05 seconds
Started Jul 13 06:25:25 PM PDT 24
Finished Jul 13 06:32:53 PM PDT 24
Peak memory 249380 kb
Host smart-369cf820-c465-4bd9-9dc9-81eb902328a0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859886205 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_ping_timeout.3859886205
Directory /workspace/38.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_random_alerts.2556174153
Short name T641
Test name
Test status
Simulation time 822435763 ps
CPU time 54.71 seconds
Started Jul 13 06:25:26 PM PDT 24
Finished Jul 13 06:26:21 PM PDT 24
Peak memory 256616 kb
Host smart-49caf15b-10cc-44fa-949e-dd3ed22a1eed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25561
74153 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_alerts.2556174153
Directory /workspace/38.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/38.alert_handler_random_classes.3476837770
Short name T401
Test name
Test status
Simulation time 1439465519 ps
CPU time 26.2 seconds
Started Jul 13 06:25:30 PM PDT 24
Finished Jul 13 06:25:57 PM PDT 24
Peak memory 248700 kb
Host smart-d6d104b4-5195-48ab-a7f0-87aca4d7be68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34768
37770 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_classes.3476837770
Directory /workspace/38.alert_handler_random_classes/latest

Test location /workspace/coverage/default/38.alert_handler_smoke.431261076
Short name T493
Test name
Test status
Simulation time 2728253390 ps
CPU time 16.06 seconds
Started Jul 13 06:25:29 PM PDT 24
Finished Jul 13 06:25:46 PM PDT 24
Peak memory 255996 kb
Host smart-95d53e64-70e0-486c-8208-104240b3a351
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43126
1076 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_smoke.431261076
Directory /workspace/38.alert_handler_smoke/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all.373096278
Short name T476
Test name
Test status
Simulation time 19274889707 ps
CPU time 1707.22 seconds
Started Jul 13 06:25:25 PM PDT 24
Finished Jul 13 06:53:54 PM PDT 24
Peak memory 289936 kb
Host smart-3e269a50-057c-4a5b-914b-b97d7c46ea2a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373096278 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_han
dler_stress_all.373096278
Directory /workspace/38.alert_handler_stress_all/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all_with_rand_reset.1134741813
Short name T49
Test name
Test status
Simulation time 81059986423 ps
CPU time 2430.13 seconds
Started Jul 13 06:25:25 PM PDT 24
Finished Jul 13 07:05:57 PM PDT 24
Peak memory 289884 kb
Host smart-0a97ca71-0320-4529-8e29-f57ef4766fff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134741813 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 38.alert_handler_stress_all_with_rand_reset.1134741813
Directory /workspace/38.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.alert_handler_entropy.3100940064
Short name T506
Test name
Test status
Simulation time 233248384778 ps
CPU time 3527.09 seconds
Started Jul 13 06:25:29 PM PDT 24
Finished Jul 13 07:24:17 PM PDT 24
Peak memory 290004 kb
Host smart-4092e01e-a1be-480a-b7d6-2378bfeba81a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100940064 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_entropy.3100940064
Directory /workspace/39.alert_handler_entropy/latest

Test location /workspace/coverage/default/39.alert_handler_esc_alert_accum.1375197737
Short name T585
Test name
Test status
Simulation time 1078489194 ps
CPU time 40.52 seconds
Started Jul 13 06:25:24 PM PDT 24
Finished Jul 13 06:26:06 PM PDT 24
Peak memory 250328 kb
Host smart-0ebe3d34-8a42-4cf3-a558-569b83377241
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13751
97737 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_alert_accum.1375197737
Directory /workspace/39.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/39.alert_handler_esc_intr_timeout.150029548
Short name T84
Test name
Test status
Simulation time 1543031871 ps
CPU time 28.48 seconds
Started Jul 13 06:25:34 PM PDT 24
Finished Jul 13 06:26:04 PM PDT 24
Peak memory 256824 kb
Host smart-a4cf1370-6398-435f-b892-73b5968baf10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15002
9548 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_intr_timeout.150029548
Directory /workspace/39.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_lpg_stub_clk.2944800075
Short name T456
Test name
Test status
Simulation time 73059117424 ps
CPU time 1441.76 seconds
Started Jul 13 06:25:38 PM PDT 24
Finished Jul 13 06:49:41 PM PDT 24
Peak memory 289432 kb
Host smart-079dbfe7-f9ee-444a-b0f8-8ea4467b8cef
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944800075 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg_stub_clk.2944800075
Directory /workspace/39.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/39.alert_handler_ping_timeout.2748063765
Short name T289
Test name
Test status
Simulation time 6199471171 ps
CPU time 238.96 seconds
Started Jul 13 06:25:41 PM PDT 24
Finished Jul 13 06:29:40 PM PDT 24
Peak memory 249268 kb
Host smart-3da29674-0fe2-4937-9a5f-5c5d17f66c81
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748063765 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_ping_timeout.2748063765
Directory /workspace/39.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_random_alerts.1476855648
Short name T706
Test name
Test status
Simulation time 3793242920 ps
CPU time 54.67 seconds
Started Jul 13 06:25:34 PM PDT 24
Finished Jul 13 06:26:30 PM PDT 24
Peak memory 249352 kb
Host smart-5b1cd18f-8d61-471b-b7d2-ae1ec1d15be3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14768
55648 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_alerts.1476855648
Directory /workspace/39.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/39.alert_handler_random_classes.1131587187
Short name T529
Test name
Test status
Simulation time 249619973 ps
CPU time 31.01 seconds
Started Jul 13 06:25:28 PM PDT 24
Finished Jul 13 06:26:00 PM PDT 24
Peak memory 256976 kb
Host smart-6433b19a-1a81-4ee9-b51a-08d5b47bef4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11315
87187 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_classes.1131587187
Directory /workspace/39.alert_handler_random_classes/latest

Test location /workspace/coverage/default/39.alert_handler_sig_int_fail.3040779677
Short name T265
Test name
Test status
Simulation time 2909112718 ps
CPU time 52.73 seconds
Started Jul 13 06:25:32 PM PDT 24
Finished Jul 13 06:26:27 PM PDT 24
Peak memory 249400 kb
Host smart-303feed5-57c0-4c40-9089-2e66b31cef06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30407
79677 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_sig_int_fail.3040779677
Directory /workspace/39.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/39.alert_handler_smoke.723080940
Short name T645
Test name
Test status
Simulation time 955720020 ps
CPU time 62.35 seconds
Started Jul 13 06:25:36 PM PDT 24
Finished Jul 13 06:26:39 PM PDT 24
Peak memory 257252 kb
Host smart-2604b14b-a4c0-46ef-b502-22360cccead3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72308
0940 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_smoke.723080940
Directory /workspace/39.alert_handler_smoke/latest

Test location /workspace/coverage/default/4.alert_handler_alert_accum_saturation.3290793896
Short name T210
Test name
Test status
Simulation time 65377868 ps
CPU time 3.29 seconds
Started Jul 13 06:24:35 PM PDT 24
Finished Jul 13 06:24:39 PM PDT 24
Peak memory 249528 kb
Host smart-5722c0c9-cccb-4b36-b95b-19798fd83c8d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3290793896 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_alert_accum_saturation.3290793896
Directory /workspace/4.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/4.alert_handler_entropy.3304402204
Short name T636
Test name
Test status
Simulation time 193337964557 ps
CPU time 2665.85 seconds
Started Jul 13 06:24:40 PM PDT 24
Finished Jul 13 07:09:08 PM PDT 24
Peak memory 287456 kb
Host smart-887bafae-48d0-478e-9747-ca2ae1cae1ac
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304402204 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy.3304402204
Directory /workspace/4.alert_handler_entropy/latest

Test location /workspace/coverage/default/4.alert_handler_entropy_stress.954423897
Short name T648
Test name
Test status
Simulation time 830620629 ps
CPU time 19.85 seconds
Started Jul 13 06:24:29 PM PDT 24
Finished Jul 13 06:24:50 PM PDT 24
Peak memory 249140 kb
Host smart-ff1187ee-8ada-4dec-bb4a-7f905a673df7
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=954423897 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy_stress.954423897
Directory /workspace/4.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/4.alert_handler_esc_alert_accum.346666116
Short name T517
Test name
Test status
Simulation time 820069630 ps
CPU time 25.91 seconds
Started Jul 13 06:24:37 PM PDT 24
Finished Jul 13 06:25:04 PM PDT 24
Peak memory 256992 kb
Host smart-2290eabd-fe09-447b-a9ac-d345144e1f9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34666
6116 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_alert_accum.346666116
Directory /workspace/4.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/4.alert_handler_esc_intr_timeout.1366936100
Short name T83
Test name
Test status
Simulation time 1635008610 ps
CPU time 47.91 seconds
Started Jul 13 06:24:35 PM PDT 24
Finished Jul 13 06:25:24 PM PDT 24
Peak memory 249216 kb
Host smart-7bd2d2b0-4854-4327-ae9d-6e69fb3ad6d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13669
36100 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_intr_timeout.1366936100
Directory /workspace/4.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_lpg.3525172843
Short name T264
Test name
Test status
Simulation time 529074750416 ps
CPU time 2378.08 seconds
Started Jul 13 06:24:35 PM PDT 24
Finished Jul 13 07:04:15 PM PDT 24
Peak memory 284508 kb
Host smart-8fce1132-ea4a-4f4d-b5e7-111cd8949068
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525172843 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg.3525172843
Directory /workspace/4.alert_handler_lpg/latest

Test location /workspace/coverage/default/4.alert_handler_lpg_stub_clk.3401780798
Short name T37
Test name
Test status
Simulation time 115559941825 ps
CPU time 1607.29 seconds
Started Jul 13 06:24:33 PM PDT 24
Finished Jul 13 06:51:22 PM PDT 24
Peak memory 273824 kb
Host smart-2839fd09-ef0a-44e9-ab07-7356dc3d529d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401780798 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg_stub_clk.3401780798
Directory /workspace/4.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/4.alert_handler_ping_timeout.1059245356
Short name T284
Test name
Test status
Simulation time 25375614841 ps
CPU time 276.92 seconds
Started Jul 13 06:24:45 PM PDT 24
Finished Jul 13 06:29:24 PM PDT 24
Peak memory 256396 kb
Host smart-66079586-27fc-4200-8cd8-98429d3f32d9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059245356 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_ping_timeout.1059245356
Directory /workspace/4.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_random_alerts.4233569881
Short name T433
Test name
Test status
Simulation time 661013100 ps
CPU time 41.96 seconds
Started Jul 13 06:24:32 PM PDT 24
Finished Jul 13 06:25:15 PM PDT 24
Peak memory 256864 kb
Host smart-684baefd-98d1-45b0-b6af-d58f3074cef9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42335
69881 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_alerts.4233569881
Directory /workspace/4.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/4.alert_handler_random_classes.3399156713
Short name T427
Test name
Test status
Simulation time 415917072 ps
CPU time 6.63 seconds
Started Jul 13 06:24:36 PM PDT 24
Finished Jul 13 06:24:44 PM PDT 24
Peak memory 249284 kb
Host smart-f0b28dde-6db8-40c8-8bed-90341637996f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33991
56713 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_classes.3399156713
Directory /workspace/4.alert_handler_random_classes/latest

Test location /workspace/coverage/default/4.alert_handler_sec_cm.4035555596
Short name T12
Test name
Test status
Simulation time 632308010 ps
CPU time 21.13 seconds
Started Jul 13 06:24:40 PM PDT 24
Finished Jul 13 06:25:04 PM PDT 24
Peak memory 270528 kb
Host smart-8ec4f6a7-e877-4e33-a8d0-5096a05e73ca
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4035555596 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sec_cm.4035555596
Directory /workspace/4.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/4.alert_handler_sig_int_fail.691672169
Short name T420
Test name
Test status
Simulation time 2988792300 ps
CPU time 45.25 seconds
Started Jul 13 06:24:36 PM PDT 24
Finished Jul 13 06:25:22 PM PDT 24
Peak memory 256664 kb
Host smart-d5b7b4b3-a8de-481a-b422-fe4783e43116
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69167
2169 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sig_int_fail.691672169
Directory /workspace/4.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/4.alert_handler_smoke.3225808483
Short name T60
Test name
Test status
Simulation time 476511701 ps
CPU time 28.99 seconds
Started Jul 13 06:24:41 PM PDT 24
Finished Jul 13 06:25:12 PM PDT 24
Peak memory 256804 kb
Host smart-bd204020-6a33-461d-afa1-07ad9cf5361a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32258
08483 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_smoke.3225808483
Directory /workspace/4.alert_handler_smoke/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all.2806182314
Short name T31
Test name
Test status
Simulation time 17255648620 ps
CPU time 1258.23 seconds
Started Jul 13 06:24:41 PM PDT 24
Finished Jul 13 06:45:41 PM PDT 24
Peak memory 287180 kb
Host smart-4365b70c-ed07-49c8-be78-118cb7296aba
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806182314 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_han
dler_stress_all.2806182314
Directory /workspace/4.alert_handler_stress_all/latest

Test location /workspace/coverage/default/40.alert_handler_entropy.680720192
Short name T115
Test name
Test status
Simulation time 68889803270 ps
CPU time 1177.28 seconds
Started Jul 13 06:25:42 PM PDT 24
Finished Jul 13 06:45:20 PM PDT 24
Peak memory 268960 kb
Host smart-e7b4d2a5-1c83-4f6e-860d-d8f06d9ed50c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=680720192 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_entropy.680720192
Directory /workspace/40.alert_handler_entropy/latest

Test location /workspace/coverage/default/40.alert_handler_esc_alert_accum.1590868263
Short name T388
Test name
Test status
Simulation time 1885194656 ps
CPU time 32.2 seconds
Started Jul 13 06:25:33 PM PDT 24
Finished Jul 13 06:26:06 PM PDT 24
Peak memory 256972 kb
Host smart-256c2125-c665-4444-9349-770fe5b9f3b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15908
68263 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_alert_accum.1590868263
Directory /workspace/40.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/40.alert_handler_esc_intr_timeout.2217982798
Short name T552
Test name
Test status
Simulation time 696335321 ps
CPU time 44.14 seconds
Started Jul 13 06:25:34 PM PDT 24
Finished Jul 13 06:26:19 PM PDT 24
Peak memory 256944 kb
Host smart-b2ac28fc-9693-4d37-96f6-a0bc19a848c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22179
82798 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_intr_timeout.2217982798
Directory /workspace/40.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_lpg_stub_clk.4027906183
Short name T261
Test name
Test status
Simulation time 81091730850 ps
CPU time 2010.61 seconds
Started Jul 13 06:25:41 PM PDT 24
Finished Jul 13 06:59:13 PM PDT 24
Peak memory 285540 kb
Host smart-7adb3eee-d67a-43fc-b7f8-bf020b061ecc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4027906183 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg_stub_clk.4027906183
Directory /workspace/40.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/40.alert_handler_ping_timeout.1320558631
Short name T90
Test name
Test status
Simulation time 6547706892 ps
CPU time 285.68 seconds
Started Jul 13 06:25:33 PM PDT 24
Finished Jul 13 06:30:20 PM PDT 24
Peak memory 255476 kb
Host smart-aedaed3c-40bc-4fe6-bdca-92f8cd8e3cab
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1320558631 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_ping_timeout.1320558631
Directory /workspace/40.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_random_alerts.1494235549
Short name T473
Test name
Test status
Simulation time 565166592 ps
CPU time 42.26 seconds
Started Jul 13 06:25:33 PM PDT 24
Finished Jul 13 06:26:17 PM PDT 24
Peak memory 249292 kb
Host smart-1735b073-7dfd-4722-96e7-12b4e2b5fa30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14942
35549 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_alerts.1494235549
Directory /workspace/40.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/40.alert_handler_random_classes.2835108332
Short name T24
Test name
Test status
Simulation time 4300455341 ps
CPU time 53.19 seconds
Started Jul 13 06:25:33 PM PDT 24
Finished Jul 13 06:26:27 PM PDT 24
Peak memory 249324 kb
Host smart-47bbf35b-6a9d-40fb-9a31-af0d9b0484c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28351
08332 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_classes.2835108332
Directory /workspace/40.alert_handler_random_classes/latest

Test location /workspace/coverage/default/40.alert_handler_sig_int_fail.669090668
Short name T95
Test name
Test status
Simulation time 777940821 ps
CPU time 42.87 seconds
Started Jul 13 06:25:35 PM PDT 24
Finished Jul 13 06:26:19 PM PDT 24
Peak memory 248468 kb
Host smart-3b9b7e2e-6cb0-4430-9386-db2b07714d8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66909
0668 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_sig_int_fail.669090668
Directory /workspace/40.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/40.alert_handler_smoke.1154371079
Short name T598
Test name
Test status
Simulation time 151199387 ps
CPU time 14.52 seconds
Started Jul 13 06:25:36 PM PDT 24
Finished Jul 13 06:25:51 PM PDT 24
Peak memory 255824 kb
Host smart-4a78a932-4189-44d8-bdcc-2da3e5090d4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11543
71079 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_smoke.1154371079
Directory /workspace/40.alert_handler_smoke/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all.3441709775
Short name T509
Test name
Test status
Simulation time 158104924354 ps
CPU time 2216.71 seconds
Started Jul 13 06:29:37 PM PDT 24
Finished Jul 13 07:06:34 PM PDT 24
Peak memory 273968 kb
Host smart-42ddcf73-690a-4d04-a8ea-e7ac8aafef32
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441709775 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_ha
ndler_stress_all.3441709775
Directory /workspace/40.alert_handler_stress_all/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all_with_rand_reset.1417592475
Short name T104
Test name
Test status
Simulation time 33091343974 ps
CPU time 1350.86 seconds
Started Jul 13 06:25:39 PM PDT 24
Finished Jul 13 06:48:11 PM PDT 24
Peak memory 282380 kb
Host smart-0ef96714-512d-4e19-81cc-e6b9ee4dddf2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417592475 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 40.alert_handler_stress_all_with_rand_reset.1417592475
Directory /workspace/40.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.alert_handler_entropy.3797462978
Short name T52
Test name
Test status
Simulation time 107561012598 ps
CPU time 1467.19 seconds
Started Jul 13 06:25:42 PM PDT 24
Finished Jul 13 06:50:10 PM PDT 24
Peak memory 287952 kb
Host smart-686f9d76-51ca-4ca5-93f1-4d851eb07425
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797462978 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_entropy.3797462978
Directory /workspace/41.alert_handler_entropy/latest

Test location /workspace/coverage/default/41.alert_handler_esc_alert_accum.302002414
Short name T270
Test name
Test status
Simulation time 8336363632 ps
CPU time 115.98 seconds
Started Jul 13 06:25:40 PM PDT 24
Finished Jul 13 06:27:36 PM PDT 24
Peak memory 257176 kb
Host smart-4c681bad-fa66-4ac1-a2e1-71d8144c9030
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30200
2414 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_alert_accum.302002414
Directory /workspace/41.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/41.alert_handler_esc_intr_timeout.186977316
Short name T230
Test name
Test status
Simulation time 651953232 ps
CPU time 49.58 seconds
Started Jul 13 06:25:41 PM PDT 24
Finished Jul 13 06:26:31 PM PDT 24
Peak memory 257416 kb
Host smart-fd2b2bea-77d1-4879-965f-e7cacae99953
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18697
7316 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_intr_timeout.186977316
Directory /workspace/41.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_lpg.3778666970
Short name T541
Test name
Test status
Simulation time 10568498137 ps
CPU time 1085.85 seconds
Started Jul 13 06:25:46 PM PDT 24
Finished Jul 13 06:43:53 PM PDT 24
Peak memory 273364 kb
Host smart-2eb97f03-da18-4f37-82a6-f8968671b553
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778666970 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg.3778666970
Directory /workspace/41.alert_handler_lpg/latest

Test location /workspace/coverage/default/41.alert_handler_lpg_stub_clk.3876127942
Short name T382
Test name
Test status
Simulation time 124539243915 ps
CPU time 1981.27 seconds
Started Jul 13 06:25:42 PM PDT 24
Finished Jul 13 06:58:44 PM PDT 24
Peak memory 290092 kb
Host smart-67ad2814-c0a1-4674-a75e-3192db81d7b0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876127942 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg_stub_clk.3876127942
Directory /workspace/41.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/41.alert_handler_ping_timeout.3345507715
Short name T7
Test name
Test status
Simulation time 7750229514 ps
CPU time 346.49 seconds
Started Jul 13 06:25:45 PM PDT 24
Finished Jul 13 06:31:32 PM PDT 24
Peak memory 256372 kb
Host smart-99416946-a77f-47c2-bc6c-6bc689eb818c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3345507715 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_ping_timeout.3345507715
Directory /workspace/41.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_random_alerts.1589538166
Short name T700
Test name
Test status
Simulation time 135018598 ps
CPU time 14.96 seconds
Started Jul 13 06:25:41 PM PDT 24
Finished Jul 13 06:25:57 PM PDT 24
Peak memory 256664 kb
Host smart-037a1979-3ada-46f9-99e3-e6c7d2971f9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15895
38166 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_alerts.1589538166
Directory /workspace/41.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/41.alert_handler_random_classes.2611123061
Short name T693
Test name
Test status
Simulation time 1950969865 ps
CPU time 36.04 seconds
Started Jul 13 06:25:45 PM PDT 24
Finished Jul 13 06:26:22 PM PDT 24
Peak memory 249284 kb
Host smart-1c4edcba-7f1c-435f-9068-2ff69b56131f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26111
23061 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_classes.2611123061
Directory /workspace/41.alert_handler_random_classes/latest

Test location /workspace/coverage/default/41.alert_handler_sig_int_fail.1899025973
Short name T409
Test name
Test status
Simulation time 33787269 ps
CPU time 4.29 seconds
Started Jul 13 06:25:40 PM PDT 24
Finished Jul 13 06:25:45 PM PDT 24
Peak memory 248584 kb
Host smart-432af327-cb09-490d-b477-8b854760b247
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18990
25973 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_sig_int_fail.1899025973
Directory /workspace/41.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/41.alert_handler_smoke.4079342824
Short name T558
Test name
Test status
Simulation time 704110929 ps
CPU time 47.94 seconds
Started Jul 13 06:25:45 PM PDT 24
Finished Jul 13 06:26:33 PM PDT 24
Peak memory 256740 kb
Host smart-5f77002f-8c1c-4b85-9cc4-cf88fa272e1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40793
42824 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_smoke.4079342824
Directory /workspace/41.alert_handler_smoke/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all.701648999
Short name T56
Test name
Test status
Simulation time 30369688243 ps
CPU time 1787.31 seconds
Started Jul 13 06:25:47 PM PDT 24
Finished Jul 13 06:55:35 PM PDT 24
Peak memory 282572 kb
Host smart-6e8c8457-f982-4b38-a7e1-fafa20c7bdc4
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701648999 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_han
dler_stress_all.701648999
Directory /workspace/41.alert_handler_stress_all/latest

Test location /workspace/coverage/default/42.alert_handler_entropy.2294499464
Short name T236
Test name
Test status
Simulation time 52564100351 ps
CPU time 1605.24 seconds
Started Jul 13 06:25:46 PM PDT 24
Finished Jul 13 06:52:32 PM PDT 24
Peak memory 273976 kb
Host smart-13532131-9ac8-4bda-a47a-dcaba8c7e786
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294499464 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_entropy.2294499464
Directory /workspace/42.alert_handler_entropy/latest

Test location /workspace/coverage/default/42.alert_handler_esc_alert_accum.2035841727
Short name T695
Test name
Test status
Simulation time 843031499 ps
CPU time 21.19 seconds
Started Jul 13 06:25:42 PM PDT 24
Finished Jul 13 06:26:04 PM PDT 24
Peak memory 256924 kb
Host smart-14e1a568-d27b-4f32-8b9d-6f794a51bde9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20358
41727 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_alert_accum.2035841727
Directory /workspace/42.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/42.alert_handler_esc_intr_timeout.3662513745
Short name T399
Test name
Test status
Simulation time 324829527 ps
CPU time 30.8 seconds
Started Jul 13 06:25:44 PM PDT 24
Finished Jul 13 06:26:15 PM PDT 24
Peak memory 256036 kb
Host smart-a3635f9a-f4ea-4a2f-bcf2-c2aaca8283d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36625
13745 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_intr_timeout.3662513745
Directory /workspace/42.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_lpg.1020892372
Short name T325
Test name
Test status
Simulation time 32090190686 ps
CPU time 1816.69 seconds
Started Jul 13 06:25:46 PM PDT 24
Finished Jul 13 06:56:04 PM PDT 24
Peak memory 273136 kb
Host smart-06a7c8c2-9db9-407c-9b2f-f1d3bd4d268c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020892372 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg.1020892372
Directory /workspace/42.alert_handler_lpg/latest

Test location /workspace/coverage/default/42.alert_handler_lpg_stub_clk.4117721225
Short name T214
Test name
Test status
Simulation time 18630054369 ps
CPU time 1226.94 seconds
Started Jul 13 06:25:50 PM PDT 24
Finished Jul 13 06:46:17 PM PDT 24
Peak memory 273340 kb
Host smart-afe99639-ebde-4074-b249-b9c52da64d89
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117721225 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg_stub_clk.4117721225
Directory /workspace/42.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/42.alert_handler_ping_timeout.271610781
Short name T466
Test name
Test status
Simulation time 22699896859 ps
CPU time 307.02 seconds
Started Jul 13 06:25:46 PM PDT 24
Finished Jul 13 06:30:54 PM PDT 24
Peak memory 249408 kb
Host smart-e121b9f5-0ef9-455f-a0a4-ff0415357b99
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271610781 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_ping_timeout.271610781
Directory /workspace/42.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_random_alerts.2698164089
Short name T513
Test name
Test status
Simulation time 143068173 ps
CPU time 12.87 seconds
Started Jul 13 06:25:45 PM PDT 24
Finished Jul 13 06:25:58 PM PDT 24
Peak memory 256464 kb
Host smart-c7be570e-397d-477c-800f-eb2aaaf758a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26981
64089 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_alerts.2698164089
Directory /workspace/42.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/42.alert_handler_random_classes.1148375638
Short name T394
Test name
Test status
Simulation time 431624163 ps
CPU time 11.48 seconds
Started Jul 13 06:25:41 PM PDT 24
Finished Jul 13 06:25:53 PM PDT 24
Peak memory 248604 kb
Host smart-af5dd508-9609-4e6f-b96e-adfb14975412
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11483
75638 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_classes.1148375638
Directory /workspace/42.alert_handler_random_classes/latest

Test location /workspace/coverage/default/42.alert_handler_sig_int_fail.1861664725
Short name T429
Test name
Test status
Simulation time 652432606 ps
CPU time 39.01 seconds
Started Jul 13 06:25:46 PM PDT 24
Finished Jul 13 06:26:26 PM PDT 24
Peak memory 257328 kb
Host smart-09b9208d-2ef4-443e-a7b2-c2abc31daea9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18616
64725 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_sig_int_fail.1861664725
Directory /workspace/42.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/42.alert_handler_smoke.732453919
Short name T599
Test name
Test status
Simulation time 352122318 ps
CPU time 31.13 seconds
Started Jul 13 06:25:40 PM PDT 24
Finished Jul 13 06:26:12 PM PDT 24
Peak memory 257284 kb
Host smart-d43619e8-699a-419d-88cd-935950ff7c72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73245
3919 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_smoke.732453919
Directory /workspace/42.alert_handler_smoke/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all.2729426872
Short name T468
Test name
Test status
Simulation time 72093230577 ps
CPU time 1386.69 seconds
Started Jul 13 06:25:47 PM PDT 24
Finished Jul 13 06:48:55 PM PDT 24
Peak memory 273320 kb
Host smart-0a4892ec-20ce-4891-88da-50b3829aea5a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729426872 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_ha
ndler_stress_all.2729426872
Directory /workspace/42.alert_handler_stress_all/latest

Test location /workspace/coverage/default/43.alert_handler_entropy.3155278306
Short name T277
Test name
Test status
Simulation time 16488361409 ps
CPU time 1302.05 seconds
Started Jul 13 06:25:54 PM PDT 24
Finished Jul 13 06:47:37 PM PDT 24
Peak memory 289936 kb
Host smart-1cfbdc66-86da-4dbc-b79f-2328cb5f988f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155278306 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_entropy.3155278306
Directory /workspace/43.alert_handler_entropy/latest

Test location /workspace/coverage/default/43.alert_handler_esc_alert_accum.555285949
Short name T505
Test name
Test status
Simulation time 21932136908 ps
CPU time 344.46 seconds
Started Jul 13 06:25:48 PM PDT 24
Finished Jul 13 06:31:33 PM PDT 24
Peak memory 257116 kb
Host smart-b9729d41-d6a0-4a56-bd80-4dd91efbd7be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55528
5949 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_alert_accum.555285949
Directory /workspace/43.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/43.alert_handler_esc_intr_timeout.4034573092
Short name T479
Test name
Test status
Simulation time 593520171 ps
CPU time 19.26 seconds
Started Jul 13 06:25:47 PM PDT 24
Finished Jul 13 06:26:07 PM PDT 24
Peak memory 249208 kb
Host smart-7eba1ff7-8fe6-4933-b648-58a797abc389
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40345
73092 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_intr_timeout.4034573092
Directory /workspace/43.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_lpg.811694947
Short name T328
Test name
Test status
Simulation time 111666783063 ps
CPU time 2425.52 seconds
Started Jul 13 06:25:54 PM PDT 24
Finished Jul 13 07:06:21 PM PDT 24
Peak memory 282164 kb
Host smart-6c550138-3051-4462-a6e4-509036ef4d73
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811694947 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg.811694947
Directory /workspace/43.alert_handler_lpg/latest

Test location /workspace/coverage/default/43.alert_handler_lpg_stub_clk.1892331186
Short name T99
Test name
Test status
Simulation time 23464375881 ps
CPU time 1176.72 seconds
Started Jul 13 06:25:52 PM PDT 24
Finished Jul 13 06:45:29 PM PDT 24
Peak memory 282152 kb
Host smart-fa75eac8-4d4d-4ad8-8cc3-6e58e5a9f01b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892331186 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg_stub_clk.1892331186
Directory /workspace/43.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/43.alert_handler_ping_timeout.1651216737
Short name T292
Test name
Test status
Simulation time 10299910520 ps
CPU time 428.44 seconds
Started Jul 13 06:25:54 PM PDT 24
Finished Jul 13 06:33:03 PM PDT 24
Peak memory 249308 kb
Host smart-dc801190-fe56-4b6d-b113-d9f543089975
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651216737 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_ping_timeout.1651216737
Directory /workspace/43.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_random_alerts.3580799717
Short name T50
Test name
Test status
Simulation time 346827532 ps
CPU time 25.24 seconds
Started Jul 13 06:25:46 PM PDT 24
Finished Jul 13 06:26:12 PM PDT 24
Peak memory 249228 kb
Host smart-05c45df0-47ea-469f-b3b5-c1761da37a30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35807
99717 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_alerts.3580799717
Directory /workspace/43.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/43.alert_handler_random_classes.591400262
Short name T256
Test name
Test status
Simulation time 449838093 ps
CPU time 11.59 seconds
Started Jul 13 06:25:45 PM PDT 24
Finished Jul 13 06:25:57 PM PDT 24
Peak memory 255664 kb
Host smart-ce2f8e07-0db0-4b13-85d3-3528c80b8cc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59140
0262 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_classes.591400262
Directory /workspace/43.alert_handler_random_classes/latest

Test location /workspace/coverage/default/43.alert_handler_sig_int_fail.775418264
Short name T580
Test name
Test status
Simulation time 556943330 ps
CPU time 41.07 seconds
Started Jul 13 06:25:48 PM PDT 24
Finished Jul 13 06:26:29 PM PDT 24
Peak memory 248628 kb
Host smart-f947ed4c-f49c-46f6-b3b5-a2d1dcbf2cfa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77541
8264 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_sig_int_fail.775418264
Directory /workspace/43.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/43.alert_handler_smoke.3349781396
Short name T393
Test name
Test status
Simulation time 480422556 ps
CPU time 32.91 seconds
Started Jul 13 06:25:48 PM PDT 24
Finished Jul 13 06:26:21 PM PDT 24
Peak memory 257424 kb
Host smart-b6fdd84c-8615-4ae3-b363-c83fab11f267
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33497
81396 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_smoke.3349781396
Directory /workspace/43.alert_handler_smoke/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all.1045242819
Short name T241
Test name
Test status
Simulation time 154258771448 ps
CPU time 3763.5 seconds
Started Jul 13 06:25:54 PM PDT 24
Finished Jul 13 07:28:38 PM PDT 24
Peak memory 299284 kb
Host smart-4d71cf8d-bb46-42d0-a2ed-3316c4ecc337
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045242819 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_ha
ndler_stress_all.1045242819
Directory /workspace/43.alert_handler_stress_all/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all_with_rand_reset.944280977
Short name T629
Test name
Test status
Simulation time 25324797926 ps
CPU time 1518.17 seconds
Started Jul 13 06:25:55 PM PDT 24
Finished Jul 13 06:51:14 PM PDT 24
Peak memory 290020 kb
Host smart-502f6147-aba4-4f2a-87c0-54c432d3a1c4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944280977 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 43.alert_handler_stress_all_with_rand_reset.944280977
Directory /workspace/43.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.alert_handler_entropy.2318760973
Short name T637
Test name
Test status
Simulation time 189384813468 ps
CPU time 1166.18 seconds
Started Jul 13 06:25:54 PM PDT 24
Finished Jul 13 06:45:21 PM PDT 24
Peak memory 273472 kb
Host smart-1235f711-fe04-4a85-ac79-452e97016f0b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318760973 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_entropy.2318760973
Directory /workspace/44.alert_handler_entropy/latest

Test location /workspace/coverage/default/44.alert_handler_esc_alert_accum.3558352476
Short name T673
Test name
Test status
Simulation time 1128774749 ps
CPU time 47.86 seconds
Started Jul 13 06:25:55 PM PDT 24
Finished Jul 13 06:26:44 PM PDT 24
Peak memory 257000 kb
Host smart-c9107907-06bb-442d-ae01-08af5fcc4513
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35583
52476 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_alert_accum.3558352476
Directory /workspace/44.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/44.alert_handler_esc_intr_timeout.1091691589
Short name T89
Test name
Test status
Simulation time 3385751066 ps
CPU time 53.77 seconds
Started Jul 13 06:25:53 PM PDT 24
Finished Jul 13 06:26:47 PM PDT 24
Peak memory 256640 kb
Host smart-d786ea24-788a-4c62-961d-bfe5a67fd213
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10916
91589 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_intr_timeout.1091691589
Directory /workspace/44.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_lpg.3925170761
Short name T338
Test name
Test status
Simulation time 41702692097 ps
CPU time 1121.31 seconds
Started Jul 13 06:25:55 PM PDT 24
Finished Jul 13 06:44:37 PM PDT 24
Peak memory 273056 kb
Host smart-5b18aa62-4316-4bb8-bb65-85ba53622840
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3925170761 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg.3925170761
Directory /workspace/44.alert_handler_lpg/latest

Test location /workspace/coverage/default/44.alert_handler_lpg_stub_clk.3888732572
Short name T578
Test name
Test status
Simulation time 113357396744 ps
CPU time 1732.47 seconds
Started Jul 13 06:25:54 PM PDT 24
Finished Jul 13 06:54:48 PM PDT 24
Peak memory 273604 kb
Host smart-36902c34-d731-4888-ad09-05edbc915ad2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888732572 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg_stub_clk.3888732572
Directory /workspace/44.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/44.alert_handler_ping_timeout.31187214
Short name T293
Test name
Test status
Simulation time 14239793671 ps
CPU time 309.58 seconds
Started Jul 13 06:25:55 PM PDT 24
Finished Jul 13 06:31:05 PM PDT 24
Peak memory 249368 kb
Host smart-63453bfa-dc84-44e8-929a-346ba75681c7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31187214 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_ping_timeout.31187214
Directory /workspace/44.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_random_alerts.3594345645
Short name T675
Test name
Test status
Simulation time 224287843 ps
CPU time 7.69 seconds
Started Jul 13 06:25:54 PM PDT 24
Finished Jul 13 06:26:03 PM PDT 24
Peak memory 249200 kb
Host smart-13518a42-e9eb-4653-8ec9-dc5b47d14bde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35943
45645 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_alerts.3594345645
Directory /workspace/44.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/44.alert_handler_random_classes.3413985435
Short name T665
Test name
Test status
Simulation time 335309520 ps
CPU time 6.81 seconds
Started Jul 13 06:25:54 PM PDT 24
Finished Jul 13 06:26:02 PM PDT 24
Peak memory 252392 kb
Host smart-d85a5c03-9b37-4812-b28a-77872d5603cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34139
85435 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_classes.3413985435
Directory /workspace/44.alert_handler_random_classes/latest

Test location /workspace/coverage/default/44.alert_handler_smoke.2119822965
Short name T704
Test name
Test status
Simulation time 2971887282 ps
CPU time 31.26 seconds
Started Jul 13 06:25:53 PM PDT 24
Finished Jul 13 06:26:25 PM PDT 24
Peak memory 257540 kb
Host smart-4732a42a-fbbc-48b6-bd75-32ac7deaf482
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21198
22965 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_smoke.2119822965
Directory /workspace/44.alert_handler_smoke/latest

Test location /workspace/coverage/default/45.alert_handler_entropy.3607206257
Short name T102
Test name
Test status
Simulation time 54020768707 ps
CPU time 3009.4 seconds
Started Jul 13 06:26:03 PM PDT 24
Finished Jul 13 07:16:13 PM PDT 24
Peak memory 290036 kb
Host smart-bb350f80-9150-4eca-8dca-15f0313d65e5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3607206257 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_entropy.3607206257
Directory /workspace/45.alert_handler_entropy/latest

Test location /workspace/coverage/default/45.alert_handler_esc_alert_accum.3679501825
Short name T614
Test name
Test status
Simulation time 1114474061 ps
CPU time 37.68 seconds
Started Jul 13 06:26:01 PM PDT 24
Finished Jul 13 06:26:39 PM PDT 24
Peak memory 257488 kb
Host smart-8db5885f-1da0-4321-9f26-c2adf8fd83e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36795
01825 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_alert_accum.3679501825
Directory /workspace/45.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/45.alert_handler_esc_intr_timeout.3990996745
Short name T674
Test name
Test status
Simulation time 220642832 ps
CPU time 4.21 seconds
Started Jul 13 06:25:56 PM PDT 24
Finished Jul 13 06:26:01 PM PDT 24
Peak memory 240624 kb
Host smart-7d42b9c9-a71f-4d30-ba19-b99e96f4ff7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39909
96745 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_intr_timeout.3990996745
Directory /workspace/45.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_lpg.3073050710
Short name T632
Test name
Test status
Simulation time 212424145373 ps
CPU time 1652.11 seconds
Started Jul 13 06:26:03 PM PDT 24
Finished Jul 13 06:53:35 PM PDT 24
Peak memory 273820 kb
Host smart-44c83cef-8dcc-4446-b962-4d48170e74b3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073050710 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg.3073050710
Directory /workspace/45.alert_handler_lpg/latest

Test location /workspace/coverage/default/45.alert_handler_lpg_stub_clk.1168993856
Short name T447
Test name
Test status
Simulation time 77234373335 ps
CPU time 1303.09 seconds
Started Jul 13 06:26:01 PM PDT 24
Finished Jul 13 06:47:45 PM PDT 24
Peak memory 265772 kb
Host smart-405cb07b-44ac-40e0-8540-6f7be0925bbf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168993856 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg_stub_clk.1168993856
Directory /workspace/45.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/45.alert_handler_ping_timeout.630836982
Short name T611
Test name
Test status
Simulation time 18616563200 ps
CPU time 398.65 seconds
Started Jul 13 06:26:02 PM PDT 24
Finished Jul 13 06:32:41 PM PDT 24
Peak memory 249316 kb
Host smart-201f5ed4-aa08-452f-a6a5-cd4dc3cbe500
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630836982 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_ping_timeout.630836982
Directory /workspace/45.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_random_alerts.830854553
Short name T446
Test name
Test status
Simulation time 2501315845 ps
CPU time 36.45 seconds
Started Jul 13 06:25:54 PM PDT 24
Finished Jul 13 06:26:32 PM PDT 24
Peak memory 257308 kb
Host smart-3b33a4de-a19c-48db-8cec-8e9abc60acc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83085
4553 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_alerts.830854553
Directory /workspace/45.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/45.alert_handler_random_classes.1979334897
Short name T58
Test name
Test status
Simulation time 1152882569 ps
CPU time 22.12 seconds
Started Jul 13 06:25:55 PM PDT 24
Finished Jul 13 06:26:18 PM PDT 24
Peak memory 255380 kb
Host smart-de41ad22-85b5-438b-a081-6327a5d09e26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19793
34897 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_classes.1979334897
Directory /workspace/45.alert_handler_random_classes/latest

Test location /workspace/coverage/default/45.alert_handler_sig_int_fail.1821557366
Short name T69
Test name
Test status
Simulation time 697180196 ps
CPU time 30.88 seconds
Started Jul 13 06:26:02 PM PDT 24
Finished Jul 13 06:26:34 PM PDT 24
Peak memory 249288 kb
Host smart-eace5cf5-c010-4603-aaef-d4b28b63650d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18215
57366 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_sig_int_fail.1821557366
Directory /workspace/45.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/45.alert_handler_smoke.279373167
Short name T530
Test name
Test status
Simulation time 723112150 ps
CPU time 12.94 seconds
Started Jul 13 06:25:53 PM PDT 24
Finished Jul 13 06:26:06 PM PDT 24
Peak memory 255908 kb
Host smart-4b076989-47a8-427c-9e58-df14fbbd23b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27937
3167 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_smoke.279373167
Directory /workspace/45.alert_handler_smoke/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all.1006826355
Short name T42
Test name
Test status
Simulation time 857304216 ps
CPU time 51.81 seconds
Started Jul 13 06:26:01 PM PDT 24
Finished Jul 13 06:26:53 PM PDT 24
Peak memory 256632 kb
Host smart-9fb466c2-e01c-447b-a05a-f5bf8bc8bf49
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006826355 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_ha
ndler_stress_all.1006826355
Directory /workspace/45.alert_handler_stress_all/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all_with_rand_reset.4075807905
Short name T314
Test name
Test status
Simulation time 33905706320 ps
CPU time 2231.47 seconds
Started Jul 13 06:26:01 PM PDT 24
Finished Jul 13 07:03:13 PM PDT 24
Peak memory 290436 kb
Host smart-c1ee0a30-d58d-4314-a248-545ce2e01a1f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075807905 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 45.alert_handler_stress_all_with_rand_reset.4075807905
Directory /workspace/45.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.alert_handler_entropy.719467548
Short name T33
Test name
Test status
Simulation time 78508422437 ps
CPU time 2836.91 seconds
Started Jul 13 06:26:01 PM PDT 24
Finished Jul 13 07:13:19 PM PDT 24
Peak memory 289844 kb
Host smart-150c26a2-0ff8-4d64-ada2-0c51e86af01b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719467548 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_entropy.719467548
Directory /workspace/46.alert_handler_entropy/latest

Test location /workspace/coverage/default/46.alert_handler_esc_alert_accum.226797839
Short name T413
Test name
Test status
Simulation time 1949619800 ps
CPU time 72.41 seconds
Started Jul 13 06:26:01 PM PDT 24
Finished Jul 13 06:27:14 PM PDT 24
Peak memory 256620 kb
Host smart-bcb0df00-755d-45d5-835b-6554e24cecae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22679
7839 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_alert_accum.226797839
Directory /workspace/46.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/46.alert_handler_esc_intr_timeout.3661118180
Short name T400
Test name
Test status
Simulation time 215519312 ps
CPU time 26.21 seconds
Started Jul 13 06:26:01 PM PDT 24
Finished Jul 13 06:26:28 PM PDT 24
Peak memory 249304 kb
Host smart-1a1f6ff8-f4a8-49ef-ae8e-8eaea59ba50c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36611
18180 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_intr_timeout.3661118180
Directory /workspace/46.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_lpg.3434516390
Short name T672
Test name
Test status
Simulation time 15209823312 ps
CPU time 696.57 seconds
Started Jul 13 06:26:03 PM PDT 24
Finished Jul 13 06:37:40 PM PDT 24
Peak memory 273820 kb
Host smart-c30d3a63-6565-4c1d-a87e-510c1577cfcd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434516390 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg.3434516390
Directory /workspace/46.alert_handler_lpg/latest

Test location /workspace/coverage/default/46.alert_handler_lpg_stub_clk.1824864289
Short name T430
Test name
Test status
Simulation time 55106313023 ps
CPU time 674.68 seconds
Started Jul 13 06:26:00 PM PDT 24
Finished Jul 13 06:37:15 PM PDT 24
Peak memory 273968 kb
Host smart-b9d5f3ae-2e29-4a91-9969-312118d68258
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824864289 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg_stub_clk.1824864289
Directory /workspace/46.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/46.alert_handler_ping_timeout.711267515
Short name T694
Test name
Test status
Simulation time 11024915753 ps
CPU time 377.12 seconds
Started Jul 13 06:26:01 PM PDT 24
Finished Jul 13 06:32:19 PM PDT 24
Peak memory 248328 kb
Host smart-735260cd-de9a-4941-a76e-b4d1c1f37a88
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711267515 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_ping_timeout.711267515
Directory /workspace/46.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_random_alerts.1563473495
Short name T666
Test name
Test status
Simulation time 506637961 ps
CPU time 27.38 seconds
Started Jul 13 06:26:00 PM PDT 24
Finished Jul 13 06:26:29 PM PDT 24
Peak memory 256736 kb
Host smart-c325298b-1dfa-483e-8f48-8b16154c47d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15634
73495 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_alerts.1563473495
Directory /workspace/46.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/46.alert_handler_random_classes.1324111807
Short name T220
Test name
Test status
Simulation time 1583873579 ps
CPU time 21.99 seconds
Started Jul 13 06:26:00 PM PDT 24
Finished Jul 13 06:26:23 PM PDT 24
Peak memory 249336 kb
Host smart-779d66e5-47ea-4354-970d-931b948d6dda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13241
11807 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_classes.1324111807
Directory /workspace/46.alert_handler_random_classes/latest

Test location /workspace/coverage/default/46.alert_handler_sig_int_fail.3525676067
Short name T366
Test name
Test status
Simulation time 89566459 ps
CPU time 12.66 seconds
Started Jul 13 06:26:02 PM PDT 24
Finished Jul 13 06:26:15 PM PDT 24
Peak memory 255328 kb
Host smart-fc024220-78c9-4a40-9f7c-2972bca362e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35256
76067 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_sig_int_fail.3525676067
Directory /workspace/46.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/46.alert_handler_smoke.3592551982
Short name T462
Test name
Test status
Simulation time 390832328 ps
CPU time 38.47 seconds
Started Jul 13 06:26:02 PM PDT 24
Finished Jul 13 06:26:41 PM PDT 24
Peak memory 257424 kb
Host smart-923950b3-4881-4b35-b45d-dfaf2a31679a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35925
51982 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_smoke.3592551982
Directory /workspace/46.alert_handler_smoke/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all.2048423243
Short name T617
Test name
Test status
Simulation time 137770521134 ps
CPU time 2251.59 seconds
Started Jul 13 06:26:00 PM PDT 24
Finished Jul 13 07:03:32 PM PDT 24
Peak memory 289804 kb
Host smart-bef0fe8e-093b-4b7f-99f3-4bdbdab0c873
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048423243 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_ha
ndler_stress_all.2048423243
Directory /workspace/46.alert_handler_stress_all/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all_with_rand_reset.43611832
Short name T573
Test name
Test status
Simulation time 208042217855 ps
CPU time 1518.8 seconds
Started Jul 13 06:26:00 PM PDT 24
Finished Jul 13 06:51:20 PM PDT 24
Peak memory 306748 kb
Host smart-810f954f-9093-4746-9aca-13c4188250a5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43611832 -assert nopostproc +UVM_TESTNAME=alert_
handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 46.alert_handler_stress_all_with_rand_reset.43611832
Directory /workspace/46.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.alert_handler_entropy.395535612
Short name T511
Test name
Test status
Simulation time 18511073255 ps
CPU time 777.18 seconds
Started Jul 13 06:26:06 PM PDT 24
Finished Jul 13 06:39:04 PM PDT 24
Peak memory 273968 kb
Host smart-e6c89837-4adb-4051-909f-59aeebe2b161
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395535612 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_entropy.395535612
Directory /workspace/47.alert_handler_entropy/latest

Test location /workspace/coverage/default/47.alert_handler_esc_alert_accum.2257510911
Short name T651
Test name
Test status
Simulation time 5426157409 ps
CPU time 296.22 seconds
Started Jul 13 06:26:09 PM PDT 24
Finished Jul 13 06:31:06 PM PDT 24
Peak memory 256892 kb
Host smart-26431ee6-5a78-4bc1-94ab-dd8565c594f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22575
10911 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_alert_accum.2257510911
Directory /workspace/47.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/47.alert_handler_esc_intr_timeout.4037533381
Short name T659
Test name
Test status
Simulation time 904407249 ps
CPU time 16.26 seconds
Started Jul 13 06:26:07 PM PDT 24
Finished Jul 13 06:26:23 PM PDT 24
Peak memory 254808 kb
Host smart-3742a69e-f2c7-463d-bd4d-3dfa87409ce2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40375
33381 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_intr_timeout.4037533381
Directory /workspace/47.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_lpg.226811949
Short name T337
Test name
Test status
Simulation time 72689517265 ps
CPU time 2200.98 seconds
Started Jul 13 06:26:07 PM PDT 24
Finished Jul 13 07:02:49 PM PDT 24
Peak memory 273236 kb
Host smart-61710255-aae2-4e55-ac2d-292235bcfd98
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226811949 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg.226811949
Directory /workspace/47.alert_handler_lpg/latest

Test location /workspace/coverage/default/47.alert_handler_lpg_stub_clk.3252226687
Short name T361
Test name
Test status
Simulation time 19717394591 ps
CPU time 1063.69 seconds
Started Jul 13 06:26:08 PM PDT 24
Finished Jul 13 06:43:52 PM PDT 24
Peak memory 287136 kb
Host smart-6df72ce8-3bec-4400-bd15-11c895913f10
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252226687 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg_stub_clk.3252226687
Directory /workspace/47.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/47.alert_handler_ping_timeout.3948400856
Short name T294
Test name
Test status
Simulation time 35731421590 ps
CPU time 396.74 seconds
Started Jul 13 06:26:07 PM PDT 24
Finished Jul 13 06:32:45 PM PDT 24
Peak memory 249368 kb
Host smart-0cd446b7-8b92-43fb-95bf-aec657701dfe
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3948400856 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_ping_timeout.3948400856
Directory /workspace/47.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_random_alerts.1730074446
Short name T560
Test name
Test status
Simulation time 568078510 ps
CPU time 11.38 seconds
Started Jul 13 06:26:09 PM PDT 24
Finished Jul 13 06:26:22 PM PDT 24
Peak memory 249276 kb
Host smart-476ca595-688d-400f-9277-edc7ec87fbc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17300
74446 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_alerts.1730074446
Directory /workspace/47.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/47.alert_handler_random_classes.76384932
Short name T184
Test name
Test status
Simulation time 159154062 ps
CPU time 13.9 seconds
Started Jul 13 06:26:09 PM PDT 24
Finished Jul 13 06:26:24 PM PDT 24
Peak memory 248580 kb
Host smart-91f6f98b-51a2-46fc-a0ff-65d112028f94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76384
932 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_classes.76384932
Directory /workspace/47.alert_handler_random_classes/latest

Test location /workspace/coverage/default/47.alert_handler_sig_int_fail.1790714331
Short name T624
Test name
Test status
Simulation time 249232993 ps
CPU time 13.97 seconds
Started Jul 13 06:26:10 PM PDT 24
Finished Jul 13 06:26:25 PM PDT 24
Peak memory 257472 kb
Host smart-83a9a7db-de09-479b-8b3c-020b52718836
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17907
14331 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_sig_int_fail.1790714331
Directory /workspace/47.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/47.alert_handler_smoke.1018232045
Short name T450
Test name
Test status
Simulation time 1570462569 ps
CPU time 30.31 seconds
Started Jul 13 06:26:07 PM PDT 24
Finished Jul 13 06:26:38 PM PDT 24
Peak memory 256032 kb
Host smart-a9f0ab53-503f-45b5-9d0d-a4875b2d23f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10182
32045 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_smoke.1018232045
Directory /workspace/47.alert_handler_smoke/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all.1342125580
Short name T271
Test name
Test status
Simulation time 95090642377 ps
CPU time 2745.2 seconds
Started Jul 13 06:26:08 PM PDT 24
Finished Jul 13 07:11:54 PM PDT 24
Peak memory 289368 kb
Host smart-d7413382-4544-41e7-adde-ddfa2f2ea775
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342125580 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_ha
ndler_stress_all.1342125580
Directory /workspace/47.alert_handler_stress_all/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all_with_rand_reset.446521456
Short name T109
Test name
Test status
Simulation time 37229991174 ps
CPU time 1804.73 seconds
Started Jul 13 06:26:07 PM PDT 24
Finished Jul 13 06:56:13 PM PDT 24
Peak memory 298612 kb
Host smart-fd8d33c3-a73e-4341-b53d-571a1749843a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446521456 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 47.alert_handler_stress_all_with_rand_reset.446521456
Directory /workspace/47.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.alert_handler_entropy.423602959
Short name T397
Test name
Test status
Simulation time 9256266706 ps
CPU time 808.32 seconds
Started Jul 13 06:26:09 PM PDT 24
Finished Jul 13 06:39:38 PM PDT 24
Peak memory 273308 kb
Host smart-376ff872-99c3-482c-a2dd-021997c635ac
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423602959 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_entropy.423602959
Directory /workspace/48.alert_handler_entropy/latest

Test location /workspace/coverage/default/48.alert_handler_esc_alert_accum.1192586
Short name T407
Test name
Test status
Simulation time 671671526 ps
CPU time 47.01 seconds
Started Jul 13 06:26:08 PM PDT 24
Finished Jul 13 06:26:56 PM PDT 24
Peak memory 256576 kb
Host smart-484d810e-0f7c-4b23-ab56-8d8815cdf0f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11925
86 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_alert_accum.1192586
Directory /workspace/48.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/48.alert_handler_esc_intr_timeout.3163374739
Short name T705
Test name
Test status
Simulation time 853829548 ps
CPU time 53.98 seconds
Started Jul 13 06:26:09 PM PDT 24
Finished Jul 13 06:27:04 PM PDT 24
Peak memory 248936 kb
Host smart-11cff824-cd81-4dbf-aed8-6bb8df04da8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31633
74739 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_intr_timeout.3163374739
Directory /workspace/48.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_lpg.3478880185
Short name T299
Test name
Test status
Simulation time 18825221630 ps
CPU time 1143.7 seconds
Started Jul 13 06:26:07 PM PDT 24
Finished Jul 13 06:45:11 PM PDT 24
Peak memory 265700 kb
Host smart-dcbf55a5-a7b1-496a-b35f-8f72f2f91701
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478880185 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg.3478880185
Directory /workspace/48.alert_handler_lpg/latest

Test location /workspace/coverage/default/48.alert_handler_lpg_stub_clk.3496222799
Short name T218
Test name
Test status
Simulation time 46171069986 ps
CPU time 2681.32 seconds
Started Jul 13 06:26:09 PM PDT 24
Finished Jul 13 07:10:52 PM PDT 24
Peak memory 282116 kb
Host smart-d80f9291-aaf0-4d4b-8fb0-050c8b3f28fd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496222799 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg_stub_clk.3496222799
Directory /workspace/48.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/48.alert_handler_random_alerts.2584427505
Short name T532
Test name
Test status
Simulation time 3612416994 ps
CPU time 56.9 seconds
Started Jul 13 06:26:09 PM PDT 24
Finished Jul 13 06:27:07 PM PDT 24
Peak memory 257444 kb
Host smart-cd1a0774-91a3-4924-aa90-6df7ca08ac9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25844
27505 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_alerts.2584427505
Directory /workspace/48.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/48.alert_handler_random_classes.2625176343
Short name T536
Test name
Test status
Simulation time 97993262 ps
CPU time 7.64 seconds
Started Jul 13 06:26:08 PM PDT 24
Finished Jul 13 06:26:16 PM PDT 24
Peak memory 254996 kb
Host smart-5f3d43ca-4633-4f5a-8fcd-9e369e49770d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26251
76343 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_classes.2625176343
Directory /workspace/48.alert_handler_random_classes/latest

Test location /workspace/coverage/default/48.alert_handler_sig_int_fail.3412882173
Short name T663
Test name
Test status
Simulation time 1195483655 ps
CPU time 13.34 seconds
Started Jul 13 06:26:09 PM PDT 24
Finished Jul 13 06:26:23 PM PDT 24
Peak memory 249296 kb
Host smart-e534d140-6e0f-40f8-809f-5f910aef4983
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34128
82173 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_sig_int_fail.3412882173
Directory /workspace/48.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/48.alert_handler_smoke.3878349315
Short name T444
Test name
Test status
Simulation time 1592439556 ps
CPU time 37.68 seconds
Started Jul 13 06:26:07 PM PDT 24
Finished Jul 13 06:26:45 PM PDT 24
Peak memory 256452 kb
Host smart-70347f02-e0dc-4db9-bf1f-b3a2bda97d79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38783
49315 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_smoke.3878349315
Directory /workspace/48.alert_handler_smoke/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all.1933354520
Short name T654
Test name
Test status
Simulation time 59768711129 ps
CPU time 1622.29 seconds
Started Jul 13 06:26:09 PM PDT 24
Finished Jul 13 06:53:12 PM PDT 24
Peak memory 290276 kb
Host smart-8d3ddcc2-dbf6-4eb3-bb4b-6af5d6b7936a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933354520 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_ha
ndler_stress_all.1933354520
Directory /workspace/48.alert_handler_stress_all/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all_with_rand_reset.2836338466
Short name T103
Test name
Test status
Simulation time 56743727740 ps
CPU time 2975.25 seconds
Started Jul 13 06:26:07 PM PDT 24
Finished Jul 13 07:15:44 PM PDT 24
Peak memory 323244 kb
Host smart-6adc1b7b-46d3-42fc-9cee-1e9d0c853d21
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836338466 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 48.alert_handler_stress_all_with_rand_reset.2836338466
Directory /workspace/48.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.alert_handler_entropy.2225301552
Short name T384
Test name
Test status
Simulation time 24405630007 ps
CPU time 1137.26 seconds
Started Jul 13 06:26:07 PM PDT 24
Finished Jul 13 06:45:05 PM PDT 24
Peak memory 290276 kb
Host smart-1fc9a9af-a627-461a-a32f-12b27af902a4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225301552 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_entropy.2225301552
Directory /workspace/49.alert_handler_entropy/latest

Test location /workspace/coverage/default/49.alert_handler_esc_alert_accum.1546364506
Short name T570
Test name
Test status
Simulation time 1508004542 ps
CPU time 110 seconds
Started Jul 13 06:26:09 PM PDT 24
Finished Jul 13 06:27:59 PM PDT 24
Peak memory 256980 kb
Host smart-3c9f0963-1bd7-41f1-a5d4-6e0fcfd4b97a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15463
64506 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_alert_accum.1546364506
Directory /workspace/49.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/49.alert_handler_esc_intr_timeout.304805783
Short name T522
Test name
Test status
Simulation time 386094642 ps
CPU time 26.64 seconds
Started Jul 13 06:26:07 PM PDT 24
Finished Jul 13 06:26:34 PM PDT 24
Peak memory 248884 kb
Host smart-3e872513-a500-462a-a90a-806d1de3568c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30480
5783 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_intr_timeout.304805783
Directory /workspace/49.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_lpg.4133418651
Short name T451
Test name
Test status
Simulation time 55621020009 ps
CPU time 1083.01 seconds
Started Jul 13 06:26:06 PM PDT 24
Finished Jul 13 06:44:10 PM PDT 24
Peak memory 273888 kb
Host smart-a78319e4-e282-4b38-bb95-6344a4fb7cf0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133418651 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg.4133418651
Directory /workspace/49.alert_handler_lpg/latest

Test location /workspace/coverage/default/49.alert_handler_lpg_stub_clk.702274062
Short name T586
Test name
Test status
Simulation time 179639453255 ps
CPU time 1256.18 seconds
Started Jul 13 06:26:13 PM PDT 24
Finished Jul 13 06:47:10 PM PDT 24
Peak memory 287888 kb
Host smart-ff2a2dff-8a01-4491-9961-9a479a5f3c52
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=702274062 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg_stub_clk.702274062
Directory /workspace/49.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/49.alert_handler_ping_timeout.2169500505
Short name T539
Test name
Test status
Simulation time 25681920425 ps
CPU time 530.89 seconds
Started Jul 13 06:26:07 PM PDT 24
Finished Jul 13 06:34:59 PM PDT 24
Peak memory 249376 kb
Host smart-c334849b-d703-48c7-8ca1-9bc51509d3cd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169500505 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_ping_timeout.2169500505
Directory /workspace/49.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_random_alerts.2645263660
Short name T464
Test name
Test status
Simulation time 1310571514 ps
CPU time 25.66 seconds
Started Jul 13 06:26:09 PM PDT 24
Finished Jul 13 06:26:35 PM PDT 24
Peak memory 249208 kb
Host smart-0633e033-e113-4920-ba6f-98d65477c206
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26452
63660 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_alerts.2645263660
Directory /workspace/49.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/49.alert_handler_random_classes.2682762914
Short name T246
Test name
Test status
Simulation time 3450048909 ps
CPU time 30.21 seconds
Started Jul 13 06:26:07 PM PDT 24
Finished Jul 13 06:26:38 PM PDT 24
Peak memory 256312 kb
Host smart-fbc33f40-df3b-463c-9eec-2ffbb92f0e88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26827
62914 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_classes.2682762914
Directory /workspace/49.alert_handler_random_classes/latest

Test location /workspace/coverage/default/49.alert_handler_smoke.875370
Short name T425
Test name
Test status
Simulation time 1137552239 ps
CPU time 30.34 seconds
Started Jul 13 06:26:05 PM PDT 24
Finished Jul 13 06:26:36 PM PDT 24
Peak memory 256340 kb
Host smart-1a4b42f3-d092-4e30-b813-dc7cd6344c47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87537
0 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_smoke.875370
Directory /workspace/49.alert_handler_smoke/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all.2650057678
Short name T631
Test name
Test status
Simulation time 127861143647 ps
CPU time 1925.39 seconds
Started Jul 13 06:26:13 PM PDT 24
Finished Jul 13 06:58:18 PM PDT 24
Peak memory 282812 kb
Host smart-2089a80b-70a3-4b32-bf32-58ce9b53fec5
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650057678 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_ha
ndler_stress_all.2650057678
Directory /workspace/49.alert_handler_stress_all/latest

Test location /workspace/coverage/default/5.alert_handler_alert_accum_saturation.2275297532
Short name T207
Test name
Test status
Simulation time 230457076 ps
CPU time 3.88 seconds
Started Jul 13 06:24:35 PM PDT 24
Finished Jul 13 06:24:46 PM PDT 24
Peak memory 249580 kb
Host smart-3990c130-29da-4036-9930-941b10ab4928
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2275297532 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_alert_accum_saturation.2275297532
Directory /workspace/5.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/5.alert_handler_entropy.3577625596
Short name T538
Test name
Test status
Simulation time 10770465555 ps
CPU time 979.57 seconds
Started Jul 13 06:24:38 PM PDT 24
Finished Jul 13 06:40:59 PM PDT 24
Peak memory 273356 kb
Host smart-8de2c15b-fb03-440f-8d83-b5635f512ddb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577625596 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy.3577625596
Directory /workspace/5.alert_handler_entropy/latest

Test location /workspace/coverage/default/5.alert_handler_entropy_stress.2264844184
Short name T557
Test name
Test status
Simulation time 2138483727 ps
CPU time 23.99 seconds
Started Jul 13 06:24:33 PM PDT 24
Finished Jul 13 06:24:57 PM PDT 24
Peak memory 249224 kb
Host smart-53509a5b-fd49-4798-a216-93f531bac402
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2264844184 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy_stress.2264844184
Directory /workspace/5.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/5.alert_handler_esc_alert_accum.2615041634
Short name T556
Test name
Test status
Simulation time 89829620 ps
CPU time 7.41 seconds
Started Jul 13 06:24:46 PM PDT 24
Finished Jul 13 06:24:55 PM PDT 24
Peak memory 248904 kb
Host smart-31a1a9f4-002d-45ff-ab73-9ce2e7695d55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26150
41634 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_alert_accum.2615041634
Directory /workspace/5.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/5.alert_handler_esc_intr_timeout.2659585372
Short name T80
Test name
Test status
Simulation time 1393323157 ps
CPU time 25.02 seconds
Started Jul 13 06:24:39 PM PDT 24
Finished Jul 13 06:25:06 PM PDT 24
Peak memory 249644 kb
Host smart-fd2f76cf-c6b6-42d7-a249-1e32118af197
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26595
85372 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_intr_timeout.2659585372
Directory /workspace/5.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_ping_timeout.1979165546
Short name T222
Test name
Test status
Simulation time 16486956613 ps
CPU time 363.78 seconds
Started Jul 13 06:24:33 PM PDT 24
Finished Jul 13 06:30:38 PM PDT 24
Peak memory 255964 kb
Host smart-7a3293d4-ce4b-425d-8e50-3710def0651a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1979165546 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_ping_timeout.1979165546
Directory /workspace/5.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_random_alerts.3048403398
Short name T449
Test name
Test status
Simulation time 1826302804 ps
CPU time 36.38 seconds
Started Jul 13 06:24:53 PM PDT 24
Finished Jul 13 06:25:30 PM PDT 24
Peak memory 257176 kb
Host smart-f1aed55f-7a47-47c4-a10b-ec0934935f27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30484
03398 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_alerts.3048403398
Directory /workspace/5.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/5.alert_handler_random_classes.15591153
Short name T537
Test name
Test status
Simulation time 879497935 ps
CPU time 61.06 seconds
Started Jul 13 06:24:42 PM PDT 24
Finished Jul 13 06:25:45 PM PDT 24
Peak memory 248792 kb
Host smart-8636103c-c78e-4610-bab8-87925c4e7d0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15591
153 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_classes.15591153
Directory /workspace/5.alert_handler_random_classes/latest

Test location /workspace/coverage/default/5.alert_handler_smoke.2471107838
Short name T71
Test name
Test status
Simulation time 235632347 ps
CPU time 4.32 seconds
Started Jul 13 06:24:46 PM PDT 24
Finished Jul 13 06:24:52 PM PDT 24
Peak memory 249240 kb
Host smart-f5aa235f-d12a-4cfe-8475-eff71304036e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24711
07838 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_smoke.2471107838
Directory /workspace/5.alert_handler_smoke/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all.2899038524
Short name T249
Test name
Test status
Simulation time 13559900601 ps
CPU time 1498.36 seconds
Started Jul 13 06:24:39 PM PDT 24
Finished Jul 13 06:49:39 PM PDT 24
Peak memory 290068 kb
Host smart-a410597a-6fc3-43ed-96e6-e2567c92214c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899038524 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_han
dler_stress_all.2899038524
Directory /workspace/5.alert_handler_stress_all/latest

Test location /workspace/coverage/default/6.alert_handler_alert_accum_saturation.1889475268
Short name T211
Test name
Test status
Simulation time 91403915 ps
CPU time 3.04 seconds
Started Jul 13 06:24:43 PM PDT 24
Finished Jul 13 06:24:47 PM PDT 24
Peak memory 249580 kb
Host smart-208d4d3f-a0c0-4893-a29c-75141e0b5db1
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1889475268 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_alert_accum_saturation.1889475268
Directory /workspace/6.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/6.alert_handler_entropy.1882200563
Short name T250
Test name
Test status
Simulation time 10866538025 ps
CPU time 699.97 seconds
Started Jul 13 06:24:31 PM PDT 24
Finished Jul 13 06:36:12 PM PDT 24
Peak memory 273660 kb
Host smart-bc47ac6f-fd2d-4c9c-9948-cc0da850c1f5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882200563 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy.1882200563
Directory /workspace/6.alert_handler_entropy/latest

Test location /workspace/coverage/default/6.alert_handler_entropy_stress.411846560
Short name T385
Test name
Test status
Simulation time 737565241 ps
CPU time 19.26 seconds
Started Jul 13 06:24:43 PM PDT 24
Finished Jul 13 06:25:03 PM PDT 24
Peak memory 249284 kb
Host smart-fef2340c-80b7-428b-8e1c-5b74772e1288
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=411846560 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy_stress.411846560
Directory /workspace/6.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/6.alert_handler_esc_alert_accum.4142355595
Short name T656
Test name
Test status
Simulation time 1875532146 ps
CPU time 113.71 seconds
Started Jul 13 06:24:39 PM PDT 24
Finished Jul 13 06:26:35 PM PDT 24
Peak memory 256728 kb
Host smart-55b2a0bd-e4f1-42ed-a4b9-e6222e6352b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41423
55595 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_alert_accum.4142355595
Directory /workspace/6.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/6.alert_handler_esc_intr_timeout.3319667935
Short name T234
Test name
Test status
Simulation time 916395062 ps
CPU time 59.47 seconds
Started Jul 13 06:24:32 PM PDT 24
Finished Jul 13 06:25:32 PM PDT 24
Peak memory 249304 kb
Host smart-7437ef50-5b2f-4483-830a-d62c37b46b46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33196
67935 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_intr_timeout.3319667935
Directory /workspace/6.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_lpg.4185309813
Short name T597
Test name
Test status
Simulation time 134381268282 ps
CPU time 1757.59 seconds
Started Jul 13 06:24:31 PM PDT 24
Finished Jul 13 06:53:49 PM PDT 24
Peak memory 273768 kb
Host smart-a0ec545c-6a7a-403f-9a6f-e19c71c2b858
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185309813 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg.4185309813
Directory /workspace/6.alert_handler_lpg/latest

Test location /workspace/coverage/default/6.alert_handler_lpg_stub_clk.48773540
Short name T549
Test name
Test status
Simulation time 11061232366 ps
CPU time 1053.44 seconds
Started Jul 13 06:24:56 PM PDT 24
Finished Jul 13 06:42:36 PM PDT 24
Peak memory 282180 kb
Host smart-e9bc8430-4757-413d-b9b7-f28f1e2bd828
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48773540 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg_stub_clk.48773540
Directory /workspace/6.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/6.alert_handler_ping_timeout.3925247214
Short name T298
Test name
Test status
Simulation time 8965466694 ps
CPU time 99.47 seconds
Started Jul 13 06:24:40 PM PDT 24
Finished Jul 13 06:26:22 PM PDT 24
Peak memory 249224 kb
Host smart-28ee6310-3512-4001-aedd-991b99127b6a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3925247214 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_ping_timeout.3925247214
Directory /workspace/6.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_random_alerts.1071388187
Short name T379
Test name
Test status
Simulation time 987279615 ps
CPU time 15.1 seconds
Started Jul 13 06:24:48 PM PDT 24
Finished Jul 13 06:25:05 PM PDT 24
Peak memory 249300 kb
Host smart-870a9f87-7e36-4b2f-a364-86db50699a5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10713
88187 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_alerts.1071388187
Directory /workspace/6.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/6.alert_handler_random_classes.2006355640
Short name T55
Test name
Test status
Simulation time 260095177 ps
CPU time 16.71 seconds
Started Jul 13 06:24:37 PM PDT 24
Finished Jul 13 06:24:55 PM PDT 24
Peak memory 249316 kb
Host smart-50ae8b72-8216-4081-b2bc-d60361a78e6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20063
55640 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_classes.2006355640
Directory /workspace/6.alert_handler_random_classes/latest

Test location /workspace/coverage/default/6.alert_handler_sig_int_fail.3352313500
Short name T63
Test name
Test status
Simulation time 3865284270 ps
CPU time 56.29 seconds
Started Jul 13 06:25:00 PM PDT 24
Finished Jul 13 06:25:57 PM PDT 24
Peak memory 256692 kb
Host smart-270757a2-0076-4cbe-bd69-856114fd7344
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33523
13500 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_sig_int_fail.3352313500
Directory /workspace/6.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/6.alert_handler_smoke.488590530
Short name T481
Test name
Test status
Simulation time 771298002 ps
CPU time 31.65 seconds
Started Jul 13 06:24:46 PM PDT 24
Finished Jul 13 06:25:19 PM PDT 24
Peak memory 249268 kb
Host smart-cec85165-0c65-421b-86c2-650766d7356d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48859
0530 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_smoke.488590530
Directory /workspace/6.alert_handler_smoke/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all_with_rand_reset.54665355
Short name T316
Test name
Test status
Simulation time 63449807260 ps
CPU time 1668.15 seconds
Started Jul 13 06:24:39 PM PDT 24
Finished Jul 13 06:52:29 PM PDT 24
Peak memory 305888 kb
Host smart-e6b20118-7508-4e1d-88f1-58902fa2415c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54665355 -assert nopostproc +UVM_TESTNAME=alert_
handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 6.alert_handler_stress_all_with_rand_reset.54665355
Directory /workspace/6.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.alert_handler_alert_accum_saturation.730570636
Short name T206
Test name
Test status
Simulation time 21660432 ps
CPU time 2.34 seconds
Started Jul 13 06:24:40 PM PDT 24
Finished Jul 13 06:24:45 PM PDT 24
Peak memory 249556 kb
Host smart-fea63ef5-5c24-4250-b4e3-90160558e362
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=730570636 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_alert_accum_saturation.730570636
Directory /workspace/7.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/7.alert_handler_entropy.2724926177
Short name T579
Test name
Test status
Simulation time 64152812075 ps
CPU time 2091.31 seconds
Started Jul 13 06:24:45 PM PDT 24
Finished Jul 13 06:59:38 PM PDT 24
Peak memory 289840 kb
Host smart-2fe14ba9-13fe-4482-8263-947f76c98101
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724926177 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy.2724926177
Directory /workspace/7.alert_handler_entropy/latest

Test location /workspace/coverage/default/7.alert_handler_entropy_stress.1638818694
Short name T458
Test name
Test status
Simulation time 3359157525 ps
CPU time 21.26 seconds
Started Jul 13 06:24:35 PM PDT 24
Finished Jul 13 06:24:57 PM PDT 24
Peak memory 249396 kb
Host smart-4d10bc9c-438e-48a6-80c0-c1181d2e3924
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1638818694 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy_stress.1638818694
Directory /workspace/7.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/7.alert_handler_esc_alert_accum.1298179928
Short name T370
Test name
Test status
Simulation time 1247196693 ps
CPU time 84.82 seconds
Started Jul 13 06:25:10 PM PDT 24
Finished Jul 13 06:26:36 PM PDT 24
Peak memory 257468 kb
Host smart-2dfbcdcb-b4ec-4db9-995e-a706b9c7e471
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12981
79928 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_alert_accum.1298179928
Directory /workspace/7.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/7.alert_handler_esc_intr_timeout.375042266
Short name T415
Test name
Test status
Simulation time 4015185737 ps
CPU time 16.91 seconds
Started Jul 13 06:24:33 PM PDT 24
Finished Jul 13 06:24:51 PM PDT 24
Peak memory 248820 kb
Host smart-08be55ce-465c-414b-a16f-58145238f61b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37504
2266 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_intr_timeout.375042266
Directory /workspace/7.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_lpg.3137576199
Short name T334
Test name
Test status
Simulation time 15079078724 ps
CPU time 820.39 seconds
Started Jul 13 06:24:45 PM PDT 24
Finished Jul 13 06:38:26 PM PDT 24
Peak memory 273944 kb
Host smart-a6571c13-8028-4f5e-ace8-82266790d412
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137576199 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg.3137576199
Directory /workspace/7.alert_handler_lpg/latest

Test location /workspace/coverage/default/7.alert_handler_lpg_stub_clk.2162913889
Short name T454
Test name
Test status
Simulation time 17526755686 ps
CPU time 1084.17 seconds
Started Jul 13 06:24:33 PM PDT 24
Finished Jul 13 06:42:38 PM PDT 24
Peak memory 272412 kb
Host smart-65062219-3a5b-442e-a41f-8f1497a1d4cf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2162913889 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg_stub_clk.2162913889
Directory /workspace/7.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/7.alert_handler_ping_timeout.2160527318
Short name T604
Test name
Test status
Simulation time 16363867374 ps
CPU time 444.82 seconds
Started Jul 13 06:24:49 PM PDT 24
Finished Jul 13 06:32:15 PM PDT 24
Peak memory 249376 kb
Host smart-5129fced-ea3a-478f-8500-8b317c8e802f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160527318 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_ping_timeout.2160527318
Directory /workspace/7.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_random_alerts.2454649050
Short name T358
Test name
Test status
Simulation time 937735726 ps
CPU time 58.63 seconds
Started Jul 13 06:24:46 PM PDT 24
Finished Jul 13 06:25:46 PM PDT 24
Peak memory 256772 kb
Host smart-3e6dfca5-7c0c-4254-84f0-d6ca9e765b6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24546
49050 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_alerts.2454649050
Directory /workspace/7.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/7.alert_handler_random_classes.3062653233
Short name T252
Test name
Test status
Simulation time 1783170871 ps
CPU time 32.51 seconds
Started Jul 13 06:25:02 PM PDT 24
Finished Jul 13 06:25:40 PM PDT 24
Peak memory 256628 kb
Host smart-98833569-f664-4632-9f97-e4fb17384d05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30626
53233 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_classes.3062653233
Directory /workspace/7.alert_handler_random_classes/latest

Test location /workspace/coverage/default/7.alert_handler_sig_int_fail.557024495
Short name T310
Test name
Test status
Simulation time 583735808 ps
CPU time 41.69 seconds
Started Jul 13 06:24:38 PM PDT 24
Finished Jul 13 06:25:22 PM PDT 24
Peak memory 248984 kb
Host smart-60d84c16-5d33-4d19-bf8d-c625bc4fa000
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55702
4495 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_sig_int_fail.557024495
Directory /workspace/7.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/7.alert_handler_smoke.2163777096
Short name T562
Test name
Test status
Simulation time 4652381459 ps
CPU time 63.93 seconds
Started Jul 13 06:24:42 PM PDT 24
Finished Jul 13 06:25:48 PM PDT 24
Peak memory 249404 kb
Host smart-c17955b9-e180-46a8-8a96-844f791b2bdc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21637
77096 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_smoke.2163777096
Directory /workspace/7.alert_handler_smoke/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all.3701565796
Short name T45
Test name
Test status
Simulation time 65942962203 ps
CPU time 1428.22 seconds
Started Jul 13 06:24:57 PM PDT 24
Finished Jul 13 06:48:47 PM PDT 24
Peak memory 290236 kb
Host smart-3b709a9b-7887-4cad-a097-7b8dd7a1bf02
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701565796 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_han
dler_stress_all.3701565796
Directory /workspace/7.alert_handler_stress_all/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all_with_rand_reset.67242210
Short name T523
Test name
Test status
Simulation time 247028527789 ps
CPU time 3826.11 seconds
Started Jul 13 06:24:40 PM PDT 24
Finished Jul 13 07:28:28 PM PDT 24
Peak memory 290416 kb
Host smart-095f0610-75f6-4ba5-8b72-95bcc4536d53
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67242210 -assert nopostproc +UVM_TESTNAME=alert_
handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 7.alert_handler_stress_all_with_rand_reset.67242210
Directory /workspace/7.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.alert_handler_alert_accum_saturation.1409919770
Short name T205
Test name
Test status
Simulation time 31250236 ps
CPU time 3.36 seconds
Started Jul 13 06:24:59 PM PDT 24
Finished Jul 13 06:25:03 PM PDT 24
Peak memory 249548 kb
Host smart-d263e9c1-2a0d-421e-9c74-d160e7bae7ba
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1409919770 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_alert_accum_saturation.1409919770
Directory /workspace/8.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/8.alert_handler_entropy.1228739128
Short name T78
Test name
Test status
Simulation time 64365922818 ps
CPU time 1074.95 seconds
Started Jul 13 06:24:48 PM PDT 24
Finished Jul 13 06:42:44 PM PDT 24
Peak memory 286100 kb
Host smart-09dad879-2825-4037-986e-97688fef3bcc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1228739128 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy.1228739128
Directory /workspace/8.alert_handler_entropy/latest

Test location /workspace/coverage/default/8.alert_handler_entropy_stress.2039675072
Short name T630
Test name
Test status
Simulation time 5607927426 ps
CPU time 62.61 seconds
Started Jul 13 06:24:37 PM PDT 24
Finished Jul 13 06:25:40 PM PDT 24
Peak memory 249328 kb
Host smart-dfb1530e-6cf2-444e-b0a1-43bebb8aaabd
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2039675072 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy_stress.2039675072
Directory /workspace/8.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/8.alert_handler_esc_alert_accum.1807004561
Short name T396
Test name
Test status
Simulation time 226526256 ps
CPU time 19.36 seconds
Started Jul 13 06:24:41 PM PDT 24
Finished Jul 13 06:25:03 PM PDT 24
Peak memory 257004 kb
Host smart-e091a06f-4d70-4b8f-8dca-715ede1a46ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18070
04561 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_alert_accum.1807004561
Directory /workspace/8.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/8.alert_handler_esc_intr_timeout.3802154242
Short name T6
Test name
Test status
Simulation time 264828124 ps
CPU time 4.2 seconds
Started Jul 13 06:24:47 PM PDT 24
Finished Jul 13 06:24:53 PM PDT 24
Peak memory 249220 kb
Host smart-d95ee662-3683-4fa0-ac8b-7439fec7060b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38021
54242 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_intr_timeout.3802154242
Directory /workspace/8.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_lpg.1170992707
Short name T185
Test name
Test status
Simulation time 18920984894 ps
CPU time 1079.73 seconds
Started Jul 13 06:24:46 PM PDT 24
Finished Jul 13 06:42:47 PM PDT 24
Peak memory 273088 kb
Host smart-9ef6486e-01cc-42d1-bd6f-c9034c69ff8e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1170992707 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg.1170992707
Directory /workspace/8.alert_handler_lpg/latest

Test location /workspace/coverage/default/8.alert_handler_lpg_stub_clk.4009828322
Short name T266
Test name
Test status
Simulation time 19695464556 ps
CPU time 1267 seconds
Started Jul 13 06:25:09 PM PDT 24
Finished Jul 13 06:46:18 PM PDT 24
Peak memory 273912 kb
Host smart-45c4254b-6636-4d62-a1d8-8075b35ec6a8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009828322 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg_stub_clk.4009828322
Directory /workspace/8.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/8.alert_handler_ping_timeout.3496261099
Short name T290
Test name
Test status
Simulation time 50116362922 ps
CPU time 544.36 seconds
Started Jul 13 06:24:45 PM PDT 24
Finished Jul 13 06:33:52 PM PDT 24
Peak memory 248612 kb
Host smart-7be4264c-c77e-45dc-9b9c-c5490a897d7e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496261099 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_ping_timeout.3496261099
Directory /workspace/8.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_random_alerts.2878925769
Short name T677
Test name
Test status
Simulation time 903008532 ps
CPU time 49.9 seconds
Started Jul 13 06:24:41 PM PDT 24
Finished Jul 13 06:25:33 PM PDT 24
Peak memory 256456 kb
Host smart-e7230ccf-b2ec-42b5-948e-13bf13c7084b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28789
25769 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_alerts.2878925769
Directory /workspace/8.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/8.alert_handler_random_classes.2911679601
Short name T114
Test name
Test status
Simulation time 417514369 ps
CPU time 25.89 seconds
Started Jul 13 06:24:58 PM PDT 24
Finished Jul 13 06:25:25 PM PDT 24
Peak memory 249056 kb
Host smart-07a49c3a-021a-4251-90d9-139384ff66a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29116
79601 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_classes.2911679601
Directory /workspace/8.alert_handler_random_classes/latest

Test location /workspace/coverage/default/8.alert_handler_sig_int_fail.2924879456
Short name T20
Test name
Test status
Simulation time 304511496 ps
CPU time 40.5 seconds
Started Jul 13 06:24:48 PM PDT 24
Finished Jul 13 06:25:30 PM PDT 24
Peak memory 249304 kb
Host smart-3e6e4f7e-e570-4546-bcb9-79f6e5e920fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29248
79456 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_sig_int_fail.2924879456
Directory /workspace/8.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/8.alert_handler_smoke.3832947068
Short name T421
Test name
Test status
Simulation time 3758676362 ps
CPU time 41.82 seconds
Started Jul 13 06:24:37 PM PDT 24
Finished Jul 13 06:25:22 PM PDT 24
Peak memory 257304 kb
Host smart-b3a2a12b-9537-42f9-9785-ab5738609e73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38329
47068 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_smoke.3832947068
Directory /workspace/8.alert_handler_smoke/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all.1119877498
Short name T243
Test name
Test status
Simulation time 46909771160 ps
CPU time 842.55 seconds
Started Jul 13 06:24:39 PM PDT 24
Finished Jul 13 06:38:44 PM PDT 24
Peak memory 289056 kb
Host smart-3630fe8f-3993-48d0-a165-cac29fbbdcd8
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119877498 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_han
dler_stress_all.1119877498
Directory /workspace/8.alert_handler_stress_all/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all_with_rand_reset.819784624
Short name T97
Test name
Test status
Simulation time 289034619093 ps
CPU time 7344.8 seconds
Started Jul 13 06:24:39 PM PDT 24
Finished Jul 13 08:27:07 PM PDT 24
Peak memory 348176 kb
Host smart-9777b871-8bfa-4571-8d71-fda661964646
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819784624 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 8.alert_handler_stress_all_with_rand_reset.819784624
Directory /workspace/8.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.alert_handler_alert_accum_saturation.1309268027
Short name T208
Test name
Test status
Simulation time 18373194 ps
CPU time 2.51 seconds
Started Jul 13 06:24:45 PM PDT 24
Finished Jul 13 06:24:49 PM PDT 24
Peak memory 249500 kb
Host smart-0a411be1-1c0f-44b0-acb2-ce8603f7c563
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1309268027 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_alert_accum_saturation.1309268027
Directory /workspace/9.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/9.alert_handler_entropy.300728983
Short name T623
Test name
Test status
Simulation time 110973369785 ps
CPU time 1489.71 seconds
Started Jul 13 06:25:11 PM PDT 24
Finished Jul 13 06:50:02 PM PDT 24
Peak memory 273720 kb
Host smart-6b6b4f5d-33eb-4c81-a384-371b856a8a36
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300728983 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy.300728983
Directory /workspace/9.alert_handler_entropy/latest

Test location /workspace/coverage/default/9.alert_handler_entropy_stress.2144036950
Short name T484
Test name
Test status
Simulation time 8235012608 ps
CPU time 19.76 seconds
Started Jul 13 06:24:40 PM PDT 24
Finished Jul 13 06:25:02 PM PDT 24
Peak memory 249372 kb
Host smart-d4de45fc-cd3e-415c-861e-bb774454f07f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2144036950 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy_stress.2144036950
Directory /workspace/9.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/9.alert_handler_esc_alert_accum.2192879331
Short name T478
Test name
Test status
Simulation time 1840829227 ps
CPU time 184.19 seconds
Started Jul 13 06:24:41 PM PDT 24
Finished Jul 13 06:27:47 PM PDT 24
Peak memory 257428 kb
Host smart-b8f6e8a0-3726-45d4-82fa-2178623458b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21928
79331 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_alert_accum.2192879331
Directory /workspace/9.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/9.alert_handler_esc_intr_timeout.1193504318
Short name T646
Test name
Test status
Simulation time 1854182297 ps
CPU time 23.62 seconds
Started Jul 13 06:24:59 PM PDT 24
Finished Jul 13 06:25:24 PM PDT 24
Peak memory 248520 kb
Host smart-173c8b30-9554-4c48-8310-a82c46b8a024
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11935
04318 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_intr_timeout.1193504318
Directory /workspace/9.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_lpg.370954327
Short name T70
Test name
Test status
Simulation time 10434389581 ps
CPU time 996.96 seconds
Started Jul 13 06:24:33 PM PDT 24
Finished Jul 13 06:41:11 PM PDT 24
Peak memory 271868 kb
Host smart-64556d4d-422b-4731-b092-97711b94ee8b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370954327 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg.370954327
Directory /workspace/9.alert_handler_lpg/latest

Test location /workspace/coverage/default/9.alert_handler_lpg_stub_clk.3602688364
Short name T333
Test name
Test status
Simulation time 96296483054 ps
CPU time 2992.35 seconds
Started Jul 13 06:24:41 PM PDT 24
Finished Jul 13 07:14:36 PM PDT 24
Peak memory 282052 kb
Host smart-776fa42b-f01e-4fda-a7c7-41451fdc1e30
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602688364 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg_stub_clk.3602688364
Directory /workspace/9.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/9.alert_handler_ping_timeout.1834935696
Short name T670
Test name
Test status
Simulation time 2910383238 ps
CPU time 129.75 seconds
Started Jul 13 06:24:39 PM PDT 24
Finished Jul 13 06:26:51 PM PDT 24
Peak memory 249380 kb
Host smart-61777d68-f9d8-4621-8bda-7511c4158e69
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834935696 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_ping_timeout.1834935696
Directory /workspace/9.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_random_alerts.3771531724
Short name T582
Test name
Test status
Simulation time 97075256 ps
CPU time 7.53 seconds
Started Jul 13 06:24:36 PM PDT 24
Finished Jul 13 06:24:45 PM PDT 24
Peak memory 249260 kb
Host smart-bcda11b7-299f-4276-ada4-40e378a3ed2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37715
31724 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_alerts.3771531724
Directory /workspace/9.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/9.alert_handler_random_classes.626162914
Short name T356
Test name
Test status
Simulation time 1838134666 ps
CPU time 30.05 seconds
Started Jul 13 06:24:47 PM PDT 24
Finished Jul 13 06:25:18 PM PDT 24
Peak memory 257436 kb
Host smart-fa8ef3f4-8b20-4b4b-88ed-174dc9fa5e1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62616
2914 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_classes.626162914
Directory /workspace/9.alert_handler_random_classes/latest

Test location /workspace/coverage/default/9.alert_handler_sig_int_fail.867781612
Short name T216
Test name
Test status
Simulation time 298199383 ps
CPU time 35 seconds
Started Jul 13 06:24:48 PM PDT 24
Finished Jul 13 06:25:24 PM PDT 24
Peak memory 257364 kb
Host smart-7cb2216b-5c15-459f-9dcf-ee89291ee50e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86778
1612 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_sig_int_fail.867781612
Directory /workspace/9.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/9.alert_handler_smoke.2818741750
Short name T390
Test name
Test status
Simulation time 1096174695 ps
CPU time 38.75 seconds
Started Jul 13 06:24:49 PM PDT 24
Finished Jul 13 06:25:28 PM PDT 24
Peak memory 256464 kb
Host smart-feb3041c-b8e4-45d0-a814-0cefcbc2b060
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28187
41750 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_smoke.2818741750
Directory /workspace/9.alert_handler_smoke/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all.717821961
Short name T27
Test name
Test status
Simulation time 2642587345 ps
CPU time 67.92 seconds
Started Jul 13 06:24:38 PM PDT 24
Finished Jul 13 06:25:47 PM PDT 24
Peak memory 257604 kb
Host smart-2b362b34-47d0-4818-ad67-c5094317a8f0
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717821961 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_hand
ler_stress_all.717821961
Directory /workspace/9.alert_handler_stress_all/latest
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