Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
esc_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	8	0	8	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	102307	1			T19	11		T4	3		T20	748
class_i[0x1]	36153	1			T17	1914		T15	2208		T62	536
class_i[0x2]	57907	1			T17	2462		T20	13		T7	2
class_i[0x3]	68013	1			T20	3		T29	795		T15	2

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Summary for Variable esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	63123	1			T17	1058		T4	2		T20	229
alert[0x1]	68838	1			T17	1128		T20	13		T7	1
alert[0x2]	63217	1			T17	1011		T19	4		T4	1
alert[0x3]	69202	1			T17	1179		T19	7		T20	521

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Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

esc_integrity_fail

264129

1

T17

4376

T19

11

T20

764

esc_ping_fail

251

1

T4

3

T9

7

T10

3

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Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	esc_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	alert[0x0]	63047	1			T17	1058		T20	229		T7	5
esc_integrity_fail	alert[0x1]	68776	1			T17	1128		T20	13		T7	1
esc_integrity_fail	alert[0x2]	63159	1			T17	1011		T19	4		T20	1
esc_integrity_fail	alert[0x3]	69147	1			T17	1179		T19	7		T20	521
esc_ping_fail	alert[0x0]	76	1			T4	2		T9	1		T10	1
esc_ping_fail	alert[0x1]	62	1			T9	4		T10	1		T102	2
esc_ping_fail	alert[0x2]	58	1			T4	1		T9	1		T102	2
esc_ping_fail	alert[0x3]	55	1			T9	1		T10	1		T102	4

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Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	class_i[0x0]	102247	1			T19	11		T20	748		T7	4
esc_integrity_fail	class_i[0x1]	36105	1			T17	1914		T15	2208		T62	536
esc_integrity_fail	class_i[0x2]	57821	1			T17	2462		T20	13		T7	2
esc_integrity_fail	class_i[0x3]	67956	1			T20	3		T29	795		T15	2
esc_ping_fail	class_i[0x0]	60	1			T4	3		T9	6		T202	5
esc_ping_fail	class_i[0x1]	48	1			T9	1		T102	11		T300	2
esc_ping_fail	class_i[0x2]	86	1			T10	3		T196	1		T296	1
esc_ping_fail	class_i[0x3]	57	1			T196	8		T304	2		T303	1