Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
94.44	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	40	3	37	92.50

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
intr_timeout_cnt_cp	10	0	10	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	40	3	37	92.50	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	69	1			T20	1		T21	1		T7	1
class_index[0x1]	61	1			T17	2		T18	2		T19	1
class_index[0x2]	68	1			T70	1		T33	2		T72	1
class_index[0x3]	64	1			T25	1		T33	1		T31	1

---

Summary for Variable intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for intr_timeout_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
intr_timeout_cnt[0]	92	1			T7	1		T60	1		T25	1
intr_timeout_cnt[1]	71	1			T17	1		T18	2		T21	1
intr_timeout_cnt[2]	19	1			T17	1		T67	1		T33	2
intr_timeout_cnt[3]	16	1			T74	1		T96	1		T274	1
intr_timeout_cnt[4]	14	1			T19	1		T20	1		T52	1
intr_timeout_cnt[5]	12	1			T62	1		T46	1		T275	1
intr_timeout_cnt[6]	17	1			T70	1		T120	3		T52	2
intr_timeout_cnt[7]	11	1			T20	1		T74	1		T52	1
intr_timeout_cnt[8]	2	1			T85	1		T58	1		-	-
intr_timeout_cnt[9]	8	1			T33	2		T52	1		T264	1

---

Summary for Cross class_cnt_cross

Samples crossed: class_index_cp intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	3	37	92.50	3

Automatically Generated Cross Bins for class_cnt_cross

Uncovered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	NUMBER	STATUS
[class_index[0x0] , class_index[0x1]]	[intr_timeout_cnt[8]]	--	--	2
[class_index[0x3]]	[intr_timeout_cnt[8]]	0	1	1

Covered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	intr_timeout_cnt[0]	29	1			T7	1		T70	1		T27	3
class_index[0x0]	intr_timeout_cnt[1]	16	1			T21	1		T68	1		T25	3
class_index[0x0]	intr_timeout_cnt[2]	4	1			T33	1		T58	1		T276	1
class_index[0x0]	intr_timeout_cnt[3]	2	1			T251	1		T277	1		-	-
class_index[0x0]	intr_timeout_cnt[4]	5	1			T20	1		T85	1		T57	1
class_index[0x0]	intr_timeout_cnt[5]	5	1			T62	1		T275	1		T278	1
class_index[0x0]	intr_timeout_cnt[6]	3	1			T52	2		T91	1		-	-
class_index[0x0]	intr_timeout_cnt[7]	3	1			T54	3		-	-		-	-
class_index[0x0]	intr_timeout_cnt[9]	2	1			T264	1		T253	1		-	-
class_index[0x1]	intr_timeout_cnt[0]	14	1			T60	1		T46	1		T251	1
class_index[0x1]	intr_timeout_cnt[1]	20	1			T17	1		T18	2		T68	1
class_index[0x1]	intr_timeout_cnt[2]	6	1			T17	1		T67	1		T98	1
class_index[0x1]	intr_timeout_cnt[3]	5	1			T274	1		T97	1		T81	1
class_index[0x1]	intr_timeout_cnt[4]	3	1			T19	1		T26	1		T279	1
class_index[0x1]	intr_timeout_cnt[5]	2	1			T46	1		T280	1		-	-
class_index[0x1]	intr_timeout_cnt[6]	7	1			T120	3		T97	1		T86	1
class_index[0x1]	intr_timeout_cnt[7]	3	1			T20	1		T74	1		T52	1
class_index[0x1]	intr_timeout_cnt[9]	1	1			T33	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[0]	27	1			T33	1		T74	1		T51	1
class_index[0x2]	intr_timeout_cnt[1]	14	1			T72	1		T47	1		T48	1
class_index[0x2]	intr_timeout_cnt[2]	5	1			T33	1		T86	1		T281	1
class_index[0x2]	intr_timeout_cnt[3]	5	1			T74	1		T96	1		T282	1
class_index[0x2]	intr_timeout_cnt[4]	4	1			T52	1		T283	1		T284	1
class_index[0x2]	intr_timeout_cnt[5]	3	1			T85	1		T111	2		-	-
class_index[0x2]	intr_timeout_cnt[6]	5	1			T70	1		T284	1		T285	1
class_index[0x2]	intr_timeout_cnt[7]	2	1			T54	1		T286	1		-	-
class_index[0x2]	intr_timeout_cnt[8]	2	1			T85	1		T58	1		-	-
class_index[0x2]	intr_timeout_cnt[9]	1	1			T270	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[0]	22	1			T25	1		T31	1		T49	1
class_index[0x3]	intr_timeout_cnt[1]	21	1			T49	1		T96	1		T287	1
class_index[0x3]	intr_timeout_cnt[2]	4	1			T95	1		T288	1		T289	1
class_index[0x3]	intr_timeout_cnt[3]	4	1			T97	1		T284	1		T290	2
class_index[0x3]	intr_timeout_cnt[4]	2	1			T277	1		T81	1		-	-
class_index[0x3]	intr_timeout_cnt[5]	2	1			T253	1		T291	1		-	-
class_index[0x3]	intr_timeout_cnt[6]	2	1			T97	1		T278	1		-	-
class_index[0x3]	intr_timeout_cnt[7]	3	1			T98	1		T112	2		-	-
class_index[0x3]	intr_timeout_cnt[9]	4	1			T33	1		T52	1		T286	1