Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	361520	1			T1	1157		T2	137		T3	119
all_values[1]	361520	1			T1	1157		T2	137		T3	119
all_values[2]	361520	1			T1	1157		T2	137		T3	119
all_values[3]	361520	1			T1	1157		T2	137		T3	119

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

719445

1

T1

2321

T2

297

T3

219

auto[1]

726635

1

T1

2307

T2

251

T3

257

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

870027

1

T1

3437

T2

284

T3

240

auto[1]

576053

1

T1

1191

T2

264

T3

236

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	104306	1			T1	452		T2	42		T3	29
all_values[0]	auto[0]	auto[1]	76595	1			T1	147		T2	37		T3	28
all_values[0]	auto[1]	auto[0]	104495	1			T1	430		T2	29		T3	31
all_values[0]	auto[1]	auto[1]	76124	1			T1	128		T2	29		T3	31
all_values[1]	auto[0]	auto[0]	109622	1			T1	337		T2	39		T3	29
all_values[1]	auto[0]	auto[1]	69781	1			T1	251		T2	38		T3	29
all_values[1]	auto[1]	auto[0]	111651	1			T1	326		T2	30		T3	31
all_values[1]	auto[1]	auto[1]	70466	1			T1	243		T2	30		T3	30
all_values[2]	auto[0]	auto[0]	109139	1			T1	379		T2	36		T3	28
all_values[2]	auto[0]	auto[1]	71138	1			T1	216		T2	34		T3	27
all_values[2]	auto[1]	auto[0]	109945	1			T1	360		T2	35		T3	32
all_values[2]	auto[1]	auto[1]	71298	1			T1	202		T2	32		T3	32
all_values[3]	auto[0]	auto[0]	108983	1			T1	537		T2	39		T3	25
all_values[3]	auto[0]	auto[1]	69881	1			T1	2		T2	32		T3	24
all_values[3]	auto[1]	auto[0]	111886	1			T1	616		T2	34		T3	35
all_values[3]	auto[1]	auto[1]	70770	1			T1	2		T2	32		T3	35