Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	4	0	4	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	361520	1			T1	1157		T2	137		T3	119
all_pins[1]	361520	1			T1	1157		T2	137		T3	119
all_pins[2]	361520	1			T1	1157		T2	137		T3	119
all_pins[3]	361520	1			T1	1157		T2	137		T3	119

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1157422	1			T1	4053		T2	425		T3	348
values[0x1]	288658	1			T1	575		T2	123		T3	128
transitions[0x0=>0x1]	192513	1			T1	439		T2	85		T3	76
transitions[0x1=>0x0]	192765	1			T1	439		T2	86		T3	76

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	285396	1			T1	1029		T2	108		T3	88
all_pins[0]	values[0x1]	76124	1			T1	128		T2	29		T3	31
all_pins[0]	transitions[0x0=>0x1]	75470	1			T1	128		T2	28		T3	31
all_pins[0]	transitions[0x1=>0x0]	70368	1			T1	2		T2	32		T3	35
all_pins[1]	values[0x0]	291054	1			T1	914		T2	107		T3	89
all_pins[1]	values[0x1]	70466	1			T1	243		T2	30		T3	30
all_pins[1]	transitions[0x0=>0x1]	38660	1			T1	185		T2	20		T3	15
all_pins[1]	transitions[0x1=>0x0]	44318	1			T1	70		T2	19		T3	16
all_pins[2]	values[0x0]	290222	1			T1	955		T2	105		T3	87
all_pins[2]	values[0x1]	71298	1			T1	202		T2	32		T3	32
all_pins[2]	transitions[0x0=>0x1]	39411	1			T1	124		T2	20		T3	15
all_pins[2]	transitions[0x1=>0x0]	38579	1			T1	165		T2	18		T3	13
all_pins[3]	values[0x0]	290750	1			T1	1155		T2	105		T3	84
all_pins[3]	values[0x1]	70770	1			T1	2		T2	32		T3	35
all_pins[3]	transitions[0x0=>0x1]	38972	1			T1	2		T2	17		T3	15
all_pins[3]	transitions[0x1=>0x0]	39500	1			T1	202		T2	17		T3	12