Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	269	1			T162	7		T163	7		T164	4
all_values[1]	269	1			T162	7		T163	7		T164	4
all_values[2]	269	1			T162	7		T163	7		T164	4
all_values[3]	269	1			T162	7		T163	7		T164	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

618

1

T162

17

T163

19

T164

9

auto[1]

458

1

T162

11

T163

9

T164

7

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

389

1

T162

10

T163

8

T164

6

auto[1]

687

1

T162

18

T163

20

T164

10

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

636

1

T162

15

T163

12

T164

9

auto[1]

440

1

T162

13

T163

16

T164

7

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	24	0	24	100.00
Automatically Generated Cross Bins	24	0	24	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr

cp_intr_test

cp_intr_en

cp_intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_values[0]

auto[0]

auto[0]

auto[0]

68

1

T163

3

T164

1

T339

3

all_values[0]

auto[0]

auto[0]

auto[1]

41

1

T162

2

T164

1

T339

1

all_values[0]

auto[0]

auto[1]

auto[0]

38

1

T162

2

T164

1

T339

2

all_values[0]

auto[0]

auto[1]

auto[1]

23

1

T163

1

T340

3

T341

1

all_values[0]

auto[1]

auto[0]

auto[1]

53

1

T162

3

T163

2

T342

1

all_values[0]

auto[1]

auto[1]

auto[1]

46

1

T163

1

T164

1

T339

1

all_values[1]

auto[0]

auto[0]

auto[0]

61

1

T162

3

T163

1

T342

3

all_values[1]

auto[0]

auto[0]

auto[1]

28

1

T163

1

T343

1

T340

1

all_values[1]

auto[0]

auto[1]

auto[0]

33

1

T164

1

T339

1

T344

1

all_values[1]

auto[0]

auto[1]

auto[1]

27

1

T162

1

T164

1

T339

2

all_values[1]

auto[1]

auto[0]

auto[1]

63

1

T163

4

T164

2

T339

1

all_values[1]

auto[1]

auto[1]

auto[1]

57

1

T162

3

T163

1

T339

3

all_values[2]

auto[0]

auto[0]

auto[0]

61

1

T163

4

T164

2

T339

2

all_values[2]

auto[0]

auto[0]

auto[1]

24

1

T162

1

T344

1

T340

4

all_values[2]

auto[0]

auto[1]

auto[0]

44

1

T164

1

T339

1

T342

2

all_values[2]

auto[0]

auto[1]

auto[1]

35

1

T162

1

T163

1

T339

1

all_values[2]

auto[1]

auto[0]

auto[1]

62

1

T162

4

T163

1

T164

1

all_values[2]

auto[1]

auto[1]

auto[1]

43

1

T162

1

T163

1

T339

3

all_values[3]

auto[0]

auto[0]

auto[0]

51

1

T162

3

T339

1

T342

1

all_values[3]

auto[0]

auto[0]

auto[1]

39

1

T163

1

T339

1

T343

1

all_values[3]

auto[0]

auto[1]

auto[0]

33

1

T162

2

T339

1

T342

2

all_values[3]

auto[0]

auto[1]

auto[1]

30

1

T164

1

T344

2

T340

1

all_values[3]

auto[1]

auto[0]

auto[1]

67

1

T162

1

T163

2

T164

2

all_values[3]

auto[1]

auto[1]

auto[1]

49

1

T162

1

T163

4

T164

1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal