Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
accum_cnt_cp	6	0	6	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	24	0	24	100.00	100	1	1	0

Summary for Variable accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for accum_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
accum_cnt_2000	86570	1			T17	415		T7	374		T6	1202
accum_cnt_1000	217599	1			T1	1212		T2	8		T3	13
accum_cnt_100	24788	1			T1	209		T2	29		T3	49
accum_cnt_50	69926	1			T1	200		T2	89		T3	36
accum_cnt_10	180943	1			T1	937		T2	10		T3	129
accum_cnt_0	449773	1			T1	890		T2	136		T3	9

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Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	266966	1			T1	862		T2	68		T3	59
class_index[0x1]	266966	1			T1	862		T2	68		T3	59
class_index[0x2]	266966	1			T1	862		T2	68		T3	59
class_index[0x3]	266966	1			T1	862		T2	68		T3	59

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Summary for Cross class_cnt_cross

Samples crossed: class_index_cp accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for class_cnt_cross

Bins

class_index_cp	accum_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	accum_cnt_2000	27313	1			T17	244		T7	229		T14	274
class_index[0x0]	accum_cnt_1000	61109	1			T1	535		T3	4		T17	348
class_index[0x0]	accum_cnt_100	6398	1			T1	137		T3	22		T17	74
class_index[0x0]	accum_cnt_50	20284	1			T1	129		T3	17		T17	59
class_index[0x0]	accum_cnt_10	37056	1			T1	33		T3	11		T17	20
class_index[0x0]	accum_cnt_0	98787	1			T1	28		T2	68		T3	5
class_index[0x1]	accum_cnt_2000	21186	1			T17	120		T7	69		T6	660
class_index[0x1]	accum_cnt_1000	55788	1			T17	801		T7	1465		T6	741
class_index[0x1]	accum_cnt_100	5932	1			T17	87		T19	8		T7	52
class_index[0x1]	accum_cnt_50	18309	1			T2	64		T17	72		T19	39
class_index[0x1]	accum_cnt_10	50091	1			T1	862		T2	4		T3	56
class_index[0x1]	accum_cnt_0	106895	1			T3	3		T17	1837		T18	5
class_index[0x2]	accum_cnt_2000	18372	1			T7	76		T15	97		T66	428
class_index[0x2]	accum_cnt_1000	49581	1			T1	677		T5	767		T7	823
class_index[0x2]	accum_cnt_100	6592	1			T1	72		T17	11		T5	77
class_index[0x2]	accum_cnt_50	17278	1			T1	71		T17	232		T21	24
class_index[0x2]	accum_cnt_10	56210	1			T1	42		T3	58		T17	873
class_index[0x2]	accum_cnt_0	111976	1			T2	68		T3	1		T17	1833
class_index[0x3]	accum_cnt_2000	19699	1			T17	51		T6	542		T15	104
class_index[0x3]	accum_cnt_1000	51121	1			T2	8		T3	9		T17	954
class_index[0x3]	accum_cnt_100	5866	1			T2	29		T3	27		T17	61
class_index[0x3]	accum_cnt_50	14055	1			T2	25		T3	19		T17	63
class_index[0x3]	accum_cnt_10	37586	1			T2	6		T3	4		T17	26
class_index[0x3]	accum_cnt_0	132115	1			T1	862		T17	1794		T18	8