Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	71	0	71	100.00
Crosses	138	0	138	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
alert_index_cp	65	0	65	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	130	0	130	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for alert_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	7290	1			T17	27		T4	1		T39	1
alert[0x1]	6328	1			T17	233		T4	1		T20	1
alert[0x2]	10616	1			T17	425		T39	2		T29	1
alert[0x3]	6993	1			T17	25		T7	115		T10	1
alert[0x4]	7115	1			T17	7		T29	3		T9	1
alert[0x5]	9683	1			T17	2194		T45	14		T70	9
alert[0x6]	9934	1			T19	1		T25	2		T65	20
alert[0x7]	8832	1			T39	2		T9	2		T46	2
alert[0x8]	8735	1			T17	499		T39	1		T16	1
alert[0x9]	9539	1			T63	2		T9	1		T66	103
alert[0xa]	3589	1			T5	2		T7	1		T25	5
alert[0xb]	10621	1			T17	44		T29	7		T63	8
alert[0xc]	6985	1			T4	1		T9	1		T65	29
alert[0xd]	9268	1			T17	850		T45	121		T196	1
alert[0xe]	8642	1			T10	1		T45	161		T66	165
alert[0xf]	3914	1			T17	5		T39	21		T9	1
alert[0x10]	4482	1			T4	1		T7	8		T9	1
alert[0x11]	6862	1			T17	6		T7	18		T63	1
alert[0x12]	5901	1			T7	2		T25	3		T196	1
alert[0x13]	8618	1			T39	3		T29	1		T62	8
alert[0x14]	4129	1			T4	1		T63	1		T94	1
alert[0x15]	6306	1			T17	354		T20	8		T8	1
alert[0x16]	8929	1			T9	1		T45	15		T65	51
alert[0x17]	4622	1			T25	3		T70	173		T46	286
alert[0x18]	3564	1			T17	63		T19	1		T45	34
alert[0x19]	7228	1			T19	2		T29	1		T70	1
alert[0x1a]	11394	1			T63	2		T9	1		T10	1
alert[0x1b]	8289	1			T17	49		T29	4		T9	1
alert[0x1c]	23277	1			T17	1318		T63	3		T45	24
alert[0x1d]	3495	1			T17	84		T4	1		T20	2
alert[0x1e]	12878	1			T17	33		T7	28		T63	1
alert[0x1f]	13557	1			T17	2		T45	107		T65	14
alert[0x20]	4336	1			T17	174		T20	7		T7	1
alert[0x21]	10931	1			T17	90		T45	695		T77	2
alert[0x22]	3543	1			T17	9		T7	78		T8	1
alert[0x23]	11708	1			T17	5652		T29	3		T15	42
alert[0x24]	21105	1			T9	1		T65	49		T66	33
alert[0x25]	4735	1			T7	59		T39	5		T66	428
alert[0x26]	6330	1			T17	21		T65	231		T46	1794
alert[0x27]	18716	1			T7	5		T65	529		T66	95
alert[0x28]	13308	1			T102	1		T196	1		T33	2
alert[0x29]	3957	1			T15	1		T65	18		T46	373
alert[0x2a]	9416	1			T45	247		T25	6		T65	153
alert[0x2b]	2801	1			T63	1		T25	1		T66	4
alert[0x2c]	7566	1			T17	40		T63	4		T102	1
alert[0x2d]	8430	1			T7	1		T25	2		T65	11
alert[0x2e]	4494	1			T25	3		T65	101		T66	32
alert[0x2f]	7697	1			T20	1		T7	71		T102	1
alert[0x30]	2903	1			T5	1		T94	1		T10	1
alert[0x31]	3405	1			T17	113		T7	60		T65	5
alert[0x32]	11151	1			T17	21		T39	1		T65	182
alert[0x33]	3889	1			T39	5		T65	264		T102	1
alert[0x34]	21704	1			T17	10		T62	7		T25	17
alert[0x35]	6830	1			T17	102		T39	3		T63	1
alert[0x36]	5787	1			T17	1069		T9	1		T10	1
alert[0x37]	13061	1			T7	15		T39	3		T65	178
alert[0x38]	3853	1			T17	12		T45	32		T66	93
alert[0x39]	3354	1			T7	7		T9	1		T45	73
alert[0x3a]	8070	1			T17	42		T45	599		T65	549
alert[0x3b]	5095	1			T17	36		T7	1		T15	1
alert[0x3c]	8929	1			T4	1		T62	17		T25	5
alert[0x3d]	11180	1			T17	106		T20	1		T7	371
alert[0x3e]	6125	1			T17	2813		T19	2		T4	1
alert[0x3f]	4645	1			T17	10		T63	8		T66	58
alert[0x40]	2462	1			T17	13		T20	1		T7	19

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	128032	1			T17	3822		T19	4		T4	6
class_i[0x1]	133313	1			T17	12729		T19	2		T4	1
class_i[0x2]	115168	1			T4	1		T39	32		T8	2
class_i[0x3]	146618	1			T20	3		T7	915		T39	14

---

Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

alert_integrity_fail

522523

1

T17

16551

T19

6

T20

21

alert_ping_fail

608

1

T4

8

T5

3

T8

2

---

Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	0	130	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	alert_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	alert[0x0]	7281	1			T17	27		T39	1		T46	31
alert_integrity_fail	alert[0x1]	6324	1			T17	233		T20	1		T7	84
alert_integrity_fail	alert[0x2]	10607	1			T17	425		T39	2		T29	1
alert_integrity_fail	alert[0x3]	6984	1			T17	25		T7	115		T45	4
alert_integrity_fail	alert[0x4]	7108	1			T17	7		T29	3		T46	947
alert_integrity_fail	alert[0x5]	9676	1			T17	2194		T45	14		T70	9
alert_integrity_fail	alert[0x6]	9922	1			T19	1		T25	2		T65	20
alert_integrity_fail	alert[0x7]	8822	1			T39	2		T46	2		T47	1
alert_integrity_fail	alert[0x8]	8725	1			T17	499		T39	1		T25	3
alert_integrity_fail	alert[0x9]	9526	1			T63	2		T66	103		T46	63
alert_integrity_fail	alert[0xa]	3578	1			T7	1		T25	5		T27	43
alert_integrity_fail	alert[0xb]	10614	1			T17	44		T29	7		T63	8
alert_integrity_fail	alert[0xc]	6974	1			T65	29		T66	12		T70	198
alert_integrity_fail	alert[0xd]	9260	1			T17	850		T45	121		T47	2
alert_integrity_fail	alert[0xe]	8632	1			T45	161		T66	165		T70	2025
alert_integrity_fail	alert[0xf]	3909	1			T17	5		T39	21		T66	13
alert_integrity_fail	alert[0x10]	4472	1			T7	8		T65	78		T66	279
alert_integrity_fail	alert[0x11]	6855	1			T17	6		T7	18		T63	1
alert_integrity_fail	alert[0x12]	5892	1			T7	2		T25	3		T70	2429
alert_integrity_fail	alert[0x13]	8610	1			T39	3		T29	1		T62	8
alert_integrity_fail	alert[0x14]	4116	1			T63	1		T65	41		T70	38
alert_integrity_fail	alert[0x15]	6292	1			T17	354		T20	8		T25	1
alert_integrity_fail	alert[0x16]	8918	1			T45	15		T65	51		T46	2
alert_integrity_fail	alert[0x17]	4615	1			T25	3		T70	173		T46	286
alert_integrity_fail	alert[0x18]	3556	1			T17	63		T19	1		T45	34
alert_integrity_fail	alert[0x19]	7223	1			T19	2		T29	1		T70	1
alert_integrity_fail	alert[0x1a]	11381	1			T63	2		T27	608		T33	1
alert_integrity_fail	alert[0x1b]	8280	1			T17	49		T29	4		T65	5
alert_integrity_fail	alert[0x1c]	23270	1			T17	1318		T63	3		T45	24
alert_integrity_fail	alert[0x1d]	3484	1			T17	84		T20	2		T63	2
alert_integrity_fail	alert[0x1e]	12874	1			T17	33		T7	28		T63	1
alert_integrity_fail	alert[0x1f]	13541	1			T17	2		T45	107		T65	14
alert_integrity_fail	alert[0x20]	4328	1			T17	174		T20	7		T7	1
alert_integrity_fail	alert[0x21]	10925	1			T17	90		T45	695		T77	2
alert_integrity_fail	alert[0x22]	3530	1			T17	9		T7	78		T45	94
alert_integrity_fail	alert[0x23]	11699	1			T17	5652		T29	3		T15	42
alert_integrity_fail	alert[0x24]	21101	1			T65	49		T66	33		T27	86
alert_integrity_fail	alert[0x25]	4724	1			T7	59		T39	5		T66	428
alert_integrity_fail	alert[0x26]	6321	1			T17	21		T65	231		T46	1794
alert_integrity_fail	alert[0x27]	18705	1			T7	5		T65	529		T66	95
alert_integrity_fail	alert[0x28]	13299	1			T33	2		T292	14		T31	4
alert_integrity_fail	alert[0x29]	3952	1			T15	1		T65	18		T46	373
alert_integrity_fail	alert[0x2a]	9406	1			T45	247		T25	6		T65	153
alert_integrity_fail	alert[0x2b]	2793	1			T63	1		T25	1		T66	4
alert_integrity_fail	alert[0x2c]	7549	1			T17	40		T63	4		T70	1
alert_integrity_fail	alert[0x2d]	8415	1			T7	1		T25	2		T65	11
alert_integrity_fail	alert[0x2e]	4485	1			T25	3		T65	101		T66	32
alert_integrity_fail	alert[0x2f]	7684	1			T20	1		T7	71		T292	285
alert_integrity_fail	alert[0x30]	2885	1			T65	2		T27	226		T74	5
alert_integrity_fail	alert[0x31]	3393	1			T17	113		T7	60		T65	5
alert_integrity_fail	alert[0x32]	11140	1			T17	21		T39	1		T65	182
alert_integrity_fail	alert[0x33]	3879	1			T39	5		T65	264		T27	25
alert_integrity_fail	alert[0x34]	21697	1			T17	10		T62	7		T25	17
alert_integrity_fail	alert[0x35]	6824	1			T17	102		T39	3		T63	1
alert_integrity_fail	alert[0x36]	5776	1			T17	1069		T66	87		T70	12
alert_integrity_fail	alert[0x37]	13051	1			T7	15		T39	3		T65	178
alert_integrity_fail	alert[0x38]	3845	1			T17	12		T45	32		T66	93
alert_integrity_fail	alert[0x39]	3348	1			T7	7		T45	73		T46	8
alert_integrity_fail	alert[0x3a]	8059	1			T17	42		T45	599		T65	549
alert_integrity_fail	alert[0x3b]	5091	1			T17	36		T7	1		T15	1
alert_integrity_fail	alert[0x3c]	8918	1			T62	17		T25	5		T65	9
alert_integrity_fail	alert[0x3d]	11170	1			T17	106		T20	1		T7	371
alert_integrity_fail	alert[0x3e]	6114	1			T17	2813		T19	2		T7	10
alert_integrity_fail	alert[0x3f]	4640	1			T17	10		T63	8		T66	58
alert_integrity_fail	alert[0x40]	2456	1			T17	13		T20	1		T7	19
alert_ping_fail	alert[0x0]	9	1			T4	1		T9	1		T196	1
alert_ping_fail	alert[0x1]	4	1			T4	1		T196	1		T293	1
alert_ping_fail	alert[0x2]	9	1			T196	1		T199	1		T244	1
alert_ping_fail	alert[0x3]	9	1			T10	1		T294	1		T295	1
alert_ping_fail	alert[0x4]	7	1			T9	1		T296	1		T294	1
alert_ping_fail	alert[0x5]	7	1			T104	1		T297	1		T298	1
alert_ping_fail	alert[0x6]	12	1			T202	1		T294	1		T299	1
alert_ping_fail	alert[0x7]	10	1			T9	2		T199	1		T300	1
alert_ping_fail	alert[0x8]	10	1			T16	1		T9	1		T299	1
alert_ping_fail	alert[0x9]	13	1			T9	1		T196	1		T294	1
alert_ping_fail	alert[0xa]	11	1			T5	2		T202	1		T106	1
alert_ping_fail	alert[0xb]	7	1			T9	1		T294	1		T262	1
alert_ping_fail	alert[0xc]	11	1			T4	1		T9	1		T196	1
alert_ping_fail	alert[0xd]	8	1			T196	1		T104	1		T299	1
alert_ping_fail	alert[0xe]	10	1			T10	1		T102	1		T196	1
alert_ping_fail	alert[0xf]	5	1			T9	1		T301	1		T302	1
alert_ping_fail	alert[0x10]	10	1			T4	1		T9	1		T196	1
alert_ping_fail	alert[0x11]	7	1			T9	1		T294	1		T244	1
alert_ping_fail	alert[0x12]	9	1			T196	1		T296	1		T244	1
alert_ping_fail	alert[0x13]	8	1			T102	1		T104	1		T303	1
alert_ping_fail	alert[0x14]	13	1			T4	1		T94	1		T76	1
alert_ping_fail	alert[0x15]	14	1			T8	1		T102	2		T304	1
alert_ping_fail	alert[0x16]	11	1			T9	1		T202	1		T300	1
alert_ping_fail	alert[0x17]	7	1			T199	1		T296	1		T294	1
alert_ping_fail	alert[0x18]	8	1			T301	1		T262	1		T305	1
alert_ping_fail	alert[0x19]	5	1			T304	1		T306	1		T307	1
alert_ping_fail	alert[0x1a]	13	1			T9	1		T10	1		T102	1
alert_ping_fail	alert[0x1b]	9	1			T9	1		T104	1		T262	2
alert_ping_fail	alert[0x1c]	7	1			T196	1		T201	1		T199	2
alert_ping_fail	alert[0x1d]	11	1			T4	1		T9	1		T196	3
alert_ping_fail	alert[0x1e]	4	1			T104	2		T262	1		T308	1
alert_ping_fail	alert[0x1f]	16	1			T104	2		T300	1		T309	2
alert_ping_fail	alert[0x20]	8	1			T102	2		T294	1		T302	1
alert_ping_fail	alert[0x21]	6	1			T299	1		T241	1		T305	1
alert_ping_fail	alert[0x22]	13	1			T8	1		T102	1		T199	1
alert_ping_fail	alert[0x23]	9	1			T199	1		T294	1		T303	1
alert_ping_fail	alert[0x24]	4	1			T9	1		T310	1		T311	1
alert_ping_fail	alert[0x25]	11	1			T196	1		T294	1		T312	1
alert_ping_fail	alert[0x26]	9	1			T104	1		T294	1		T244	1
alert_ping_fail	alert[0x27]	11	1			T102	1		T196	1		T312	1
alert_ping_fail	alert[0x28]	9	1			T102	1		T196	1		T241	1
alert_ping_fail	alert[0x29]	5	1			T199	1		T312	1		T313	1
alert_ping_fail	alert[0x2a]	10	1			T196	1		T294	1		T241	1
alert_ping_fail	alert[0x2b]	8	1			T199	3		T104	1		T314	1
alert_ping_fail	alert[0x2c]	17	1			T102	1		T241	1		T315	2
alert_ping_fail	alert[0x2d]	15	1			T102	1		T294	1		T304	1
alert_ping_fail	alert[0x2e]	9	1			T241	1		T244	1		T314	1
alert_ping_fail	alert[0x2f]	13	1			T102	1		T199	1		T312	1
alert_ping_fail	alert[0x30]	18	1			T5	1		T94	1		T10	1
alert_ping_fail	alert[0x31]	12	1			T294	1		T299	1		T244	2
alert_ping_fail	alert[0x32]	11	1			T102	2		T104	1		T294	1
alert_ping_fail	alert[0x33]	10	1			T102	1		T104	1		T304	1
alert_ping_fail	alert[0x34]	7	1			T104	1		T303	1		T316	1
alert_ping_fail	alert[0x35]	6	1			T304	1		T262	1		T306	1
alert_ping_fail	alert[0x36]	11	1			T9	1		T10	1		T294	1
alert_ping_fail	alert[0x37]	10	1			T196	1		T300	1		T244	1
alert_ping_fail	alert[0x38]	8	1			T104	1		T294	1		T262	1
alert_ping_fail	alert[0x39]	6	1			T9	1		T104	1		T294	1
alert_ping_fail	alert[0x3a]	11	1			T196	1		T199	1		T312	1
alert_ping_fail	alert[0x3b]	4	1			T102	1		T196	1		T295	1
alert_ping_fail	alert[0x3c]	11	1			T4	1		T102	1		T202	1
alert_ping_fail	alert[0x3d]	10	1			T102	1		T202	2		T104	1
alert_ping_fail	alert[0x3e]	11	1			T4	1		T244	1		T317	1
alert_ping_fail	alert[0x3f]	5	1			T104	1		T241	1		T316	1
alert_ping_fail	alert[0x40]	6	1			T196	1		T294	1		T302	2

---

Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	class_i[0x0]	127886	1			T17	3822		T19	4		T20	18
alert_integrity_fail	class_i[0x1]	133167	1			T17	12729		T19	2		T7	35
alert_integrity_fail	class_i[0x2]	115025	1			T39	32		T63	39		T65	6229
alert_integrity_fail	class_i[0x3]	146445	1			T20	3		T7	915		T39	14
alert_ping_fail	class_i[0x0]	146	1			T4	6		T94	2		T10	5
alert_ping_fail	class_i[0x1]	146	1			T4	1		T5	3		T16	1
alert_ping_fail	class_i[0x2]	143	1			T4	1		T8	2		T9	17
alert_ping_fail	class_i[0x3]	173	1			T102	3		T196	3		T76	1