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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.63 99.99 98.64 99.97 100.00 100.00 99.38 99.44


Total test records in report: 832
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html
T154 /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.1676830800 Jul 19 04:34:32 PM PDT 24 Jul 19 04:36:52 PM PDT 24 3582017575 ps
T772 /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.2950256073 Jul 19 04:34:47 PM PDT 24 Jul 19 04:34:50 PM PDT 24 7912498 ps
T773 /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.4152569547 Jul 19 04:34:32 PM PDT 24 Jul 19 04:34:59 PM PDT 24 1203385737 ps
T140 /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.2710969841 Jul 19 04:34:21 PM PDT 24 Jul 19 04:37:53 PM PDT 24 6516732567 ps
T131 /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.691207981 Jul 19 04:35:54 PM PDT 24 Jul 19 04:53:55 PM PDT 24 63867853551 ps
T774 /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.393894095 Jul 19 04:34:37 PM PDT 24 Jul 19 04:34:52 PM PDT 24 382483591 ps
T775 /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.1012457373 Jul 19 04:34:34 PM PDT 24 Jul 19 04:34:51 PM PDT 24 247004690 ps
T141 /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.3898046206 Jul 19 04:34:55 PM PDT 24 Jul 19 04:36:44 PM PDT 24 4858034496 ps
T776 /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.1168464808 Jul 19 04:34:37 PM PDT 24 Jul 19 04:34:45 PM PDT 24 8061606 ps
T777 /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.1354114476 Jul 19 04:34:52 PM PDT 24 Jul 19 04:38:19 PM PDT 24 3122559002 ps
T175 /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.2014238085 Jul 19 04:34:53 PM PDT 24 Jul 19 04:34:57 PM PDT 24 56525315 ps
T778 /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.388179680 Jul 19 04:34:28 PM PDT 24 Jul 19 04:34:45 PM PDT 24 115448716 ps
T779 /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.3866149724 Jul 19 04:34:59 PM PDT 24 Jul 19 04:35:03 PM PDT 24 7959596 ps
T142 /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.4110894681 Jul 19 04:34:24 PM PDT 24 Jul 19 04:38:47 PM PDT 24 2457596935 ps
T780 /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.2963410673 Jul 19 04:34:19 PM PDT 24 Jul 19 04:39:03 PM PDT 24 4774584906 ps
T781 /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.3202795375 Jul 19 04:34:36 PM PDT 24 Jul 19 04:34:56 PM PDT 24 810309084 ps
T132 /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.362422761 Jul 19 04:34:32 PM PDT 24 Jul 19 04:43:09 PM PDT 24 21584282311 ps
T782 /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.1934669817 Jul 19 04:34:56 PM PDT 24 Jul 19 04:35:00 PM PDT 24 20187866 ps
T783 /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.3343003483 Jul 19 04:34:51 PM PDT 24 Jul 19 04:34:55 PM PDT 24 10925151 ps
T784 /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.1040915832 Jul 19 04:34:55 PM PDT 24 Jul 19 04:35:11 PM PDT 24 308479281 ps
T785 /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.1809815363 Jul 19 04:34:46 PM PDT 24 Jul 19 04:34:49 PM PDT 24 6896646 ps
T786 /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.2047717262 Jul 19 04:34:29 PM PDT 24 Jul 19 04:34:58 PM PDT 24 309660967 ps
T158 /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.1064373106 Jul 19 04:34:55 PM PDT 24 Jul 19 04:43:17 PM PDT 24 27974459983 ps
T787 /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.960803091 Jul 19 04:34:56 PM PDT 24 Jul 19 04:35:23 PM PDT 24 217516168 ps
T345 /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.1950617137 Jul 19 04:34:53 PM PDT 24 Jul 19 04:40:04 PM PDT 24 11050370492 ps
T172 /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.2157278659 Jul 19 04:34:27 PM PDT 24 Jul 19 04:34:41 PM PDT 24 46140809 ps
T788 /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.3063317237 Jul 19 04:34:43 PM PDT 24 Jul 19 04:34:55 PM PDT 24 134213338 ps
T789 /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.2282285223 Jul 19 04:34:19 PM PDT 24 Jul 19 04:34:54 PM PDT 24 645304504 ps
T790 /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.1307879123 Jul 19 04:34:14 PM PDT 24 Jul 19 04:34:47 PM PDT 24 661332607 ps
T791 /workspace/coverage/cover_reg_top/33.alert_handler_intr_test.117302298 Jul 19 04:35:02 PM PDT 24 Jul 19 04:35:05 PM PDT 24 19237458 ps
T792 /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.3539530389 Jul 19 04:34:33 PM PDT 24 Jul 19 04:38:49 PM PDT 24 13480905180 ps
T793 /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.252535364 Jul 19 04:34:35 PM PDT 24 Jul 19 04:34:47 PM PDT 24 326874442 ps
T794 /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.3984087646 Jul 19 04:34:59 PM PDT 24 Jul 19 04:35:03 PM PDT 24 9551386 ps
T795 /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.3045880239 Jul 19 04:34:20 PM PDT 24 Jul 19 04:34:37 PM PDT 24 255763297 ps
T796 /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.3590452640 Jul 19 04:34:57 PM PDT 24 Jul 19 04:35:01 PM PDT 24 11353146 ps
T797 /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.1457257645 Jul 19 04:34:26 PM PDT 24 Jul 19 04:34:42 PM PDT 24 36771886 ps
T798 /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.4115237069 Jul 19 04:35:03 PM PDT 24 Jul 19 04:35:06 PM PDT 24 20133796 ps
T799 /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.2984321798 Jul 19 04:34:36 PM PDT 24 Jul 19 04:34:57 PM PDT 24 726927375 ps
T800 /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.1167270759 Jul 19 04:34:36 PM PDT 24 Jul 19 04:34:46 PM PDT 24 119186086 ps
T801 /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.881793909 Jul 19 04:34:40 PM PDT 24 Jul 19 04:34:55 PM PDT 24 273467546 ps
T802 /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.375664069 Jul 19 04:34:58 PM PDT 24 Jul 19 04:35:02 PM PDT 24 15006489 ps
T803 /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.304795956 Jul 19 04:34:27 PM PDT 24 Jul 19 04:34:39 PM PDT 24 10080136 ps
T804 /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.94554148 Jul 19 04:34:56 PM PDT 24 Jul 19 04:35:01 PM PDT 24 9953123 ps
T805 /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.4122795591 Jul 19 04:34:53 PM PDT 24 Jul 19 04:35:04 PM PDT 24 112081306 ps
T806 /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.1134395812 Jul 19 04:34:21 PM PDT 24 Jul 19 04:34:40 PM PDT 24 208495672 ps
T807 /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.2142996517 Jul 19 04:34:24 PM PDT 24 Jul 19 04:34:40 PM PDT 24 34741499 ps
T808 /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.3544764918 Jul 19 04:34:24 PM PDT 24 Jul 19 04:34:45 PM PDT 24 144428070 ps
T809 /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.83038898 Jul 19 04:34:58 PM PDT 24 Jul 19 04:35:02 PM PDT 24 7595281 ps
T810 /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.1099850855 Jul 19 04:34:58 PM PDT 24 Jul 19 04:35:02 PM PDT 24 13947166 ps
T811 /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.2839237368 Jul 19 04:34:21 PM PDT 24 Jul 19 04:34:41 PM PDT 24 438222066 ps
T812 /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.848306292 Jul 19 04:34:47 PM PDT 24 Jul 19 04:34:54 PM PDT 24 39667846 ps
T177 /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.3659331076 Jul 19 04:34:39 PM PDT 24 Jul 19 04:34:48 PM PDT 24 51663249 ps
T171 /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.4165094858 Jul 19 04:34:49 PM PDT 24 Jul 19 04:34:53 PM PDT 24 91684995 ps
T813 /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.3287566007 Jul 19 04:34:49 PM PDT 24 Jul 19 04:35:06 PM PDT 24 102135761 ps
T155 /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.315991339 Jul 19 04:34:35 PM PDT 24 Jul 19 04:40:21 PM PDT 24 9831434647 ps
T167 /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.2873268387 Jul 19 04:34:52 PM PDT 24 Jul 19 04:34:56 PM PDT 24 28745243 ps
T814 /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.384061432 Jul 19 04:34:46 PM PDT 24 Jul 19 04:34:53 PM PDT 24 64355875 ps
T815 /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.1656197643 Jul 19 04:34:54 PM PDT 24 Jul 19 04:35:03 PM PDT 24 675186205 ps
T176 /workspace/coverage/cover_reg_top/12.alert_handler_tl_intg_err.1398744686 Jul 19 04:34:40 PM PDT 24 Jul 19 04:34:47 PM PDT 24 82200013 ps
T346 /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.1646588316 Jul 19 04:34:40 PM PDT 24 Jul 19 04:40:08 PM PDT 24 2219226439 ps
T816 /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.620051848 Jul 19 04:34:25 PM PDT 24 Jul 19 04:34:46 PM PDT 24 139710060 ps
T817 /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.1883398013 Jul 19 04:34:40 PM PDT 24 Jul 19 04:35:33 PM PDT 24 2188156706 ps
T818 /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.2418981189 Jul 19 04:35:00 PM PDT 24 Jul 19 04:35:03 PM PDT 24 10323858 ps
T145 /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.272479781 Jul 19 04:34:38 PM PDT 24 Jul 19 04:40:34 PM PDT 24 6626059945 ps
T819 /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.2521629889 Jul 19 04:34:47 PM PDT 24 Jul 19 04:35:14 PM PDT 24 1829866975 ps
T156 /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.1075568455 Jul 19 04:34:27 PM PDT 24 Jul 19 04:54:52 PM PDT 24 33639952882 ps
T820 /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.934543373 Jul 19 04:34:25 PM PDT 24 Jul 19 04:35:01 PM PDT 24 371657576 ps
T821 /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.4208967504 Jul 19 04:34:23 PM PDT 24 Jul 19 04:35:12 PM PDT 24 589779854 ps
T166 /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.1253087654 Jul 19 04:34:55 PM PDT 24 Jul 19 04:35:15 PM PDT 24 449697150 ps
T822 /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.560432932 Jul 19 04:34:56 PM PDT 24 Jul 19 04:35:00 PM PDT 24 19447477 ps
T823 /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.1766782777 Jul 19 04:35:01 PM PDT 24 Jul 19 04:35:05 PM PDT 24 9950282 ps
T824 /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.2991368763 Jul 19 04:34:47 PM PDT 24 Jul 19 04:35:25 PM PDT 24 3363953296 ps
T825 /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.2158217718 Jul 19 04:34:56 PM PDT 24 Jul 19 04:35:17 PM PDT 24 1016465073 ps
T826 /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.1127521101 Jul 19 04:34:53 PM PDT 24 Jul 19 04:34:55 PM PDT 24 20141661 ps
T157 /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.812356409 Jul 19 04:34:36 PM PDT 24 Jul 19 04:36:27 PM PDT 24 4059377524 ps
T827 /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.3789818656 Jul 19 04:34:24 PM PDT 24 Jul 19 04:34:40 PM PDT 24 48065741 ps
T828 /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.3179747052 Jul 19 04:34:48 PM PDT 24 Jul 19 04:34:55 PM PDT 24 196884224 ps
T829 /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.344987573 Jul 19 04:34:39 PM PDT 24 Jul 19 04:34:58 PM PDT 24 108984538 ps
T830 /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.781543475 Jul 19 04:34:24 PM PDT 24 Jul 19 04:34:40 PM PDT 24 17803184 ps
T153 /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.3834526124 Jul 19 04:34:55 PM PDT 24 Jul 19 04:38:14 PM PDT 24 7078887834 ps
T831 /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.118230748 Jul 19 04:34:30 PM PDT 24 Jul 19 04:34:44 PM PDT 24 40705713 ps
T832 /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.3584175394 Jul 19 04:34:36 PM PDT 24 Jul 19 04:34:53 PM PDT 24 621607461 ps

Test location /workspace/coverage/default/2.alert_handler_stress_all_with_rand_reset.3612661798
Short name T17
Test name
Test status
Simulation time 266836717983 ps
CPU time 9568.2 seconds
Started Jul 19 04:48:43 PM PDT 24
Finished Jul 19 07:28:29 PM PDT 24
Peak memory 355068 kb
Host smart-7b86cf35-cb4b-4b1b-80e1-9c8c71e04396
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612661798 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.alert_handler_stress_all_with_rand_reset.3612661798
Directory /workspace/2.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.alert_handler_sec_cm.2070146009
Short name T11
Test name
Test status
Simulation time 1792212614 ps
CPU time 23.9 seconds
Started Jul 19 04:48:43 PM PDT 24
Finished Jul 19 04:49:24 PM PDT 24
Peak memory 271368 kb
Host smart-93b591f4-c020-43be-86e8-488ccd7dd4cb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2070146009 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sec_cm.2070146009
Directory /workspace/1.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all_with_rand_reset.3135324804
Short name T7
Test name
Test status
Simulation time 41104682894 ps
CPU time 4191.6 seconds
Started Jul 19 04:48:41 PM PDT 24
Finished Jul 19 05:58:50 PM PDT 24
Peak memory 321456 kb
Host smart-c452d2af-376c-47e5-8325-ff176acad2ca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135324804 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.alert_handler_stress_all_with_rand_reset.3135324804
Directory /workspace/3.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.alert_handler_entropy_stress.3899056285
Short name T195
Test name
Test status
Simulation time 731387363 ps
CPU time 16.8 seconds
Started Jul 19 04:48:45 PM PDT 24
Finished Jul 19 04:49:18 PM PDT 24
Peak memory 248892 kb
Host smart-55cad437-8707-4117-a553-d966a398ff04
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3899056285 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy_stress.3899056285
Directory /workspace/10.alert_handler_entropy_stress/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.196248631
Short name T160
Test name
Test status
Simulation time 312591997 ps
CPU time 41.33 seconds
Started Jul 19 04:34:28 PM PDT 24
Finished Jul 19 04:35:19 PM PDT 24
Peak memory 237752 kb
Host smart-308d8ad9-5176-452a-b7e4-1e5452eb8d4e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=196248631 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_intg_err.196248631
Directory /workspace/7.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all_with_rand_reset.3313087929
Short name T87
Test name
Test status
Simulation time 213012407634 ps
CPU time 3461.48 seconds
Started Jul 19 04:49:36 PM PDT 24
Finished Jul 19 05:47:33 PM PDT 24
Peak memory 290084 kb
Host smart-cfebaad0-e6ca-42f8-9061-e1d5971ef367
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313087929 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 33.alert_handler_stress_all_with_rand_reset.3313087929
Directory /workspace/33.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all.2593738564
Short name T33
Test name
Test status
Simulation time 34771722720 ps
CPU time 1494.57 seconds
Started Jul 19 04:49:27 PM PDT 24
Finished Jul 19 05:14:35 PM PDT 24
Peak memory 289560 kb
Host smart-4e7e659a-4a6a-4c98-9c02-98946ce6b527
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593738564 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_ha
ndler_stress_all.2593738564
Directory /workspace/25.alert_handler_stress_all/latest

Test location /workspace/coverage/default/38.alert_handler_entropy.3098791335
Short name T606
Test name
Test status
Simulation time 16928340516 ps
CPU time 1207.86 seconds
Started Jul 19 04:49:50 PM PDT 24
Finished Jul 19 05:10:07 PM PDT 24
Peak memory 273576 kb
Host smart-a0f6efe2-e31a-455c-ad94-9dd597c567e8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098791335 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_entropy.3098791335
Directory /workspace/38.alert_handler_entropy/latest

Test location /workspace/coverage/default/18.alert_handler_lpg.534744658
Short name T94
Test name
Test status
Simulation time 50723820082 ps
CPU time 3144.49 seconds
Started Jul 19 04:49:10 PM PDT 24
Finished Jul 19 05:41:45 PM PDT 24
Peak memory 289752 kb
Host smart-fb0baa53-4961-4764-9a5f-2c96eaf617b2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534744658 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg.534744658
Directory /workspace/18.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.1740904536
Short name T126
Test name
Test status
Simulation time 4513774253 ps
CPU time 558.92 seconds
Started Jul 19 04:34:40 PM PDT 24
Finished Jul 19 04:44:04 PM PDT 24
Peak memory 265404 kb
Host smart-d34cd4f0-73d8-48f4-a70d-5e1d9fdc9cbf
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740904536 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 13.alert_handler_shadow_reg_errors_with_csr_rw.1740904536
Directory /workspace/13.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all_with_rand_reset.2647379858
Short name T31
Test name
Test status
Simulation time 193247611906 ps
CPU time 4940.85 seconds
Started Jul 19 04:49:18 PM PDT 24
Finished Jul 19 06:11:51 PM PDT 24
Peak memory 370696 kb
Host smart-ee0f402c-4036-45c5-aae1-cb1b453e83e2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647379858 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 19.alert_handler_stress_all_with_rand_reset.2647379858
Directory /workspace/19.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.4011291950
Short name T138
Test name
Test status
Simulation time 16128662355 ps
CPU time 204.62 seconds
Started Jul 19 04:34:13 PM PDT 24
Finished Jul 19 04:37:51 PM PDT 24
Peak memory 265476 kb
Host smart-0cd2e5e9-386a-44e9-ba46-6d169534a8d9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4011291950 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shadow_reg_erro
rs.4011291950
Directory /workspace/2.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/17.alert_handler_lpg.4289420153
Short name T255
Test name
Test status
Simulation time 78126342787 ps
CPU time 1368.58 seconds
Started Jul 19 04:49:14 PM PDT 24
Finished Jul 19 05:12:14 PM PDT 24
Peak memory 272920 kb
Host smart-ac6bef46-2306-4ded-adab-d5ad636c627b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289420153 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg.4289420153
Directory /workspace/17.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.315991339
Short name T155
Test name
Test status
Simulation time 9831434647 ps
CPU time 338.39 seconds
Started Jul 19 04:34:35 PM PDT 24
Finished Jul 19 04:40:21 PM PDT 24
Peak memory 266560 kb
Host smart-f252e062-9776-4d5d-a0c3-a78ae8650465
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=315991339 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shadow_reg_error
s.315991339
Directory /workspace/8.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/41.alert_handler_ping_timeout.2646601891
Short name T196
Test name
Test status
Simulation time 14497379098 ps
CPU time 596.35 seconds
Started Jul 19 04:50:04 PM PDT 24
Finished Jul 19 05:00:03 PM PDT 24
Peak memory 248032 kb
Host smart-c93c710b-0f12-4cd3-9d5f-3f33e12dde60
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646601891 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_ping_timeout.2646601891
Directory /workspace/41.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_sig_int_fail.1301474423
Short name T81
Test name
Test status
Simulation time 1278713992 ps
CPU time 23.42 seconds
Started Jul 19 04:49:21 PM PDT 24
Finished Jul 19 04:49:57 PM PDT 24
Peak memory 256324 kb
Host smart-148f112b-87f5-4f43-ae5a-3c0da25fa0d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13014
74423 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_sig_int_fail.1301474423
Directory /workspace/28.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.3507777147
Short name T149
Test name
Test status
Simulation time 5296674988 ps
CPU time 581.75 seconds
Started Jul 19 04:34:45 PM PDT 24
Finished Jul 19 04:44:29 PM PDT 24
Peak memory 265484 kb
Host smart-d06dd079-dfe8-4679-9448-b3566094bef8
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507777147 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.alert_handler_shadow_reg_errors_with_csr_rw.3507777147
Directory /workspace/5.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/12.alert_handler_entropy.3148732898
Short name T65
Test name
Test status
Simulation time 39725206407 ps
CPU time 1582.26 seconds
Started Jul 19 04:48:50 PM PDT 24
Finished Jul 19 05:15:27 PM PDT 24
Peak memory 288660 kb
Host smart-79a4c968-0929-471a-88f0-24d09e44e04e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148732898 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy.3148732898
Directory /workspace/12.alert_handler_entropy/latest

Test location /workspace/coverage/default/28.alert_handler_lpg.3349203703
Short name T315
Test name
Test status
Simulation time 249482363108 ps
CPU time 2537.67 seconds
Started Jul 19 04:49:22 PM PDT 24
Finished Jul 19 05:31:52 PM PDT 24
Peak memory 281696 kb
Host smart-86a438ad-b041-459a-ad51-e4f4f018dadf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3349203703 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg.3349203703
Directory /workspace/28.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.1542862962
Short name T340
Test name
Test status
Simulation time 10740201 ps
CPU time 1.31 seconds
Started Jul 19 04:34:49 PM PDT 24
Finished Jul 19 04:34:52 PM PDT 24
Peak memory 236664 kb
Host smart-deb70864-1a13-4a4c-99b5-77a1ab68e742
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1542862962 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_intr_test.1542862962
Directory /workspace/18.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.691207981
Short name T131
Test name
Test status
Simulation time 63867853551 ps
CPU time 1080.95 seconds
Started Jul 19 04:35:54 PM PDT 24
Finished Jul 19 04:53:55 PM PDT 24
Peak memory 272588 kb
Host smart-0cfda453-660e-4308-87b2-afa3ba410895
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691207981 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 14.alert_handler_shadow_reg_errors_with_csr_rw.691207981
Directory /workspace/14.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/30.alert_handler_ping_timeout.388724187
Short name T104
Test name
Test status
Simulation time 11998961650 ps
CPU time 460.48 seconds
Started Jul 19 04:49:33 PM PDT 24
Finished Jul 19 04:57:30 PM PDT 24
Peak memory 248932 kb
Host smart-11c7e9f8-fcd2-43c4-9727-3c136166ff3e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388724187 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_ping_timeout.388724187
Directory /workspace/30.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.272479781
Short name T145
Test name
Test status
Simulation time 6626059945 ps
CPU time 349.72 seconds
Started Jul 19 04:34:38 PM PDT 24
Finished Jul 19 04:40:34 PM PDT 24
Peak memory 273524 kb
Host smart-5b80cc67-027e-41d3-a77d-509949f18f56
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=272479781 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shadow_reg_erro
rs.272479781
Directory /workspace/11.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/2.alert_handler_ping_timeout.3882355761
Short name T9
Test name
Test status
Simulation time 8836655456 ps
CPU time 382.87 seconds
Started Jul 19 04:48:37 PM PDT 24
Finished Jul 19 04:55:18 PM PDT 24
Peak memory 249036 kb
Host smart-a0925679-2c3d-46ae-b933-44829b8e650b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3882355761 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_ping_timeout.3882355761
Directory /workspace/2.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_lpg.1064251069
Short name T5
Test name
Test status
Simulation time 103397809850 ps
CPU time 1789.22 seconds
Started Jul 19 04:49:20 PM PDT 24
Finished Jul 19 05:19:20 PM PDT 24
Peak memory 272884 kb
Host smart-aae99fe4-5dfb-40b3-ac59-18d5a2bc0157
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064251069 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg.1064251069
Directory /workspace/26.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.2195483737
Short name T136
Test name
Test status
Simulation time 18139528406 ps
CPU time 542.43 seconds
Started Jul 19 04:34:55 PM PDT 24
Finished Jul 19 04:44:00 PM PDT 24
Peak memory 265512 kb
Host smart-0ae2c882-cc8d-403d-af6d-21949b80126d
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195483737 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 15.alert_handler_shadow_reg_errors_with_csr_rw.2195483737
Directory /workspace/15.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all.763572646
Short name T52
Test name
Test status
Simulation time 60428537798 ps
CPU time 3580.23 seconds
Started Jul 19 04:50:06 PM PDT 24
Finished Jul 19 05:49:49 PM PDT 24
Peak memory 289344 kb
Host smart-4042de02-b918-4078-8532-1b7ea52f96bf
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763572646 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_han
dler_stress_all.763572646
Directory /workspace/42.alert_handler_stress_all/latest

Test location /workspace/coverage/default/11.alert_handler_lpg.758359739
Short name T560
Test name
Test status
Simulation time 129067956947 ps
CPU time 1776.27 seconds
Started Jul 19 04:49:10 PM PDT 24
Finished Jul 19 05:18:57 PM PDT 24
Peak memory 273212 kb
Host smart-89da2602-44b4-4127-b84f-1fb6665f04f6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758359739 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg.758359739
Directory /workspace/11.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.680667533
Short name T135
Test name
Test status
Simulation time 18841820562 ps
CPU time 320.59 seconds
Started Jul 19 04:34:46 PM PDT 24
Finished Jul 19 04:40:09 PM PDT 24
Peak memory 273128 kb
Host smart-8f0382a5-aa44-4301-934c-35f64362febf
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=680667533 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shadow_reg_erro
rs.680667533
Directory /workspace/16.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all.1378284900
Short name T39
Test name
Test status
Simulation time 9401605853 ps
CPU time 279.33 seconds
Started Jul 19 04:48:41 PM PDT 24
Finished Jul 19 04:53:37 PM PDT 24
Peak memory 257320 kb
Host smart-d18f9c1d-fead-44e6-af24-9388fdca9f93
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378284900 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_han
dler_stress_all.1378284900
Directory /workspace/7.alert_handler_stress_all/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all.1270689073
Short name T58
Test name
Test status
Simulation time 50531466351 ps
CPU time 2887.13 seconds
Started Jul 19 04:49:36 PM PDT 24
Finished Jul 19 05:37:59 PM PDT 24
Peak memory 289828 kb
Host smart-372fd1ee-7fdb-41f4-a98f-5c96f86f3464
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270689073 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_ha
ndler_stress_all.1270689073
Directory /workspace/27.alert_handler_stress_all/latest

Test location /workspace/coverage/default/4.alert_handler_ping_timeout.1511102742
Short name T199
Test name
Test status
Simulation time 202763958254 ps
CPU time 488.01 seconds
Started Jul 19 04:48:44 PM PDT 24
Finished Jul 19 04:57:08 PM PDT 24
Peak memory 248624 kb
Host smart-07722731-a0f2-48f9-856d-c6e895ff3458
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511102742 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_ping_timeout.1511102742
Directory /workspace/4.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.1646588316
Short name T346
Test name
Test status
Simulation time 2219226439 ps
CPU time 322.75 seconds
Started Jul 19 04:34:40 PM PDT 24
Finished Jul 19 04:40:08 PM PDT 24
Peak memory 265480 kb
Host smart-b9367b8b-5159-4267-a660-849db0268818
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646588316 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 11.alert_handler_shadow_reg_errors_with_csr_rw.1646588316
Directory /workspace/11.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/32.alert_handler_lpg.77547431
Short name T328
Test name
Test status
Simulation time 39795333199 ps
CPU time 1180.31 seconds
Started Jul 19 04:49:35 PM PDT 24
Finished Jul 19 05:09:30 PM PDT 24
Peak memory 273636 kb
Host smart-1406ca5b-544f-4e4c-a1fe-36fc20184134
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77547431 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg.77547431
Directory /workspace/32.alert_handler_lpg/latest

Test location /workspace/coverage/default/15.alert_handler_lpg.500180900
Short name T106
Test name
Test status
Simulation time 32816699394 ps
CPU time 1842.39 seconds
Started Jul 19 04:49:05 PM PDT 24
Finished Jul 19 05:19:58 PM PDT 24
Peak memory 273632 kb
Host smart-6ae6290f-d758-4645-bf16-0474d86addb1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500180900 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg.500180900
Directory /workspace/15.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.3990986799
Short name T339
Test name
Test status
Simulation time 8296038 ps
CPU time 1.41 seconds
Started Jul 19 04:34:43 PM PDT 24
Finished Jul 19 04:34:47 PM PDT 24
Peak memory 236740 kb
Host smart-886c36fc-dfb8-4b0b-8278-ed4d8abe345e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3990986799 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.alert_handler_intr_test.3990986799
Directory /workspace/27.alert_handler_intr_test/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all.3655364091
Short name T270
Test name
Test status
Simulation time 16445923285 ps
CPU time 1824.95 seconds
Started Jul 19 04:48:34 PM PDT 24
Finished Jul 19 05:19:17 PM PDT 24
Peak memory 303352 kb
Host smart-3fbc9cc5-09d4-425b-b412-4866361365af
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655364091 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_han
dler_stress_all.3655364091
Directory /workspace/1.alert_handler_stress_all/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all_with_rand_reset.2855840778
Short name T97
Test name
Test status
Simulation time 77953862090 ps
CPU time 1653.49 seconds
Started Jul 19 04:49:38 PM PDT 24
Finished Jul 19 05:17:26 PM PDT 24
Peak memory 290160 kb
Host smart-19b830ed-6118-4f74-a769-7c8e352134af
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855840778 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.alert_handler_stress_all_with_rand_reset.2855840778
Directory /workspace/30.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all.3564672247
Short name T47
Test name
Test status
Simulation time 414513862999 ps
CPU time 3007.51 seconds
Started Jul 19 04:48:39 PM PDT 24
Finished Jul 19 05:39:05 PM PDT 24
Peak memory 289492 kb
Host smart-22cfc918-2ab5-4858-8dd9-f02faed94218
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564672247 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_han
dler_stress_all.3564672247
Directory /workspace/2.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.3221045170
Short name T123
Test name
Test status
Simulation time 4843738454 ps
CPU time 336.83 seconds
Started Jul 19 04:34:34 PM PDT 24
Finished Jul 19 04:40:19 PM PDT 24
Peak memory 273528 kb
Host smart-9e641855-08f8-4f34-bc6e-0a97df0a4ece
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3221045170 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shadow_reg_err
ors.3221045170
Directory /workspace/13.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all_with_rand_reset.3675174416
Short name T253
Test name
Test status
Simulation time 42677007969 ps
CPU time 4162.63 seconds
Started Jul 19 04:49:22 PM PDT 24
Finished Jul 19 05:58:58 PM PDT 24
Peak memory 337708 kb
Host smart-84c6e62a-1920-407d-8b76-4dd3b4422d09
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675174416 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 23.alert_handler_stress_all_with_rand_reset.3675174416
Directory /workspace/23.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.alert_handler_ping_timeout.2927322783
Short name T574
Test name
Test status
Simulation time 13923059981 ps
CPU time 292.98 seconds
Started Jul 19 04:50:34 PM PDT 24
Finished Jul 19 04:55:29 PM PDT 24
Peak memory 256040 kb
Host smart-221eb553-356d-402e-9b23-8ec0ba615ae1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927322783 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_ping_timeout.2927322783
Directory /workspace/47.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.4165094858
Short name T171
Test name
Test status
Simulation time 91684995 ps
CPU time 2.39 seconds
Started Jul 19 04:34:49 PM PDT 24
Finished Jul 19 04:34:53 PM PDT 24
Peak memory 237732 kb
Host smart-e6d6b9f1-075c-424f-9b9e-7bd5768a5d11
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4165094858 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_intg_err.4165094858
Directory /workspace/10.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.2761801165
Short name T150
Test name
Test status
Simulation time 2520961141 ps
CPU time 287.93 seconds
Started Jul 19 04:34:37 PM PDT 24
Finished Jul 19 04:39:31 PM PDT 24
Peak memory 265564 kb
Host smart-43eae5b6-6d6e-4712-904b-a0e2273e9686
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761801165 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.alert_handler_shadow_reg_errors_with_csr_rw.2761801165
Directory /workspace/8.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/35.alert_handler_ping_timeout.860139879
Short name T262
Test name
Test status
Simulation time 62115372614 ps
CPU time 527.2 seconds
Started Jul 19 04:49:39 PM PDT 24
Finished Jul 19 04:58:40 PM PDT 24
Peak memory 256292 kb
Host smart-99a8aec5-f23a-4db0-b3da-8c92126848f7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860139879 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_ping_timeout.860139879
Directory /workspace/35.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all_with_rand_reset.1750152730
Short name T110
Test name
Test status
Simulation time 396199729656 ps
CPU time 6730.65 seconds
Started Jul 19 04:49:36 PM PDT 24
Finished Jul 19 06:42:03 PM PDT 24
Peak memory 371424 kb
Host smart-6b31dd14-f50e-4a52-b430-655d4d4867e1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750152730 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.alert_handler_stress_all_with_rand_reset.1750152730
Directory /workspace/27.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all.4023504806
Short name T254
Test name
Test status
Simulation time 180824335925 ps
CPU time 1657.54 seconds
Started Jul 19 04:49:34 PM PDT 24
Finished Jul 19 05:17:27 PM PDT 24
Peak memory 289300 kb
Host smart-41c2cfac-90d3-4b2d-96c8-df369600c750
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023504806 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_ha
ndler_stress_all.4023504806
Directory /workspace/30.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.4056436444
Short name T127
Test name
Test status
Simulation time 14440030646 ps
CPU time 299.25 seconds
Started Jul 19 04:34:53 PM PDT 24
Finished Jul 19 04:39:54 PM PDT 24
Peak memory 265628 kb
Host smart-b39ca33a-d87c-4373-9a83-234b26674993
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056436444 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 10.alert_handler_shadow_reg_errors_with_csr_rw.4056436444
Directory /workspace/10.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.2710969841
Short name T140
Test name
Test status
Simulation time 6516732567 ps
CPU time 199.13 seconds
Started Jul 19 04:34:21 PM PDT 24
Finished Jul 19 04:37:53 PM PDT 24
Peak memory 265480 kb
Host smart-65959aec-82d4-4045-895c-1be2dfcfc716
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2710969841 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shadow_reg_erro
rs.2710969841
Directory /workspace/4.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/0.alert_handler_alert_accum_saturation.985675045
Short name T208
Test name
Test status
Simulation time 229442399 ps
CPU time 3.94 seconds
Started Jul 19 04:48:40 PM PDT 24
Finished Jul 19 04:49:01 PM PDT 24
Peak memory 249180 kb
Host smart-fa331bcd-6da4-43b6-852f-e447f5a51874
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=985675045 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_alert_accum_saturation.985675045
Directory /workspace/0.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/1.alert_handler_alert_accum_saturation.1132288832
Short name T207
Test name
Test status
Simulation time 17082868 ps
CPU time 2.69 seconds
Started Jul 19 04:48:36 PM PDT 24
Finished Jul 19 04:48:56 PM PDT 24
Peak memory 249208 kb
Host smart-71573e7e-f8cd-4d9c-89ee-4fdff8c3ac5b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1132288832 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_alert_accum_saturation.1132288832
Directory /workspace/1.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/11.alert_handler_alert_accum_saturation.3289586549
Short name T210
Test name
Test status
Simulation time 29899704 ps
CPU time 2.38 seconds
Started Jul 19 04:49:09 PM PDT 24
Finished Jul 19 04:49:22 PM PDT 24
Peak memory 249224 kb
Host smart-8318e303-090f-4d0d-a515-4c595fd10c9e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3289586549 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_alert_accum_saturation.3289586549
Directory /workspace/11.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/16.alert_handler_alert_accum_saturation.2861984892
Short name T221
Test name
Test status
Simulation time 58621208 ps
CPU time 2.77 seconds
Started Jul 19 04:49:03 PM PDT 24
Finished Jul 19 04:49:17 PM PDT 24
Peak memory 249164 kb
Host smart-540811c9-c216-4871-9ada-ea9bd03b3b02
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2861984892 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_alert_accum_saturation.2861984892
Directory /workspace/16.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/1.alert_handler_lpg.2663811403
Short name T336
Test name
Test status
Simulation time 74014701840 ps
CPU time 2267.89 seconds
Started Jul 19 04:48:46 PM PDT 24
Finished Jul 19 05:26:50 PM PDT 24
Peak memory 289228 kb
Host smart-4d9f8c88-e4c0-4ef8-8e2c-4ad966f9518c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663811403 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg.2663811403
Directory /workspace/1.alert_handler_lpg/latest

Test location /workspace/coverage/default/13.alert_handler_lpg.129698584
Short name T332
Test name
Test status
Simulation time 7338459357 ps
CPU time 833.96 seconds
Started Jul 19 04:49:03 PM PDT 24
Finished Jul 19 05:03:08 PM PDT 24
Peak memory 273600 kb
Host smart-8c6dd739-6a77-4829-a3eb-af0a48156b1e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129698584 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg.129698584
Directory /workspace/13.alert_handler_lpg/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all.2487861337
Short name T279
Test name
Test status
Simulation time 39421617577 ps
CPU time 2219.67 seconds
Started Jul 19 04:49:48 PM PDT 24
Finished Jul 19 05:26:57 PM PDT 24
Peak memory 288020 kb
Host smart-3b9468b5-9348-4ca0-8662-d57ea5668709
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487861337 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_ha
ndler_stress_all.2487861337
Directory /workspace/37.alert_handler_stress_all/latest

Test location /workspace/coverage/default/38.alert_handler_ping_timeout.2570526833
Short name T304
Test name
Test status
Simulation time 3700762141 ps
CPU time 149.34 seconds
Started Jul 19 04:49:46 PM PDT 24
Finished Jul 19 04:52:26 PM PDT 24
Peak memory 249016 kb
Host smart-ea3db351-5bc9-4daa-9590-c1a3be24fe60
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570526833 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_ping_timeout.2570526833
Directory /workspace/38.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all_with_rand_reset.4071094101
Short name T85
Test name
Test status
Simulation time 105391863010 ps
CPU time 4587.51 seconds
Started Jul 19 04:49:55 PM PDT 24
Finished Jul 19 06:06:29 PM PDT 24
Peak memory 322900 kb
Host smart-c0baaa15-0938-4ad6-af18-ac6910068758
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071094101 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 38.alert_handler_stress_all_with_rand_reset.4071094101
Directory /workspace/38.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all.1324439835
Short name T54
Test name
Test status
Simulation time 281021320375 ps
CPU time 2908.61 seconds
Started Jul 19 04:50:03 PM PDT 24
Finished Jul 19 05:38:34 PM PDT 24
Peak memory 289896 kb
Host smart-80d804f4-f72f-4aaf-af6d-38ddc1789ce0
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324439835 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_ha
ndler_stress_all.1324439835
Directory /workspace/41.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.1688958125
Short name T146
Test name
Test status
Simulation time 16165637170 ps
CPU time 546.28 seconds
Started Jul 19 04:34:19 PM PDT 24
Finished Jul 19 04:43:37 PM PDT 24
Peak memory 269696 kb
Host smart-f4e24dc9-d0c5-4f7a-bd06-7208b4d65578
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688958125 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.alert_handler_shadow_reg_errors_with_csr_rw.1688958125
Directory /workspace/2.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.1805328330
Short name T137
Test name
Test status
Simulation time 15281162422 ps
CPU time 1155.93 seconds
Started Jul 19 04:34:26 PM PDT 24
Finished Jul 19 04:53:52 PM PDT 24
Peak memory 273664 kb
Host smart-e1a90478-8b0c-46f6-a4a7-fb1c82a38714
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805328330 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.alert_handler_shadow_reg_errors_with_csr_rw.1805328330
Directory /workspace/7.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.2157278659
Short name T172
Test name
Test status
Simulation time 46140809 ps
CPU time 3.17 seconds
Started Jul 19 04:34:27 PM PDT 24
Finished Jul 19 04:34:41 PM PDT 24
Peak memory 236552 kb
Host smart-b9d3003d-a4f2-4e98-9f0d-e8f9610896a2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2157278659 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_intg_err.2157278659
Directory /workspace/3.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.812356409
Short name T157
Test name
Test status
Simulation time 4059377524 ps
CPU time 104.38 seconds
Started Jul 19 04:34:36 PM PDT 24
Finished Jul 19 04:36:27 PM PDT 24
Peak memory 265664 kb
Host smart-63f82067-7afc-4b84-a5ea-22a938101988
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=812356409 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shadow_reg_erro
rs.812356409
Directory /workspace/10.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.3834526124
Short name T153
Test name
Test status
Simulation time 7078887834 ps
CPU time 196.34 seconds
Started Jul 19 04:34:55 PM PDT 24
Finished Jul 19 04:38:14 PM PDT 24
Peak memory 271912 kb
Host smart-ce09b17e-5c09-4141-a55f-30da526d88b0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3834526124 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shadow_reg_err
ors.3834526124
Directory /workspace/19.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all.313823062
Short name T46
Test name
Test status
Simulation time 42048213399 ps
CPU time 1274.71 seconds
Started Jul 19 04:50:24 PM PDT 24
Finished Jul 19 05:11:40 PM PDT 24
Peak memory 288912 kb
Host smart-70325d18-a878-4e23-9c0c-06dba8815204
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313823062 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_han
dler_stress_all.313823062
Directory /workspace/45.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.2684225728
Short name T139
Test name
Test status
Simulation time 1014965171 ps
CPU time 105.94 seconds
Started Jul 19 04:34:41 PM PDT 24
Finished Jul 19 04:36:31 PM PDT 24
Peak memory 267520 kb
Host smart-9cd181c5-7c7b-4405-b074-2ebd793fc774
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2684225728 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shadow_reg_err
ors.2684225728
Directory /workspace/18.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.2713306588
Short name T735
Test name
Test status
Simulation time 6824453 ps
CPU time 1.4 seconds
Started Jul 19 04:34:32 PM PDT 24
Finished Jul 19 04:34:41 PM PDT 24
Peak memory 236724 kb
Host smart-10d606ef-1b91-4160-82a0-e5368cfde574
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2713306588 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_intr_test.2713306588
Directory /workspace/1.alert_handler_intr_test/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all.2962537540
Short name T282
Test name
Test status
Simulation time 3094571469 ps
CPU time 258.24 seconds
Started Jul 19 04:48:36 PM PDT 24
Finished Jul 19 04:53:12 PM PDT 24
Peak memory 257236 kb
Host smart-ad93cb71-e4b1-4fb5-92fe-4d9ad2947680
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962537540 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_han
dler_stress_all.2962537540
Directory /workspace/0.alert_handler_stress_all/latest

Test location /workspace/coverage/default/14.alert_handler_esc_intr_timeout.1377126481
Short name T662
Test name
Test status
Simulation time 751439529 ps
CPU time 12.21 seconds
Started Jul 19 04:48:58 PM PDT 24
Finished Jul 19 04:49:22 PM PDT 24
Peak memory 248684 kb
Host smart-dc31d4fd-3335-4292-8d4e-3c0fa12ccd63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13771
26481 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_intr_timeout.1377126481
Directory /workspace/14.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_sig_int_fail.822532192
Short name T62
Test name
Test status
Simulation time 418478903 ps
CPU time 15.6 seconds
Started Jul 19 04:49:18 PM PDT 24
Finished Jul 19 04:49:46 PM PDT 24
Peak memory 248916 kb
Host smart-d7c2d890-6d9e-4a96-9582-43bc2caba079
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82253
2192 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_sig_int_fail.822532192
Directory /workspace/18.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all.784619263
Short name T112
Test name
Test status
Simulation time 55181049232 ps
CPU time 1403.05 seconds
Started Jul 19 04:49:31 PM PDT 24
Finished Jul 19 05:13:10 PM PDT 24
Peak memory 289988 kb
Host smart-ae347d94-07e5-4202-ada4-dcb1e81c7560
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784619263 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_han
dler_stress_all.784619263
Directory /workspace/24.alert_handler_stress_all/latest

Test location /workspace/coverage/default/26.alert_handler_sig_int_fail.1730302528
Short name T67
Test name
Test status
Simulation time 4946416263 ps
CPU time 68.25 seconds
Started Jul 19 04:49:35 PM PDT 24
Finished Jul 19 04:50:58 PM PDT 24
Peak memory 249628 kb
Host smart-cf7400a5-8909-41ef-a10b-baeba27a1325
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17303
02528 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_sig_int_fail.1730302528
Directory /workspace/26.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/39.alert_handler_lpg.3962085859
Short name T256
Test name
Test status
Simulation time 32225747355 ps
CPU time 2003 seconds
Started Jul 19 04:50:04 PM PDT 24
Finished Jul 19 05:23:29 PM PDT 24
Peak memory 287656 kb
Host smart-e694db6a-f145-4f3a-9bbc-5180deae30bf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962085859 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg.3962085859
Directory /workspace/39.alert_handler_lpg/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all_with_rand_reset.239424316
Short name T277
Test name
Test status
Simulation time 28515931221 ps
CPU time 2021.96 seconds
Started Jul 19 04:48:49 PM PDT 24
Finished Jul 19 05:22:46 PM PDT 24
Peak memory 285508 kb
Host smart-75a0d95f-4717-4179-a8c6-5138823df3de
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239424316 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 4.alert_handler_stress_all_with_rand_reset.239424316
Directory /workspace/4.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.4152952174
Short name T178
Test name
Test status
Simulation time 1838635116 ps
CPU time 67.57 seconds
Started Jul 19 04:34:24 PM PDT 24
Finished Jul 19 04:35:43 PM PDT 24
Peak memory 240596 kb
Host smart-556b03da-887b-4fb7-9b85-e1394b9d56ab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4152952174 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_intg_err.4152952174
Directory /workspace/6.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.3823364533
Short name T168
Test name
Test status
Simulation time 59177713 ps
CPU time 2.09 seconds
Started Jul 19 04:34:54 PM PDT 24
Finished Jul 19 04:34:59 PM PDT 24
Peak memory 237832 kb
Host smart-095c26cd-af08-496c-a110-92b74e75b8b1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3823364533 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_intg_err.3823364533
Directory /workspace/19.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.1347669504
Short name T128
Test name
Test status
Simulation time 1927384782 ps
CPU time 136.93 seconds
Started Jul 19 04:34:20 PM PDT 24
Finished Jul 19 04:36:49 PM PDT 24
Peak memory 257196 kb
Host smart-8ea6298f-d7c9-4474-acb4-e0a60f687f49
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1347669504 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shadow_reg_erro
rs.1347669504
Directory /workspace/0.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.1676830800
Short name T154
Test name
Test status
Simulation time 3582017575 ps
CPU time 132.33 seconds
Started Jul 19 04:34:32 PM PDT 24
Finished Jul 19 04:36:52 PM PDT 24
Peak memory 266720 kb
Host smart-194141db-248e-4f9c-97d4-a9e45b638cc5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1676830800 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shadow_reg_erro
rs.1676830800
Directory /workspace/1.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.301030802
Short name T165
Test name
Test status
Simulation time 163131739 ps
CPU time 20.33 seconds
Started Jul 19 04:34:18 PM PDT 24
Finished Jul 19 04:34:51 PM PDT 24
Peak memory 240604 kb
Host smart-17fc35cd-1851-4cc6-8a2d-66f218305292
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=301030802 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_intg_err.301030802
Directory /workspace/1.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.1253087654
Short name T166
Test name
Test status
Simulation time 449697150 ps
CPU time 17.34 seconds
Started Jul 19 04:34:55 PM PDT 24
Finished Jul 19 04:35:15 PM PDT 24
Peak memory 237672 kb
Host smart-5f5e2a9c-3c12-43bc-bc28-01094f97f878
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1253087654 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_intg_err.1253087654
Directory /workspace/11.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_intg_err.1398744686
Short name T176
Test name
Test status
Simulation time 82200013 ps
CPU time 2.05 seconds
Started Jul 19 04:34:40 PM PDT 24
Finished Jul 19 04:34:47 PM PDT 24
Peak memory 238096 kb
Host smart-2e752a75-ebd3-4e13-b742-e317b8de49f5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1398744686 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_intg_err.1398744686
Directory /workspace/12.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.2014238085
Short name T175
Test name
Test status
Simulation time 56525315 ps
CPU time 3.29 seconds
Started Jul 19 04:34:53 PM PDT 24
Finished Jul 19 04:34:57 PM PDT 24
Peak memory 237672 kb
Host smart-bd1f61ff-513d-46a3-a53d-439073f02aa5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2014238085 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_intg_err.2014238085
Directory /workspace/16.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.3505227129
Short name T170
Test name
Test status
Simulation time 921470569 ps
CPU time 32.48 seconds
Started Jul 19 04:34:18 PM PDT 24
Finished Jul 19 04:35:03 PM PDT 24
Peak memory 240668 kb
Host smart-9abf61ec-0ed3-4b6c-9901-c87c90ca61d1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3505227129 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_intg_err.3505227129
Directory /workspace/2.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.697289791
Short name T159
Test name
Test status
Simulation time 621560342 ps
CPU time 41.12 seconds
Started Jul 19 04:34:26 PM PDT 24
Finished Jul 19 04:35:17 PM PDT 24
Peak memory 246196 kb
Host smart-9986ee99-ad3a-47da-94e6-1a27615f3faa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=697289791 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_intg_err.697289791
Directory /workspace/5.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.1147102231
Short name T161
Test name
Test status
Simulation time 177388232 ps
CPU time 3.01 seconds
Started Jul 19 04:34:18 PM PDT 24
Finished Jul 19 04:34:33 PM PDT 24
Peak memory 237816 kb
Host smart-e0abbead-a926-40e6-aee3-fbd258c331fc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1147102231 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_intg_err.1147102231
Directory /workspace/0.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.3659331076
Short name T177
Test name
Test status
Simulation time 51663249 ps
CPU time 3.51 seconds
Started Jul 19 04:34:39 PM PDT 24
Finished Jul 19 04:34:48 PM PDT 24
Peak memory 237672 kb
Host smart-1a3322d0-0c62-45b3-b905-071e182efec4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3659331076 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_intg_err.3659331076
Directory /workspace/13.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.500641028
Short name T173
Test name
Test status
Simulation time 3286003596 ps
CPU time 66.53 seconds
Started Jul 19 04:34:51 PM PDT 24
Finished Jul 19 04:35:59 PM PDT 24
Peak memory 240676 kb
Host smart-02535a1e-f05c-4fe0-80bd-c10b5fee5577
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=500641028 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_intg_err.500641028
Directory /workspace/14.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.4009114105
Short name T181
Test name
Test status
Simulation time 2167163236 ps
CPU time 72.32 seconds
Started Jul 19 04:34:55 PM PDT 24
Finished Jul 19 04:36:10 PM PDT 24
Peak memory 240616 kb
Host smart-d5fa741f-0a11-4093-b7de-92773286204d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4009114105 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_intg_err.4009114105
Directory /workspace/15.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.2873268387
Short name T167
Test name
Test status
Simulation time 28745243 ps
CPU time 2.7 seconds
Started Jul 19 04:34:52 PM PDT 24
Finished Jul 19 04:34:56 PM PDT 24
Peak memory 236704 kb
Host smart-d53b7f5a-94d2-46a2-8ec8-e83e4ad30b41
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2873268387 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_intg_err.2873268387
Directory /workspace/17.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.2163674543
Short name T169
Test name
Test status
Simulation time 22276648 ps
CPU time 2.4 seconds
Started Jul 19 04:34:14 PM PDT 24
Finished Jul 19 04:34:29 PM PDT 24
Peak memory 237948 kb
Host smart-a5b380b2-a2d9-4eba-a0f4-3cf59d389646
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2163674543 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_intg_err.2163674543
Directory /workspace/4.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.3004806163
Short name T174
Test name
Test status
Simulation time 90902108 ps
CPU time 2.56 seconds
Started Jul 19 04:34:36 PM PDT 24
Finished Jul 19 04:34:45 PM PDT 24
Peak memory 236656 kb
Host smart-425c917f-ae48-4b2c-bf29-6e198b669e38
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3004806163 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_intg_err.3004806163
Directory /workspace/8.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all.3474399709
Short name T25
Test name
Test status
Simulation time 57270957037 ps
CPU time 1416.63 seconds
Started Jul 19 04:49:44 PM PDT 24
Finished Jul 19 05:13:33 PM PDT 24
Peak memory 289560 kb
Host smart-6ab539f8-348f-4815-a73e-45d21744c700
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474399709 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_ha
ndler_stress_all.3474399709
Directory /workspace/35.alert_handler_stress_all/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all_with_rand_reset.493267529
Short name T26
Test name
Test status
Simulation time 64331858254 ps
CPU time 6977.56 seconds
Started Jul 19 04:49:57 PM PDT 24
Finished Jul 19 06:46:21 PM PDT 24
Peak memory 355656 kb
Host smart-e22eb645-1611-4816-97f1-f259861a6941
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493267529 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 39.alert_handler_stress_all_with_rand_reset.493267529
Directory /workspace/39.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.alert_handler_lpg.512461827
Short name T23
Test name
Test status
Simulation time 42122859755 ps
CPU time 2327.32 seconds
Started Jul 19 04:50:25 PM PDT 24
Finished Jul 19 05:29:14 PM PDT 24
Peak memory 289692 kb
Host smart-3df3fe61-0a4b-4d84-88d8-f51d8bb97ace
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=512461827 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg.512461827
Directory /workspace/46.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.3209287410
Short name T758
Test name
Test status
Simulation time 8830311689 ps
CPU time 163.79 seconds
Started Jul 19 04:34:21 PM PDT 24
Finished Jul 19 04:37:16 PM PDT 24
Peak memory 240668 kb
Host smart-da137166-1fb9-42af-87fe-1ba92cff6fdd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3209287410 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_aliasing.3209287410
Directory /workspace/0.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.1562226364
Short name T761
Test name
Test status
Simulation time 1706133228 ps
CPU time 204.41 seconds
Started Jul 19 04:34:13 PM PDT 24
Finished Jul 19 04:37:50 PM PDT 24
Peak memory 237684 kb
Host smart-f058ebef-e37a-4ae0-b8d8-0abd4bfb07de
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1562226364 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_bit_bash.1562226364
Directory /workspace/0.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.3007585513
Short name T765
Test name
Test status
Simulation time 119493113 ps
CPU time 9.34 seconds
Started Jul 19 04:34:18 PM PDT 24
Finished Jul 19 04:34:40 PM PDT 24
Peak memory 249292 kb
Host smart-702e6efb-7ff5-413b-ab4f-8b0b0b44ef4d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3007585513 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_hw_reset.3007585513
Directory /workspace/0.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.271715998
Short name T757
Test name
Test status
Simulation time 30788009 ps
CPU time 4.72 seconds
Started Jul 19 04:34:12 PM PDT 24
Finished Jul 19 04:34:29 PM PDT 24
Peak memory 240276 kb
Host smart-ced967af-cc39-482e-b9af-4688fb100883
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271715998 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 0.alert_handler_csr_mem_rw_with_rand_reset.271715998
Directory /workspace/0.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.1479583406
Short name T737
Test name
Test status
Simulation time 269582052 ps
CPU time 4.93 seconds
Started Jul 19 04:34:17 PM PDT 24
Finished Jul 19 04:34:35 PM PDT 24
Peak memory 237676 kb
Host smart-5e2e2c91-d681-40d3-99d7-5ec2e84a671a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1479583406 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_rw.1479583406
Directory /workspace/0.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.124266279
Short name T736
Test name
Test status
Simulation time 8184462 ps
CPU time 1.43 seconds
Started Jul 19 04:34:20 PM PDT 24
Finished Jul 19 04:34:33 PM PDT 24
Peak memory 235676 kb
Host smart-bd8e074f-9f67-483f-a1fa-3c36954a340a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=124266279 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_intr_test.124266279
Directory /workspace/0.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.2282285223
Short name T789
Test name
Test status
Simulation time 645304504 ps
CPU time 22.74 seconds
Started Jul 19 04:34:19 PM PDT 24
Finished Jul 19 04:34:54 PM PDT 24
Peak memory 245724 kb
Host smart-274b7f9a-8895-444f-ae52-0e800a8c938b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2282285223 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_same_csr_out
standing.2282285223
Directory /workspace/0.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.362422761
Short name T132
Test name
Test status
Simulation time 21584282311 ps
CPU time 508.58 seconds
Started Jul 19 04:34:32 PM PDT 24
Finished Jul 19 04:43:09 PM PDT 24
Peak memory 268232 kb
Host smart-f4ab5800-5396-4ea0-a5df-1d4557e36dec
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362422761 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.alert_handler_shadow_reg_errors_with_csr_rw.362422761
Directory /workspace/0.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.4152569547
Short name T773
Test name
Test status
Simulation time 1203385737 ps
CPU time 18.52 seconds
Started Jul 19 04:34:32 PM PDT 24
Finished Jul 19 04:34:59 PM PDT 24
Peak memory 256416 kb
Host smart-90f64bf9-047a-4036-93f8-23b76e290356
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4152569547 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_errors.4152569547
Directory /workspace/0.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.742521141
Short name T180
Test name
Test status
Simulation time 3944756373 ps
CPU time 241.5 seconds
Started Jul 19 04:34:24 PM PDT 24
Finished Jul 19 04:38:37 PM PDT 24
Peak memory 240644 kb
Host smart-366de9c6-8b1f-4229-94ff-478589838e51
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=742521141 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_aliasing.742521141
Directory /workspace/1.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.499566195
Short name T741
Test name
Test status
Simulation time 23704087342 ps
CPU time 396.36 seconds
Started Jul 19 04:34:16 PM PDT 24
Finished Jul 19 04:41:06 PM PDT 24
Peak memory 237724 kb
Host smart-56a21e8f-41a3-44f5-a308-739b870fcfa3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=499566195 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_bit_bash.499566195
Directory /workspace/1.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.3544764918
Short name T808
Test name
Test status
Simulation time 144428070 ps
CPU time 10.04 seconds
Started Jul 19 04:34:24 PM PDT 24
Finished Jul 19 04:34:45 PM PDT 24
Peak memory 240616 kb
Host smart-95041bca-ea67-47f1-8679-950e2be6be91
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3544764918 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_hw_reset.3544764918
Directory /workspace/1.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.4033463889
Short name T752
Test name
Test status
Simulation time 296408595 ps
CPU time 9.31 seconds
Started Jul 19 04:34:13 PM PDT 24
Finished Jul 19 04:34:35 PM PDT 24
Peak memory 240660 kb
Host smart-9ee69af3-8a8d-47ae-a2d0-72be05280971
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033463889 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 1.alert_handler_csr_mem_rw_with_rand_reset.4033463889
Directory /workspace/1.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.2839237368
Short name T811
Test name
Test status
Simulation time 438222066 ps
CPU time 7.99 seconds
Started Jul 19 04:34:21 PM PDT 24
Finished Jul 19 04:34:41 PM PDT 24
Peak memory 240580 kb
Host smart-5673c397-3b04-4f2c-bb36-071abdaa739c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2839237368 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_rw.2839237368
Directory /workspace/1.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.1307879123
Short name T790
Test name
Test status
Simulation time 661332607 ps
CPU time 20.79 seconds
Started Jul 19 04:34:14 PM PDT 24
Finished Jul 19 04:34:47 PM PDT 24
Peak memory 248792 kb
Host smart-a8cbff0c-d795-49fa-8e8a-5961971c0acd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1307879123 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_same_csr_out
standing.1307879123
Directory /workspace/1.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.3292851247
Short name T143
Test name
Test status
Simulation time 2067990975 ps
CPU time 324.2 seconds
Started Jul 19 04:34:16 PM PDT 24
Finished Jul 19 04:39:53 PM PDT 24
Peak memory 273032 kb
Host smart-35cd1c63-a784-499a-8e7b-c6808fbaf4bd
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292851247 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.alert_handler_shadow_reg_errors_with_csr_rw.3292851247
Directory /workspace/1.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.2261117337
Short name T762
Test name
Test status
Simulation time 663023782 ps
CPU time 11.29 seconds
Started Jul 19 04:34:19 PM PDT 24
Finished Jul 19 04:34:42 PM PDT 24
Peak memory 248844 kb
Host smart-6bce5ef8-f371-443c-81d8-4cba606d46d5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2261117337 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_errors.2261117337
Directory /workspace/1.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.3041145195
Short name T726
Test name
Test status
Simulation time 34138875 ps
CPU time 5.83 seconds
Started Jul 19 04:34:42 PM PDT 24
Finished Jul 19 04:34:51 PM PDT 24
Peak memory 242416 kb
Host smart-db9bbfff-7dcd-4cad-b210-99a5ec514699
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041145195 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 10.alert_handler_csr_mem_rw_with_rand_reset.3041145195
Directory /workspace/10.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.1012457373
Short name T775
Test name
Test status
Simulation time 247004690 ps
CPU time 9.33 seconds
Started Jul 19 04:34:34 PM PDT 24
Finished Jul 19 04:34:51 PM PDT 24
Peak memory 240572 kb
Host smart-c76796bd-719b-4a8b-b432-72206c6d77bf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1012457373 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_csr_rw.1012457373
Directory /workspace/10.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.2752051518
Short name T749
Test name
Test status
Simulation time 8791178 ps
CPU time 1.58 seconds
Started Jul 19 04:34:36 PM PDT 24
Finished Jul 19 04:34:44 PM PDT 24
Peak memory 237676 kb
Host smart-d11b051e-228b-42f8-9082-f22a52e5bf14
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2752051518 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_intr_test.2752051518
Directory /workspace/10.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.3287566007
Short name T813
Test name
Test status
Simulation time 102135761 ps
CPU time 15.44 seconds
Started Jul 19 04:34:49 PM PDT 24
Finished Jul 19 04:35:06 PM PDT 24
Peak memory 248800 kb
Host smart-c4390ae3-8a7e-4bec-af40-b38f999f3ec4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3287566007 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_same_csr_ou
tstanding.3287566007
Directory /workspace/10.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.127637086
Short name T738
Test name
Test status
Simulation time 115338171 ps
CPU time 14.1 seconds
Started Jul 19 04:34:36 PM PDT 24
Finished Jul 19 04:34:57 PM PDT 24
Peak memory 255132 kb
Host smart-295636de-ac44-4c07-82e7-36a268227c3b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=127637086 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_errors.127637086
Directory /workspace/10.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.881793909
Short name T801
Test name
Test status
Simulation time 273467546 ps
CPU time 10.01 seconds
Started Jul 19 04:34:40 PM PDT 24
Finished Jul 19 04:34:55 PM PDT 24
Peak memory 239836 kb
Host smart-c7a03716-f8cb-4e87-b2eb-d0f5518b53f3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881793909 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 11.alert_handler_csr_mem_rw_with_rand_reset.881793909
Directory /workspace/11.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.252535364
Short name T793
Test name
Test status
Simulation time 326874442 ps
CPU time 5.43 seconds
Started Jul 19 04:34:35 PM PDT 24
Finished Jul 19 04:34:47 PM PDT 24
Peak memory 237888 kb
Host smart-328489f4-fce0-43fb-a716-d8265c25c0ea
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=252535364 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_csr_rw.252535364
Directory /workspace/11.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.3362677420
Short name T760
Test name
Test status
Simulation time 19966478 ps
CPU time 1.42 seconds
Started Jul 19 04:34:40 PM PDT 24
Finished Jul 19 04:34:46 PM PDT 24
Peak memory 236708 kb
Host smart-f902ee10-2fc5-4329-8a2a-20a77a16f5f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3362677420 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_intr_test.3362677420
Directory /workspace/11.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.344987573
Short name T829
Test name
Test status
Simulation time 108984538 ps
CPU time 13.62 seconds
Started Jul 19 04:34:39 PM PDT 24
Finished Jul 19 04:34:58 PM PDT 24
Peak memory 245848 kb
Host smart-67ebcfa4-3cc1-4128-b32c-7f2f0865818a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=344987573 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_same_csr_out
standing.344987573
Directory /workspace/11.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.3202795375
Short name T781
Test name
Test status
Simulation time 810309084 ps
CPU time 13.59 seconds
Started Jul 19 04:34:36 PM PDT 24
Finished Jul 19 04:34:56 PM PDT 24
Peak memory 254056 kb
Host smart-501706cd-20b7-4ea8-a2f9-98934fce2386
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3202795375 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_errors.3202795375
Directory /workspace/11.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.696585482
Short name T733
Test name
Test status
Simulation time 62514936 ps
CPU time 9.22 seconds
Started Jul 19 04:34:41 PM PDT 24
Finished Jul 19 04:34:55 PM PDT 24
Peak memory 253520 kb
Host smart-f449b0de-7673-4b76-b02e-e375c5f160e9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696585482 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 12.alert_handler_csr_mem_rw_with_rand_reset.696585482
Directory /workspace/12.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.1167270759
Short name T800
Test name
Test status
Simulation time 119186086 ps
CPU time 3.45 seconds
Started Jul 19 04:34:36 PM PDT 24
Finished Jul 19 04:34:46 PM PDT 24
Peak memory 240532 kb
Host smart-755f8a7d-b7a6-4e82-aaa0-40d357b10d7c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1167270759 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_csr_rw.1167270759
Directory /workspace/12.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.2950256073
Short name T772
Test name
Test status
Simulation time 7912498 ps
CPU time 1.5 seconds
Started Jul 19 04:34:47 PM PDT 24
Finished Jul 19 04:34:50 PM PDT 24
Peak memory 236752 kb
Host smart-0d14afea-af06-41f8-908f-744b61eea74f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2950256073 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_intr_test.2950256073
Directory /workspace/12.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.3290748095
Short name T189
Test name
Test status
Simulation time 975345883 ps
CPU time 17.78 seconds
Started Jul 19 04:34:34 PM PDT 24
Finished Jul 19 04:34:59 PM PDT 24
Peak memory 244908 kb
Host smart-53347992-71f6-49f0-aa33-988fe61a4767
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3290748095 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_same_csr_ou
tstanding.3290748095
Directory /workspace/12.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.2060891708
Short name T134
Test name
Test status
Simulation time 8912100825 ps
CPU time 204.84 seconds
Started Jul 19 04:34:52 PM PDT 24
Finished Jul 19 04:38:19 PM PDT 24
Peak memory 265464 kb
Host smart-a53a4847-5192-499c-9307-13959780ebe4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2060891708 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shadow_reg_err
ors.2060891708
Directory /workspace/12.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.1834894602
Short name T130
Test name
Test status
Simulation time 30260385938 ps
CPU time 863.65 seconds
Started Jul 19 04:34:46 PM PDT 24
Finished Jul 19 04:49:12 PM PDT 24
Peak memory 265500 kb
Host smart-19d3bd26-9f5b-4b1b-a428-dea80bb08ba2
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834894602 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 12.alert_handler_shadow_reg_errors_with_csr_rw.1834894602
Directory /workspace/12.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.2786129875
Short name T728
Test name
Test status
Simulation time 102140188 ps
CPU time 4.67 seconds
Started Jul 19 04:34:34 PM PDT 24
Finished Jul 19 04:34:46 PM PDT 24
Peak memory 250948 kb
Host smart-e2c91036-580c-4b73-86f2-091ca7fd73ed
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2786129875 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_errors.2786129875
Directory /workspace/12.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.1834688637
Short name T179
Test name
Test status
Simulation time 231357248 ps
CPU time 8.31 seconds
Started Jul 19 04:34:42 PM PDT 24
Finished Jul 19 04:34:54 PM PDT 24
Peak memory 238100 kb
Host smart-6b7c1d25-1013-4ec5-ab15-2d041db84c3d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834688637 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 13.alert_handler_csr_mem_rw_with_rand_reset.1834688637
Directory /workspace/13.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.809498471
Short name T770
Test name
Test status
Simulation time 162406321 ps
CPU time 5.75 seconds
Started Jul 19 04:34:47 PM PDT 24
Finished Jul 19 04:34:55 PM PDT 24
Peak memory 237652 kb
Host smart-390acf3c-5e36-43f1-ba2b-e538615fa228
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=809498471 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_csr_rw.809498471
Directory /workspace/13.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.1807615721
Short name T744
Test name
Test status
Simulation time 6505357 ps
CPU time 1.4 seconds
Started Jul 19 04:34:51 PM PDT 24
Finished Jul 19 04:34:54 PM PDT 24
Peak memory 235776 kb
Host smart-ac7a8e14-c660-477f-8e67-1b288f09d803
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1807615721 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_intr_test.1807615721
Directory /workspace/13.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.2991368763
Short name T824
Test name
Test status
Simulation time 3363953296 ps
CPU time 36.63 seconds
Started Jul 19 04:34:47 PM PDT 24
Finished Jul 19 04:35:25 PM PDT 24
Peak memory 245908 kb
Host smart-479fd90c-92f0-460d-a168-70cfb6b364b6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2991368763 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_same_csr_ou
tstanding.2991368763
Directory /workspace/13.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.393894095
Short name T774
Test name
Test status
Simulation time 382483591 ps
CPU time 8.97 seconds
Started Jul 19 04:34:37 PM PDT 24
Finished Jul 19 04:34:52 PM PDT 24
Peak memory 248956 kb
Host smart-6bd70c35-bc52-4b2b-8e13-1dec24705128
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=393894095 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_errors.393894095
Directory /workspace/13.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.1040915832
Short name T784
Test name
Test status
Simulation time 308479281 ps
CPU time 12.62 seconds
Started Jul 19 04:34:55 PM PDT 24
Finished Jul 19 04:35:11 PM PDT 24
Peak memory 252300 kb
Host smart-cea801ad-ca9e-4e23-bf35-a19e407f8f51
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040915832 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 14.alert_handler_csr_mem_rw_with_rand_reset.1040915832
Directory /workspace/14.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.2891883510
Short name T720
Test name
Test status
Simulation time 210317640 ps
CPU time 4.43 seconds
Started Jul 19 04:34:51 PM PDT 24
Finished Jul 19 04:34:57 PM PDT 24
Peak memory 240604 kb
Host smart-ce21fcd4-6c97-4663-aa94-7c6e1d3897d6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2891883510 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_csr_rw.2891883510
Directory /workspace/14.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.2167137732
Short name T759
Test name
Test status
Simulation time 10282847 ps
CPU time 1.47 seconds
Started Jul 19 04:34:56 PM PDT 24
Finished Jul 19 04:35:00 PM PDT 24
Peak memory 235860 kb
Host smart-b1ba4fdb-35fc-4196-aec2-701ffa12e843
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2167137732 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_intr_test.2167137732
Directory /workspace/14.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.2013880328
Short name T186
Test name
Test status
Simulation time 297469231 ps
CPU time 12.79 seconds
Started Jul 19 04:34:52 PM PDT 24
Finished Jul 19 04:35:07 PM PDT 24
Peak memory 248792 kb
Host smart-4edf7dec-ad76-435f-9da9-9f3042cd28bb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2013880328 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_same_csr_ou
tstanding.2013880328
Directory /workspace/14.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.1252068461
Short name T129
Test name
Test status
Simulation time 6722962678 ps
CPU time 137.2 seconds
Started Jul 19 04:34:51 PM PDT 24
Finished Jul 19 04:37:10 PM PDT 24
Peak memory 264996 kb
Host smart-687414c1-6775-41e1-988a-bbc6f8622c8c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1252068461 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shadow_reg_err
ors.1252068461
Directory /workspace/14.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.3154441160
Short name T764
Test name
Test status
Simulation time 152732022 ps
CPU time 9.22 seconds
Started Jul 19 04:34:48 PM PDT 24
Finished Jul 19 04:34:59 PM PDT 24
Peak memory 248600 kb
Host smart-ca555c73-d6f6-44ec-84da-e5c2d006641f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3154441160 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_errors.3154441160
Directory /workspace/14.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.3965190091
Short name T740
Test name
Test status
Simulation time 162005733 ps
CPU time 15.4 seconds
Started Jul 19 04:34:55 PM PDT 24
Finished Jul 19 04:35:13 PM PDT 24
Peak memory 252680 kb
Host smart-cafb3a11-6445-4374-8bdb-bcf2c33233d5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965190091 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 15.alert_handler_csr_mem_rw_with_rand_reset.3965190091
Directory /workspace/15.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.3179747052
Short name T828
Test name
Test status
Simulation time 196884224 ps
CPU time 4.58 seconds
Started Jul 19 04:34:48 PM PDT 24
Finished Jul 19 04:34:55 PM PDT 24
Peak memory 236708 kb
Host smart-26e96c40-c340-4661-a356-d5d4f9620a7e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3179747052 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_csr_rw.3179747052
Directory /workspace/15.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.3343003483
Short name T783
Test name
Test status
Simulation time 10925151 ps
CPU time 1.8 seconds
Started Jul 19 04:34:51 PM PDT 24
Finished Jul 19 04:34:55 PM PDT 24
Peak memory 237644 kb
Host smart-51c87445-7ba3-484e-ab5f-dd6eaa06aaa6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3343003483 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_intr_test.3343003483
Directory /workspace/15.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.3110790144
Short name T188
Test name
Test status
Simulation time 2112872353 ps
CPU time 37.45 seconds
Started Jul 19 04:34:54 PM PDT 24
Finished Jul 19 04:35:34 PM PDT 24
Peak memory 245840 kb
Host smart-20304948-a1d4-4b2e-bbf8-382a63bc7343
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3110790144 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_same_csr_ou
tstanding.3110790144
Directory /workspace/15.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.3898046206
Short name T141
Test name
Test status
Simulation time 4858034496 ps
CPU time 106.18 seconds
Started Jul 19 04:34:55 PM PDT 24
Finished Jul 19 04:36:44 PM PDT 24
Peak memory 265232 kb
Host smart-5ecbd2bd-3382-499f-baa0-227973da8b55
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3898046206 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shadow_reg_err
ors.3898046206
Directory /workspace/15.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.1790445717
Short name T711
Test name
Test status
Simulation time 219491846 ps
CPU time 14.74 seconds
Started Jul 19 04:34:48 PM PDT 24
Finished Jul 19 04:35:05 PM PDT 24
Peak memory 247544 kb
Host smart-b03d027c-9761-4b86-b37d-66daf7f3354c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1790445717 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_errors.1790445717
Directory /workspace/15.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.848306292
Short name T812
Test name
Test status
Simulation time 39667846 ps
CPU time 5.96 seconds
Started Jul 19 04:34:47 PM PDT 24
Finished Jul 19 04:34:54 PM PDT 24
Peak memory 248884 kb
Host smart-b726adbe-0aaf-4914-8c63-d83a1f2cdacf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848306292 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 16.alert_handler_csr_mem_rw_with_rand_reset.848306292
Directory /workspace/16.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.1506129348
Short name T734
Test name
Test status
Simulation time 27636844 ps
CPU time 3.71 seconds
Started Jul 19 04:34:54 PM PDT 24
Finished Jul 19 04:35:01 PM PDT 24
Peak memory 240508 kb
Host smart-1ae2f40f-5c7d-4673-bece-a218731698f5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1506129348 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_csr_rw.1506129348
Directory /workspace/16.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.232652637
Short name T771
Test name
Test status
Simulation time 9957205 ps
CPU time 1.27 seconds
Started Jul 19 04:46:29 PM PDT 24
Finished Jul 19 04:46:37 PM PDT 24
Peak memory 237764 kb
Host smart-3f289214-62a0-4c2e-baa5-4e36223d22d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=232652637 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_intr_test.232652637
Directory /workspace/16.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.1240046772
Short name T739
Test name
Test status
Simulation time 182601967 ps
CPU time 21.05 seconds
Started Jul 19 04:34:52 PM PDT 24
Finished Jul 19 04:35:14 PM PDT 24
Peak memory 248784 kb
Host smart-644f8e81-2515-439e-b746-fe84d3000f9e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1240046772 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_same_csr_ou
tstanding.1240046772
Directory /workspace/16.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.1064373106
Short name T158
Test name
Test status
Simulation time 27974459983 ps
CPU time 498.72 seconds
Started Jul 19 04:34:55 PM PDT 24
Finished Jul 19 04:43:17 PM PDT 24
Peak memory 265492 kb
Host smart-67213593-d8b8-43c5-9515-8e88f9904f2e
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064373106 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 16.alert_handler_shadow_reg_errors_with_csr_rw.1064373106
Directory /workspace/16.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.3197104788
Short name T766
Test name
Test status
Simulation time 987466778 ps
CPU time 15.82 seconds
Started Jul 19 04:34:53 PM PDT 24
Finished Jul 19 04:35:10 PM PDT 24
Peak memory 248872 kb
Host smart-4c304666-7e41-4608-93bf-24cd4ee4d236
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3197104788 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_errors.3197104788
Directory /workspace/16.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.722190799
Short name T347
Test name
Test status
Simulation time 77636583 ps
CPU time 5 seconds
Started Jul 19 04:34:41 PM PDT 24
Finished Jul 19 04:34:50 PM PDT 24
Peak memory 239772 kb
Host smart-2bcec68e-230f-4323-9039-b89df6a22e8f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722190799 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 17.alert_handler_csr_mem_rw_with_rand_reset.722190799
Directory /workspace/17.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.384061432
Short name T814
Test name
Test status
Simulation time 64355875 ps
CPU time 5.14 seconds
Started Jul 19 04:34:46 PM PDT 24
Finished Jul 19 04:34:53 PM PDT 24
Peak memory 237676 kb
Host smart-ec2940d5-ad74-4bc9-afa3-816447d2dfe0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=384061432 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_csr_rw.384061432
Directory /workspace/17.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.375664069
Short name T802
Test name
Test status
Simulation time 15006489 ps
CPU time 1.36 seconds
Started Jul 19 04:34:58 PM PDT 24
Finished Jul 19 04:35:02 PM PDT 24
Peak memory 237676 kb
Host smart-de7bf6ba-104c-4551-86cd-deb24cd77dd5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=375664069 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_intr_test.375664069
Directory /workspace/17.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.960803091
Short name T787
Test name
Test status
Simulation time 217516168 ps
CPU time 23.75 seconds
Started Jul 19 04:34:56 PM PDT 24
Finished Jul 19 04:35:23 PM PDT 24
Peak memory 245876 kb
Host smart-6afed05f-6063-4bf4-ab84-4a7ddb167fa4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=960803091 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_same_csr_out
standing.960803091
Directory /workspace/17.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.2191144403
Short name T144
Test name
Test status
Simulation time 10754914863 ps
CPU time 173.19 seconds
Started Jul 19 04:34:52 PM PDT 24
Finished Jul 19 04:37:47 PM PDT 24
Peak memory 265536 kb
Host smart-3dd964e5-062a-4139-bbf7-c237d724b7de
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2191144403 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shadow_reg_err
ors.2191144403
Directory /workspace/17.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.1950617137
Short name T345
Test name
Test status
Simulation time 11050370492 ps
CPU time 308.39 seconds
Started Jul 19 04:34:53 PM PDT 24
Finished Jul 19 04:40:04 PM PDT 24
Peak memory 267284 kb
Host smart-60a6a8ae-d958-4512-8fad-7d81e685f743
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950617137 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 17.alert_handler_shadow_reg_errors_with_csr_rw.1950617137
Directory /workspace/17.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.389477921
Short name T245
Test name
Test status
Simulation time 920424705 ps
CPU time 15.31 seconds
Started Jul 19 04:34:54 PM PDT 24
Finished Jul 19 04:35:12 PM PDT 24
Peak memory 249824 kb
Host smart-b072268f-4eaa-47f8-be21-a5323d64444a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=389477921 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_errors.389477921
Directory /workspace/17.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.3688526194
Short name T746
Test name
Test status
Simulation time 37096605 ps
CPU time 5.47 seconds
Started Jul 19 04:34:50 PM PDT 24
Finished Jul 19 04:34:57 PM PDT 24
Peak memory 241224 kb
Host smart-d9d30542-7761-4971-bd7c-c36f87e81e04
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688526194 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 18.alert_handler_csr_mem_rw_with_rand_reset.3688526194
Directory /workspace/18.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.1585501103
Short name T725
Test name
Test status
Simulation time 187054694 ps
CPU time 4.39 seconds
Started Jul 19 04:34:50 PM PDT 24
Finished Jul 19 04:34:56 PM PDT 24
Peak memory 240568 kb
Host smart-5cfb65f1-469b-4cc1-9d77-c46e33ac9b79
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1585501103 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_csr_rw.1585501103
Directory /workspace/18.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.2521629889
Short name T819
Test name
Test status
Simulation time 1829866975 ps
CPU time 24.79 seconds
Started Jul 19 04:34:47 PM PDT 24
Finished Jul 19 04:35:14 PM PDT 24
Peak memory 248792 kb
Host smart-68b6ea4d-3423-49c0-af5d-24f90864e4e1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2521629889 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_same_csr_ou
tstanding.2521629889
Directory /workspace/18.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.1924941148
Short name T151
Test name
Test status
Simulation time 4136476264 ps
CPU time 256.87 seconds
Started Jul 19 04:34:43 PM PDT 24
Finished Jul 19 04:39:03 PM PDT 24
Peak memory 265432 kb
Host smart-33101aac-37d0-49c6-9405-81c6e6b2cfb5
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924941148 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 18.alert_handler_shadow_reg_errors_with_csr_rw.1924941148
Directory /workspace/18.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.3660215785
Short name T730
Test name
Test status
Simulation time 46487042 ps
CPU time 8.41 seconds
Started Jul 19 04:34:55 PM PDT 24
Finished Jul 19 04:35:06 PM PDT 24
Peak memory 248060 kb
Host smart-77a90d03-66e8-47fd-8fa8-0f2380f5df2c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3660215785 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_errors.3660215785
Directory /workspace/18.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.1396097831
Short name T273
Test name
Test status
Simulation time 915108420 ps
CPU time 56.79 seconds
Started Jul 19 04:34:48 PM PDT 24
Finished Jul 19 04:35:47 PM PDT 24
Peak memory 245984 kb
Host smart-6d40654a-1fe2-41f6-b89a-c7712e7335f7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1396097831 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_intg_err.1396097831
Directory /workspace/18.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.1656197643
Short name T815
Test name
Test status
Simulation time 675186205 ps
CPU time 5.52 seconds
Started Jul 19 04:34:54 PM PDT 24
Finished Jul 19 04:35:03 PM PDT 24
Peak memory 252524 kb
Host smart-5cc66e67-8a09-447b-9135-a4f27108f124
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656197643 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 19.alert_handler_csr_mem_rw_with_rand_reset.1656197643
Directory /workspace/19.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.475074288
Short name T714
Test name
Test status
Simulation time 127944888 ps
CPU time 5.4 seconds
Started Jul 19 04:34:56 PM PDT 24
Finished Jul 19 04:35:04 PM PDT 24
Peak memory 237628 kb
Host smart-9c9ad0b4-d56f-4b89-ab46-32907c3b635e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=475074288 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_csr_rw.475074288
Directory /workspace/19.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.3866149724
Short name T779
Test name
Test status
Simulation time 7959596 ps
CPU time 1.52 seconds
Started Jul 19 04:34:59 PM PDT 24
Finished Jul 19 04:35:03 PM PDT 24
Peak memory 236880 kb
Host smart-567fa94f-3579-4ec9-b662-7d0c2ab7fc8f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3866149724 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_intr_test.3866149724
Directory /workspace/19.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.3286458416
Short name T724
Test name
Test status
Simulation time 155400925 ps
CPU time 11.45 seconds
Started Jul 19 04:34:55 PM PDT 24
Finished Jul 19 04:35:10 PM PDT 24
Peak memory 245848 kb
Host smart-157fb96f-99fa-4584-b0ff-6cd6d278c987
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3286458416 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_same_csr_ou
tstanding.3286458416
Directory /workspace/19.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.1165909357
Short name T148
Test name
Test status
Simulation time 6062685919 ps
CPU time 484.08 seconds
Started Jul 19 04:37:19 PM PDT 24
Finished Jul 19 04:45:34 PM PDT 24
Peak memory 265596 kb
Host smart-da9cfb92-f697-4ad1-9c8c-bb9092bb23b2
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165909357 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 19.alert_handler_shadow_reg_errors_with_csr_rw.1165909357
Directory /workspace/19.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.2158217718
Short name T825
Test name
Test status
Simulation time 1016465073 ps
CPU time 18.05 seconds
Started Jul 19 04:34:56 PM PDT 24
Finished Jul 19 04:35:17 PM PDT 24
Peak memory 254232 kb
Host smart-04e0da61-6608-47b0-b12a-daf2cdccf6ff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2158217718 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_errors.2158217718
Directory /workspace/19.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.3619078901
Short name T767
Test name
Test status
Simulation time 1695019790 ps
CPU time 74.26 seconds
Started Jul 19 04:34:15 PM PDT 24
Finished Jul 19 04:35:43 PM PDT 24
Peak memory 237672 kb
Host smart-58c0ccaa-7039-413f-beb0-b24b5d5457ff
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3619078901 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_aliasing.3619078901
Directory /workspace/2.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.3302976648
Short name T183
Test name
Test status
Simulation time 1705420181 ps
CPU time 172.18 seconds
Started Jul 19 04:34:20 PM PDT 24
Finished Jul 19 04:37:24 PM PDT 24
Peak memory 240608 kb
Host smart-8b30ae84-c308-470c-a0d7-e90915d37b81
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3302976648 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_bit_bash.3302976648
Directory /workspace/2.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.3045880239
Short name T795
Test name
Test status
Simulation time 255763297 ps
CPU time 5.45 seconds
Started Jul 19 04:34:20 PM PDT 24
Finished Jul 19 04:34:37 PM PDT 24
Peak memory 248780 kb
Host smart-c8a1d0f9-0cba-443f-8f5e-472edde5655a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3045880239 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_hw_reset.3045880239
Directory /workspace/2.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.3931386244
Short name T246
Test name
Test status
Simulation time 1145385106 ps
CPU time 5.58 seconds
Started Jul 19 04:34:28 PM PDT 24
Finished Jul 19 04:34:43 PM PDT 24
Peak memory 239908 kb
Host smart-e9c460c0-f0db-4d5d-9800-e621bacd2087
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931386244 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 2.alert_handler_csr_mem_rw_with_rand_reset.3931386244
Directory /workspace/2.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.2962242414
Short name T185
Test name
Test status
Simulation time 68857428 ps
CPU time 5.42 seconds
Started Jul 19 04:34:19 PM PDT 24
Finished Jul 19 04:34:36 PM PDT 24
Peak memory 237740 kb
Host smart-0e6b5453-527c-4bf4-ba49-9d0dbe8b0a32
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2962242414 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_rw.2962242414
Directory /workspace/2.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.896095940
Short name T748
Test name
Test status
Simulation time 11355311 ps
CPU time 1.61 seconds
Started Jul 19 04:34:18 PM PDT 24
Finished Jul 19 04:34:32 PM PDT 24
Peak memory 236624 kb
Host smart-db429078-dc60-4a98-a2f2-98de1bc23c91
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=896095940 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_intr_test.896095940
Directory /workspace/2.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.115512617
Short name T716
Test name
Test status
Simulation time 1370418416 ps
CPU time 19.38 seconds
Started Jul 19 04:34:27 PM PDT 24
Finished Jul 19 04:34:57 PM PDT 24
Peak memory 245732 kb
Host smart-6489bf5d-c44e-47ae-a615-b083edb20f8b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=115512617 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_same_csr_outs
tanding.115512617
Directory /workspace/2.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.1817949596
Short name T710
Test name
Test status
Simulation time 121553623 ps
CPU time 7.19 seconds
Started Jul 19 04:34:18 PM PDT 24
Finished Jul 19 04:34:37 PM PDT 24
Peak memory 252204 kb
Host smart-60a759ed-6f90-4be6-81b0-58beff899c00
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1817949596 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_errors.1817949596
Directory /workspace/2.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.3590452640
Short name T796
Test name
Test status
Simulation time 11353146 ps
CPU time 1.27 seconds
Started Jul 19 04:34:57 PM PDT 24
Finished Jul 19 04:35:01 PM PDT 24
Peak memory 236844 kb
Host smart-29af9aff-cebc-45a4-8a72-0841d3fd9390
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3590452640 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.alert_handler_intr_test.3590452640
Directory /workspace/20.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.1934669817
Short name T782
Test name
Test status
Simulation time 20187866 ps
CPU time 1.36 seconds
Started Jul 19 04:34:56 PM PDT 24
Finished Jul 19 04:35:00 PM PDT 24
Peak memory 236740 kb
Host smart-2d92783d-98f1-4db2-acc6-17ad52751dba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1934669817 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.alert_handler_intr_test.1934669817
Directory /workspace/21.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.94554148
Short name T804
Test name
Test status
Simulation time 9953123 ps
CPU time 1.64 seconds
Started Jul 19 04:34:56 PM PDT 24
Finished Jul 19 04:35:01 PM PDT 24
Peak memory 237672 kb
Host smart-18350813-4523-4114-8bbb-ecf8244deac0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=94554148 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.alert_handler_intr_test.94554148
Directory /workspace/22.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.2164093244
Short name T162
Test name
Test status
Simulation time 11656327 ps
CPU time 1.27 seconds
Started Jul 19 04:34:55 PM PDT 24
Finished Jul 19 04:34:59 PM PDT 24
Peak memory 236732 kb
Host smart-91f82b7b-0aa7-4a9f-8a8d-dc218d3d6268
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2164093244 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.alert_handler_intr_test.2164093244
Directory /workspace/23.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.3191523475
Short name T247
Test name
Test status
Simulation time 8839191 ps
CPU time 1.51 seconds
Started Jul 19 04:34:49 PM PDT 24
Finished Jul 19 04:34:53 PM PDT 24
Peak memory 235672 kb
Host smart-a9c4c404-31e6-4727-9f1b-a7cbf7853331
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3191523475 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.alert_handler_intr_test.3191523475
Directory /workspace/24.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.3946982310
Short name T742
Test name
Test status
Simulation time 37881800 ps
CPU time 2.53 seconds
Started Jul 19 04:34:51 PM PDT 24
Finished Jul 19 04:34:56 PM PDT 24
Peak memory 237752 kb
Host smart-7d412dfe-a52e-491e-acb9-ac85b7f0d0be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3946982310 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.alert_handler_intr_test.3946982310
Directory /workspace/25.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.4225728553
Short name T763
Test name
Test status
Simulation time 6473100 ps
CPU time 1.38 seconds
Started Jul 19 04:34:56 PM PDT 24
Finished Jul 19 04:35:01 PM PDT 24
Peak memory 235704 kb
Host smart-e99bc6f9-4345-46cb-9a56-dabb0d26131d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4225728553 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.alert_handler_intr_test.4225728553
Directory /workspace/26.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.1261041238
Short name T769
Test name
Test status
Simulation time 12206121 ps
CPU time 1.4 seconds
Started Jul 19 04:34:56 PM PDT 24
Finished Jul 19 04:35:00 PM PDT 24
Peak memory 237684 kb
Host smart-6a8b7ab9-83f4-4c67-bf1f-a66167ae678a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1261041238 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.alert_handler_intr_test.1261041238
Directory /workspace/28.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.2357191035
Short name T164
Test name
Test status
Simulation time 10568415 ps
CPU time 1.64 seconds
Started Jul 19 04:34:54 PM PDT 24
Finished Jul 19 04:34:57 PM PDT 24
Peak memory 237656 kb
Host smart-4e64d54e-4b2e-47af-af00-3eedc9645caa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2357191035 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.alert_handler_intr_test.2357191035
Directory /workspace/29.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.2855403915
Short name T745
Test name
Test status
Simulation time 1156148206 ps
CPU time 68.43 seconds
Started Jul 19 04:34:18 PM PDT 24
Finished Jul 19 04:35:39 PM PDT 24
Peak memory 237608 kb
Host smart-69cdc3b3-6fbc-45ac-8b32-357e43bd2f3b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2855403915 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_aliasing.2855403915
Directory /workspace/3.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.2963410673
Short name T780
Test name
Test status
Simulation time 4774584906 ps
CPU time 271.6 seconds
Started Jul 19 04:34:19 PM PDT 24
Finished Jul 19 04:39:03 PM PDT 24
Peak memory 240680 kb
Host smart-c5af5d9f-4927-4201-bdef-e4db42787868
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2963410673 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_bit_bash.2963410673
Directory /workspace/3.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.226493337
Short name T721
Test name
Test status
Simulation time 803742951 ps
CPU time 8.94 seconds
Started Jul 19 04:34:28 PM PDT 24
Finished Jul 19 04:34:50 PM PDT 24
Peak memory 248764 kb
Host smart-18977682-1c41-4529-8223-bf066122f3ec
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=226493337 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_hw_reset.226493337
Directory /workspace/3.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.4191468653
Short name T723
Test name
Test status
Simulation time 414939866 ps
CPU time 7.99 seconds
Started Jul 19 04:34:17 PM PDT 24
Finished Jul 19 04:34:37 PM PDT 24
Peak memory 240868 kb
Host smart-835e913e-366c-4d02-9469-5ce255df0c13
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191468653 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 3.alert_handler_csr_mem_rw_with_rand_reset.4191468653
Directory /workspace/3.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.134656973
Short name T754
Test name
Test status
Simulation time 120707731 ps
CPU time 4.52 seconds
Started Jul 19 04:34:22 PM PDT 24
Finished Jul 19 04:34:38 PM PDT 24
Peak memory 240592 kb
Host smart-d739cb4d-f3b0-41a1-85cd-40fefd9d23e8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=134656973 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_rw.134656973
Directory /workspace/3.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.759218923
Short name T718
Test name
Test status
Simulation time 6308374 ps
CPU time 1.37 seconds
Started Jul 19 04:34:18 PM PDT 24
Finished Jul 19 04:34:32 PM PDT 24
Peak memory 235644 kb
Host smart-6c0e1ac5-3443-446a-95cf-56b5299c4cb7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=759218923 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_intr_test.759218923
Directory /workspace/3.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.2047717262
Short name T786
Test name
Test status
Simulation time 309660967 ps
CPU time 19.13 seconds
Started Jul 19 04:34:29 PM PDT 24
Finished Jul 19 04:34:58 PM PDT 24
Peak memory 244900 kb
Host smart-a18abe9e-608f-4074-bb4e-076a03ea6a15
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2047717262 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_same_csr_out
standing.2047717262
Directory /workspace/3.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.2315529491
Short name T125
Test name
Test status
Simulation time 15125698060 ps
CPU time 270.33 seconds
Started Jul 19 04:34:32 PM PDT 24
Finished Jul 19 04:39:10 PM PDT 24
Peak memory 273552 kb
Host smart-b3fa83ae-a24d-4e40-8e8a-03261ba65054
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2315529491 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shadow_reg_erro
rs.2315529491
Directory /workspace/3.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.488771534
Short name T122
Test name
Test status
Simulation time 2344605660 ps
CPU time 324.61 seconds
Started Jul 19 04:34:14 PM PDT 24
Finished Jul 19 04:39:52 PM PDT 24
Peak memory 265452 kb
Host smart-cef41f1e-e966-4df1-9084-92953c21f7d1
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488771534 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.alert_handler_shadow_reg_errors_with_csr_rw.488771534
Directory /workspace/3.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.1134395812
Short name T806
Test name
Test status
Simulation time 208495672 ps
CPU time 6.99 seconds
Started Jul 19 04:34:21 PM PDT 24
Finished Jul 19 04:34:40 PM PDT 24
Peak memory 248908 kb
Host smart-294a6a2c-594c-4507-8366-36009023148c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1134395812 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_errors.1134395812
Directory /workspace/3.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.3127923613
Short name T163
Test name
Test status
Simulation time 16583421 ps
CPU time 1.87 seconds
Started Jul 19 04:34:59 PM PDT 24
Finished Jul 19 04:35:03 PM PDT 24
Peak memory 237676 kb
Host smart-964c53ec-0900-4815-a51c-ef8e5d5e392a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3127923613 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.alert_handler_intr_test.3127923613
Directory /workspace/30.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.4115237069
Short name T798
Test name
Test status
Simulation time 20133796 ps
CPU time 1.43 seconds
Started Jul 19 04:35:03 PM PDT 24
Finished Jul 19 04:35:06 PM PDT 24
Peak memory 236692 kb
Host smart-d4c187c8-72d4-4d0b-afe3-6fbf76d7d8de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4115237069 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.alert_handler_intr_test.4115237069
Directory /workspace/31.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.3345435489
Short name T751
Test name
Test status
Simulation time 67746508 ps
CPU time 1.38 seconds
Started Jul 19 04:35:00 PM PDT 24
Finished Jul 19 04:35:04 PM PDT 24
Peak memory 237508 kb
Host smart-cd6fe52c-8815-49b1-886a-bc40718767a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3345435489 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.alert_handler_intr_test.3345435489
Directory /workspace/32.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.alert_handler_intr_test.117302298
Short name T791
Test name
Test status
Simulation time 19237458 ps
CPU time 1.41 seconds
Started Jul 19 04:35:02 PM PDT 24
Finished Jul 19 04:35:05 PM PDT 24
Peak memory 237540 kb
Host smart-c60c2166-6632-4bce-812e-17a31d85ec37
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=117302298 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.alert_handler_intr_test.117302298
Directory /workspace/33.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.1099850855
Short name T810
Test name
Test status
Simulation time 13947166 ps
CPU time 1.44 seconds
Started Jul 19 04:34:58 PM PDT 24
Finished Jul 19 04:35:02 PM PDT 24
Peak memory 235788 kb
Host smart-1555278e-cf7e-4759-b420-3303780602c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1099850855 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.alert_handler_intr_test.1099850855
Directory /workspace/34.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.560432932
Short name T822
Test name
Test status
Simulation time 19447477 ps
CPU time 1.32 seconds
Started Jul 19 04:34:56 PM PDT 24
Finished Jul 19 04:35:00 PM PDT 24
Peak memory 237736 kb
Host smart-528feb71-4eb8-4b12-b3d3-c82fcd449a56
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=560432932 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.alert_handler_intr_test.560432932
Directory /workspace/35.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.3722741519
Short name T768
Test name
Test status
Simulation time 11564992 ps
CPU time 1.41 seconds
Started Jul 19 04:35:05 PM PDT 24
Finished Jul 19 04:35:07 PM PDT 24
Peak memory 237680 kb
Host smart-13ec7a12-0521-4038-b4e6-aa130b913e60
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3722741519 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.alert_handler_intr_test.3722741519
Directory /workspace/36.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.3984087646
Short name T794
Test name
Test status
Simulation time 9551386 ps
CPU time 1.25 seconds
Started Jul 19 04:34:59 PM PDT 24
Finished Jul 19 04:35:03 PM PDT 24
Peak memory 237412 kb
Host smart-5f94a90a-98c6-4cd0-bb58-e2d342f4f311
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3984087646 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.alert_handler_intr_test.3984087646
Directory /workspace/37.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.3620989531
Short name T715
Test name
Test status
Simulation time 10549817 ps
CPU time 1.33 seconds
Started Jul 19 04:34:56 PM PDT 24
Finished Jul 19 04:35:01 PM PDT 24
Peak memory 235736 kb
Host smart-15e8c780-98b8-485e-9d24-89ff686e85b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3620989531 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.alert_handler_intr_test.3620989531
Directory /workspace/38.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.2868380931
Short name T344
Test name
Test status
Simulation time 8885365 ps
CPU time 1.33 seconds
Started Jul 19 04:34:55 PM PDT 24
Finished Jul 19 04:34:59 PM PDT 24
Peak memory 237680 kb
Host smart-665aec33-2356-40d7-b070-7d7695850f2e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2868380931 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.alert_handler_intr_test.2868380931
Directory /workspace/39.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.3539530389
Short name T792
Test name
Test status
Simulation time 13480905180 ps
CPU time 247.92 seconds
Started Jul 19 04:34:33 PM PDT 24
Finished Jul 19 04:38:49 PM PDT 24
Peak memory 241680 kb
Host smart-fb09939c-9e80-43a7-bc1e-349caa8166a8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3539530389 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_aliasing.3539530389
Directory /workspace/4.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.1663143887
Short name T719
Test name
Test status
Simulation time 94978137542 ps
CPU time 369.76 seconds
Started Jul 19 04:34:23 PM PDT 24
Finished Jul 19 04:40:44 PM PDT 24
Peak memory 240664 kb
Host smart-05239b82-4e9b-4d3d-857e-c9af9fc92125
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1663143887 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_bit_bash.1663143887
Directory /workspace/4.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.2081224330
Short name T184
Test name
Test status
Simulation time 27834595 ps
CPU time 4.11 seconds
Started Jul 19 04:34:25 PM PDT 24
Finished Jul 19 04:34:40 PM PDT 24
Peak memory 248880 kb
Host smart-80c39649-a9f7-40f4-8553-29138ccbb746
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2081224330 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_hw_reset.2081224330
Directory /workspace/4.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.620051848
Short name T816
Test name
Test status
Simulation time 139710060 ps
CPU time 9.78 seconds
Started Jul 19 04:34:25 PM PDT 24
Finished Jul 19 04:34:46 PM PDT 24
Peak memory 240668 kb
Host smart-5e531c0a-4038-4a62-989b-f36e7be2462e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620051848 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 4.alert_handler_csr_mem_rw_with_rand_reset.620051848
Directory /workspace/4.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.2142996517
Short name T807
Test name
Test status
Simulation time 34741499 ps
CPU time 5.02 seconds
Started Jul 19 04:34:24 PM PDT 24
Finished Jul 19 04:34:40 PM PDT 24
Peak memory 236668 kb
Host smart-4f2796b5-e4c5-4d87-ba12-0b5b7c284310
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2142996517 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_rw.2142996517
Directory /workspace/4.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.781543475
Short name T830
Test name
Test status
Simulation time 17803184 ps
CPU time 1.5 seconds
Started Jul 19 04:34:24 PM PDT 24
Finished Jul 19 04:34:40 PM PDT 24
Peak memory 236792 kb
Host smart-f76410ab-5b6d-48f2-b9d5-537bf5ef09d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=781543475 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_intr_test.781543475
Directory /workspace/4.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.3232276776
Short name T727
Test name
Test status
Simulation time 2763599439 ps
CPU time 37.86 seconds
Started Jul 19 04:34:30 PM PDT 24
Finished Jul 19 04:35:17 PM PDT 24
Peak memory 245916 kb
Host smart-21a41f2a-8406-47c9-a330-8da949d85ef2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3232276776 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_same_csr_out
standing.3232276776
Directory /workspace/4.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.338415246
Short name T152
Test name
Test status
Simulation time 25097026723 ps
CPU time 491.98 seconds
Started Jul 19 04:34:17 PM PDT 24
Finished Jul 19 04:42:42 PM PDT 24
Peak memory 265560 kb
Host smart-6c7d52df-5ebf-48d0-9e76-69811f99a39b
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338415246 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.alert_handler_shadow_reg_errors_with_csr_rw.338415246
Directory /workspace/4.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.388179680
Short name T778
Test name
Test status
Simulation time 115448716 ps
CPU time 7.2 seconds
Started Jul 19 04:34:28 PM PDT 24
Finished Jul 19 04:34:45 PM PDT 24
Peak memory 248876 kb
Host smart-ca9ccb51-9374-4375-8399-f82242f57d81
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=388179680 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_errors.388179680
Directory /workspace/4.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.1127521101
Short name T826
Test name
Test status
Simulation time 20141661 ps
CPU time 1.33 seconds
Started Jul 19 04:34:53 PM PDT 24
Finished Jul 19 04:34:55 PM PDT 24
Peak memory 236728 kb
Host smart-fc1fcc5e-dc5c-4271-8667-0581ac2bc996
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1127521101 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.alert_handler_intr_test.1127521101
Directory /workspace/40.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.83038898
Short name T809
Test name
Test status
Simulation time 7595281 ps
CPU time 1.59 seconds
Started Jul 19 04:34:58 PM PDT 24
Finished Jul 19 04:35:02 PM PDT 24
Peak memory 237684 kb
Host smart-f4404679-957e-45ae-a93d-102ad922bb8f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=83038898 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.alert_handler_intr_test.83038898
Directory /workspace/41.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.2517535904
Short name T343
Test name
Test status
Simulation time 10689779 ps
CPU time 1.26 seconds
Started Jul 19 04:34:57 PM PDT 24
Finished Jul 19 04:35:01 PM PDT 24
Peak memory 236732 kb
Host smart-47a92223-80ad-4b21-ab71-9a7aa35b70f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2517535904 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.alert_handler_intr_test.2517535904
Directory /workspace/42.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.1766782777
Short name T823
Test name
Test status
Simulation time 9950282 ps
CPU time 1.57 seconds
Started Jul 19 04:35:01 PM PDT 24
Finished Jul 19 04:35:05 PM PDT 24
Peak memory 237660 kb
Host smart-19a2d254-625b-4b19-b5ea-4f75394cb8e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1766782777 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.alert_handler_intr_test.1766782777
Directory /workspace/43.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.4116581534
Short name T712
Test name
Test status
Simulation time 12766676 ps
CPU time 1.5 seconds
Started Jul 19 04:35:01 PM PDT 24
Finished Jul 19 04:35:05 PM PDT 24
Peak memory 236724 kb
Host smart-0ab432b5-e888-401c-ae56-ee9915144515
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4116581534 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.alert_handler_intr_test.4116581534
Directory /workspace/44.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.2418981189
Short name T818
Test name
Test status
Simulation time 10323858 ps
CPU time 1.42 seconds
Started Jul 19 04:35:00 PM PDT 24
Finished Jul 19 04:35:03 PM PDT 24
Peak memory 235732 kb
Host smart-835ae792-a9a2-4ddc-8925-1d658bb0455d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2418981189 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.alert_handler_intr_test.2418981189
Directory /workspace/45.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.3876680240
Short name T731
Test name
Test status
Simulation time 16461829 ps
CPU time 1.86 seconds
Started Jul 19 04:34:56 PM PDT 24
Finished Jul 19 04:35:01 PM PDT 24
Peak memory 237684 kb
Host smart-7f1533a9-7835-4bc2-8fd5-e5ba55ee2bf0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3876680240 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.alert_handler_intr_test.3876680240
Directory /workspace/46.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.2587365738
Short name T756
Test name
Test status
Simulation time 48066580 ps
CPU time 1.35 seconds
Started Jul 19 04:34:59 PM PDT 24
Finished Jul 19 04:35:03 PM PDT 24
Peak memory 236432 kb
Host smart-7dd0de57-19c6-476d-b2b5-61516dcacd80
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2587365738 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.alert_handler_intr_test.2587365738
Directory /workspace/47.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.1530201478
Short name T342
Test name
Test status
Simulation time 9904068 ps
CPU time 1.31 seconds
Started Jul 19 04:35:01 PM PDT 24
Finished Jul 19 04:35:05 PM PDT 24
Peak memory 237680 kb
Host smart-f5562a2c-8ec8-4688-b4ea-d092d6036e90
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1530201478 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.alert_handler_intr_test.1530201478
Directory /workspace/48.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.765077024
Short name T713
Test name
Test status
Simulation time 15980155 ps
CPU time 1.32 seconds
Started Jul 19 04:35:12 PM PDT 24
Finished Jul 19 04:35:13 PM PDT 24
Peak memory 237860 kb
Host smart-030dd2ad-84e8-480c-8e87-c3fdc776b357
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=765077024 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.alert_handler_intr_test.765077024
Directory /workspace/49.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.2779081902
Short name T729
Test name
Test status
Simulation time 174492376 ps
CPU time 6.64 seconds
Started Jul 19 04:34:22 PM PDT 24
Finished Jul 19 04:34:40 PM PDT 24
Peak memory 239904 kb
Host smart-a33530ca-347e-488f-bb6b-8e6a3170a077
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779081902 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 5.alert_handler_csr_mem_rw_with_rand_reset.2779081902
Directory /workspace/5.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.3789818656
Short name T827
Test name
Test status
Simulation time 48065741 ps
CPU time 4.05 seconds
Started Jul 19 04:34:24 PM PDT 24
Finished Jul 19 04:34:40 PM PDT 24
Peak memory 236708 kb
Host smart-df2a6e90-e984-4094-9a04-a7ea7f629d4e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3789818656 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_csr_rw.3789818656
Directory /workspace/5.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.1168464808
Short name T776
Test name
Test status
Simulation time 8061606 ps
CPU time 1.32 seconds
Started Jul 19 04:34:37 PM PDT 24
Finished Jul 19 04:34:45 PM PDT 24
Peak memory 237676 kb
Host smart-fcf989b2-67a3-4339-bf2b-548215f7bc75
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1168464808 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_intr_test.1168464808
Directory /workspace/5.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.4208967504
Short name T821
Test name
Test status
Simulation time 589779854 ps
CPU time 38.34 seconds
Started Jul 19 04:34:23 PM PDT 24
Finished Jul 19 04:35:12 PM PDT 24
Peak memory 244892 kb
Host smart-03c114a8-5546-46de-afac-81c616a3c3c4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4208967504 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_same_csr_out
standing.4208967504
Directory /workspace/5.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.1292523599
Short name T147
Test name
Test status
Simulation time 10068850411 ps
CPU time 331.23 seconds
Started Jul 19 04:34:25 PM PDT 24
Finished Jul 19 04:40:07 PM PDT 24
Peak memory 265508 kb
Host smart-a6fd2ea4-067f-4781-bc0e-457d69a1e69c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1292523599 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shadow_reg_erro
rs.1292523599
Directory /workspace/5.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.672712819
Short name T750
Test name
Test status
Simulation time 179727590 ps
CPU time 4.51 seconds
Started Jul 19 04:34:24 PM PDT 24
Finished Jul 19 04:34:40 PM PDT 24
Peak memory 253172 kb
Host smart-f0a29d1d-8560-420b-946b-cfc61b6bc29a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=672712819 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_errors.672712819
Directory /workspace/5.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.1457257645
Short name T797
Test name
Test status
Simulation time 36771886 ps
CPU time 5.83 seconds
Started Jul 19 04:34:26 PM PDT 24
Finished Jul 19 04:34:42 PM PDT 24
Peak memory 244592 kb
Host smart-4f2802e8-c161-4cd1-9787-748e6e4cdb4a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457257645 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 6.alert_handler_csr_mem_rw_with_rand_reset.1457257645
Directory /workspace/6.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.118230748
Short name T831
Test name
Test status
Simulation time 40705713 ps
CPU time 5.67 seconds
Started Jul 19 04:34:30 PM PDT 24
Finished Jul 19 04:34:44 PM PDT 24
Peak memory 237628 kb
Host smart-88954ae9-8ad5-4051-8906-f9934a467350
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=118230748 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_csr_rw.118230748
Directory /workspace/6.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.304795956
Short name T803
Test name
Test status
Simulation time 10080136 ps
CPU time 1.45 seconds
Started Jul 19 04:34:27 PM PDT 24
Finished Jul 19 04:34:39 PM PDT 24
Peak memory 235664 kb
Host smart-981508e0-f422-4c87-8171-149913a89978
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=304795956 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_intr_test.304795956
Directory /workspace/6.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.1924115191
Short name T191
Test name
Test status
Simulation time 3831680364 ps
CPU time 39.71 seconds
Started Jul 19 04:34:24 PM PDT 24
Finished Jul 19 04:35:15 PM PDT 24
Peak memory 244988 kb
Host smart-ec35061a-97d0-4cc4-baab-e30fc718a5f9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1924115191 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_same_csr_out
standing.1924115191
Directory /workspace/6.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.1196966770
Short name T124
Test name
Test status
Simulation time 2156908825 ps
CPU time 206.22 seconds
Started Jul 19 04:34:22 PM PDT 24
Finished Jul 19 04:38:00 PM PDT 24
Peak memory 273664 kb
Host smart-ebde422e-186e-44ff-a6d8-e4613bb0c5e5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1196966770 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shadow_reg_erro
rs.1196966770
Directory /workspace/6.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.1075568455
Short name T156
Test name
Test status
Simulation time 33639952882 ps
CPU time 1215.18 seconds
Started Jul 19 04:34:27 PM PDT 24
Finished Jul 19 04:54:52 PM PDT 24
Peak memory 265464 kb
Host smart-691fdae7-9cc8-4780-9dde-07f3ddd7b5c6
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075568455 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.alert_handler_shadow_reg_errors_with_csr_rw.1075568455
Directory /workspace/6.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.1858970945
Short name T753
Test name
Test status
Simulation time 141414857 ps
CPU time 6.05 seconds
Started Jul 19 04:34:27 PM PDT 24
Finished Jul 19 04:34:43 PM PDT 24
Peak memory 255016 kb
Host smart-6648cc2b-503b-4323-bc11-311071b9c122
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1858970945 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_errors.1858970945
Directory /workspace/6.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.4122795591
Short name T805
Test name
Test status
Simulation time 112081306 ps
CPU time 8.83 seconds
Started Jul 19 04:34:53 PM PDT 24
Finished Jul 19 04:35:04 PM PDT 24
Peak memory 240572 kb
Host smart-90e6891d-e6d4-407a-88db-dc7bed8264c1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122795591 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 7.alert_handler_csr_mem_rw_with_rand_reset.4122795591
Directory /workspace/7.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.3063317237
Short name T788
Test name
Test status
Simulation time 134213338 ps
CPU time 9.17 seconds
Started Jul 19 04:34:43 PM PDT 24
Finished Jul 19 04:34:55 PM PDT 24
Peak memory 237652 kb
Host smart-f6dda103-3963-497b-ac99-c2ca5dcb3538
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3063317237 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_csr_rw.3063317237
Directory /workspace/7.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.3322342603
Short name T341
Test name
Test status
Simulation time 6467707 ps
CPU time 1.38 seconds
Started Jul 19 04:34:55 PM PDT 24
Finished Jul 19 04:35:00 PM PDT 24
Peak memory 236736 kb
Host smart-3532ec59-f4ed-4e48-a5cc-ca779323f311
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3322342603 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_intr_test.3322342603
Directory /workspace/7.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.2073969468
Short name T190
Test name
Test status
Simulation time 2176405505 ps
CPU time 34.75 seconds
Started Jul 19 04:34:39 PM PDT 24
Finished Jul 19 04:35:19 PM PDT 24
Peak memory 244984 kb
Host smart-769934f5-a46f-425e-a73c-2fa9e54bd31d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2073969468 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_same_csr_out
standing.2073969468
Directory /workspace/7.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.4110894681
Short name T142
Test name
Test status
Simulation time 2457596935 ps
CPU time 252.11 seconds
Started Jul 19 04:34:24 PM PDT 24
Finished Jul 19 04:38:47 PM PDT 24
Peak memory 265520 kb
Host smart-72e53381-0ad4-4276-b557-64daa7792fdf
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4110894681 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shadow_reg_erro
rs.4110894681
Directory /workspace/7.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.934543373
Short name T820
Test name
Test status
Simulation time 371657576 ps
CPU time 24.33 seconds
Started Jul 19 04:34:25 PM PDT 24
Finished Jul 19 04:35:01 PM PDT 24
Peak memory 249904 kb
Host smart-6cdf50c4-e2ef-4026-a16f-c2d48cf12908
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=934543373 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_errors.934543373
Directory /workspace/7.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.644775342
Short name T747
Test name
Test status
Simulation time 1896126860 ps
CPU time 11.76 seconds
Started Jul 19 04:34:39 PM PDT 24
Finished Jul 19 04:34:56 PM PDT 24
Peak memory 254912 kb
Host smart-ee2731f0-5052-4ed3-ae10-b422987bfd31
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644775342 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 8.alert_handler_csr_mem_rw_with_rand_reset.644775342
Directory /workspace/8.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.1282119460
Short name T732
Test name
Test status
Simulation time 35161837 ps
CPU time 5.33 seconds
Started Jul 19 04:34:37 PM PDT 24
Finished Jul 19 04:34:49 PM PDT 24
Peak memory 237660 kb
Host smart-bf14ff59-349c-489f-860f-82de71b7c056
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1282119460 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_csr_rw.1282119460
Directory /workspace/8.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.2508955671
Short name T717
Test name
Test status
Simulation time 19697936 ps
CPU time 1.37 seconds
Started Jul 19 04:34:39 PM PDT 24
Finished Jul 19 04:34:46 PM PDT 24
Peak memory 235688 kb
Host smart-ab7d9ea4-8c58-4ce6-b467-1ac17977a6e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2508955671 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_intr_test.2508955671
Directory /workspace/8.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.3537465635
Short name T755
Test name
Test status
Simulation time 325680931 ps
CPU time 11.25 seconds
Started Jul 19 04:34:44 PM PDT 24
Finished Jul 19 04:34:58 PM PDT 24
Peak memory 245884 kb
Host smart-940b0456-d043-4eae-bcd9-5921db7999fb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3537465635 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_same_csr_out
standing.3537465635
Directory /workspace/8.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.3584175394
Short name T832
Test name
Test status
Simulation time 621607461 ps
CPU time 10.76 seconds
Started Jul 19 04:34:36 PM PDT 24
Finished Jul 19 04:34:53 PM PDT 24
Peak memory 248848 kb
Host smart-c2816941-9555-4380-92ab-6ba7d898fa76
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3584175394 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_errors.3584175394
Directory /workspace/8.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.2984321798
Short name T799
Test name
Test status
Simulation time 726927375 ps
CPU time 14.52 seconds
Started Jul 19 04:34:36 PM PDT 24
Finished Jul 19 04:34:57 PM PDT 24
Peak memory 251512 kb
Host smart-f116b946-c495-4b25-90f6-e369492b7ff2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984321798 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 9.alert_handler_csr_mem_rw_with_rand_reset.2984321798
Directory /workspace/9.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.413825700
Short name T187
Test name
Test status
Simulation time 37738960 ps
CPU time 6.14 seconds
Started Jul 19 04:34:48 PM PDT 24
Finished Jul 19 04:34:56 PM PDT 24
Peak memory 240608 kb
Host smart-3f9b9a88-ac24-424a-a325-9c7a22c2a5a7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=413825700 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_csr_rw.413825700
Directory /workspace/9.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.1809815363
Short name T785
Test name
Test status
Simulation time 6896646 ps
CPU time 1.44 seconds
Started Jul 19 04:34:46 PM PDT 24
Finished Jul 19 04:34:49 PM PDT 24
Peak memory 236748 kb
Host smart-f6a1a438-6a8b-4f70-a426-0ae901bd7e12
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1809815363 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_intr_test.1809815363
Directory /workspace/9.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.812184567
Short name T743
Test name
Test status
Simulation time 1551099189 ps
CPU time 19.13 seconds
Started Jul 19 04:34:37 PM PDT 24
Finished Jul 19 04:35:02 PM PDT 24
Peak memory 244932 kb
Host smart-41d95973-e8b5-4e2f-a5a0-2e74f173edab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=812184567 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_same_csr_outs
tanding.812184567
Directory /workspace/9.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.1354114476
Short name T777
Test name
Test status
Simulation time 3122559002 ps
CPU time 204.93 seconds
Started Jul 19 04:34:52 PM PDT 24
Finished Jul 19 04:38:19 PM PDT 24
Peak memory 272656 kb
Host smart-6b4cd792-ead0-4cf6-800d-1dc554089a63
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1354114476 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shadow_reg_erro
rs.1354114476
Directory /workspace/9.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.4189725313
Short name T133
Test name
Test status
Simulation time 5957496234 ps
CPU time 462.22 seconds
Started Jul 19 04:34:38 PM PDT 24
Finished Jul 19 04:42:26 PM PDT 24
Peak memory 265524 kb
Host smart-7a6f251a-28b6-4048-aeec-47a3ae549c3e
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189725313 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.alert_handler_shadow_reg_errors_with_csr_rw.4189725313
Directory /workspace/9.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.2608588583
Short name T722
Test name
Test status
Simulation time 217890200 ps
CPU time 15.53 seconds
Started Jul 19 04:34:40 PM PDT 24
Finished Jul 19 04:35:00 PM PDT 24
Peak memory 248872 kb
Host smart-de44192f-90df-4c96-9a99-8912b52d7bf4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2608588583 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_errors.2608588583
Directory /workspace/9.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.1883398013
Short name T817
Test name
Test status
Simulation time 2188156706 ps
CPU time 48.33 seconds
Started Jul 19 04:34:40 PM PDT 24
Finished Jul 19 04:35:33 PM PDT 24
Peak memory 240652 kb
Host smart-206bf17c-23f5-4aed-b7ff-616d7f04dc55
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1883398013 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_intg_err.1883398013
Directory /workspace/9.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/0.alert_handler_entropy.3882732920
Short name T114
Test name
Test status
Simulation time 108693304944 ps
CPU time 1777.67 seconds
Started Jul 19 04:48:28 PM PDT 24
Finished Jul 19 05:18:25 PM PDT 24
Peak memory 273176 kb
Host smart-21570005-eb39-46cc-8b58-a5b374af08e2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3882732920 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy.3882732920
Directory /workspace/0.alert_handler_entropy/latest

Test location /workspace/coverage/default/0.alert_handler_entropy_stress.4055581620
Short name T503
Test name
Test status
Simulation time 648343776 ps
CPU time 31.66 seconds
Started Jul 19 04:48:31 PM PDT 24
Finished Jul 19 04:49:21 PM PDT 24
Peak memory 248868 kb
Host smart-f6f37a26-6b0c-425e-b0f7-f4da4ff300a4
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4055581620 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy_stress.4055581620
Directory /workspace/0.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/0.alert_handler_esc_alert_accum.3830639197
Short name T349
Test name
Test status
Simulation time 23532127732 ps
CPU time 335.23 seconds
Started Jul 19 04:48:40 PM PDT 24
Finished Jul 19 04:54:33 PM PDT 24
Peak memory 257288 kb
Host smart-70a1c4a7-90f7-4ff1-8f37-3d40d3bfec8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38306
39197 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_alert_accum.3830639197
Directory /workspace/0.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/0.alert_handler_esc_intr_timeout.1131512022
Short name T497
Test name
Test status
Simulation time 639845351 ps
CPU time 25.57 seconds
Started Jul 19 04:48:40 PM PDT 24
Finished Jul 19 04:49:23 PM PDT 24
Peak memory 248576 kb
Host smart-4d1ce40b-1c4c-4d3a-8b64-d4dca7aeb8b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11315
12022 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_intr_timeout.1131512022
Directory /workspace/0.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_lpg.1752123963
Short name T638
Test name
Test status
Simulation time 56310434432 ps
CPU time 1570.21 seconds
Started Jul 19 04:48:34 PM PDT 24
Finished Jul 19 05:15:02 PM PDT 24
Peak memory 273008 kb
Host smart-69b2243d-c8b2-46e8-bc71-01c5831271fa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1752123963 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg.1752123963
Directory /workspace/0.alert_handler_lpg/latest

Test location /workspace/coverage/default/0.alert_handler_lpg_stub_clk.1169839247
Short name T257
Test name
Test status
Simulation time 53127516597 ps
CPU time 1488.32 seconds
Started Jul 19 04:48:34 PM PDT 24
Finished Jul 19 05:13:41 PM PDT 24
Peak memory 272948 kb
Host smart-00a397f7-bfc5-4016-9185-9165eb33c35e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1169839247 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg_stub_clk.1169839247
Directory /workspace/0.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/0.alert_handler_ping_timeout.1501248908
Short name T308
Test name
Test status
Simulation time 55606962278 ps
CPU time 526.85 seconds
Started Jul 19 04:48:41 PM PDT 24
Finished Jul 19 04:57:45 PM PDT 24
Peak memory 247892 kb
Host smart-9c7cb28c-847f-464b-9538-4cac62cba4c6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501248908 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_ping_timeout.1501248908
Directory /workspace/0.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_random_alerts.1606650960
Short name T534
Test name
Test status
Simulation time 2074563841 ps
CPU time 25.32 seconds
Started Jul 19 04:48:28 PM PDT 24
Finished Jul 19 04:49:12 PM PDT 24
Peak memory 256904 kb
Host smart-b4b7afe1-9ecf-4ebf-973f-d1dcb228f3ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16066
50960 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_alerts.1606650960
Directory /workspace/0.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/0.alert_handler_random_classes.4146860968
Short name T653
Test name
Test status
Simulation time 1679753458 ps
CPU time 25.13 seconds
Started Jul 19 04:48:51 PM PDT 24
Finished Jul 19 04:49:31 PM PDT 24
Peak memory 256216 kb
Host smart-057728da-c698-405a-8ef5-d7b63e5f474a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41468
60968 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_classes.4146860968
Directory /workspace/0.alert_handler_random_classes/latest

Test location /workspace/coverage/default/0.alert_handler_sec_cm.695060106
Short name T37
Test name
Test status
Simulation time 1067101185 ps
CPU time 44.69 seconds
Started Jul 19 04:48:34 PM PDT 24
Finished Jul 19 04:49:37 PM PDT 24
Peak memory 270248 kb
Host smart-0357a764-2f09-4a94-866f-3a3e9e753b92
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=695060106 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sec_cm.695060106
Directory /workspace/0.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/0.alert_handler_sig_int_fail.2060217258
Short name T647
Test name
Test status
Simulation time 119058199 ps
CPU time 4.94 seconds
Started Jul 19 04:48:47 PM PDT 24
Finished Jul 19 04:49:08 PM PDT 24
Peak memory 240736 kb
Host smart-afe1d273-6b93-4d67-b61e-65a6af3ba98c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20602
17258 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sig_int_fail.2060217258
Directory /workspace/0.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/0.alert_handler_smoke.2875163595
Short name T637
Test name
Test status
Simulation time 495335193 ps
CPU time 23.99 seconds
Started Jul 19 04:48:29 PM PDT 24
Finished Jul 19 04:49:12 PM PDT 24
Peak memory 256780 kb
Host smart-355f703b-2205-48d1-917f-1f8673d84f1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28751
63595 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_smoke.2875163595
Directory /workspace/0.alert_handler_smoke/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all_with_rand_reset.1042279435
Short name T648
Test name
Test status
Simulation time 31286993726 ps
CPU time 2298.14 seconds
Started Jul 19 04:48:43 PM PDT 24
Finished Jul 19 05:27:17 PM PDT 24
Peak memory 290172 kb
Host smart-11c4fa07-1178-4002-a635-5e90d2b2e8fe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042279435 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.alert_handler_stress_all_with_rand_reset.1042279435
Directory /workspace/0.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.alert_handler_entropy.2810686787
Short name T631
Test name
Test status
Simulation time 102756759424 ps
CPU time 3139.06 seconds
Started Jul 19 04:48:40 PM PDT 24
Finished Jul 19 05:41:17 PM PDT 24
Peak memory 289872 kb
Host smart-b4839149-671c-401c-9244-8a889f45ef9c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810686787 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy.2810686787
Directory /workspace/1.alert_handler_entropy/latest

Test location /workspace/coverage/default/1.alert_handler_entropy_stress.125198007
Short name T451
Test name
Test status
Simulation time 303553091 ps
CPU time 15.77 seconds
Started Jul 19 04:48:39 PM PDT 24
Finished Jul 19 04:49:12 PM PDT 24
Peak memory 248984 kb
Host smart-dc95a61a-b936-479d-ae6b-95cbab17f35e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=125198007 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy_stress.125198007
Directory /workspace/1.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/1.alert_handler_esc_alert_accum.1672012552
Short name T78
Test name
Test status
Simulation time 4373419570 ps
CPU time 221.69 seconds
Started Jul 19 04:48:33 PM PDT 24
Finished Jul 19 04:52:33 PM PDT 24
Peak memory 256856 kb
Host smart-7dd3b6ba-5b28-4d78-be82-ce70b9221cb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16720
12552 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_alert_accum.1672012552
Directory /workspace/1.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/1.alert_handler_esc_intr_timeout.679671792
Short name T422
Test name
Test status
Simulation time 748490866 ps
CPU time 42.38 seconds
Started Jul 19 04:48:33 PM PDT 24
Finished Jul 19 04:49:34 PM PDT 24
Peak memory 256100 kb
Host smart-b871e398-6468-4d54-85df-7a27cc99266a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67967
1792 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_intr_timeout.679671792
Directory /workspace/1.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_lpg_stub_clk.3722632997
Short name T391
Test name
Test status
Simulation time 11856422277 ps
CPU time 1143.02 seconds
Started Jul 19 04:48:34 PM PDT 24
Finished Jul 19 05:07:56 PM PDT 24
Peak memory 273684 kb
Host smart-c0901684-9134-4c53-b434-dca98664b6e0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722632997 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg_stub_clk.3722632997
Directory /workspace/1.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/1.alert_handler_ping_timeout.4076505431
Short name T293
Test name
Test status
Simulation time 39727307141 ps
CPU time 268.83 seconds
Started Jul 19 04:48:32 PM PDT 24
Finished Jul 19 04:53:19 PM PDT 24
Peak memory 249104 kb
Host smart-78904faa-3522-4c8e-b86e-e81bb8ad5231
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076505431 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_ping_timeout.4076505431
Directory /workspace/1.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_random_alerts.1257176354
Short name T403
Test name
Test status
Simulation time 1026769550 ps
CPU time 63.31 seconds
Started Jul 19 04:48:31 PM PDT 24
Finished Jul 19 04:49:52 PM PDT 24
Peak memory 256500 kb
Host smart-827b8bf0-a570-4339-a43a-67a6d37bac75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12571
76354 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_alerts.1257176354
Directory /workspace/1.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/1.alert_handler_random_classes.780582528
Short name T440
Test name
Test status
Simulation time 370781406 ps
CPU time 36.2 seconds
Started Jul 19 04:48:34 PM PDT 24
Finished Jul 19 04:49:28 PM PDT 24
Peak memory 248964 kb
Host smart-09270cce-6be8-412f-8df5-838df6546fdc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78058
2528 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_classes.780582528
Directory /workspace/1.alert_handler_random_classes/latest

Test location /workspace/coverage/default/1.alert_handler_sig_int_fail.4100778866
Short name T404
Test name
Test status
Simulation time 80518923 ps
CPU time 8.86 seconds
Started Jul 19 04:48:33 PM PDT 24
Finished Jul 19 04:49:00 PM PDT 24
Peak memory 248876 kb
Host smart-209554cb-7670-4b59-a6b6-a6f86aabb455
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41007
78866 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sig_int_fail.4100778866
Directory /workspace/1.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/1.alert_handler_smoke.1716917072
Short name T681
Test name
Test status
Simulation time 1487475898 ps
CPU time 50.58 seconds
Started Jul 19 04:48:37 PM PDT 24
Finished Jul 19 04:49:45 PM PDT 24
Peak memory 257132 kb
Host smart-4ca99399-46f6-432f-a8c1-73ce77c480c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17169
17072 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_smoke.1716917072
Directory /workspace/1.alert_handler_smoke/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all_with_rand_reset.3068428081
Short name T80
Test name
Test status
Simulation time 51271060607 ps
CPU time 1901.28 seconds
Started Jul 19 04:48:43 PM PDT 24
Finished Jul 19 05:20:41 PM PDT 24
Peak memory 281936 kb
Host smart-f49bcc57-7e38-4038-ae75-f02391d5ce07
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068428081 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.alert_handler_stress_all_with_rand_reset.3068428081
Directory /workspace/1.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.alert_handler_alert_accum_saturation.3795728395
Short name T219
Test name
Test status
Simulation time 41207066 ps
CPU time 2.26 seconds
Started Jul 19 04:49:01 PM PDT 24
Finished Jul 19 04:49:15 PM PDT 24
Peak memory 249180 kb
Host smart-aad8818f-2219-4ead-9d94-31da9900ef2d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3795728395 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_alert_accum_saturation.3795728395
Directory /workspace/10.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/10.alert_handler_entropy.387505304
Short name T532
Test name
Test status
Simulation time 132015469971 ps
CPU time 1252.32 seconds
Started Jul 19 04:48:43 PM PDT 24
Finished Jul 19 05:09:52 PM PDT 24
Peak memory 289180 kb
Host smart-4457550a-35b2-4031-8725-b395eae8e008
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387505304 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy.387505304
Directory /workspace/10.alert_handler_entropy/latest

Test location /workspace/coverage/default/10.alert_handler_esc_alert_accum.2578550867
Short name T34
Test name
Test status
Simulation time 51592346317 ps
CPU time 319.5 seconds
Started Jul 19 04:48:49 PM PDT 24
Finished Jul 19 04:54:23 PM PDT 24
Peak memory 256772 kb
Host smart-60675e9c-cef6-4df1-99d5-275116d4ae5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25785
50867 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_alert_accum.2578550867
Directory /workspace/10.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/10.alert_handler_esc_intr_timeout.1997851744
Short name T690
Test name
Test status
Simulation time 90825210 ps
CPU time 10.87 seconds
Started Jul 19 04:48:46 PM PDT 24
Finished Jul 19 04:49:13 PM PDT 24
Peak memory 248508 kb
Host smart-d7c12bcb-215d-4d07-b559-33382308a3d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19978
51744 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_intr_timeout.1997851744
Directory /workspace/10.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_lpg.447083197
Short name T319
Test name
Test status
Simulation time 187914754209 ps
CPU time 2837.42 seconds
Started Jul 19 04:48:52 PM PDT 24
Finished Jul 19 05:36:24 PM PDT 24
Peak memory 281864 kb
Host smart-42d6e7a1-d28a-4c44-8045-f323f9920dba
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447083197 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg.447083197
Directory /workspace/10.alert_handler_lpg/latest

Test location /workspace/coverage/default/10.alert_handler_lpg_stub_clk.1775094959
Short name T598
Test name
Test status
Simulation time 27617254933 ps
CPU time 1010.9 seconds
Started Jul 19 04:48:51 PM PDT 24
Finished Jul 19 05:05:57 PM PDT 24
Peak memory 289780 kb
Host smart-765cb8a5-4b1b-4db9-b257-1fea8c76c212
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775094959 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg_stub_clk.1775094959
Directory /workspace/10.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/10.alert_handler_ping_timeout.3576344534
Short name T102
Test name
Test status
Simulation time 29986295783 ps
CPU time 620.55 seconds
Started Jul 19 04:48:51 PM PDT 24
Finished Jul 19 04:59:26 PM PDT 24
Peak memory 257240 kb
Host smart-8e05691a-3041-4537-b4c7-160221b6411c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576344534 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_ping_timeout.3576344534
Directory /workspace/10.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_random_alerts.1157588603
Short name T399
Test name
Test status
Simulation time 1522756428 ps
CPU time 36.59 seconds
Started Jul 19 04:48:59 PM PDT 24
Finished Jul 19 04:49:47 PM PDT 24
Peak memory 256472 kb
Host smart-822cc1f6-f955-453b-80d8-0a8b9424e93f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11575
88603 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_alerts.1157588603
Directory /workspace/10.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/10.alert_handler_random_classes.2874157877
Short name T402
Test name
Test status
Simulation time 1200777148 ps
CPU time 66.02 seconds
Started Jul 19 04:48:52 PM PDT 24
Finished Jul 19 04:50:12 PM PDT 24
Peak memory 249968 kb
Host smart-7f26be22-abab-448b-9fe9-a719975675b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28741
57877 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_classes.2874157877
Directory /workspace/10.alert_handler_random_classes/latest

Test location /workspace/coverage/default/10.alert_handler_sig_int_fail.444565785
Short name T551
Test name
Test status
Simulation time 4321132294 ps
CPU time 59.29 seconds
Started Jul 19 04:48:58 PM PDT 24
Finished Jul 19 04:50:10 PM PDT 24
Peak memory 248720 kb
Host smart-8c8492a9-aede-43d1-804b-daf253debde2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44456
5785 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_sig_int_fail.444565785
Directory /workspace/10.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/10.alert_handler_smoke.1225198858
Short name T698
Test name
Test status
Simulation time 53342350 ps
CPU time 2.99 seconds
Started Jul 19 04:48:51 PM PDT 24
Finished Jul 19 04:49:09 PM PDT 24
Peak memory 251036 kb
Host smart-ce81e17f-008a-4826-9c8b-9b04012affcf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12251
98858 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_smoke.1225198858
Directory /workspace/10.alert_handler_smoke/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all.564257627
Short name T553
Test name
Test status
Simulation time 48054683993 ps
CPU time 1700.76 seconds
Started Jul 19 04:48:51 PM PDT 24
Finished Jul 19 05:17:26 PM PDT 24
Peak memory 297988 kb
Host smart-af121a24-8bac-4417-b389-a7c94e87d63d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564257627 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_han
dler_stress_all.564257627
Directory /workspace/10.alert_handler_stress_all/latest

Test location /workspace/coverage/default/11.alert_handler_entropy.349761634
Short name T605
Test name
Test status
Simulation time 6948583493 ps
CPU time 620.47 seconds
Started Jul 19 04:49:10 PM PDT 24
Finished Jul 19 04:59:41 PM PDT 24
Peak memory 265272 kb
Host smart-c9c4d1d0-ba58-43bf-b471-eb2fd05873a1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349761634 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy.349761634
Directory /workspace/11.alert_handler_entropy/latest

Test location /workspace/coverage/default/11.alert_handler_entropy_stress.1588234536
Short name T672
Test name
Test status
Simulation time 809634715 ps
CPU time 20.46 seconds
Started Jul 19 04:48:55 PM PDT 24
Finished Jul 19 04:49:29 PM PDT 24
Peak memory 248884 kb
Host smart-63a69bb1-fd3f-4bd9-bd1d-706503d715f6
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1588234536 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy_stress.1588234536
Directory /workspace/11.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/11.alert_handler_esc_alert_accum.1404498373
Short name T689
Test name
Test status
Simulation time 4444541689 ps
CPU time 117.62 seconds
Started Jul 19 04:48:58 PM PDT 24
Finished Jul 19 04:51:08 PM PDT 24
Peak memory 256552 kb
Host smart-1a884a3d-b3da-4cd2-9dcc-ce930a8e9cfa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14044
98373 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_alert_accum.1404498373
Directory /workspace/11.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/11.alert_handler_esc_intr_timeout.501382097
Short name T42
Test name
Test status
Simulation time 8877037538 ps
CPU time 25.6 seconds
Started Jul 19 04:48:47 PM PDT 24
Finished Jul 19 04:49:28 PM PDT 24
Peak memory 256136 kb
Host smart-e91a17f2-0c07-4369-bb46-79eb376727f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50138
2097 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_intr_timeout.501382097
Directory /workspace/11.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_lpg_stub_clk.1028326095
Short name T614
Test name
Test status
Simulation time 76898997283 ps
CPU time 2264.74 seconds
Started Jul 19 04:48:55 PM PDT 24
Finished Jul 19 05:26:54 PM PDT 24
Peak memory 289728 kb
Host smart-86d54ddf-d6c8-4352-8396-4d0448a77aae
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028326095 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg_stub_clk.1028326095
Directory /workspace/11.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/11.alert_handler_ping_timeout.4123808785
Short name T311
Test name
Test status
Simulation time 16679379095 ps
CPU time 329.96 seconds
Started Jul 19 04:49:34 PM PDT 24
Finished Jul 19 04:55:19 PM PDT 24
Peak memory 248928 kb
Host smart-f2febd3f-3d34-40bb-8d9e-ee4fc6e35310
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123808785 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_ping_timeout.4123808785
Directory /workspace/11.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_random_alerts.2282552567
Short name T373
Test name
Test status
Simulation time 274752295 ps
CPU time 16.92 seconds
Started Jul 19 04:48:55 PM PDT 24
Finished Jul 19 04:49:26 PM PDT 24
Peak memory 248848 kb
Host smart-efdf6969-4eda-4ee0-9ae9-9d21d521c83a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22825
52567 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_alerts.2282552567
Directory /workspace/11.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/11.alert_handler_random_classes.2983023372
Short name T452
Test name
Test status
Simulation time 3959271219 ps
CPU time 25.11 seconds
Started Jul 19 04:48:52 PM PDT 24
Finished Jul 19 04:49:31 PM PDT 24
Peak memory 256200 kb
Host smart-178bccb4-5451-458f-b321-a8ba2eb6518a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29830
23372 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_classes.2983023372
Directory /workspace/11.alert_handler_random_classes/latest

Test location /workspace/coverage/default/11.alert_handler_sig_int_fail.77883824
Short name T358
Test name
Test status
Simulation time 2796570564 ps
CPU time 41.49 seconds
Started Jul 19 04:49:15 PM PDT 24
Finished Jul 19 04:50:08 PM PDT 24
Peak memory 249384 kb
Host smart-d4f92cef-336c-40ef-aae2-625ac1f1f204
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77883
824 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_sig_int_fail.77883824
Directory /workspace/11.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/11.alert_handler_smoke.542536848
Short name T449
Test name
Test status
Simulation time 316341182 ps
CPU time 14.87 seconds
Started Jul 19 04:49:01 PM PDT 24
Finished Jul 19 04:49:27 PM PDT 24
Peak memory 256824 kb
Host smart-eaf23322-73e0-4bf8-9b99-6a260548e8c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54253
6848 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_smoke.542536848
Directory /workspace/11.alert_handler_smoke/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all.1775842144
Short name T426
Test name
Test status
Simulation time 137806017 ps
CPU time 11.58 seconds
Started Jul 19 04:49:09 PM PDT 24
Finished Jul 19 04:49:31 PM PDT 24
Peak memory 254036 kb
Host smart-11ee1768-269f-4bf0-87b4-59a5f03a4dda
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775842144 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_ha
ndler_stress_all.1775842144
Directory /workspace/11.alert_handler_stress_all/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all_with_rand_reset.2632256688
Short name T93
Test name
Test status
Simulation time 694621740563 ps
CPU time 7883.07 seconds
Started Jul 19 04:48:56 PM PDT 24
Finished Jul 19 07:00:34 PM PDT 24
Peak memory 322744 kb
Host smart-c967544c-a2b5-4584-82e0-45a23118c044
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632256688 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 11.alert_handler_stress_all_with_rand_reset.2632256688
Directory /workspace/11.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.alert_handler_alert_accum_saturation.1650153197
Short name T100
Test name
Test status
Simulation time 31277184 ps
CPU time 3.3 seconds
Started Jul 19 04:49:17 PM PDT 24
Finished Jul 19 04:49:33 PM PDT 24
Peak memory 249016 kb
Host smart-ab83bdcc-7faf-4d05-bd51-18f49b03b07d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1650153197 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_alert_accum_saturation.1650153197
Directory /workspace/12.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/12.alert_handler_entropy_stress.2770726014
Short name T198
Test name
Test status
Simulation time 5027869257 ps
CPU time 50.31 seconds
Started Jul 19 04:49:00 PM PDT 24
Finished Jul 19 04:50:02 PM PDT 24
Peak memory 249072 kb
Host smart-b2d38f75-3509-4540-9ed6-2fc730a029a8
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2770726014 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy_stress.2770726014
Directory /workspace/12.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/12.alert_handler_esc_alert_accum.3602644116
Short name T554
Test name
Test status
Simulation time 2471361322 ps
CPU time 124.78 seconds
Started Jul 19 04:49:04 PM PDT 24
Finished Jul 19 04:51:20 PM PDT 24
Peak memory 256540 kb
Host smart-600913a7-2546-4bd3-8b06-34470d9e81cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36026
44116 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_alert_accum.3602644116
Directory /workspace/12.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/12.alert_handler_esc_intr_timeout.3142946605
Short name T664
Test name
Test status
Simulation time 157655112 ps
CPU time 6.2 seconds
Started Jul 19 04:48:48 PM PDT 24
Finished Jul 19 04:49:09 PM PDT 24
Peak memory 248460 kb
Host smart-22a74542-9998-45b7-9cb9-7470e9671ab2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31429
46605 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_intr_timeout.3142946605
Directory /workspace/12.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_lpg.3498478187
Short name T687
Test name
Test status
Simulation time 234944214402 ps
CPU time 1846.64 seconds
Started Jul 19 04:48:54 PM PDT 24
Finished Jul 19 05:19:55 PM PDT 24
Peak memory 273640 kb
Host smart-c44dc7fe-5dff-485c-b7be-93174999a6e5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3498478187 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg.3498478187
Directory /workspace/12.alert_handler_lpg/latest

Test location /workspace/coverage/default/12.alert_handler_lpg_stub_clk.636956090
Short name T197
Test name
Test status
Simulation time 27163144496 ps
CPU time 1307.92 seconds
Started Jul 19 04:49:09 PM PDT 24
Finished Jul 19 05:11:08 PM PDT 24
Peak memory 289700 kb
Host smart-dff87331-caf6-4685-995f-491e57bd613f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636956090 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg_stub_clk.636956090
Directory /workspace/12.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/12.alert_handler_ping_timeout.469398958
Short name T529
Test name
Test status
Simulation time 6722043137 ps
CPU time 286.78 seconds
Started Jul 19 04:49:00 PM PDT 24
Finished Jul 19 04:53:59 PM PDT 24
Peak memory 247988 kb
Host smart-78984a73-4120-45d8-bbc8-5e9518ab65ca
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469398958 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_ping_timeout.469398958
Directory /workspace/12.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_random_alerts.2110049419
Short name T22
Test name
Test status
Simulation time 4004236215 ps
CPU time 56.72 seconds
Started Jul 19 04:48:49 PM PDT 24
Finished Jul 19 04:50:00 PM PDT 24
Peak memory 255964 kb
Host smart-cfabf22b-099e-4e33-9678-ef08160ed247
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21100
49419 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_alerts.2110049419
Directory /workspace/12.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/12.alert_handler_random_classes.268730978
Short name T571
Test name
Test status
Simulation time 1226905800 ps
CPU time 9.14 seconds
Started Jul 19 04:48:48 PM PDT 24
Finished Jul 19 04:49:13 PM PDT 24
Peak memory 252532 kb
Host smart-e56b3276-8c68-42e3-8bc8-10caa71fc54c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26873
0978 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_classes.268730978
Directory /workspace/12.alert_handler_random_classes/latest

Test location /workspace/coverage/default/12.alert_handler_sig_int_fail.585802977
Short name T238
Test name
Test status
Simulation time 1825836672 ps
CPU time 51.18 seconds
Started Jul 19 04:48:53 PM PDT 24
Finished Jul 19 04:49:58 PM PDT 24
Peak memory 256424 kb
Host smart-9bfe3f37-411c-428d-8d9f-9527a9952f81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58580
2977 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_sig_int_fail.585802977
Directory /workspace/12.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/12.alert_handler_smoke.3686007004
Short name T619
Test name
Test status
Simulation time 315230949 ps
CPU time 18.78 seconds
Started Jul 19 04:49:08 PM PDT 24
Finished Jul 19 04:49:38 PM PDT 24
Peak memory 248972 kb
Host smart-18db6092-9f3a-45ab-baf8-ae889c62273d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36860
07004 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_smoke.3686007004
Directory /workspace/12.alert_handler_smoke/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all.3810541494
Short name T611
Test name
Test status
Simulation time 7077330598 ps
CPU time 395.74 seconds
Started Jul 19 04:49:07 PM PDT 24
Finished Jul 19 04:55:53 PM PDT 24
Peak memory 257020 kb
Host smart-d6e0da8e-426b-43be-ba07-cc8238a470c1
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810541494 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_ha
ndler_stress_all.3810541494
Directory /workspace/12.alert_handler_stress_all/latest

Test location /workspace/coverage/default/13.alert_handler_alert_accum_saturation.3207740426
Short name T209
Test name
Test status
Simulation time 15382621 ps
CPU time 2.22 seconds
Started Jul 19 04:49:16 PM PDT 24
Finished Jul 19 04:49:29 PM PDT 24
Peak memory 249264 kb
Host smart-7fef6f57-2a8d-4c5b-a86e-5863badaf77f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3207740426 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_alert_accum_saturation.3207740426
Directory /workspace/13.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/13.alert_handler_entropy.2820449098
Short name T292
Test name
Test status
Simulation time 148862640069 ps
CPU time 1433.65 seconds
Started Jul 19 04:49:01 PM PDT 24
Finished Jul 19 05:13:07 PM PDT 24
Peak memory 273656 kb
Host smart-d1ad2190-b701-4d8f-8489-5f9b25a8aa6e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2820449098 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy.2820449098
Directory /workspace/13.alert_handler_entropy/latest

Test location /workspace/coverage/default/13.alert_handler_entropy_stress.429357334
Short name T378
Test name
Test status
Simulation time 565662204 ps
CPU time 8.66 seconds
Started Jul 19 04:48:56 PM PDT 24
Finished Jul 19 04:49:18 PM PDT 24
Peak memory 248876 kb
Host smart-c7dac510-18b7-4ab8-a099-970fbbf5fcbe
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=429357334 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy_stress.429357334
Directory /workspace/13.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/13.alert_handler_esc_alert_accum.2073684429
Short name T429
Test name
Test status
Simulation time 3202782762 ps
CPU time 146.53 seconds
Started Jul 19 04:49:04 PM PDT 24
Finished Jul 19 04:51:41 PM PDT 24
Peak memory 251096 kb
Host smart-5a696c4f-d379-4d71-abe4-9dd606e055f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20736
84429 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_alert_accum.2073684429
Directory /workspace/13.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/13.alert_handler_esc_intr_timeout.3288029465
Short name T498
Test name
Test status
Simulation time 1236157931 ps
CPU time 68.55 seconds
Started Jul 19 04:48:57 PM PDT 24
Finished Jul 19 04:50:18 PM PDT 24
Peak memory 256968 kb
Host smart-1f982666-f5d3-4ecd-af7c-c2de7bc971d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32880
29465 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_intr_timeout.3288029465
Directory /workspace/13.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_lpg_stub_clk.3813286972
Short name T272
Test name
Test status
Simulation time 103233123166 ps
CPU time 1433.06 seconds
Started Jul 19 04:49:06 PM PDT 24
Finished Jul 19 05:13:09 PM PDT 24
Peak memory 273576 kb
Host smart-8e2e0f5e-941a-4e75-9cbf-3f8a2cbb815f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813286972 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg_stub_clk.3813286972
Directory /workspace/13.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/13.alert_handler_ping_timeout.69066239
Short name T575
Test name
Test status
Simulation time 2648306557 ps
CPU time 108.15 seconds
Started Jul 19 04:49:01 PM PDT 24
Finished Jul 19 04:51:01 PM PDT 24
Peak memory 248960 kb
Host smart-9a7b46f1-6605-48e8-b65d-432df68dc24c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69066239 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_ping_timeout.69066239
Directory /workspace/13.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_random_alerts.1107379186
Short name T692
Test name
Test status
Simulation time 698953278 ps
CPU time 45.39 seconds
Started Jul 19 04:49:09 PM PDT 24
Finished Jul 19 04:50:05 PM PDT 24
Peak memory 256024 kb
Host smart-db614b9e-3ae1-4f28-9ab8-5fc2e68ae67d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11073
79186 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_alerts.1107379186
Directory /workspace/13.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/13.alert_handler_random_classes.1904720251
Short name T69
Test name
Test status
Simulation time 1936520785 ps
CPU time 45.04 seconds
Started Jul 19 04:49:20 PM PDT 24
Finished Jul 19 04:50:16 PM PDT 24
Peak memory 256792 kb
Host smart-8a263853-b60e-4746-869c-e4600610e7c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19047
20251 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_classes.1904720251
Directory /workspace/13.alert_handler_random_classes/latest

Test location /workspace/coverage/default/13.alert_handler_sig_int_fail.31203954
Short name T284
Test name
Test status
Simulation time 4462290874 ps
CPU time 35.36 seconds
Started Jul 19 04:48:55 PM PDT 24
Finished Jul 19 04:49:44 PM PDT 24
Peak memory 256624 kb
Host smart-e9f1fd66-b1bb-460b-9d00-9679f4a847a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31203
954 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_sig_int_fail.31203954
Directory /workspace/13.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/13.alert_handler_smoke.4286663751
Short name T350
Test name
Test status
Simulation time 921672755 ps
CPU time 48.76 seconds
Started Jul 19 04:49:29 PM PDT 24
Finished Jul 19 04:50:32 PM PDT 24
Peak memory 256176 kb
Host smart-b86a320b-3292-4d57-bada-0414a1e0ca76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42866
63751 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_smoke.4286663751
Directory /workspace/13.alert_handler_smoke/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all.1719498017
Short name T40
Test name
Test status
Simulation time 18755691976 ps
CPU time 55.89 seconds
Started Jul 19 04:48:57 PM PDT 24
Finished Jul 19 04:50:06 PM PDT 24
Peak memory 256328 kb
Host smart-de520132-3b71-4f5a-8aa8-6e3106f47c78
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719498017 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_ha
ndler_stress_all.1719498017
Directory /workspace/13.alert_handler_stress_all/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all_with_rand_reset.3253739497
Short name T83
Test name
Test status
Simulation time 76844622801 ps
CPU time 2162.78 seconds
Started Jul 19 04:49:02 PM PDT 24
Finished Jul 19 05:25:16 PM PDT 24
Peak memory 305444 kb
Host smart-f16153e4-2dd8-4687-807f-5080a3959ff4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253739497 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.alert_handler_stress_all_with_rand_reset.3253739497
Directory /workspace/13.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.alert_handler_alert_accum_saturation.2193483224
Short name T214
Test name
Test status
Simulation time 36930426 ps
CPU time 3.32 seconds
Started Jul 19 04:49:12 PM PDT 24
Finished Jul 19 04:49:26 PM PDT 24
Peak memory 249140 kb
Host smart-e5f24d1f-c3f7-46de-afdd-9a5170cae3b4
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2193483224 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_alert_accum_saturation.2193483224
Directory /workspace/14.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/14.alert_handler_entropy.4086530229
Short name T108
Test name
Test status
Simulation time 91625120839 ps
CPU time 912.75 seconds
Started Jul 19 04:49:04 PM PDT 24
Finished Jul 19 05:04:28 PM PDT 24
Peak memory 269572 kb
Host smart-65a8e029-e172-4d26-bcc1-75b0ded39e4a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086530229 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy.4086530229
Directory /workspace/14.alert_handler_entropy/latest

Test location /workspace/coverage/default/14.alert_handler_entropy_stress.2363659176
Short name T446
Test name
Test status
Simulation time 464240132 ps
CPU time 21.54 seconds
Started Jul 19 04:49:01 PM PDT 24
Finished Jul 19 04:49:34 PM PDT 24
Peak memory 248820 kb
Host smart-efb065dc-6a25-4528-a299-64e002a0fbb5
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2363659176 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy_stress.2363659176
Directory /workspace/14.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/14.alert_handler_esc_alert_accum.652331679
Short name T411
Test name
Test status
Simulation time 58710853703 ps
CPU time 271.22 seconds
Started Jul 19 04:49:03 PM PDT 24
Finished Jul 19 04:53:45 PM PDT 24
Peak memory 256712 kb
Host smart-62aeb192-6a1c-4e5d-b0e6-92b9a3838c8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65233
1679 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_alert_accum.652331679
Directory /workspace/14.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/14.alert_handler_lpg.1163451941
Short name T201
Test name
Test status
Simulation time 63145883196 ps
CPU time 1758.46 seconds
Started Jul 19 04:49:00 PM PDT 24
Finished Jul 19 05:18:31 PM PDT 24
Peak memory 273652 kb
Host smart-396920f1-dade-4fd9-aca4-6f3f4e240bdb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1163451941 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg.1163451941
Directory /workspace/14.alert_handler_lpg/latest

Test location /workspace/coverage/default/14.alert_handler_lpg_stub_clk.2382439377
Short name T587
Test name
Test status
Simulation time 19732701039 ps
CPU time 888.88 seconds
Started Jul 19 04:48:53 PM PDT 24
Finished Jul 19 05:03:56 PM PDT 24
Peak memory 273600 kb
Host smart-9d79a1ff-65e0-44d1-a430-ce79b3a5f62a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382439377 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg_stub_clk.2382439377
Directory /workspace/14.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/14.alert_handler_ping_timeout.4123733450
Short name T244
Test name
Test status
Simulation time 7547879167 ps
CPU time 325.4 seconds
Started Jul 19 04:49:12 PM PDT 24
Finished Jul 19 04:54:48 PM PDT 24
Peak memory 249196 kb
Host smart-466204b1-43c5-418f-81d9-2830b608c5ba
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123733450 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_ping_timeout.4123733450
Directory /workspace/14.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_random_alerts.3161234446
Short name T386
Test name
Test status
Simulation time 55919757 ps
CPU time 7.18 seconds
Started Jul 19 04:48:52 PM PDT 24
Finished Jul 19 04:49:14 PM PDT 24
Peak memory 248956 kb
Host smart-11f65cbf-c626-4244-b4a7-e65edb1917c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31612
34446 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_alerts.3161234446
Directory /workspace/14.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/14.alert_handler_random_classes.777701901
Short name T502
Test name
Test status
Simulation time 1197985492 ps
CPU time 65.93 seconds
Started Jul 19 04:49:03 PM PDT 24
Finished Jul 19 04:50:20 PM PDT 24
Peak memory 248308 kb
Host smart-c18430f2-89aa-4cf1-90b8-bf6297a96d85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77770
1901 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_classes.777701901
Directory /workspace/14.alert_handler_random_classes/latest

Test location /workspace/coverage/default/14.alert_handler_sig_int_fail.1363879998
Short name T700
Test name
Test status
Simulation time 626324490 ps
CPU time 6.38 seconds
Started Jul 19 04:49:11 PM PDT 24
Finished Jul 19 04:49:27 PM PDT 24
Peak memory 249568 kb
Host smart-84349285-a741-476b-b7ea-2511ad669fa1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13638
79998 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_sig_int_fail.1363879998
Directory /workspace/14.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/14.alert_handler_smoke.1160649503
Short name T406
Test name
Test status
Simulation time 716660498 ps
CPU time 37.97 seconds
Started Jul 19 04:49:02 PM PDT 24
Finished Jul 19 04:49:51 PM PDT 24
Peak memory 248868 kb
Host smart-6413cb43-6a0f-4798-a3c6-25597224df7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11606
49503 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_smoke.1160649503
Directory /workspace/14.alert_handler_smoke/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all.886953459
Short name T477
Test name
Test status
Simulation time 1524788434 ps
CPU time 25.93 seconds
Started Jul 19 04:49:12 PM PDT 24
Finished Jul 19 04:49:49 PM PDT 24
Peak memory 256600 kb
Host smart-2e43473e-72a5-45d7-8996-62b3a1958e9c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886953459 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_han
dler_stress_all.886953459
Directory /workspace/14.alert_handler_stress_all/latest

Test location /workspace/coverage/default/15.alert_handler_alert_accum_saturation.2628568952
Short name T213
Test name
Test status
Simulation time 44554007 ps
CPU time 3.8 seconds
Started Jul 19 04:49:08 PM PDT 24
Finished Jul 19 04:49:22 PM PDT 24
Peak memory 249192 kb
Host smart-22658aa8-6388-45cf-90fa-8608669660b4
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2628568952 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_alert_accum_saturation.2628568952
Directory /workspace/15.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/15.alert_handler_entropy.123464243
Short name T644
Test name
Test status
Simulation time 41622531361 ps
CPU time 2369.07 seconds
Started Jul 19 04:49:01 PM PDT 24
Finished Jul 19 05:28:42 PM PDT 24
Peak memory 289316 kb
Host smart-e42dd492-5ae2-4297-8297-d8858b8eb086
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=123464243 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy.123464243
Directory /workspace/15.alert_handler_entropy/latest

Test location /workspace/coverage/default/15.alert_handler_entropy_stress.261215727
Short name T200
Test name
Test status
Simulation time 454694243 ps
CPU time 8.17 seconds
Started Jul 19 04:49:09 PM PDT 24
Finished Jul 19 04:49:28 PM PDT 24
Peak memory 248864 kb
Host smart-bf989372-5798-44f1-933a-9bf814bed42f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=261215727 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy_stress.261215727
Directory /workspace/15.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/15.alert_handler_esc_alert_accum.1416938907
Short name T239
Test name
Test status
Simulation time 1543022427 ps
CPU time 162.17 seconds
Started Jul 19 04:49:09 PM PDT 24
Finished Jul 19 04:52:02 PM PDT 24
Peak memory 257112 kb
Host smart-64d7dde4-0362-4750-b633-02190a8d5c0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14169
38907 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_alert_accum.1416938907
Directory /workspace/15.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/15.alert_handler_esc_intr_timeout.3348302179
Short name T18
Test name
Test status
Simulation time 1520464432 ps
CPU time 20.6 seconds
Started Jul 19 04:49:06 PM PDT 24
Finished Jul 19 04:49:37 PM PDT 24
Peak memory 248436 kb
Host smart-e7f3ad6c-f2f7-4936-9fa2-3bfd0f6bd5de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33483
02179 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_intr_timeout.3348302179
Directory /workspace/15.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_lpg_stub_clk.409608490
Short name T36
Test name
Test status
Simulation time 38765576130 ps
CPU time 730.05 seconds
Started Jul 19 04:49:18 PM PDT 24
Finished Jul 19 05:01:40 PM PDT 24
Peak memory 273616 kb
Host smart-5e1a10c3-6de2-49a4-b4b0-e10fc03c3ed6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409608490 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg_stub_clk.409608490
Directory /workspace/15.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/15.alert_handler_ping_timeout.4242583548
Short name T252
Test name
Test status
Simulation time 14310331421 ps
CPU time 203.79 seconds
Started Jul 19 04:48:58 PM PDT 24
Finished Jul 19 04:52:34 PM PDT 24
Peak memory 249100 kb
Host smart-050e44f4-e3bc-4d74-96a3-639dae8833b3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242583548 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_ping_timeout.4242583548
Directory /workspace/15.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_random_alerts.494928928
Short name T365
Test name
Test status
Simulation time 1232755889 ps
CPU time 45.79 seconds
Started Jul 19 04:49:09 PM PDT 24
Finished Jul 19 04:50:05 PM PDT 24
Peak memory 256308 kb
Host smart-776e9832-a8d9-42c5-bd9c-aed72f3181c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49492
8928 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_alerts.494928928
Directory /workspace/15.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/15.alert_handler_random_classes.2348470552
Short name T461
Test name
Test status
Simulation time 715520426 ps
CPU time 41.64 seconds
Started Jul 19 04:49:15 PM PDT 24
Finished Jul 19 04:50:08 PM PDT 24
Peak memory 256884 kb
Host smart-01363ddd-91c0-492d-8500-bb785fbcf809
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23484
70552 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_classes.2348470552
Directory /workspace/15.alert_handler_random_classes/latest

Test location /workspace/coverage/default/15.alert_handler_sig_int_fail.3315781322
Short name T290
Test name
Test status
Simulation time 1054077193 ps
CPU time 30.07 seconds
Started Jul 19 04:48:57 PM PDT 24
Finished Jul 19 04:49:40 PM PDT 24
Peak memory 248860 kb
Host smart-08fc523e-2de0-497d-88e1-24be95ee1b9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33157
81322 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_sig_int_fail.3315781322
Directory /workspace/15.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/15.alert_handler_smoke.697514986
Short name T228
Test name
Test status
Simulation time 1641011441 ps
CPU time 47.96 seconds
Started Jul 19 04:49:05 PM PDT 24
Finished Jul 19 04:50:03 PM PDT 24
Peak memory 257160 kb
Host smart-dc83ac33-0d82-4508-90f1-1cc30c43ec8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69751
4986 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_smoke.697514986
Directory /workspace/15.alert_handler_smoke/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all.2658010024
Short name T45
Test name
Test status
Simulation time 57227943533 ps
CPU time 1378.03 seconds
Started Jul 19 04:49:09 PM PDT 24
Finished Jul 19 05:12:18 PM PDT 24
Peak memory 284168 kb
Host smart-a680d6da-48b6-46fe-9e27-654abd072878
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658010024 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_ha
ndler_stress_all.2658010024
Directory /workspace/15.alert_handler_stress_all/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all_with_rand_reset.436291850
Short name T546
Test name
Test status
Simulation time 64245632543 ps
CPU time 2364.15 seconds
Started Jul 19 04:48:53 PM PDT 24
Finished Jul 19 05:28:31 PM PDT 24
Peak memory 290096 kb
Host smart-b8c61106-9908-4477-81e9-d3a2740d5672
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436291850 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 15.alert_handler_stress_all_with_rand_reset.436291850
Directory /workspace/15.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.alert_handler_entropy.945966997
Short name T356
Test name
Test status
Simulation time 86856272317 ps
CPU time 1699.8 seconds
Started Jul 19 04:49:13 PM PDT 24
Finished Jul 19 05:17:44 PM PDT 24
Peak memory 273172 kb
Host smart-b058fc51-47aa-4edc-9eed-d6f70449d36e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945966997 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy.945966997
Directory /workspace/16.alert_handler_entropy/latest

Test location /workspace/coverage/default/16.alert_handler_entropy_stress.5936083
Short name T542
Test name
Test status
Simulation time 647945614 ps
CPU time 14.77 seconds
Started Jul 19 04:49:10 PM PDT 24
Finished Jul 19 04:49:36 PM PDT 24
Peak memory 248852 kb
Host smart-ef6502f5-321e-481a-af83-cf479127b88d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=5936083 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy_stress.5936083
Directory /workspace/16.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/16.alert_handler_esc_alert_accum.488444871
Short name T500
Test name
Test status
Simulation time 1881401234 ps
CPU time 125.4 seconds
Started Jul 19 04:49:21 PM PDT 24
Finished Jul 19 04:51:38 PM PDT 24
Peak memory 256632 kb
Host smart-9fa7d605-258e-4368-a492-bc5673796049
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48844
4871 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_alert_accum.488444871
Directory /workspace/16.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/16.alert_handler_esc_intr_timeout.393982486
Short name T594
Test name
Test status
Simulation time 120670186 ps
CPU time 9.28 seconds
Started Jul 19 04:49:05 PM PDT 24
Finished Jul 19 04:49:25 PM PDT 24
Peak memory 248900 kb
Host smart-8b40b5da-182a-4031-9ccd-50538c81c187
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39398
2486 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_intr_timeout.393982486
Directory /workspace/16.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_lpg.319780806
Short name T335
Test name
Test status
Simulation time 259638524534 ps
CPU time 1545.8 seconds
Started Jul 19 04:49:15 PM PDT 24
Finished Jul 19 05:15:12 PM PDT 24
Peak memory 273528 kb
Host smart-1ad0a7a0-f5ac-4003-be77-d519d3a7b215
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319780806 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg.319780806
Directory /workspace/16.alert_handler_lpg/latest

Test location /workspace/coverage/default/16.alert_handler_lpg_stub_clk.3591900968
Short name T14
Test name
Test status
Simulation time 61728613131 ps
CPU time 687.68 seconds
Started Jul 19 04:49:18 PM PDT 24
Finished Jul 19 05:00:58 PM PDT 24
Peak memory 268728 kb
Host smart-711062e4-d947-4b29-90df-091542d90f7e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591900968 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg_stub_clk.3591900968
Directory /workspace/16.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/16.alert_handler_ping_timeout.4177719394
Short name T303
Test name
Test status
Simulation time 6449733392 ps
CPU time 164.77 seconds
Started Jul 19 04:49:09 PM PDT 24
Finished Jul 19 04:52:04 PM PDT 24
Peak memory 248856 kb
Host smart-192dfda3-e881-4fc3-b725-4a3c928ae6d2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177719394 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_ping_timeout.4177719394
Directory /workspace/16.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_random_alerts.2198964532
Short name T557
Test name
Test status
Simulation time 1512447634 ps
CPU time 33.2 seconds
Started Jul 19 04:49:12 PM PDT 24
Finished Jul 19 04:49:57 PM PDT 24
Peak memory 256460 kb
Host smart-fa809111-4425-4622-857c-d431cc9c7933
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21989
64532 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_alerts.2198964532
Directory /workspace/16.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/16.alert_handler_random_classes.72298878
Short name T434
Test name
Test status
Simulation time 275066300 ps
CPU time 15.93 seconds
Started Jul 19 04:49:13 PM PDT 24
Finished Jul 19 04:49:40 PM PDT 24
Peak memory 254504 kb
Host smart-4ddc1e5f-6db2-40eb-88fe-ce660cc6a964
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72298
878 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_classes.72298878
Directory /workspace/16.alert_handler_random_classes/latest

Test location /workspace/coverage/default/16.alert_handler_sig_int_fail.362173684
Short name T544
Test name
Test status
Simulation time 258157681 ps
CPU time 15.56 seconds
Started Jul 19 04:49:14 PM PDT 24
Finished Jul 19 04:49:41 PM PDT 24
Peak memory 249256 kb
Host smart-819afaa8-f407-4ae4-a4da-0227991c4ba4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36217
3684 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_sig_int_fail.362173684
Directory /workspace/16.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/16.alert_handler_smoke.3341855711
Short name T439
Test name
Test status
Simulation time 443460960 ps
CPU time 8.24 seconds
Started Jul 19 04:49:05 PM PDT 24
Finished Jul 19 04:49:24 PM PDT 24
Peak memory 248972 kb
Host smart-a67af05d-c34c-4203-ad3b-d4d7c61e9d0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33418
55711 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_smoke.3341855711
Directory /workspace/16.alert_handler_smoke/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all.449280997
Short name T53
Test name
Test status
Simulation time 53073560139 ps
CPU time 3451.48 seconds
Started Jul 19 04:49:09 PM PDT 24
Finished Jul 19 05:46:51 PM PDT 24
Peak memory 289504 kb
Host smart-3f3a1a05-1c0f-4840-bb05-3f34265ed7d9
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449280997 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_han
dler_stress_all.449280997
Directory /workspace/16.alert_handler_stress_all/latest

Test location /workspace/coverage/default/17.alert_handler_alert_accum_saturation.4023719658
Short name T204
Test name
Test status
Simulation time 69232822 ps
CPU time 2.79 seconds
Started Jul 19 04:49:01 PM PDT 24
Finished Jul 19 04:49:15 PM PDT 24
Peak memory 249052 kb
Host smart-0c81b4c6-c9ee-440e-8fcd-924ddfea70f7
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4023719658 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_alert_accum_saturation.4023719658
Directory /workspace/17.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/17.alert_handler_entropy.209539756
Short name T654
Test name
Test status
Simulation time 28227514435 ps
CPU time 923.91 seconds
Started Jul 19 04:49:12 PM PDT 24
Finished Jul 19 05:04:47 PM PDT 24
Peak memory 272840 kb
Host smart-11027678-d129-40cb-8c97-791daecff405
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209539756 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy.209539756
Directory /workspace/17.alert_handler_entropy/latest

Test location /workspace/coverage/default/17.alert_handler_entropy_stress.619686661
Short name T533
Test name
Test status
Simulation time 594728549 ps
CPU time 16.18 seconds
Started Jul 19 04:49:07 PM PDT 24
Finished Jul 19 04:49:34 PM PDT 24
Peak memory 248904 kb
Host smart-e30d721b-b7ce-47a1-a29e-ae183087bc7c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=619686661 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy_stress.619686661
Directory /workspace/17.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/17.alert_handler_esc_alert_accum.2612533017
Short name T545
Test name
Test status
Simulation time 2153351615 ps
CPU time 149.81 seconds
Started Jul 19 04:49:09 PM PDT 24
Finished Jul 19 04:51:50 PM PDT 24
Peak memory 257204 kb
Host smart-46fc817e-dbef-4621-a9ab-ac690087ee1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26125
33017 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_alert_accum.2612533017
Directory /workspace/17.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/17.alert_handler_esc_intr_timeout.3293613747
Short name T625
Test name
Test status
Simulation time 121386246 ps
CPU time 4.86 seconds
Started Jul 19 04:49:30 PM PDT 24
Finished Jul 19 04:49:49 PM PDT 24
Peak memory 240304 kb
Host smart-df855e85-41b2-4f13-9ef5-547ea0c42987
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32936
13747 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_intr_timeout.3293613747
Directory /workspace/17.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_lpg_stub_clk.1468173774
Short name T410
Test name
Test status
Simulation time 155485531565 ps
CPU time 2344.91 seconds
Started Jul 19 04:49:06 PM PDT 24
Finished Jul 19 05:28:21 PM PDT 24
Peak memory 289220 kb
Host smart-4f90965a-5398-48f6-a543-11c7d74f5c70
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468173774 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg_stub_clk.1468173774
Directory /workspace/17.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/17.alert_handler_ping_timeout.4091431864
Short name T673
Test name
Test status
Simulation time 52559441128 ps
CPU time 475.03 seconds
Started Jul 19 04:49:13 PM PDT 24
Finished Jul 19 04:57:19 PM PDT 24
Peak memory 249108 kb
Host smart-48c87ef8-99d2-4746-8e9f-358171f0605d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091431864 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_ping_timeout.4091431864
Directory /workspace/17.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_random_alerts.4261481062
Short name T425
Test name
Test status
Simulation time 543687453 ps
CPU time 9.97 seconds
Started Jul 19 04:49:12 PM PDT 24
Finished Jul 19 04:49:33 PM PDT 24
Peak memory 248900 kb
Host smart-c07230ee-ab05-4443-a370-44866c57adbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42614
81062 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_alerts.4261481062
Directory /workspace/17.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/17.alert_handler_random_classes.2467419978
Short name T480
Test name
Test status
Simulation time 417197409 ps
CPU time 14.33 seconds
Started Jul 19 04:49:15 PM PDT 24
Finished Jul 19 04:49:41 PM PDT 24
Peak memory 256236 kb
Host smart-869180ee-5e9c-4f8a-997f-ccca75135b47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24674
19978 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_classes.2467419978
Directory /workspace/17.alert_handler_random_classes/latest

Test location /workspace/coverage/default/17.alert_handler_sig_int_fail.913107229
Short name T237
Test name
Test status
Simulation time 3536786150 ps
CPU time 23.25 seconds
Started Jul 19 04:49:19 PM PDT 24
Finished Jul 19 04:49:54 PM PDT 24
Peak memory 256536 kb
Host smart-6a1f67c8-84ec-4efe-9989-06d607b4bae2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91310
7229 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_sig_int_fail.913107229
Directory /workspace/17.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/17.alert_handler_smoke.1571092996
Short name T75
Test name
Test status
Simulation time 1840788933 ps
CPU time 54.99 seconds
Started Jul 19 04:49:11 PM PDT 24
Finished Jul 19 04:50:17 PM PDT 24
Peak memory 256568 kb
Host smart-8a642fb8-2975-49df-8d86-07c146b678f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15710
92996 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_smoke.1571092996
Directory /workspace/17.alert_handler_smoke/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all.2763750095
Short name T91
Test name
Test status
Simulation time 37730391059 ps
CPU time 2177.86 seconds
Started Jul 19 04:49:14 PM PDT 24
Finished Jul 19 05:25:43 PM PDT 24
Peak memory 285520 kb
Host smart-f30720aa-9f51-4ba3-913b-4b5d10af1179
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763750095 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_ha
ndler_stress_all.2763750095
Directory /workspace/17.alert_handler_stress_all/latest

Test location /workspace/coverage/default/18.alert_handler_alert_accum_saturation.670416655
Short name T216
Test name
Test status
Simulation time 221923010 ps
CPU time 3.69 seconds
Started Jul 19 04:49:13 PM PDT 24
Finished Jul 19 04:49:27 PM PDT 24
Peak memory 249148 kb
Host smart-fd39cdd2-0b46-4a4a-9990-d55bf5e5bfbc
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=670416655 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_alert_accum_saturation.670416655
Directory /workspace/18.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/18.alert_handler_entropy.959362823
Short name T577
Test name
Test status
Simulation time 50442127953 ps
CPU time 2966.41 seconds
Started Jul 19 04:49:05 PM PDT 24
Finished Jul 19 05:38:42 PM PDT 24
Peak memory 289052 kb
Host smart-d72b64fc-4003-4e7f-a4ce-c6fc86392671
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959362823 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy.959362823
Directory /workspace/18.alert_handler_entropy/latest

Test location /workspace/coverage/default/18.alert_handler_entropy_stress.1968117565
Short name T703
Test name
Test status
Simulation time 439818019 ps
CPU time 19.24 seconds
Started Jul 19 04:49:14 PM PDT 24
Finished Jul 19 04:49:45 PM PDT 24
Peak memory 248952 kb
Host smart-be6ce573-e54b-4131-a295-8c25b51875ef
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1968117565 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy_stress.1968117565
Directory /workspace/18.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/18.alert_handler_esc_alert_accum.1302442298
Short name T226
Test name
Test status
Simulation time 4014572560 ps
CPU time 198.2 seconds
Started Jul 19 04:49:17 PM PDT 24
Finished Jul 19 04:52:48 PM PDT 24
Peak memory 256672 kb
Host smart-e6f24ec0-eb27-4ce6-94c8-529a5a9f0979
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13024
42298 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_alert_accum.1302442298
Directory /workspace/18.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/18.alert_handler_esc_intr_timeout.4019579253
Short name T354
Test name
Test status
Simulation time 785580974 ps
CPU time 27.99 seconds
Started Jul 19 04:49:15 PM PDT 24
Finished Jul 19 04:49:54 PM PDT 24
Peak memory 256708 kb
Host smart-f9c7d76a-11a5-46d3-ae9e-3a4ed0eda76f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40195
79253 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_intr_timeout.4019579253
Directory /workspace/18.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_lpg_stub_clk.3344010623
Short name T641
Test name
Test status
Simulation time 146011105210 ps
CPU time 2197.42 seconds
Started Jul 19 04:49:15 PM PDT 24
Finished Jul 19 05:26:04 PM PDT 24
Peak memory 273412 kb
Host smart-28c52682-63b8-4111-8153-94ad220e2d31
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344010623 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg_stub_clk.3344010623
Directory /workspace/18.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/18.alert_handler_ping_timeout.87773821
Short name T302
Test name
Test status
Simulation time 18116982710 ps
CPU time 361.53 seconds
Started Jul 19 04:49:14 PM PDT 24
Finished Jul 19 04:55:27 PM PDT 24
Peak memory 257040 kb
Host smart-09b3d577-400d-4a35-9b1d-19dbf36f109c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87773821 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_ping_timeout.87773821
Directory /workspace/18.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_random_alerts.890310557
Short name T486
Test name
Test status
Simulation time 5071530403 ps
CPU time 50.34 seconds
Started Jul 19 04:49:27 PM PDT 24
Finished Jul 19 04:50:30 PM PDT 24
Peak memory 257192 kb
Host smart-ac24b594-245d-4e0b-8f9f-602f2e59601d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89031
0557 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_alerts.890310557
Directory /workspace/18.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/18.alert_handler_random_classes.1820036385
Short name T84
Test name
Test status
Simulation time 7279964293 ps
CPU time 69.25 seconds
Started Jul 19 04:49:15 PM PDT 24
Finished Jul 19 04:50:36 PM PDT 24
Peak memory 248872 kb
Host smart-56d043a3-7fff-4b36-b180-10e5eac38595
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18200
36385 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_classes.1820036385
Directory /workspace/18.alert_handler_random_classes/latest

Test location /workspace/coverage/default/18.alert_handler_smoke.3030359618
Short name T362
Test name
Test status
Simulation time 3104269384 ps
CPU time 44.98 seconds
Started Jul 19 04:49:13 PM PDT 24
Finished Jul 19 04:50:09 PM PDT 24
Peak memory 256556 kb
Host smart-e035f924-36fe-4378-ae30-0f9f89477145
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30303
59618 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_smoke.3030359618
Directory /workspace/18.alert_handler_smoke/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all.3361043140
Short name T88
Test name
Test status
Simulation time 1064961685988 ps
CPU time 3742.47 seconds
Started Jul 19 04:49:07 PM PDT 24
Finished Jul 19 05:51:40 PM PDT 24
Peak memory 299356 kb
Host smart-bec95998-9735-43a6-9831-263d0f7623ec
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361043140 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_ha
ndler_stress_all.3361043140
Directory /workspace/18.alert_handler_stress_all/latest

Test location /workspace/coverage/default/19.alert_handler_alert_accum_saturation.2415102024
Short name T217
Test name
Test status
Simulation time 42343895 ps
CPU time 3.39 seconds
Started Jul 19 04:49:17 PM PDT 24
Finished Jul 19 04:49:32 PM PDT 24
Peak memory 249264 kb
Host smart-18de3ff3-6cfe-4402-b7d3-a0aa984ea848
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2415102024 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_alert_accum_saturation.2415102024
Directory /workspace/19.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/19.alert_handler_entropy.2981423948
Short name T526
Test name
Test status
Simulation time 195795938815 ps
CPU time 2670.04 seconds
Started Jul 19 04:49:15 PM PDT 24
Finished Jul 19 05:33:57 PM PDT 24
Peak memory 286548 kb
Host smart-09ca175e-b9ba-4ba9-8f30-cbc4609b1016
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2981423948 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy.2981423948
Directory /workspace/19.alert_handler_entropy/latest

Test location /workspace/coverage/default/19.alert_handler_entropy_stress.1315185121
Short name T626
Test name
Test status
Simulation time 299357484 ps
CPU time 8.71 seconds
Started Jul 19 04:49:15 PM PDT 24
Finished Jul 19 04:49:35 PM PDT 24
Peak memory 248860 kb
Host smart-4815d563-db3c-4ec4-b415-32082aa72557
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1315185121 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy_stress.1315185121
Directory /workspace/19.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/19.alert_handler_esc_alert_accum.4047440040
Short name T267
Test name
Test status
Simulation time 12054490469 ps
CPU time 165.31 seconds
Started Jul 19 04:49:04 PM PDT 24
Finished Jul 19 04:52:00 PM PDT 24
Peak memory 257088 kb
Host smart-a7c6c9bb-c0ae-410c-8848-fb846ebd8334
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40474
40040 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_alert_accum.4047440040
Directory /workspace/19.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/19.alert_handler_esc_intr_timeout.371234314
Short name T585
Test name
Test status
Simulation time 101567614 ps
CPU time 3.46 seconds
Started Jul 19 04:49:15 PM PDT 24
Finished Jul 19 04:49:30 PM PDT 24
Peak memory 249328 kb
Host smart-1e8ba348-a4d7-41cf-a37b-561df0e95904
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37123
4314 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_intr_timeout.371234314
Directory /workspace/19.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_lpg.283515051
Short name T329
Test name
Test status
Simulation time 43868976163 ps
CPU time 1549.41 seconds
Started Jul 19 04:49:16 PM PDT 24
Finished Jul 19 05:15:17 PM PDT 24
Peak memory 265352 kb
Host smart-0d5c30cd-c9f9-43ed-b255-d48d9d2c3c9d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283515051 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg.283515051
Directory /workspace/19.alert_handler_lpg/latest

Test location /workspace/coverage/default/19.alert_handler_lpg_stub_clk.3493136041
Short name T530
Test name
Test status
Simulation time 21811640582 ps
CPU time 1448.28 seconds
Started Jul 19 04:49:05 PM PDT 24
Finished Jul 19 05:13:24 PM PDT 24
Peak memory 273536 kb
Host smart-670dd3c7-600d-46db-9546-7fcbaa2ec1ad
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3493136041 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg_stub_clk.3493136041
Directory /workspace/19.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/19.alert_handler_ping_timeout.3962802514
Short name T294
Test name
Test status
Simulation time 13893502025 ps
CPU time 571.76 seconds
Started Jul 19 04:49:22 PM PDT 24
Finished Jul 19 04:59:07 PM PDT 24
Peak memory 249104 kb
Host smart-39596143-f895-4848-b91f-79af0299935b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962802514 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_ping_timeout.3962802514
Directory /workspace/19.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_random_alerts.3057492602
Short name T457
Test name
Test status
Simulation time 202134108 ps
CPU time 13.1 seconds
Started Jul 19 04:49:09 PM PDT 24
Finished Jul 19 04:49:32 PM PDT 24
Peak memory 249012 kb
Host smart-1533ec9b-300d-41d1-bacd-d9bafa555081
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30574
92602 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_alerts.3057492602
Directory /workspace/19.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/19.alert_handler_random_classes.60336128
Short name T666
Test name
Test status
Simulation time 457439124 ps
CPU time 8.59 seconds
Started Jul 19 04:49:15 PM PDT 24
Finished Jul 19 04:49:35 PM PDT 24
Peak memory 251492 kb
Host smart-e83897a5-f07d-4c14-87b7-43d0763c301f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60336
128 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_classes.60336128
Directory /workspace/19.alert_handler_random_classes/latest

Test location /workspace/coverage/default/19.alert_handler_sig_int_fail.3702593116
Short name T668
Test name
Test status
Simulation time 174231768 ps
CPU time 12.73 seconds
Started Jul 19 04:49:12 PM PDT 24
Finished Jul 19 04:49:35 PM PDT 24
Peak memory 248444 kb
Host smart-8d6c6726-964d-4470-aea7-98ffd0ed899a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37025
93116 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_sig_int_fail.3702593116
Directory /workspace/19.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/19.alert_handler_smoke.239917814
Short name T227
Test name
Test status
Simulation time 2555023734 ps
CPU time 21.53 seconds
Started Jul 19 04:49:15 PM PDT 24
Finished Jul 19 04:49:48 PM PDT 24
Peak memory 256144 kb
Host smart-ac223c0e-09cf-4524-a128-66a2213b21e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23991
7814 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_smoke.239917814
Directory /workspace/19.alert_handler_smoke/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all.1189527088
Short name T289
Test name
Test status
Simulation time 4051489171 ps
CPU time 87.08 seconds
Started Jul 19 04:49:15 PM PDT 24
Finished Jul 19 04:50:54 PM PDT 24
Peak memory 257180 kb
Host smart-d4dfe0f7-e162-47a7-a95d-aead0fb1c4fc
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189527088 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_ha
ndler_stress_all.1189527088
Directory /workspace/19.alert_handler_stress_all/latest

Test location /workspace/coverage/default/2.alert_handler_alert_accum_saturation.2461504775
Short name T206
Test name
Test status
Simulation time 17280090 ps
CPU time 2.46 seconds
Started Jul 19 04:48:39 PM PDT 24
Finished Jul 19 04:48:59 PM PDT 24
Peak memory 249172 kb
Host smart-e1eea989-0722-4a2e-84d0-40d385dab84d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2461504775 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_alert_accum_saturation.2461504775
Directory /workspace/2.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/2.alert_handler_entropy.2890374824
Short name T90
Test name
Test status
Simulation time 113655523448 ps
CPU time 1819.19 seconds
Started Jul 19 04:48:45 PM PDT 24
Finished Jul 19 05:19:20 PM PDT 24
Peak memory 289212 kb
Host smart-15bddbbc-26ac-47fc-9d4a-02122ba5994b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890374824 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy.2890374824
Directory /workspace/2.alert_handler_entropy/latest

Test location /workspace/coverage/default/2.alert_handler_entropy_stress.3931793418
Short name T466
Test name
Test status
Simulation time 715386765 ps
CPU time 15.16 seconds
Started Jul 19 04:48:41 PM PDT 24
Finished Jul 19 04:49:13 PM PDT 24
Peak memory 248956 kb
Host smart-ad38f4bd-997a-4570-9c89-39016ba9aef4
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3931793418 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy_stress.3931793418
Directory /workspace/2.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/2.alert_handler_esc_alert_accum.1102236943
Short name T375
Test name
Test status
Simulation time 1295445803 ps
CPU time 93.87 seconds
Started Jul 19 04:48:32 PM PDT 24
Finished Jul 19 04:50:25 PM PDT 24
Peak memory 257152 kb
Host smart-a0f311ee-fc7a-4802-b0a6-9a2c7374b0db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11022
36943 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_alert_accum.1102236943
Directory /workspace/2.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/2.alert_handler_esc_intr_timeout.2972661392
Short name T73
Test name
Test status
Simulation time 995284728 ps
CPU time 53.08 seconds
Started Jul 19 04:48:42 PM PDT 24
Finished Jul 19 04:49:52 PM PDT 24
Peak memory 256276 kb
Host smart-b192ed4b-e841-43cf-a281-7b7efed4bb3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29726
61392 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_intr_timeout.2972661392
Directory /workspace/2.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_lpg.1618227665
Short name T322
Test name
Test status
Simulation time 534471785405 ps
CPU time 1955.91 seconds
Started Jul 19 04:48:47 PM PDT 24
Finished Jul 19 05:21:38 PM PDT 24
Peak memory 288984 kb
Host smart-379ec784-0759-48f9-acb8-5283f68709bd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618227665 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg.1618227665
Directory /workspace/2.alert_handler_lpg/latest

Test location /workspace/coverage/default/2.alert_handler_lpg_stub_clk.1266518576
Short name T397
Test name
Test status
Simulation time 90126196955 ps
CPU time 2747.78 seconds
Started Jul 19 04:48:41 PM PDT 24
Finished Jul 19 05:34:51 PM PDT 24
Peak memory 281144 kb
Host smart-d62182eb-94b3-45eb-80fb-852b34e526cc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266518576 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg_stub_clk.1266518576
Directory /workspace/2.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/2.alert_handler_random_alerts.1631888242
Short name T593
Test name
Test status
Simulation time 360124612 ps
CPU time 32.39 seconds
Started Jul 19 04:48:32 PM PDT 24
Finished Jul 19 04:49:23 PM PDT 24
Peak memory 248920 kb
Host smart-3e4239a0-1b37-464c-baae-2110c048690d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16318
88242 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_alerts.1631888242
Directory /workspace/2.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/2.alert_handler_random_classes.3564039543
Short name T24
Test name
Test status
Simulation time 413902403 ps
CPU time 13.82 seconds
Started Jul 19 04:48:34 PM PDT 24
Finished Jul 19 04:49:06 PM PDT 24
Peak memory 249312 kb
Host smart-00c178f8-d623-4b29-a976-e82417824b82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35640
39543 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_classes.3564039543
Directory /workspace/2.alert_handler_random_classes/latest

Test location /workspace/coverage/default/2.alert_handler_sec_cm.3732485330
Short name T12
Test name
Test status
Simulation time 243483488 ps
CPU time 14.13 seconds
Started Jul 19 04:48:41 PM PDT 24
Finished Jul 19 04:49:12 PM PDT 24
Peak memory 267396 kb
Host smart-8203d91b-7e8a-4966-8d79-9aadfdc7ce82
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3732485330 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sec_cm.3732485330
Directory /workspace/2.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/2.alert_handler_sig_int_fail.1444672257
Short name T285
Test name
Test status
Simulation time 668514405 ps
CPU time 22.47 seconds
Started Jul 19 04:48:33 PM PDT 24
Finished Jul 19 04:49:14 PM PDT 24
Peak memory 248912 kb
Host smart-52366ef4-106b-46db-ab04-9b7cff53f1a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14446
72257 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sig_int_fail.1444672257
Directory /workspace/2.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/2.alert_handler_smoke.1073290601
Short name T453
Test name
Test status
Simulation time 161129102 ps
CPU time 18.01 seconds
Started Jul 19 04:48:32 PM PDT 24
Finished Jul 19 04:49:08 PM PDT 24
Peak memory 256528 kb
Host smart-9635b4f8-adcd-4fb9-82fd-1fad3bf939ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10732
90601 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_smoke.1073290601
Directory /workspace/2.alert_handler_smoke/latest

Test location /workspace/coverage/default/20.alert_handler_entropy.3403591988
Short name T55
Test name
Test status
Simulation time 12188934249 ps
CPU time 586.51 seconds
Started Jul 19 04:49:13 PM PDT 24
Finished Jul 19 04:59:10 PM PDT 24
Peak memory 267548 kb
Host smart-a9cb923c-139b-4b53-bc78-3eaadc0f2c1f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403591988 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_entropy.3403591988
Directory /workspace/20.alert_handler_entropy/latest

Test location /workspace/coverage/default/20.alert_handler_esc_alert_accum.110073612
Short name T79
Test name
Test status
Simulation time 2954643081 ps
CPU time 145.62 seconds
Started Jul 19 04:49:32 PM PDT 24
Finished Jul 19 04:52:14 PM PDT 24
Peak memory 256768 kb
Host smart-2ece3d23-2f09-4930-aeb9-d1d60005886a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11007
3612 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_alert_accum.110073612
Directory /workspace/20.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/20.alert_handler_esc_intr_timeout.4210008511
Short name T697
Test name
Test status
Simulation time 732004269 ps
CPU time 20.01 seconds
Started Jul 19 04:49:17 PM PDT 24
Finished Jul 19 04:49:50 PM PDT 24
Peak memory 256676 kb
Host smart-4f476fb7-c26b-4e4d-8cb8-8482410f16ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42100
08511 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_intr_timeout.4210008511
Directory /workspace/20.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_lpg.3328265614
Short name T580
Test name
Test status
Simulation time 677003363801 ps
CPU time 2426.28 seconds
Started Jul 19 04:49:12 PM PDT 24
Finished Jul 19 05:29:50 PM PDT 24
Peak memory 288768 kb
Host smart-118db639-c5d7-4cf7-a23a-89b99fcc96b0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328265614 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg.3328265614
Directory /workspace/20.alert_handler_lpg/latest

Test location /workspace/coverage/default/20.alert_handler_lpg_stub_clk.1422984706
Short name T376
Test name
Test status
Simulation time 12843622771 ps
CPU time 1263.72 seconds
Started Jul 19 04:49:27 PM PDT 24
Finished Jul 19 05:10:45 PM PDT 24
Peak memory 289436 kb
Host smart-fa0cff5b-8c21-4997-b0a0-dfbf5074cceb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422984706 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg_stub_clk.1422984706
Directory /workspace/20.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/20.alert_handler_ping_timeout.2226382893
Short name T298
Test name
Test status
Simulation time 15014946385 ps
CPU time 166.27 seconds
Started Jul 19 04:49:28 PM PDT 24
Finished Jul 19 04:52:28 PM PDT 24
Peak memory 249016 kb
Host smart-9a442bdf-8a0e-4b6d-8c30-fffd1531db5f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226382893 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_ping_timeout.2226382893
Directory /workspace/20.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_random_alerts.1442421709
Short name T101
Test name
Test status
Simulation time 1382668083 ps
CPU time 37.57 seconds
Started Jul 19 04:49:18 PM PDT 24
Finished Jul 19 04:50:08 PM PDT 24
Peak memory 257120 kb
Host smart-86f61165-d938-4508-9c90-4783240bbe78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14424
21709 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_alerts.1442421709
Directory /workspace/20.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/20.alert_handler_random_classes.1466027034
Short name T72
Test name
Test status
Simulation time 2364040635 ps
CPU time 38.77 seconds
Started Jul 19 04:49:20 PM PDT 24
Finished Jul 19 04:50:11 PM PDT 24
Peak memory 249044 kb
Host smart-81a31a03-932f-4cda-8209-1de3afd4f4df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14660
27034 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_classes.1466027034
Directory /workspace/20.alert_handler_random_classes/latest

Test location /workspace/coverage/default/20.alert_handler_sig_int_fail.802759820
Short name T702
Test name
Test status
Simulation time 2478554814 ps
CPU time 41.54 seconds
Started Jul 19 04:49:22 PM PDT 24
Finished Jul 19 04:50:16 PM PDT 24
Peak memory 256208 kb
Host smart-83a8fd37-5f33-4667-b211-2b0c2fb53570
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80275
9820 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_sig_int_fail.802759820
Directory /workspace/20.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/20.alert_handler_smoke.2345422117
Short name T604
Test name
Test status
Simulation time 109881150 ps
CPU time 4.32 seconds
Started Jul 19 04:49:20 PM PDT 24
Finished Jul 19 04:49:35 PM PDT 24
Peak memory 251116 kb
Host smart-3f07234a-7724-4ca1-8593-239b506a8e58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23454
22117 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_smoke.2345422117
Directory /workspace/20.alert_handler_smoke/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all.3317542300
Short name T21
Test name
Test status
Simulation time 16368602217 ps
CPU time 463.1 seconds
Started Jul 19 04:49:14 PM PDT 24
Finished Jul 19 04:57:08 PM PDT 24
Peak memory 257272 kb
Host smart-97c670fc-2db7-4e1d-ba10-64b0122a6ffe
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317542300 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_ha
ndler_stress_all.3317542300
Directory /workspace/20.alert_handler_stress_all/latest

Test location /workspace/coverage/default/21.alert_handler_entropy.3153809119
Short name T518
Test name
Test status
Simulation time 78169039278 ps
CPU time 1337.5 seconds
Started Jul 19 04:49:26 PM PDT 24
Finished Jul 19 05:11:57 PM PDT 24
Peak memory 273084 kb
Host smart-23b08bd7-2652-41be-afa9-74f05e875472
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153809119 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_entropy.3153809119
Directory /workspace/21.alert_handler_entropy/latest

Test location /workspace/coverage/default/21.alert_handler_esc_alert_accum.2766110703
Short name T3
Test name
Test status
Simulation time 10428106536 ps
CPU time 167.41 seconds
Started Jul 19 04:49:30 PM PDT 24
Finished Jul 19 04:52:32 PM PDT 24
Peak memory 257224 kb
Host smart-e5e5791c-44d3-4eed-9824-c9d6ba9ab5b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27661
10703 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_alert_accum.2766110703
Directory /workspace/21.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/21.alert_handler_esc_intr_timeout.3478123902
Short name T525
Test name
Test status
Simulation time 293589317 ps
CPU time 18.97 seconds
Started Jul 19 04:49:12 PM PDT 24
Finished Jul 19 04:49:42 PM PDT 24
Peak memory 249556 kb
Host smart-74bf7695-a419-4da4-b980-031861d7008e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34781
23902 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_intr_timeout.3478123902
Directory /workspace/21.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_lpg.186151889
Short name T659
Test name
Test status
Simulation time 16106602933 ps
CPU time 1446.42 seconds
Started Jul 19 04:49:26 PM PDT 24
Finished Jul 19 05:13:46 PM PDT 24
Peak memory 289128 kb
Host smart-cd21f9c8-1f93-479d-a9d8-aa80cd0e17c4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186151889 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg.186151889
Directory /workspace/21.alert_handler_lpg/latest

Test location /workspace/coverage/default/21.alert_handler_lpg_stub_clk.504113730
Short name T248
Test name
Test status
Simulation time 117478819752 ps
CPU time 1617.08 seconds
Started Jul 19 04:49:16 PM PDT 24
Finished Jul 19 05:16:25 PM PDT 24
Peak memory 273636 kb
Host smart-1d782d04-74ad-40ae-8ba9-6d55b51196d1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504113730 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg_stub_clk.504113730
Directory /workspace/21.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/21.alert_handler_ping_timeout.2965279294
Short name T10
Test name
Test status
Simulation time 2594145054 ps
CPU time 112.76 seconds
Started Jul 19 04:49:29 PM PDT 24
Finished Jul 19 04:51:35 PM PDT 24
Peak memory 249028 kb
Host smart-7e53eda0-fc71-4941-a225-9201a871ac27
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965279294 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_ping_timeout.2965279294
Directory /workspace/21.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_random_alerts.3451738678
Short name T683
Test name
Test status
Simulation time 490888796 ps
CPU time 29.59 seconds
Started Jul 19 04:49:17 PM PDT 24
Finished Jul 19 04:49:59 PM PDT 24
Peak memory 255484 kb
Host smart-3445dbc8-9e12-4e9e-b9af-3f7470275e43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34517
38678 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_alerts.3451738678
Directory /workspace/21.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/21.alert_handler_random_classes.2233237007
Short name T56
Test name
Test status
Simulation time 1103330725 ps
CPU time 39.07 seconds
Started Jul 19 04:49:17 PM PDT 24
Finished Jul 19 04:50:09 PM PDT 24
Peak memory 248500 kb
Host smart-e3c45750-ba9d-4210-a124-034f51f6d445
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22332
37007 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_classes.2233237007
Directory /workspace/21.alert_handler_random_classes/latest

Test location /workspace/coverage/default/21.alert_handler_sig_int_fail.732052461
Short name T366
Test name
Test status
Simulation time 1010311500 ps
CPU time 20.98 seconds
Started Jul 19 04:49:28 PM PDT 24
Finished Jul 19 04:50:03 PM PDT 24
Peak memory 248852 kb
Host smart-0cfdea5a-a33c-414a-9880-aa31a9a8d4e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73205
2461 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_sig_int_fail.732052461
Directory /workspace/21.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/21.alert_handler_smoke.2776289588
Short name T493
Test name
Test status
Simulation time 524620374 ps
CPU time 31.31 seconds
Started Jul 19 04:49:22 PM PDT 24
Finished Jul 19 04:50:06 PM PDT 24
Peak memory 257312 kb
Host smart-907ab1d2-c2e6-4e22-982b-ad4d3274a6eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27762
89588 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_smoke.2776289588
Directory /workspace/21.alert_handler_smoke/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all.3675097203
Short name T467
Test name
Test status
Simulation time 26005119726 ps
CPU time 383.84 seconds
Started Jul 19 04:49:13 PM PDT 24
Finished Jul 19 04:55:48 PM PDT 24
Peak memory 257304 kb
Host smart-0ecb19ae-3ce1-4f80-8e8f-40a9e0ea81e3
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675097203 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_ha
ndler_stress_all.3675097203
Directory /workspace/21.alert_handler_stress_all/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all_with_rand_reset.3106891772
Short name T194
Test name
Test status
Simulation time 26924727043 ps
CPU time 3346.19 seconds
Started Jul 19 04:49:28 PM PDT 24
Finished Jul 19 05:45:27 PM PDT 24
Peak memory 319344 kb
Host smart-c699c604-13cd-4438-861c-21cc8c00f215
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106891772 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.alert_handler_stress_all_with_rand_reset.3106891772
Directory /workspace/21.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.alert_handler_entropy.249488621
Short name T48
Test name
Test status
Simulation time 156692092572 ps
CPU time 2608.82 seconds
Started Jul 19 04:49:14 PM PDT 24
Finished Jul 19 05:32:54 PM PDT 24
Peak memory 289192 kb
Host smart-43d22d86-3f8d-4bda-9d56-9a3f1d626719
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249488621 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_entropy.249488621
Directory /workspace/22.alert_handler_entropy/latest

Test location /workspace/coverage/default/22.alert_handler_esc_alert_accum.518191944
Short name T705
Test name
Test status
Simulation time 2581346572 ps
CPU time 105.95 seconds
Started Jul 19 04:49:22 PM PDT 24
Finished Jul 19 04:51:21 PM PDT 24
Peak memory 256448 kb
Host smart-5e948426-3ee8-4c2f-bee2-4ad4c2159ec1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51819
1944 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_alert_accum.518191944
Directory /workspace/22.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/22.alert_handler_esc_intr_timeout.2250497082
Short name T71
Test name
Test status
Simulation time 4493288372 ps
CPU time 43.05 seconds
Started Jul 19 04:49:29 PM PDT 24
Finished Jul 19 04:50:26 PM PDT 24
Peak memory 256808 kb
Host smart-448406de-9bfc-49f2-b069-33468715305e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22504
97082 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_intr_timeout.2250497082
Directory /workspace/22.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_lpg.706118733
Short name T325
Test name
Test status
Simulation time 53733842025 ps
CPU time 2822.59 seconds
Started Jul 19 04:49:13 PM PDT 24
Finished Jul 19 05:36:26 PM PDT 24
Peak memory 286400 kb
Host smart-512f680b-3eeb-4794-a655-1357c0965eb0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706118733 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg.706118733
Directory /workspace/22.alert_handler_lpg/latest

Test location /workspace/coverage/default/22.alert_handler_lpg_stub_clk.1711983694
Short name T416
Test name
Test status
Simulation time 10752193130 ps
CPU time 1069.87 seconds
Started Jul 19 04:49:23 PM PDT 24
Finished Jul 19 05:07:26 PM PDT 24
Peak memory 289148 kb
Host smart-5764f80e-1283-4cd4-87bd-7f0cafeb0c98
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711983694 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg_stub_clk.1711983694
Directory /workspace/22.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/22.alert_handler_ping_timeout.2960674292
Short name T562
Test name
Test status
Simulation time 2145822946 ps
CPU time 92.9 seconds
Started Jul 19 04:49:17 PM PDT 24
Finished Jul 19 04:51:03 PM PDT 24
Peak memory 248932 kb
Host smart-27132e5f-bd1f-45b6-b3e6-05acc5672b6e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960674292 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_ping_timeout.2960674292
Directory /workspace/22.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_random_alerts.816010204
Short name T427
Test name
Test status
Simulation time 111082838 ps
CPU time 4.36 seconds
Started Jul 19 04:49:30 PM PDT 24
Finished Jul 19 04:49:48 PM PDT 24
Peak memory 240680 kb
Host smart-f2c8761e-5280-4086-baf6-97ebbddf71d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81601
0204 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_alerts.816010204
Directory /workspace/22.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/22.alert_handler_random_classes.3378370004
Short name T475
Test name
Test status
Simulation time 737705571 ps
CPU time 48.54 seconds
Started Jul 19 04:49:13 PM PDT 24
Finished Jul 19 04:50:12 PM PDT 24
Peak memory 249168 kb
Host smart-42a529b7-bd7a-4e2b-aae0-500728561abc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33783
70004 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_classes.3378370004
Directory /workspace/22.alert_handler_random_classes/latest

Test location /workspace/coverage/default/22.alert_handler_sig_int_fail.275796507
Short name T263
Test name
Test status
Simulation time 360015252 ps
CPU time 22.2 seconds
Started Jul 19 04:49:12 PM PDT 24
Finished Jul 19 04:49:45 PM PDT 24
Peak memory 249352 kb
Host smart-75ea3357-9bf3-4405-9ef9-1e86e63ebab5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27579
6507 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_sig_int_fail.275796507
Directory /workspace/22.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/22.alert_handler_smoke.1026798798
Short name T572
Test name
Test status
Simulation time 272773713 ps
CPU time 36.8 seconds
Started Jul 19 04:49:13 PM PDT 24
Finished Jul 19 04:50:00 PM PDT 24
Peak memory 248952 kb
Host smart-c03897fa-e6e8-4e94-beac-214ffbdbbcab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10267
98798 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_smoke.1026798798
Directory /workspace/22.alert_handler_smoke/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all.540866007
Short name T523
Test name
Test status
Simulation time 60054139053 ps
CPU time 1593.31 seconds
Started Jul 19 04:49:15 PM PDT 24
Finished Jul 19 05:16:00 PM PDT 24
Peak memory 287704 kb
Host smart-036cdb53-9d84-4f18-b3c5-3b4e12eaf490
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540866007 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_han
dler_stress_all.540866007
Directory /workspace/22.alert_handler_stress_all/latest

Test location /workspace/coverage/default/23.alert_handler_entropy.764244888
Short name T482
Test name
Test status
Simulation time 15540857809 ps
CPU time 873.25 seconds
Started Jul 19 04:49:13 PM PDT 24
Finished Jul 19 05:03:57 PM PDT 24
Peak memory 273508 kb
Host smart-c5632d33-b260-4944-8758-1acab28aa91f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764244888 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_entropy.764244888
Directory /workspace/23.alert_handler_entropy/latest

Test location /workspace/coverage/default/23.alert_handler_esc_alert_accum.1014422243
Short name T531
Test name
Test status
Simulation time 4202711474 ps
CPU time 248.93 seconds
Started Jul 19 04:49:28 PM PDT 24
Finished Jul 19 04:53:51 PM PDT 24
Peak memory 256724 kb
Host smart-9c8eeaaf-edb4-43ca-96c2-ba37cd45e2f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10144
22243 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_alert_accum.1014422243
Directory /workspace/23.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/23.alert_handler_esc_intr_timeout.4130520089
Short name T620
Test name
Test status
Simulation time 653149629 ps
CPU time 20.9 seconds
Started Jul 19 04:49:32 PM PDT 24
Finished Jul 19 04:50:08 PM PDT 24
Peak memory 248544 kb
Host smart-34574cd2-700d-4e72-8be8-d707b0e45a6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41305
20089 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_intr_timeout.4130520089
Directory /workspace/23.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_lpg.3848161569
Short name T324
Test name
Test status
Simulation time 233216604760 ps
CPU time 2959.92 seconds
Started Jul 19 04:49:12 PM PDT 24
Finished Jul 19 05:38:44 PM PDT 24
Peak memory 289788 kb
Host smart-14d3c83f-163b-4273-b0f4-eef9b7da2a7c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848161569 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg.3848161569
Directory /workspace/23.alert_handler_lpg/latest

Test location /workspace/coverage/default/23.alert_handler_lpg_stub_clk.785350680
Short name T597
Test name
Test status
Simulation time 41098667446 ps
CPU time 911.35 seconds
Started Jul 19 04:49:15 PM PDT 24
Finished Jul 19 05:04:39 PM PDT 24
Peak memory 285664 kb
Host smart-c8972b28-2f64-480e-a32a-729c62fb6999
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785350680 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg_stub_clk.785350680
Directory /workspace/23.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/23.alert_handler_ping_timeout.3526243520
Short name T479
Test name
Test status
Simulation time 3935159832 ps
CPU time 155.93 seconds
Started Jul 19 04:49:20 PM PDT 24
Finished Jul 19 04:52:08 PM PDT 24
Peak memory 255392 kb
Host smart-e8b61b3a-3cf7-4b2e-a71d-3c7468b57e98
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526243520 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_ping_timeout.3526243520
Directory /workspace/23.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_random_alerts.2341981622
Short name T351
Test name
Test status
Simulation time 360087596 ps
CPU time 17.99 seconds
Started Jul 19 04:49:11 PM PDT 24
Finished Jul 19 04:49:39 PM PDT 24
Peak memory 256624 kb
Host smart-5b3ae686-6d98-4870-9ed9-2411ce9b0bb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23419
81622 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_alerts.2341981622
Directory /workspace/23.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/23.alert_handler_random_classes.1757618366
Short name T671
Test name
Test status
Simulation time 487126732 ps
CPU time 24.45 seconds
Started Jul 19 04:49:19 PM PDT 24
Finished Jul 19 04:49:55 PM PDT 24
Peak memory 248540 kb
Host smart-2098551d-3872-4cf4-b2f7-0a92ee153f4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17576
18366 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_classes.1757618366
Directory /workspace/23.alert_handler_random_classes/latest

Test location /workspace/coverage/default/23.alert_handler_sig_int_fail.2138826121
Short name T119
Test name
Test status
Simulation time 1137606726 ps
CPU time 41.93 seconds
Started Jul 19 04:49:16 PM PDT 24
Finished Jul 19 04:50:10 PM PDT 24
Peak memory 256864 kb
Host smart-27d12e67-3eb1-4ee4-a0a5-8a034eddfdca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21388
26121 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_sig_int_fail.2138826121
Directory /workspace/23.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/23.alert_handler_smoke.2210585210
Short name T370
Test name
Test status
Simulation time 902652212 ps
CPU time 19.41 seconds
Started Jul 19 04:49:28 PM PDT 24
Finished Jul 19 04:50:02 PM PDT 24
Peak memory 248820 kb
Host smart-8ba35bf7-55ac-48e7-ab72-df896df9b975
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22105
85210 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_smoke.2210585210
Directory /workspace/23.alert_handler_smoke/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all.2699017616
Short name T521
Test name
Test status
Simulation time 42557303395 ps
CPU time 1665.36 seconds
Started Jul 19 04:49:27 PM PDT 24
Finished Jul 19 05:17:26 PM PDT 24
Peak memory 300116 kb
Host smart-1916bdcb-4e35-4b4f-9de5-5ef5ce3f1d5f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699017616 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_ha
ndler_stress_all.2699017616
Directory /workspace/23.alert_handler_stress_all/latest

Test location /workspace/coverage/default/24.alert_handler_entropy.2748711587
Short name T281
Test name
Test status
Simulation time 18940098098 ps
CPU time 1246.88 seconds
Started Jul 19 04:49:24 PM PDT 24
Finished Jul 19 05:10:24 PM PDT 24
Peak memory 273116 kb
Host smart-2657042d-2e55-490d-a992-6abe1d8f0dbc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748711587 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_entropy.2748711587
Directory /workspace/24.alert_handler_entropy/latest

Test location /workspace/coverage/default/24.alert_handler_esc_alert_accum.3367589955
Short name T658
Test name
Test status
Simulation time 9021849996 ps
CPU time 147.64 seconds
Started Jul 19 04:49:29 PM PDT 24
Finished Jul 19 04:52:11 PM PDT 24
Peak memory 257264 kb
Host smart-8b6a9743-c407-45ac-8684-66af1778eb45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33675
89955 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_alert_accum.3367589955
Directory /workspace/24.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/24.alert_handler_esc_intr_timeout.1068191282
Short name T368
Test name
Test status
Simulation time 243967497 ps
CPU time 25.88 seconds
Started Jul 19 04:49:25 PM PDT 24
Finished Jul 19 04:50:04 PM PDT 24
Peak memory 255740 kb
Host smart-9ca74ec8-7774-4938-b508-50c64be7dc8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10681
91282 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_intr_timeout.1068191282
Directory /workspace/24.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_lpg.581615525
Short name T320
Test name
Test status
Simulation time 22299220075 ps
CPU time 1380.9 seconds
Started Jul 19 04:49:34 PM PDT 24
Finished Jul 19 05:12:51 PM PDT 24
Peak memory 273588 kb
Host smart-6d86cb6d-9300-4012-b879-4720194fe8d6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=581615525 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg.581615525
Directory /workspace/24.alert_handler_lpg/latest

Test location /workspace/coverage/default/24.alert_handler_lpg_stub_clk.1037302743
Short name T624
Test name
Test status
Simulation time 52861392319 ps
CPU time 3123.36 seconds
Started Jul 19 04:49:19 PM PDT 24
Finished Jul 19 05:41:34 PM PDT 24
Peak memory 289952 kb
Host smart-50b0391a-752f-4398-9374-4cca1063efac
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037302743 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg_stub_clk.1037302743
Directory /workspace/24.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/24.alert_handler_ping_timeout.1555078524
Short name T640
Test name
Test status
Simulation time 21920831198 ps
CPU time 471.6 seconds
Started Jul 19 04:49:29 PM PDT 24
Finished Jul 19 04:57:34 PM PDT 24
Peak memory 248276 kb
Host smart-d3786b00-c392-489b-b6e4-e1f5162d0219
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1555078524 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_ping_timeout.1555078524
Directory /workspace/24.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_random_alerts.3066387617
Short name T367
Test name
Test status
Simulation time 843948759 ps
CPU time 22.22 seconds
Started Jul 19 04:49:21 PM PDT 24
Finished Jul 19 04:49:55 PM PDT 24
Peak memory 256320 kb
Host smart-b4292481-424c-433c-aeba-94683d25e436
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30663
87617 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_alerts.3066387617
Directory /workspace/24.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/24.alert_handler_random_classes.3040563073
Short name T269
Test name
Test status
Simulation time 675563981 ps
CPU time 12.57 seconds
Started Jul 19 04:49:30 PM PDT 24
Finished Jul 19 04:49:56 PM PDT 24
Peak memory 248244 kb
Host smart-11bdbf26-5949-4460-8c7c-703e90f1024d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30405
63073 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_classes.3040563073
Directory /workspace/24.alert_handler_random_classes/latest

Test location /workspace/coverage/default/24.alert_handler_sig_int_fail.1369147037
Short name T258
Test name
Test status
Simulation time 470446533 ps
CPU time 9.54 seconds
Started Jul 19 04:49:32 PM PDT 24
Finished Jul 19 04:49:58 PM PDT 24
Peak memory 248304 kb
Host smart-5567c490-4822-4615-bf1f-8c6b82a40d30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13691
47037 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_sig_int_fail.1369147037
Directory /workspace/24.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/24.alert_handler_smoke.1430871551
Short name T408
Test name
Test status
Simulation time 274038395 ps
CPU time 22.62 seconds
Started Jul 19 04:49:30 PM PDT 24
Finished Jul 19 04:50:07 PM PDT 24
Peak memory 256216 kb
Host smart-b997d1bd-9b04-406b-a6b9-8615d6f73a42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14308
71551 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_smoke.1430871551
Directory /workspace/24.alert_handler_smoke/latest

Test location /workspace/coverage/default/25.alert_handler_entropy.2467261941
Short name T448
Test name
Test status
Simulation time 53071997863 ps
CPU time 1603.28 seconds
Started Jul 19 04:49:37 PM PDT 24
Finished Jul 19 05:16:35 PM PDT 24
Peak memory 273596 kb
Host smart-095c7763-ebfe-4160-9e4a-488c25d36da8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2467261941 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_entropy.2467261941
Directory /workspace/25.alert_handler_entropy/latest

Test location /workspace/coverage/default/25.alert_handler_esc_alert_accum.1745847627
Short name T549
Test name
Test status
Simulation time 8880992834 ps
CPU time 134.76 seconds
Started Jul 19 04:49:37 PM PDT 24
Finished Jul 19 04:52:07 PM PDT 24
Peak memory 257256 kb
Host smart-ad710b7e-73ef-4a5f-94ae-9b2ccd8d44d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17458
47627 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_alert_accum.1745847627
Directory /workspace/25.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/25.alert_handler_esc_intr_timeout.676293059
Short name T651
Test name
Test status
Simulation time 788353540 ps
CPU time 46.87 seconds
Started Jul 19 04:49:36 PM PDT 24
Finished Jul 19 04:50:38 PM PDT 24
Peak memory 256644 kb
Host smart-ff5a28f0-362a-4ff2-9bb5-7092304caa2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67629
3059 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_intr_timeout.676293059
Directory /workspace/25.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_lpg.2378379188
Short name T586
Test name
Test status
Simulation time 55404768143 ps
CPU time 2956.47 seconds
Started Jul 19 04:49:26 PM PDT 24
Finished Jul 19 05:38:57 PM PDT 24
Peak memory 289368 kb
Host smart-d1a436bb-4d31-4b98-b2fe-d8a376712811
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2378379188 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg.2378379188
Directory /workspace/25.alert_handler_lpg/latest

Test location /workspace/coverage/default/25.alert_handler_lpg_stub_clk.4138342473
Short name T474
Test name
Test status
Simulation time 24617915637 ps
CPU time 1504.65 seconds
Started Jul 19 04:49:22 PM PDT 24
Finished Jul 19 05:14:39 PM PDT 24
Peak memory 273588 kb
Host smart-edad3474-ffb9-4130-9457-9567a81904e2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138342473 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg_stub_clk.4138342473
Directory /workspace/25.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/25.alert_handler_ping_timeout.2513734587
Short name T271
Test name
Test status
Simulation time 2318529692 ps
CPU time 103.23 seconds
Started Jul 19 04:49:31 PM PDT 24
Finished Jul 19 04:51:28 PM PDT 24
Peak memory 249016 kb
Host smart-3826af99-6267-4c7a-8a05-c4e7893f910f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2513734587 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_ping_timeout.2513734587
Directory /workspace/25.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_random_alerts.454714970
Short name T222
Test name
Test status
Simulation time 607080413 ps
CPU time 37.1 seconds
Started Jul 19 04:49:28 PM PDT 24
Finished Jul 19 04:50:20 PM PDT 24
Peak memory 256312 kb
Host smart-6b1771e8-d0fb-4dcd-a8f4-3912b406e276
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45471
4970 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_alerts.454714970
Directory /workspace/25.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/25.alert_handler_random_classes.2244456358
Short name T116
Test name
Test status
Simulation time 809426227 ps
CPU time 44.11 seconds
Started Jul 19 04:49:20 PM PDT 24
Finished Jul 19 04:50:15 PM PDT 24
Peak memory 248520 kb
Host smart-88942e5b-2bfa-44d3-8f8d-73f2bf127083
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22444
56358 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_classes.2244456358
Directory /workspace/25.alert_handler_random_classes/latest

Test location /workspace/coverage/default/25.alert_handler_sig_int_fail.240490954
Short name T400
Test name
Test status
Simulation time 174793254 ps
CPU time 20.35 seconds
Started Jul 19 04:49:30 PM PDT 24
Finished Jul 19 04:50:05 PM PDT 24
Peak memory 256464 kb
Host smart-516ea9d5-5daa-425d-921c-42ed8bf566f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24049
0954 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_sig_int_fail.240490954
Directory /workspace/25.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/25.alert_handler_smoke.2191698868
Short name T224
Test name
Test status
Simulation time 44021848 ps
CPU time 4.05 seconds
Started Jul 19 04:49:28 PM PDT 24
Finished Jul 19 04:49:46 PM PDT 24
Peak memory 249160 kb
Host smart-56dad60e-aa72-4bd3-a8d3-ff452c8515ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21916
98868 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_smoke.2191698868
Directory /workspace/25.alert_handler_smoke/latest

Test location /workspace/coverage/default/26.alert_handler_entropy.2516653064
Short name T374
Test name
Test status
Simulation time 59842184901 ps
CPU time 1785.15 seconds
Started Jul 19 04:49:40 PM PDT 24
Finished Jul 19 05:19:39 PM PDT 24
Peak memory 288868 kb
Host smart-2e3df0a7-035f-499d-aef0-9b86914e0d00
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516653064 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_entropy.2516653064
Directory /workspace/26.alert_handler_entropy/latest

Test location /workspace/coverage/default/26.alert_handler_esc_alert_accum.3611733343
Short name T249
Test name
Test status
Simulation time 1115136799 ps
CPU time 61.74 seconds
Started Jul 19 04:49:38 PM PDT 24
Finished Jul 19 04:50:54 PM PDT 24
Peak memory 256644 kb
Host smart-e67ce51f-24ed-43b8-bf62-3e4ae7d27ad2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36117
33343 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_alert_accum.3611733343
Directory /workspace/26.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/26.alert_handler_esc_intr_timeout.1738683157
Short name T670
Test name
Test status
Simulation time 1131199021 ps
CPU time 64.33 seconds
Started Jul 19 04:49:32 PM PDT 24
Finished Jul 19 04:50:52 PM PDT 24
Peak memory 248992 kb
Host smart-27f8476f-69c4-44d8-b446-3a728371d482
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17386
83157 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_intr_timeout.1738683157
Directory /workspace/26.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_lpg_stub_clk.229061737
Short name T499
Test name
Test status
Simulation time 49882477863 ps
CPU time 2810.71 seconds
Started Jul 19 04:49:32 PM PDT 24
Finished Jul 19 05:36:39 PM PDT 24
Peak memory 281532 kb
Host smart-08de7590-edbe-4af8-8bec-76d87daaf1ba
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229061737 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg_stub_clk.229061737
Directory /workspace/26.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/26.alert_handler_ping_timeout.401937285
Short name T202
Test name
Test status
Simulation time 18010167478 ps
CPU time 174.27 seconds
Started Jul 19 04:49:35 PM PDT 24
Finished Jul 19 04:52:44 PM PDT 24
Peak memory 248748 kb
Host smart-ee6a2ea1-a701-4294-99fe-b40142e37895
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401937285 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_ping_timeout.401937285
Directory /workspace/26.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_random_alerts.364655198
Short name T579
Test name
Test status
Simulation time 185872033 ps
CPU time 18.03 seconds
Started Jul 19 04:49:21 PM PDT 24
Finished Jul 19 04:49:52 PM PDT 24
Peak memory 256488 kb
Host smart-9a0d4931-e4fc-47eb-bf5a-2e1bd904cb87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36465
5198 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_alerts.364655198
Directory /workspace/26.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/26.alert_handler_random_classes.2047622342
Short name T543
Test name
Test status
Simulation time 293968922 ps
CPU time 25.76 seconds
Started Jul 19 04:49:33 PM PDT 24
Finished Jul 19 04:50:15 PM PDT 24
Peak memory 248884 kb
Host smart-e3366158-4d7d-4b08-b362-f3d70dc9478d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20476
22342 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_classes.2047622342
Directory /workspace/26.alert_handler_random_classes/latest

Test location /workspace/coverage/default/26.alert_handler_smoke.3600928496
Short name T420
Test name
Test status
Simulation time 4062485981 ps
CPU time 17.81 seconds
Started Jul 19 04:49:22 PM PDT 24
Finished Jul 19 04:49:52 PM PDT 24
Peak memory 255108 kb
Host smart-95c662a9-494e-429d-9b03-a2f2fb51f12a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36009
28496 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_smoke.3600928496
Directory /workspace/26.alert_handler_smoke/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all.1828886527
Short name T19
Test name
Test status
Simulation time 30010602785 ps
CPU time 205.78 seconds
Started Jul 19 04:49:20 PM PDT 24
Finished Jul 19 04:52:57 PM PDT 24
Peak memory 252668 kb
Host smart-76c38d8d-fd84-47eb-aa8a-1771f90b871f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828886527 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_ha
ndler_stress_all.1828886527
Directory /workspace/26.alert_handler_stress_all/latest

Test location /workspace/coverage/default/27.alert_handler_entropy.3590802475
Short name T240
Test name
Test status
Simulation time 235712860954 ps
CPU time 2494.29 seconds
Started Jul 19 04:49:36 PM PDT 24
Finished Jul 19 05:31:26 PM PDT 24
Peak memory 281724 kb
Host smart-23ea8612-9945-4cc1-908e-c9aabe8349db
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590802475 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_entropy.3590802475
Directory /workspace/27.alert_handler_entropy/latest

Test location /workspace/coverage/default/27.alert_handler_esc_alert_accum.1155266037
Short name T602
Test name
Test status
Simulation time 405733197 ps
CPU time 26.3 seconds
Started Jul 19 04:49:20 PM PDT 24
Finished Jul 19 04:49:57 PM PDT 24
Peak memory 248760 kb
Host smart-3c4c3b55-1275-420f-942f-e90aff78e5ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11552
66037 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_alert_accum.1155266037
Directory /workspace/27.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/27.alert_handler_esc_intr_timeout.3795587855
Short name T514
Test name
Test status
Simulation time 1124599530 ps
CPU time 20.16 seconds
Started Jul 19 04:49:21 PM PDT 24
Finished Jul 19 04:49:53 PM PDT 24
Peak memory 255356 kb
Host smart-cf9a25d0-87f8-4b0f-9584-dc774e43fef8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37955
87855 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_intr_timeout.3795587855
Directory /workspace/27.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_lpg.3115153602
Short name T643
Test name
Test status
Simulation time 14701494771 ps
CPU time 1337.47 seconds
Started Jul 19 04:49:20 PM PDT 24
Finished Jul 19 05:11:49 PM PDT 24
Peak memory 289912 kb
Host smart-31a807d1-407d-4cb9-a87e-d2e1d72004b2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3115153602 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg.3115153602
Directory /workspace/27.alert_handler_lpg/latest

Test location /workspace/coverage/default/27.alert_handler_lpg_stub_clk.1756298838
Short name T464
Test name
Test status
Simulation time 27949695180 ps
CPU time 1817.48 seconds
Started Jul 19 04:49:35 PM PDT 24
Finished Jul 19 05:20:08 PM PDT 24
Peak memory 283480 kb
Host smart-e5679d6a-ba7f-41b7-83cb-342f36a015c0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756298838 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg_stub_clk.1756298838
Directory /workspace/27.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/27.alert_handler_ping_timeout.125166861
Short name T617
Test name
Test status
Simulation time 3241763453 ps
CPU time 119.71 seconds
Started Jul 19 04:49:21 PM PDT 24
Finished Jul 19 04:51:32 PM PDT 24
Peak memory 248924 kb
Host smart-826bccfa-ec24-43fd-8200-5a6b30feb103
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=125166861 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_ping_timeout.125166861
Directory /workspace/27.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_random_alerts.3246111346
Short name T389
Test name
Test status
Simulation time 911490564 ps
CPU time 59.05 seconds
Started Jul 19 04:49:38 PM PDT 24
Finished Jul 19 04:50:51 PM PDT 24
Peak memory 248872 kb
Host smart-b29ec90a-ce3d-47c5-b1ca-5d6186bcb29d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32461
11346 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_alerts.3246111346
Directory /workspace/27.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/27.alert_handler_random_classes.4084605488
Short name T28
Test name
Test status
Simulation time 955641509 ps
CPU time 55.93 seconds
Started Jul 19 04:49:29 PM PDT 24
Finished Jul 19 04:50:39 PM PDT 24
Peak memory 257116 kb
Host smart-3f69d464-9c65-42aa-95f7-d12dd30e98d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40846
05488 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_classes.4084605488
Directory /workspace/27.alert_handler_random_classes/latest

Test location /workspace/coverage/default/27.alert_handler_sig_int_fail.3090536001
Short name T360
Test name
Test status
Simulation time 803752671 ps
CPU time 53.87 seconds
Started Jul 19 04:49:21 PM PDT 24
Finished Jul 19 04:50:28 PM PDT 24
Peak memory 249932 kb
Host smart-7d39b5a2-2314-45ba-9d8b-ecbdcb41c4ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30905
36001 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_sig_int_fail.3090536001
Directory /workspace/27.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/27.alert_handler_smoke.3991538920
Short name T601
Test name
Test status
Simulation time 1018334641 ps
CPU time 21.25 seconds
Started Jul 19 04:49:37 PM PDT 24
Finished Jul 19 04:50:13 PM PDT 24
Peak memory 256144 kb
Host smart-3fbd315a-e5b1-45fe-9de6-762687f12276
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39915
38920 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_smoke.3991538920
Directory /workspace/27.alert_handler_smoke/latest

Test location /workspace/coverage/default/28.alert_handler_entropy.44567405
Short name T268
Test name
Test status
Simulation time 65631058906 ps
CPU time 1552.01 seconds
Started Jul 19 04:49:22 PM PDT 24
Finished Jul 19 05:15:27 PM PDT 24
Peak memory 289376 kb
Host smart-3ada058e-5623-4b96-bec1-0d87b7ed1691
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44567405 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_entropy.44567405
Directory /workspace/28.alert_handler_entropy/latest

Test location /workspace/coverage/default/28.alert_handler_esc_alert_accum.1565033853
Short name T663
Test name
Test status
Simulation time 401157993 ps
CPU time 36.1 seconds
Started Jul 19 04:49:21 PM PDT 24
Finished Jul 19 04:50:09 PM PDT 24
Peak memory 256668 kb
Host smart-0a38015f-28af-4ab6-b93c-ddece57b2e14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15650
33853 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_alert_accum.1565033853
Directory /workspace/28.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/28.alert_handler_esc_intr_timeout.2559181935
Short name T459
Test name
Test status
Simulation time 425762858 ps
CPU time 29.57 seconds
Started Jul 19 04:49:22 PM PDT 24
Finished Jul 19 04:50:04 PM PDT 24
Peak memory 257112 kb
Host smart-acbae971-4009-4dee-9c37-46c83b6ce510
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25591
81935 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_intr_timeout.2559181935
Directory /workspace/28.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_lpg_stub_clk.3291509288
Short name T550
Test name
Test status
Simulation time 53641642597 ps
CPU time 1611.54 seconds
Started Jul 19 04:49:32 PM PDT 24
Finished Jul 19 05:16:39 PM PDT 24
Peak memory 273412 kb
Host smart-52e80e56-c680-45f6-afa2-8c406dcd8244
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291509288 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg_stub_clk.3291509288
Directory /workspace/28.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/28.alert_handler_ping_timeout.3448541904
Short name T405
Test name
Test status
Simulation time 9514368860 ps
CPU time 108.24 seconds
Started Jul 19 04:49:36 PM PDT 24
Finished Jul 19 04:51:40 PM PDT 24
Peak memory 248972 kb
Host smart-e9772252-6b44-4ac2-90b9-63d4558b4f42
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448541904 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_ping_timeout.3448541904
Directory /workspace/28.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_random_alerts.2782974794
Short name T380
Test name
Test status
Simulation time 836897938 ps
CPU time 42.19 seconds
Started Jul 19 04:49:22 PM PDT 24
Finished Jul 19 04:50:17 PM PDT 24
Peak memory 256272 kb
Host smart-542e18d1-6b59-4f51-ac6c-00654e50260a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27829
74794 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_alerts.2782974794
Directory /workspace/28.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/28.alert_handler_random_classes.4231903352
Short name T496
Test name
Test status
Simulation time 431681950 ps
CPU time 12.88 seconds
Started Jul 19 04:49:22 PM PDT 24
Finished Jul 19 04:49:48 PM PDT 24
Peak memory 256240 kb
Host smart-4c940d23-4e2d-4589-a8ef-77ce487dbd9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42319
03352 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_classes.4231903352
Directory /workspace/28.alert_handler_random_classes/latest

Test location /workspace/coverage/default/28.alert_handler_smoke.1361535792
Short name T639
Test name
Test status
Simulation time 105336991 ps
CPU time 10.93 seconds
Started Jul 19 04:49:19 PM PDT 24
Finished Jul 19 04:49:42 PM PDT 24
Peak memory 256064 kb
Host smart-f15f0013-3e08-41ce-bc15-32a405740cea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13615
35792 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_smoke.1361535792
Directory /workspace/28.alert_handler_smoke/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all.2920916759
Short name T468
Test name
Test status
Simulation time 20725054027 ps
CPU time 1571.79 seconds
Started Jul 19 04:49:21 PM PDT 24
Finished Jul 19 05:15:45 PM PDT 24
Peak memory 289732 kb
Host smart-b7766080-525d-40a3-8f9b-77c5231b72c4
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920916759 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_ha
ndler_stress_all.2920916759
Directory /workspace/28.alert_handler_stress_all/latest

Test location /workspace/coverage/default/29.alert_handler_entropy.3621729116
Short name T509
Test name
Test status
Simulation time 371840242115 ps
CPU time 2528.87 seconds
Started Jul 19 04:49:25 PM PDT 24
Finished Jul 19 05:31:47 PM PDT 24
Peak memory 289268 kb
Host smart-ba455b63-8be5-4118-9458-bb704abc23ff
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621729116 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_entropy.3621729116
Directory /workspace/29.alert_handler_entropy/latest

Test location /workspace/coverage/default/29.alert_handler_esc_alert_accum.3039814635
Short name T423
Test name
Test status
Simulation time 11348031730 ps
CPU time 187.3 seconds
Started Jul 19 04:49:39 PM PDT 24
Finished Jul 19 04:53:01 PM PDT 24
Peak memory 257160 kb
Host smart-c12f2211-f07f-47e3-a6c1-168df8ad609c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30398
14635 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_alert_accum.3039814635
Directory /workspace/29.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/29.alert_handler_esc_intr_timeout.2027255665
Short name T470
Test name
Test status
Simulation time 1626639479 ps
CPU time 27.47 seconds
Started Jul 19 04:49:24 PM PDT 24
Finished Jul 19 04:50:04 PM PDT 24
Peak memory 256224 kb
Host smart-ce87da6d-39c6-4943-b618-fca28aa7e2b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20272
55665 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_intr_timeout.2027255665
Directory /workspace/29.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_lpg.2801899471
Short name T333
Test name
Test status
Simulation time 102278937597 ps
CPU time 1421.75 seconds
Started Jul 19 04:49:41 PM PDT 24
Finished Jul 19 05:13:36 PM PDT 24
Peak memory 288592 kb
Host smart-ce39b4dc-0790-4a43-99a6-2cb008611e17
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2801899471 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg.2801899471
Directory /workspace/29.alert_handler_lpg/latest

Test location /workspace/coverage/default/29.alert_handler_lpg_stub_clk.3543321971
Short name T363
Test name
Test status
Simulation time 88756726736 ps
CPU time 1156.51 seconds
Started Jul 19 04:49:21 PM PDT 24
Finished Jul 19 05:08:51 PM PDT 24
Peak memory 272228 kb
Host smart-3dc14e0f-97be-4faa-88f9-19ff90814729
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543321971 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg_stub_clk.3543321971
Directory /workspace/29.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/29.alert_handler_ping_timeout.692211661
Short name T305
Test name
Test status
Simulation time 4876213169 ps
CPU time 200.89 seconds
Started Jul 19 04:49:29 PM PDT 24
Finished Jul 19 04:53:04 PM PDT 24
Peak memory 249012 kb
Host smart-622999d7-a7f2-4192-bb99-477bc57c2d5f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692211661 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_ping_timeout.692211661
Directory /workspace/29.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_random_alerts.3171635206
Short name T445
Test name
Test status
Simulation time 549148568 ps
CPU time 20.61 seconds
Started Jul 19 04:49:23 PM PDT 24
Finished Jul 19 04:49:56 PM PDT 24
Peak memory 248992 kb
Host smart-699836e2-ec82-49ee-9b72-519c697ec717
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31716
35206 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_alerts.3171635206
Directory /workspace/29.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/29.alert_handler_random_classes.2498740445
Short name T537
Test name
Test status
Simulation time 3093927720 ps
CPU time 45.7 seconds
Started Jul 19 04:49:41 PM PDT 24
Finished Jul 19 04:50:40 PM PDT 24
Peak memory 248848 kb
Host smart-1c182a97-f3b3-4a77-87b1-3325161a91aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24987
40445 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_classes.2498740445
Directory /workspace/29.alert_handler_random_classes/latest

Test location /workspace/coverage/default/29.alert_handler_sig_int_fail.1087429832
Short name T646
Test name
Test status
Simulation time 891023508 ps
CPU time 23.89 seconds
Started Jul 19 04:49:24 PM PDT 24
Finished Jul 19 04:50:00 PM PDT 24
Peak memory 256328 kb
Host smart-da19803a-2040-40de-a69d-b4be0ca2e5ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10874
29832 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_sig_int_fail.1087429832
Directory /workspace/29.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/29.alert_handler_smoke.1106150128
Short name T418
Test name
Test status
Simulation time 722544867 ps
CPU time 43.76 seconds
Started Jul 19 04:49:23 PM PDT 24
Finished Jul 19 04:50:19 PM PDT 24
Peak memory 257060 kb
Host smart-1d8b8dcd-f989-44c4-9a52-5d8547dc1010
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11061
50128 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_smoke.1106150128
Directory /workspace/29.alert_handler_smoke/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all.416813995
Short name T49
Test name
Test status
Simulation time 45378507968 ps
CPU time 639.36 seconds
Started Jul 19 04:49:25 PM PDT 24
Finished Jul 19 05:00:18 PM PDT 24
Peak memory 273064 kb
Host smart-1859929d-bb2e-4bef-857a-45c51ecd2f61
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416813995 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_han
dler_stress_all.416813995
Directory /workspace/29.alert_handler_stress_all/latest

Test location /workspace/coverage/default/3.alert_handler_alert_accum_saturation.1801568455
Short name T203
Test name
Test status
Simulation time 18290429 ps
CPU time 2.81 seconds
Started Jul 19 04:48:42 PM PDT 24
Finished Jul 19 04:49:01 PM PDT 24
Peak memory 249160 kb
Host smart-c690a46a-6fa9-4eec-846d-68ecec5e4e4c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1801568455 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_alert_accum_saturation.1801568455
Directory /workspace/3.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/3.alert_handler_entropy.4056187601
Short name T66
Test name
Test status
Simulation time 36236860285 ps
CPU time 2164.85 seconds
Started Jul 19 04:48:41 PM PDT 24
Finished Jul 19 05:25:03 PM PDT 24
Peak memory 289880 kb
Host smart-f845c977-0b58-440c-a9ec-a231e604fdbc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4056187601 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy.4056187601
Directory /workspace/3.alert_handler_entropy/latest

Test location /workspace/coverage/default/3.alert_handler_entropy_stress.1306619154
Short name T515
Test name
Test status
Simulation time 2492750435 ps
CPU time 11.05 seconds
Started Jul 19 04:48:43 PM PDT 24
Finished Jul 19 04:49:11 PM PDT 24
Peak memory 248964 kb
Host smart-9110a038-5f9c-4ddb-bcc2-ff99c6c050ab
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1306619154 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy_stress.1306619154
Directory /workspace/3.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/3.alert_handler_esc_alert_accum.4045781567
Short name T442
Test name
Test status
Simulation time 14510670214 ps
CPU time 195.52 seconds
Started Jul 19 04:48:45 PM PDT 24
Finished Jul 19 04:52:17 PM PDT 24
Peak memory 257216 kb
Host smart-525d4fb1-b74b-40dd-8f78-c32283f03330
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40457
81567 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_alert_accum.4045781567
Directory /workspace/3.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/3.alert_handler_esc_intr_timeout.1791611095
Short name T581
Test name
Test status
Simulation time 240874111 ps
CPU time 8.27 seconds
Started Jul 19 04:48:35 PM PDT 24
Finished Jul 19 04:49:02 PM PDT 24
Peak memory 251824 kb
Host smart-ea8e9caa-4a88-4bab-8e04-7c3008e53b6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17916
11095 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_intr_timeout.1791611095
Directory /workspace/3.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_lpg.3188687213
Short name T259
Test name
Test status
Simulation time 169016041784 ps
CPU time 1052.67 seconds
Started Jul 19 04:48:41 PM PDT 24
Finished Jul 19 05:06:31 PM PDT 24
Peak memory 272936 kb
Host smart-3fc174a6-6d72-4b53-a4e5-df4858b3b6a2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188687213 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg.3188687213
Directory /workspace/3.alert_handler_lpg/latest

Test location /workspace/coverage/default/3.alert_handler_lpg_stub_clk.3144520234
Short name T35
Test name
Test status
Simulation time 39125434571 ps
CPU time 2358.25 seconds
Started Jul 19 04:48:47 PM PDT 24
Finished Jul 19 05:28:21 PM PDT 24
Peak memory 289384 kb
Host smart-0ba8ae30-83ef-4424-a470-bacef49651d0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3144520234 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg_stub_clk.3144520234
Directory /workspace/3.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/3.alert_handler_ping_timeout.1490583343
Short name T310
Test name
Test status
Simulation time 142158894998 ps
CPU time 516.81 seconds
Started Jul 19 04:48:47 PM PDT 24
Finished Jul 19 04:57:39 PM PDT 24
Peak memory 256240 kb
Host smart-edc94dad-f1e8-4060-ba8a-be57941ded54
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490583343 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_ping_timeout.1490583343
Directory /workspace/3.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_random_alerts.2811253748
Short name T630
Test name
Test status
Simulation time 3128943367 ps
CPU time 53.87 seconds
Started Jul 19 04:48:45 PM PDT 24
Finished Jul 19 04:49:55 PM PDT 24
Peak memory 256840 kb
Host smart-623e5b80-8e75-4e33-a052-ea6773b481ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28112
53748 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_alerts.2811253748
Directory /workspace/3.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/3.alert_handler_random_classes.2633690518
Short name T469
Test name
Test status
Simulation time 2683467304 ps
CPU time 39.82 seconds
Started Jul 19 04:48:53 PM PDT 24
Finished Jul 19 04:49:47 PM PDT 24
Peak memory 249340 kb
Host smart-b4ed5976-ca0c-474d-9de3-2f4d2569ba4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26336
90518 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_classes.2633690518
Directory /workspace/3.alert_handler_random_classes/latest

Test location /workspace/coverage/default/3.alert_handler_sec_cm.2319378260
Short name T13
Test name
Test status
Simulation time 430134065 ps
CPU time 21.73 seconds
Started Jul 19 04:48:56 PM PDT 24
Finished Jul 19 04:49:31 PM PDT 24
Peak memory 267416 kb
Host smart-de6e2592-209a-4696-a976-358ec95f4b2e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2319378260 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sec_cm.2319378260
Directory /workspace/3.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/3.alert_handler_sig_int_fail.948019518
Short name T527
Test name
Test status
Simulation time 734291928 ps
CPU time 50.53 seconds
Started Jul 19 04:48:38 PM PDT 24
Finished Jul 19 04:49:46 PM PDT 24
Peak memory 256684 kb
Host smart-eed68bb8-1ffa-43e8-a0a4-b56bbb4c8337
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94801
9518 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sig_int_fail.948019518
Directory /workspace/3.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/3.alert_handler_smoke.2847113116
Short name T618
Test name
Test status
Simulation time 373173124 ps
CPU time 16.99 seconds
Started Jul 19 04:48:37 PM PDT 24
Finished Jul 19 04:49:12 PM PDT 24
Peak memory 256968 kb
Host smart-d642b009-25cd-48f6-98b6-fd058336bc1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28471
13116 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_smoke.2847113116
Directory /workspace/3.alert_handler_smoke/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all.1051984148
Short name T98
Test name
Test status
Simulation time 76914404831 ps
CPU time 3741.61 seconds
Started Jul 19 04:49:16 PM PDT 24
Finished Jul 19 05:51:49 PM PDT 24
Peak memory 305608 kb
Host smart-419ba38b-5d85-45a5-88d5-7b0aa3a06b35
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051984148 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_han
dler_stress_all.1051984148
Directory /workspace/3.alert_handler_stress_all/latest

Test location /workspace/coverage/default/30.alert_handler_entropy.201586109
Short name T691
Test name
Test status
Simulation time 116848809036 ps
CPU time 1579.54 seconds
Started Jul 19 04:49:29 PM PDT 24
Finished Jul 19 05:16:02 PM PDT 24
Peak memory 273176 kb
Host smart-8b96bcc5-5c6e-4f95-a79c-200dc07d1fba
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201586109 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_entropy.201586109
Directory /workspace/30.alert_handler_entropy/latest

Test location /workspace/coverage/default/30.alert_handler_esc_alert_accum.1310300879
Short name T621
Test name
Test status
Simulation time 2040467885 ps
CPU time 189.64 seconds
Started Jul 19 04:49:32 PM PDT 24
Finished Jul 19 04:52:57 PM PDT 24
Peak memory 256308 kb
Host smart-621c7215-197d-48fe-88c5-21723d0c8840
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13103
00879 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_alert_accum.1310300879
Directory /workspace/30.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/30.alert_handler_esc_intr_timeout.2451742539
Short name T231
Test name
Test status
Simulation time 200144395 ps
CPU time 6.55 seconds
Started Jul 19 04:49:30 PM PDT 24
Finished Jul 19 04:49:51 PM PDT 24
Peak memory 248912 kb
Host smart-ccc023f7-79e3-43cf-a067-1300562432b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24517
42539 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_intr_timeout.2451742539
Directory /workspace/30.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_lpg.1837685541
Short name T582
Test name
Test status
Simulation time 55303811726 ps
CPU time 1064.11 seconds
Started Jul 19 04:49:38 PM PDT 24
Finished Jul 19 05:07:36 PM PDT 24
Peak memory 285404 kb
Host smart-7558f023-e9c8-4a9d-936c-86ee7a3a6e4d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837685541 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg.1837685541
Directory /workspace/30.alert_handler_lpg/latest

Test location /workspace/coverage/default/30.alert_handler_lpg_stub_clk.1422649969
Short name T6
Test name
Test status
Simulation time 471370523905 ps
CPU time 3143.98 seconds
Started Jul 19 04:49:32 PM PDT 24
Finished Jul 19 05:42:12 PM PDT 24
Peak memory 289980 kb
Host smart-1ff7b752-b770-42fa-a04e-946a498a39b5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422649969 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg_stub_clk.1422649969
Directory /workspace/30.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/30.alert_handler_random_alerts.1877621258
Short name T462
Test name
Test status
Simulation time 93939073 ps
CPU time 6.22 seconds
Started Jul 19 04:49:24 PM PDT 24
Finished Jul 19 04:49:43 PM PDT 24
Peak memory 248924 kb
Host smart-9064a7be-a5e4-427c-813f-18e87b929e03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18776
21258 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_alerts.1877621258
Directory /workspace/30.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/30.alert_handler_random_classes.2313032233
Short name T538
Test name
Test status
Simulation time 80290290 ps
CPU time 6.3 seconds
Started Jul 19 04:49:25 PM PDT 24
Finished Jul 19 04:49:45 PM PDT 24
Peak memory 248488 kb
Host smart-bd72bdce-ae87-4626-a81a-7e2db1913b8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23130
32233 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_classes.2313032233
Directory /workspace/30.alert_handler_random_classes/latest

Test location /workspace/coverage/default/30.alert_handler_sig_int_fail.3499084177
Short name T283
Test name
Test status
Simulation time 3250100633 ps
CPU time 19.03 seconds
Started Jul 19 04:49:32 PM PDT 24
Finished Jul 19 04:50:07 PM PDT 24
Peak memory 256280 kb
Host smart-bb278f40-63ef-44b1-bea0-62f21b2aa493
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34990
84177 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_sig_int_fail.3499084177
Directory /workspace/30.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/30.alert_handler_smoke.2482505781
Short name T353
Test name
Test status
Simulation time 1281817247 ps
CPU time 71.8 seconds
Started Jul 19 04:49:24 PM PDT 24
Finished Jul 19 04:50:48 PM PDT 24
Peak memory 256592 kb
Host smart-ad35b9a4-3e59-427d-a83f-43bd731150b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24825
05781 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_smoke.2482505781
Directory /workspace/30.alert_handler_smoke/latest

Test location /workspace/coverage/default/31.alert_handler_entropy.1730281059
Short name T436
Test name
Test status
Simulation time 4859542141 ps
CPU time 537.65 seconds
Started Jul 19 04:49:31 PM PDT 24
Finished Jul 19 04:58:44 PM PDT 24
Peak memory 272040 kb
Host smart-90243ac9-4eb7-409c-b017-a48e4190816c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1730281059 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_entropy.1730281059
Directory /workspace/31.alert_handler_entropy/latest

Test location /workspace/coverage/default/31.alert_handler_esc_alert_accum.4248020022
Short name T44
Test name
Test status
Simulation time 13737790037 ps
CPU time 219.29 seconds
Started Jul 19 04:49:31 PM PDT 24
Finished Jul 19 04:53:24 PM PDT 24
Peak memory 257172 kb
Host smart-41fa98ab-b994-47b2-8f71-af528ba9cf04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42480
20022 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_alert_accum.4248020022
Directory /workspace/31.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/31.alert_handler_esc_intr_timeout.796766646
Short name T483
Test name
Test status
Simulation time 688701908 ps
CPU time 15.87 seconds
Started Jul 19 04:49:29 PM PDT 24
Finished Jul 19 04:49:59 PM PDT 24
Peak memory 256324 kb
Host smart-05cc5748-e4b1-4281-8b5c-30f5dc0c480a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79676
6646 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_intr_timeout.796766646
Directory /workspace/31.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_lpg.3881476092
Short name T675
Test name
Test status
Simulation time 48001459745 ps
CPU time 1454.65 seconds
Started Jul 19 04:49:31 PM PDT 24
Finished Jul 19 05:14:00 PM PDT 24
Peak memory 289908 kb
Host smart-a69e11b3-2850-4142-af57-5c0a98afc484
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881476092 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg.3881476092
Directory /workspace/31.alert_handler_lpg/latest

Test location /workspace/coverage/default/31.alert_handler_lpg_stub_clk.2565132054
Short name T588
Test name
Test status
Simulation time 18405995600 ps
CPU time 806.66 seconds
Started Jul 19 04:49:31 PM PDT 24
Finished Jul 19 05:03:13 PM PDT 24
Peak memory 273388 kb
Host smart-28795bc2-9852-455c-b777-8a7ee24ad6ba
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565132054 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg_stub_clk.2565132054
Directory /workspace/31.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/31.alert_handler_ping_timeout.704859290
Short name T295
Test name
Test status
Simulation time 9967288158 ps
CPU time 373.63 seconds
Started Jul 19 04:49:33 PM PDT 24
Finished Jul 19 04:56:03 PM PDT 24
Peak memory 249068 kb
Host smart-5f6c23e3-a421-44bf-b305-9669db058596
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704859290 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_ping_timeout.704859290
Directory /workspace/31.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_random_alerts.4291471689
Short name T680
Test name
Test status
Simulation time 1752835419 ps
CPU time 59.78 seconds
Started Jul 19 04:49:33 PM PDT 24
Finished Jul 19 04:50:49 PM PDT 24
Peak memory 257136 kb
Host smart-563712f4-c575-4382-9834-68558fe30f66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42914
71689 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_alerts.4291471689
Directory /workspace/31.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/31.alert_handler_random_classes.3431053204
Short name T678
Test name
Test status
Simulation time 3006740561 ps
CPU time 32.72 seconds
Started Jul 19 04:49:30 PM PDT 24
Finished Jul 19 04:50:17 PM PDT 24
Peak memory 249384 kb
Host smart-e6ff41a4-6306-49d2-8717-125fc668323c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34310
53204 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_classes.3431053204
Directory /workspace/31.alert_handler_random_classes/latest

Test location /workspace/coverage/default/31.alert_handler_sig_int_fail.3570347640
Short name T476
Test name
Test status
Simulation time 410922955 ps
CPU time 26.08 seconds
Started Jul 19 04:49:32 PM PDT 24
Finished Jul 19 04:50:13 PM PDT 24
Peak memory 248472 kb
Host smart-34fa8cd5-b365-4fab-b291-0b3d7a475937
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35703
47640 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_sig_int_fail.3570347640
Directory /workspace/31.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/31.alert_handler_smoke.669242994
Short name T679
Test name
Test status
Simulation time 2208083371 ps
CPU time 53.3 seconds
Started Jul 19 04:49:30 PM PDT 24
Finished Jul 19 04:50:38 PM PDT 24
Peak memory 256680 kb
Host smart-4a8a6cf2-2950-480a-9723-67cfb1683ef9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66924
2994 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_smoke.669242994
Directory /workspace/31.alert_handler_smoke/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all.2440221486
Short name T628
Test name
Test status
Simulation time 31092863933 ps
CPU time 1369.54 seconds
Started Jul 19 04:49:42 PM PDT 24
Finished Jul 19 05:12:44 PM PDT 24
Peak memory 289324 kb
Host smart-e9df1a6a-d419-41bc-ad97-33db4e271fee
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440221486 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_ha
ndler_stress_all.2440221486
Directory /workspace/31.alert_handler_stress_all/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all_with_rand_reset.1462563393
Short name T51
Test name
Test status
Simulation time 128838771561 ps
CPU time 2146.28 seconds
Started Jul 19 04:49:31 PM PDT 24
Finished Jul 19 05:25:32 PM PDT 24
Peak memory 289884 kb
Host smart-0a2f603b-cd2a-4d57-80d0-53cf01248557
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462563393 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 31.alert_handler_stress_all_with_rand_reset.1462563393
Directory /workspace/31.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.alert_handler_entropy.196729509
Short name T414
Test name
Test status
Simulation time 14388257684 ps
CPU time 938.26 seconds
Started Jul 19 04:49:30 PM PDT 24
Finished Jul 19 05:05:23 PM PDT 24
Peak memory 272984 kb
Host smart-0db0d87e-7fa4-4c67-a421-e7732000e840
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=196729509 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_entropy.196729509
Directory /workspace/32.alert_handler_entropy/latest

Test location /workspace/coverage/default/32.alert_handler_esc_alert_accum.1185893136
Short name T566
Test name
Test status
Simulation time 26109221132 ps
CPU time 314.62 seconds
Started Jul 19 04:49:33 PM PDT 24
Finished Jul 19 04:55:04 PM PDT 24
Peak memory 256788 kb
Host smart-fd12872c-1e28-4456-a1a9-afa3145be014
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11858
93136 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_alert_accum.1185893136
Directory /workspace/32.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/32.alert_handler_esc_intr_timeout.2042323712
Short name T232
Test name
Test status
Simulation time 3478477470 ps
CPU time 27.61 seconds
Started Jul 19 04:49:30 PM PDT 24
Finished Jul 19 04:50:12 PM PDT 24
Peak memory 255624 kb
Host smart-f83e880d-3a91-41f5-b32d-9f5862211c1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20423
23712 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_intr_timeout.2042323712
Directory /workspace/32.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_lpg_stub_clk.2385151802
Short name T121
Test name
Test status
Simulation time 32116027139 ps
CPU time 955.98 seconds
Started Jul 19 04:49:41 PM PDT 24
Finished Jul 19 05:05:51 PM PDT 24
Peak memory 272004 kb
Host smart-7fb4bda5-3a2b-4c91-8b9c-254ec690d03a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385151802 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg_stub_clk.2385151802
Directory /workspace/32.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/32.alert_handler_ping_timeout.897602757
Short name T312
Test name
Test status
Simulation time 17037676275 ps
CPU time 250.06 seconds
Started Jul 19 04:49:33 PM PDT 24
Finished Jul 19 04:53:59 PM PDT 24
Peak memory 255828 kb
Host smart-58bc2893-4a68-4404-8454-8e6c92bf539e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897602757 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_ping_timeout.897602757
Directory /workspace/32.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_random_alerts.114923947
Short name T642
Test name
Test status
Simulation time 386815479 ps
CPU time 44.33 seconds
Started Jul 19 04:49:42 PM PDT 24
Finished Jul 19 04:50:39 PM PDT 24
Peak memory 248908 kb
Host smart-fee821f8-1806-4cc5-9d88-030502785249
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11492
3947 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_alerts.114923947
Directory /workspace/32.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/32.alert_handler_random_classes.1191843350
Short name T516
Test name
Test status
Simulation time 3995638358 ps
CPU time 62.43 seconds
Started Jul 19 04:49:40 PM PDT 24
Finished Jul 19 04:50:56 PM PDT 24
Peak memory 256264 kb
Host smart-49b94eb0-d1e6-482d-bfee-00ba8034f5e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11918
43350 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_classes.1191843350
Directory /workspace/32.alert_handler_random_classes/latest

Test location /workspace/coverage/default/32.alert_handler_sig_int_fail.57094240
Short name T113
Test name
Test status
Simulation time 350563605 ps
CPU time 26.16 seconds
Started Jul 19 04:49:31 PM PDT 24
Finished Jul 19 04:50:11 PM PDT 24
Peak memory 256332 kb
Host smart-a0912ec3-a656-4340-b6eb-ed66bb82fc5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57094
240 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_sig_int_fail.57094240
Directory /workspace/32.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/32.alert_handler_smoke.2842753645
Short name T504
Test name
Test status
Simulation time 239499539 ps
CPU time 22.81 seconds
Started Jul 19 04:49:30 PM PDT 24
Finished Jul 19 04:50:07 PM PDT 24
Peak memory 248840 kb
Host smart-2cc1220c-7cfd-4f86-ae32-3d4e29ba5292
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28427
53645 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_smoke.2842753645
Directory /workspace/32.alert_handler_smoke/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all.3704660066
Short name T394
Test name
Test status
Simulation time 243360533227 ps
CPU time 3952.48 seconds
Started Jul 19 04:49:30 PM PDT 24
Finished Jul 19 05:55:37 PM PDT 24
Peak memory 300184 kb
Host smart-084add5b-2d3e-400e-975f-6b1b3480ac3b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704660066 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_ha
ndler_stress_all.3704660066
Directory /workspace/32.alert_handler_stress_all/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all_with_rand_reset.3378694448
Short name T506
Test name
Test status
Simulation time 45276171010 ps
CPU time 1104.5 seconds
Started Jul 19 04:49:31 PM PDT 24
Finished Jul 19 05:08:11 PM PDT 24
Peak memory 286864 kb
Host smart-81d80866-f8aa-4927-8a94-0bca0b9ee023
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378694448 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 32.alert_handler_stress_all_with_rand_reset.3378694448
Directory /workspace/32.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.alert_handler_entropy.2884352287
Short name T693
Test name
Test status
Simulation time 24445630737 ps
CPU time 775.62 seconds
Started Jul 19 04:49:35 PM PDT 24
Finished Jul 19 05:02:46 PM PDT 24
Peak memory 273064 kb
Host smart-e144aaf1-3a27-456b-8325-a15ff721c273
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2884352287 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_entropy.2884352287
Directory /workspace/33.alert_handler_entropy/latest

Test location /workspace/coverage/default/33.alert_handler_esc_alert_accum.3749822291
Short name T592
Test name
Test status
Simulation time 16149459970 ps
CPU time 254.26 seconds
Started Jul 19 04:49:36 PM PDT 24
Finished Jul 19 04:54:06 PM PDT 24
Peak memory 256356 kb
Host smart-ea06ed0d-56a1-41d9-bc59-1d431e927415
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37498
22291 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_alert_accum.3749822291
Directory /workspace/33.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/33.alert_handler_esc_intr_timeout.582515782
Short name T447
Test name
Test status
Simulation time 363885389 ps
CPU time 27.1 seconds
Started Jul 19 04:49:31 PM PDT 24
Finished Jul 19 04:50:14 PM PDT 24
Peak memory 256644 kb
Host smart-f1cf19e5-c1de-4e0e-8412-3c223f513947
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58251
5782 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_intr_timeout.582515782
Directory /workspace/33.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_lpg.2215688013
Short name T536
Test name
Test status
Simulation time 56300938022 ps
CPU time 1092.77 seconds
Started Jul 19 04:49:39 PM PDT 24
Finished Jul 19 05:08:06 PM PDT 24
Peak memory 273684 kb
Host smart-553c1905-0ff0-489e-a6b1-261886e8f405
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215688013 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg.2215688013
Directory /workspace/33.alert_handler_lpg/latest

Test location /workspace/coverage/default/33.alert_handler_lpg_stub_clk.3384315553
Short name T489
Test name
Test status
Simulation time 35354693821 ps
CPU time 925.25 seconds
Started Jul 19 04:49:40 PM PDT 24
Finished Jul 19 05:05:19 PM PDT 24
Peak memory 285832 kb
Host smart-a31b3860-cece-417a-a50a-0810247878ad
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384315553 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg_stub_clk.3384315553
Directory /workspace/33.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/33.alert_handler_ping_timeout.4276368285
Short name T603
Test name
Test status
Simulation time 13754584567 ps
CPU time 281.44 seconds
Started Jul 19 04:49:33 PM PDT 24
Finished Jul 19 04:54:30 PM PDT 24
Peak memory 249016 kb
Host smart-69b185f2-8ce0-4b7a-80d5-24f38540b101
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276368285 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_ping_timeout.4276368285
Directory /workspace/33.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_random_alerts.960189206
Short name T32
Test name
Test status
Simulation time 182575219 ps
CPU time 20.28 seconds
Started Jul 19 04:49:32 PM PDT 24
Finished Jul 19 04:50:07 PM PDT 24
Peak memory 256428 kb
Host smart-aa94e545-413f-4d6b-b4c4-c11a94c78c2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96018
9206 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_alerts.960189206
Directory /workspace/33.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/33.alert_handler_random_classes.224517507
Short name T645
Test name
Test status
Simulation time 973391003 ps
CPU time 36.07 seconds
Started Jul 19 04:49:33 PM PDT 24
Finished Jul 19 04:50:25 PM PDT 24
Peak memory 249352 kb
Host smart-b9d0d30b-5804-473f-8f1b-76eeb8579092
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22451
7507 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_classes.224517507
Directory /workspace/33.alert_handler_random_classes/latest

Test location /workspace/coverage/default/33.alert_handler_sig_int_fail.2660319264
Short name T361
Test name
Test status
Simulation time 414649699 ps
CPU time 39.54 seconds
Started Jul 19 04:49:33 PM PDT 24
Finished Jul 19 04:50:28 PM PDT 24
Peak memory 256556 kb
Host smart-5a3ac5e3-462e-4bc3-8164-f5dd64139143
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26603
19264 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_sig_int_fail.2660319264
Directory /workspace/33.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/33.alert_handler_smoke.1814252673
Short name T612
Test name
Test status
Simulation time 1878969465 ps
CPU time 29.78 seconds
Started Jul 19 04:49:30 PM PDT 24
Finished Jul 19 04:50:14 PM PDT 24
Peak memory 257068 kb
Host smart-07e3cf63-008f-448f-ab34-e4e263c4f767
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18142
52673 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_smoke.1814252673
Directory /workspace/33.alert_handler_smoke/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all.1583832608
Short name T613
Test name
Test status
Simulation time 246893632429 ps
CPU time 3426.16 seconds
Started Jul 19 04:49:33 PM PDT 24
Finished Jul 19 05:46:56 PM PDT 24
Peak memory 297272 kb
Host smart-8ac0bf5b-149a-40b1-b6a4-b31a44315bbf
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583832608 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_ha
ndler_stress_all.1583832608
Directory /workspace/33.alert_handler_stress_all/latest

Test location /workspace/coverage/default/34.alert_handler_entropy.4193782086
Short name T495
Test name
Test status
Simulation time 10023230102 ps
CPU time 1214.55 seconds
Started Jul 19 04:49:36 PM PDT 24
Finished Jul 19 05:10:06 PM PDT 24
Peak memory 272644 kb
Host smart-f9b918ca-c0dc-4068-9f48-00c5d06c7711
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193782086 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_entropy.4193782086
Directory /workspace/34.alert_handler_entropy/latest

Test location /workspace/coverage/default/34.alert_handler_esc_alert_accum.366664921
Short name T616
Test name
Test status
Simulation time 6087930886 ps
CPU time 99.46 seconds
Started Jul 19 04:49:31 PM PDT 24
Finished Jul 19 04:51:25 PM PDT 24
Peak memory 257292 kb
Host smart-339d613f-b273-4a32-a773-e4d8c2643c1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36666
4921 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_alert_accum.366664921
Directory /workspace/34.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/34.alert_handler_esc_intr_timeout.3645504331
Short name T68
Test name
Test status
Simulation time 839873924 ps
CPU time 30.93 seconds
Started Jul 19 04:49:33 PM PDT 24
Finished Jul 19 04:50:19 PM PDT 24
Peak memory 248500 kb
Host smart-c00dad8b-890b-4d35-bffe-05e58e5f3bf6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36455
04331 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_intr_timeout.3645504331
Directory /workspace/34.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_lpg.3647877118
Short name T338
Test name
Test status
Simulation time 49601134632 ps
CPU time 3036.93 seconds
Started Jul 19 04:49:37 PM PDT 24
Finished Jul 19 05:40:29 PM PDT 24
Peak memory 288612 kb
Host smart-3033bbe5-43fa-4a4a-9ea8-f4ae0c3f383d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647877118 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg.3647877118
Directory /workspace/34.alert_handler_lpg/latest

Test location /workspace/coverage/default/34.alert_handler_lpg_stub_clk.719711970
Short name T105
Test name
Test status
Simulation time 113945383251 ps
CPU time 1582.25 seconds
Started Jul 19 04:49:33 PM PDT 24
Finished Jul 19 05:16:12 PM PDT 24
Peak memory 273520 kb
Host smart-d3670d73-cd81-466f-b5fb-b8b0142259b3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719711970 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg_stub_clk.719711970
Directory /workspace/34.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/34.alert_handler_ping_timeout.3732093709
Short name T241
Test name
Test status
Simulation time 5774400829 ps
CPU time 231.67 seconds
Started Jul 19 04:49:42 PM PDT 24
Finished Jul 19 04:53:47 PM PDT 24
Peak memory 248824 kb
Host smart-da7a4c90-5ae3-455f-bd18-15a2f17f58ac
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732093709 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_ping_timeout.3732093709
Directory /workspace/34.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_random_alerts.2156626701
Short name T510
Test name
Test status
Simulation time 260153392 ps
CPU time 14.28 seconds
Started Jul 19 04:49:32 PM PDT 24
Finished Jul 19 04:50:02 PM PDT 24
Peak memory 248952 kb
Host smart-c6c85d1b-9c4d-4c68-8bcc-b561af0747bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21566
26701 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_alerts.2156626701
Directory /workspace/34.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/34.alert_handler_random_classes.622698763
Short name T117
Test name
Test status
Simulation time 280350149 ps
CPU time 26.76 seconds
Started Jul 19 04:49:35 PM PDT 24
Finished Jul 19 04:50:17 PM PDT 24
Peak memory 256196 kb
Host smart-9e053d63-337a-4068-a795-0ec906909d15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62269
8763 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_classes.622698763
Directory /workspace/34.alert_handler_random_classes/latest

Test location /workspace/coverage/default/34.alert_handler_sig_int_fail.2815589232
Short name T274
Test name
Test status
Simulation time 1165678638 ps
CPU time 19.85 seconds
Started Jul 19 04:49:31 PM PDT 24
Finished Jul 19 04:50:07 PM PDT 24
Peak memory 247968 kb
Host smart-6eaa321c-fd1f-429d-a371-39c6b99efee9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28155
89232 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_sig_int_fail.2815589232
Directory /workspace/34.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/34.alert_handler_smoke.3170645124
Short name T607
Test name
Test status
Simulation time 315572098 ps
CPU time 19.23 seconds
Started Jul 19 04:49:31 PM PDT 24
Finished Jul 19 04:50:04 PM PDT 24
Peak memory 248928 kb
Host smart-5a5edc0d-cc97-492a-8215-bb7d1b8bcfb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31706
45124 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_smoke.3170645124
Directory /workspace/34.alert_handler_smoke/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all.1640374499
Short name T29
Test name
Test status
Simulation time 4345894459 ps
CPU time 238.5 seconds
Started Jul 19 04:49:33 PM PDT 24
Finished Jul 19 04:53:48 PM PDT 24
Peak memory 257296 kb
Host smart-d7c804d1-7609-4103-97df-36b40c55ef54
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640374499 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_ha
ndler_stress_all.1640374499
Directory /workspace/34.alert_handler_stress_all/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all_with_rand_reset.2500502841
Short name T86
Test name
Test status
Simulation time 231396642309 ps
CPU time 4620.48 seconds
Started Jul 19 04:49:41 PM PDT 24
Finished Jul 19 06:06:55 PM PDT 24
Peak memory 338516 kb
Host smart-146a2fa2-e16e-4dfa-b503-20cc42f97743
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500502841 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.alert_handler_stress_all_with_rand_reset.2500502841
Directory /workspace/34.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.alert_handler_entropy.943158591
Short name T379
Test name
Test status
Simulation time 10278166156 ps
CPU time 1108.35 seconds
Started Jul 19 04:49:41 PM PDT 24
Finished Jul 19 05:08:23 PM PDT 24
Peak memory 289360 kb
Host smart-55609391-f14b-41de-9e8d-aeb1ff771567
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943158591 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_entropy.943158591
Directory /workspace/35.alert_handler_entropy/latest

Test location /workspace/coverage/default/35.alert_handler_esc_alert_accum.1438346859
Short name T398
Test name
Test status
Simulation time 8553516220 ps
CPU time 214.54 seconds
Started Jul 19 04:49:42 PM PDT 24
Finished Jul 19 04:53:29 PM PDT 24
Peak memory 257084 kb
Host smart-d0eefbc6-dae2-4e71-b5eb-03ff7d5baf27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14383
46859 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_alert_accum.1438346859
Directory /workspace/35.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/35.alert_handler_esc_intr_timeout.2722303321
Short name T707
Test name
Test status
Simulation time 1482876294 ps
CPU time 38.21 seconds
Started Jul 19 04:49:42 PM PDT 24
Finished Jul 19 04:50:33 PM PDT 24
Peak memory 257088 kb
Host smart-08816111-407d-4f16-b677-3cfff8ec65ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27223
03321 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_intr_timeout.2722303321
Directory /workspace/35.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_lpg.3450650696
Short name T76
Test name
Test status
Simulation time 19635046850 ps
CPU time 1674.67 seconds
Started Jul 19 04:49:40 PM PDT 24
Finished Jul 19 05:17:49 PM PDT 24
Peak memory 287832 kb
Host smart-db60ae7c-b865-41a7-a302-6ae65dfd3259
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450650696 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg.3450650696
Directory /workspace/35.alert_handler_lpg/latest

Test location /workspace/coverage/default/35.alert_handler_lpg_stub_clk.1239757119
Short name T456
Test name
Test status
Simulation time 55054535048 ps
CPU time 1573.94 seconds
Started Jul 19 04:49:40 PM PDT 24
Finished Jul 19 05:16:08 PM PDT 24
Peak memory 273640 kb
Host smart-6d69acc7-3c4e-4c3b-b9fd-123b8e1862a1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239757119 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg_stub_clk.1239757119
Directory /workspace/35.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/35.alert_handler_random_alerts.2607859436
Short name T401
Test name
Test status
Simulation time 2279035312 ps
CPU time 14.62 seconds
Started Jul 19 04:49:33 PM PDT 24
Finished Jul 19 04:50:04 PM PDT 24
Peak memory 249072 kb
Host smart-4aa60c64-2688-48e7-8c30-19061c904ec8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26078
59436 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_alerts.2607859436
Directory /workspace/35.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/35.alert_handler_random_classes.1382873494
Short name T686
Test name
Test status
Simulation time 150672652 ps
CPU time 13.09 seconds
Started Jul 19 04:49:35 PM PDT 24
Finished Jul 19 04:50:04 PM PDT 24
Peak memory 249260 kb
Host smart-d7483cc4-9c73-4356-a1e9-cb7554f1daf0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13828
73494 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_classes.1382873494
Directory /workspace/35.alert_handler_random_classes/latest

Test location /workspace/coverage/default/35.alert_handler_sig_int_fail.1333259221
Short name T77
Test name
Test status
Simulation time 20850819974 ps
CPU time 67.6 seconds
Started Jul 19 04:49:33 PM PDT 24
Finished Jul 19 04:50:57 PM PDT 24
Peak memory 248716 kb
Host smart-979f5c63-e4c9-4a51-83ff-6ac4b2725cc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13332
59221 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_sig_int_fail.1333259221
Directory /workspace/35.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/35.alert_handler_smoke.945578958
Short name T501
Test name
Test status
Simulation time 474092074 ps
CPU time 19.94 seconds
Started Jul 19 04:49:33 PM PDT 24
Finished Jul 19 04:50:09 PM PDT 24
Peak memory 254780 kb
Host smart-34d061de-1f13-497c-a81c-dd8bad043f1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94557
8958 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_smoke.945578958
Directory /workspace/35.alert_handler_smoke/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all_with_rand_reset.3285245382
Short name T89
Test name
Test status
Simulation time 13770640363 ps
CPU time 1891.52 seconds
Started Jul 19 04:49:46 PM PDT 24
Finished Jul 19 05:21:28 PM PDT 24
Peak memory 290088 kb
Host smart-f1c551a4-4b5b-4f5a-8001-3cbfade139d8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285245382 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 35.alert_handler_stress_all_with_rand_reset.3285245382
Directory /workspace/35.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.alert_handler_entropy.2091891941
Short name T608
Test name
Test status
Simulation time 171677581538 ps
CPU time 2384.37 seconds
Started Jul 19 04:49:42 PM PDT 24
Finished Jul 19 05:29:40 PM PDT 24
Peak memory 289800 kb
Host smart-be94ec55-decd-497b-935e-fccf5d776151
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091891941 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_entropy.2091891941
Directory /workspace/36.alert_handler_entropy/latest

Test location /workspace/coverage/default/36.alert_handler_esc_alert_accum.2363759505
Short name T634
Test name
Test status
Simulation time 10953187367 ps
CPU time 101.24 seconds
Started Jul 19 04:49:42 PM PDT 24
Finished Jul 19 04:51:36 PM PDT 24
Peak memory 257176 kb
Host smart-b4f63655-6618-45f9-9d45-0bd133c77999
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23637
59505 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_alert_accum.2363759505
Directory /workspace/36.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/36.alert_handler_esc_intr_timeout.832682093
Short name T657
Test name
Test status
Simulation time 3640934883 ps
CPU time 51.15 seconds
Started Jul 19 04:49:50 PM PDT 24
Finished Jul 19 04:50:50 PM PDT 24
Peak memory 248712 kb
Host smart-c31819a7-14d0-4369-a5b3-daeeb0ee825f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83268
2093 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_intr_timeout.832682093
Directory /workspace/36.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_lpg.137441701
Short name T321
Test name
Test status
Simulation time 29698752276 ps
CPU time 1663.74 seconds
Started Jul 19 04:49:46 PM PDT 24
Finished Jul 19 05:17:41 PM PDT 24
Peak memory 273572 kb
Host smart-3e334cf1-da0d-42c8-aea9-be4eb7934880
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=137441701 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg.137441701
Directory /workspace/36.alert_handler_lpg/latest

Test location /workspace/coverage/default/36.alert_handler_lpg_stub_clk.709090340
Short name T460
Test name
Test status
Simulation time 186037653793 ps
CPU time 2656.4 seconds
Started Jul 19 04:49:46 PM PDT 24
Finished Jul 19 05:34:13 PM PDT 24
Peak memory 281672 kb
Host smart-7a87aeb8-1923-4aa1-ac0b-0a4cce0a1275
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709090340 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg_stub_clk.709090340
Directory /workspace/36.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/36.alert_handler_ping_timeout.1550443416
Short name T313
Test name
Test status
Simulation time 42284939443 ps
CPU time 370.09 seconds
Started Jul 19 04:49:46 PM PDT 24
Finished Jul 19 04:56:07 PM PDT 24
Peak memory 249060 kb
Host smart-7b425d64-0286-470a-ba6e-880aca959fb3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550443416 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_ping_timeout.1550443416
Directory /workspace/36.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_random_alerts.3740577495
Short name T369
Test name
Test status
Simulation time 153983326 ps
CPU time 14.38 seconds
Started Jul 19 04:49:39 PM PDT 24
Finished Jul 19 04:50:08 PM PDT 24
Peak memory 256116 kb
Host smart-c14882da-8151-4479-a4e1-f8814bca2424
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37405
77495 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_alerts.3740577495
Directory /workspace/36.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/36.alert_handler_random_classes.284430698
Short name T359
Test name
Test status
Simulation time 3099179911 ps
CPU time 30.21 seconds
Started Jul 19 04:49:42 PM PDT 24
Finished Jul 19 04:50:25 PM PDT 24
Peak memory 248528 kb
Host smart-01606b57-2c18-4742-ab1a-a24af956482e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28443
0698 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_classes.284430698
Directory /workspace/36.alert_handler_random_classes/latest

Test location /workspace/coverage/default/36.alert_handler_sig_int_fail.4213101798
Short name T278
Test name
Test status
Simulation time 339576021 ps
CPU time 8.32 seconds
Started Jul 19 04:49:39 PM PDT 24
Finished Jul 19 04:50:02 PM PDT 24
Peak memory 248896 kb
Host smart-1d81dca5-28e6-4963-b848-9e940083af1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42131
01798 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_sig_int_fail.4213101798
Directory /workspace/36.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/36.alert_handler_smoke.1135389957
Short name T540
Test name
Test status
Simulation time 36002072 ps
CPU time 3.1 seconds
Started Jul 19 04:49:40 PM PDT 24
Finished Jul 19 04:49:57 PM PDT 24
Peak memory 251208 kb
Host smart-33801071-40c5-408b-95e1-c22156624c87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11353
89957 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_smoke.1135389957
Directory /workspace/36.alert_handler_smoke/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all.3134086108
Short name T548
Test name
Test status
Simulation time 5919422369 ps
CPU time 576.28 seconds
Started Jul 19 04:49:39 PM PDT 24
Finished Jul 19 04:59:30 PM PDT 24
Peak memory 265388 kb
Host smart-5d975773-d414-48c3-a677-5e45a0cf593f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134086108 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_ha
ndler_stress_all.3134086108
Directory /workspace/36.alert_handler_stress_all/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all_with_rand_reset.540805459
Short name T74
Test name
Test status
Simulation time 54838345600 ps
CPU time 3577.44 seconds
Started Jul 19 04:49:44 PM PDT 24
Finished Jul 19 05:49:34 PM PDT 24
Peak memory 305192 kb
Host smart-bac4b6fb-be9c-4058-936f-c1ed3ebb0111
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540805459 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 36.alert_handler_stress_all_with_rand_reset.540805459
Directory /workspace/36.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.alert_handler_entropy.3709072839
Short name T472
Test name
Test status
Simulation time 151742993332 ps
CPU time 1590.26 seconds
Started Jul 19 04:49:45 PM PDT 24
Finished Jul 19 05:16:27 PM PDT 24
Peak memory 273572 kb
Host smart-ffae84a9-24cc-49f8-a6c9-6457c7bfb401
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709072839 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_entropy.3709072839
Directory /workspace/37.alert_handler_entropy/latest

Test location /workspace/coverage/default/37.alert_handler_esc_alert_accum.3776088320
Short name T569
Test name
Test status
Simulation time 832093100 ps
CPU time 73.92 seconds
Started Jul 19 04:49:47 PM PDT 24
Finished Jul 19 04:51:11 PM PDT 24
Peak memory 256256 kb
Host smart-51567527-682b-462d-938f-63b605b8892b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37760
88320 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_alert_accum.3776088320
Directory /workspace/37.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/37.alert_handler_esc_intr_timeout.1136024210
Short name T633
Test name
Test status
Simulation time 119943117 ps
CPU time 8.9 seconds
Started Jul 19 04:49:39 PM PDT 24
Finished Jul 19 04:50:02 PM PDT 24
Peak memory 253472 kb
Host smart-c6ae852b-b724-46c5-9c91-b11d5271555e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11360
24210 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_intr_timeout.1136024210
Directory /workspace/37.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_lpg.1978147242
Short name T314
Test name
Test status
Simulation time 109419942991 ps
CPU time 3230.94 seconds
Started Jul 19 04:49:41 PM PDT 24
Finished Jul 19 05:43:46 PM PDT 24
Peak memory 289900 kb
Host smart-614b2619-1896-4c10-b21a-1eb5138bf8ff
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978147242 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg.1978147242
Directory /workspace/37.alert_handler_lpg/latest

Test location /workspace/coverage/default/37.alert_handler_lpg_stub_clk.3200493651
Short name T481
Test name
Test status
Simulation time 49410281414 ps
CPU time 1395.75 seconds
Started Jul 19 04:49:40 PM PDT 24
Finished Jul 19 05:13:10 PM PDT 24
Peak memory 289808 kb
Host smart-e9cac11e-d383-4526-8239-617ca38284b1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200493651 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg_stub_clk.3200493651
Directory /workspace/37.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/37.alert_handler_ping_timeout.1904995820
Short name T299
Test name
Test status
Simulation time 3342183221 ps
CPU time 142.91 seconds
Started Jul 19 04:49:47 PM PDT 24
Finished Jul 19 04:52:20 PM PDT 24
Peak memory 255196 kb
Host smart-b395580d-51d2-4f81-8ed2-58ae89922bb5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904995820 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_ping_timeout.1904995820
Directory /workspace/37.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_random_alerts.4206094799
Short name T432
Test name
Test status
Simulation time 2402331838 ps
CPU time 43.21 seconds
Started Jul 19 04:49:44 PM PDT 24
Finished Jul 19 04:50:39 PM PDT 24
Peak memory 257164 kb
Host smart-0bf5ffce-fa69-4a5b-84ee-9ccef4ad4389
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42060
94799 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_alerts.4206094799
Directory /workspace/37.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/37.alert_handler_random_classes.3721671758
Short name T583
Test name
Test status
Simulation time 353462165 ps
CPU time 27.31 seconds
Started Jul 19 04:49:44 PM PDT 24
Finished Jul 19 04:50:24 PM PDT 24
Peak memory 248940 kb
Host smart-fecdbcaa-7908-4428-b27d-29c588786c26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37216
71758 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_classes.3721671758
Directory /workspace/37.alert_handler_random_classes/latest

Test location /workspace/coverage/default/37.alert_handler_sig_int_fail.2955370782
Short name T524
Test name
Test status
Simulation time 39239749 ps
CPU time 6.45 seconds
Started Jul 19 04:49:47 PM PDT 24
Finished Jul 19 04:50:04 PM PDT 24
Peak memory 248356 kb
Host smart-a225e386-40fc-469c-ab1b-14a81970e8e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29553
70782 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_sig_int_fail.2955370782
Directory /workspace/37.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/37.alert_handler_smoke.3916186370
Short name T435
Test name
Test status
Simulation time 122735170 ps
CPU time 7.35 seconds
Started Jul 19 04:49:44 PM PDT 24
Finished Jul 19 04:50:04 PM PDT 24
Peak memory 255372 kb
Host smart-55fdd039-80d6-421f-8974-c345111305a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39161
86370 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_smoke.3916186370
Directory /workspace/37.alert_handler_smoke/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all_with_rand_reset.2135628524
Short name T264
Test name
Test status
Simulation time 38576161579 ps
CPU time 4388.76 seconds
Started Jul 19 04:49:48 PM PDT 24
Finished Jul 19 06:03:07 PM PDT 24
Peak memory 316532 kb
Host smart-0b521a58-0052-4151-8b31-f591a848e9fc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135628524 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 37.alert_handler_stress_all_with_rand_reset.2135628524
Directory /workspace/37.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.alert_handler_esc_alert_accum.2321873387
Short name T392
Test name
Test status
Simulation time 4335428418 ps
CPU time 226.47 seconds
Started Jul 19 04:49:49 PM PDT 24
Finished Jul 19 04:53:45 PM PDT 24
Peak memory 256632 kb
Host smart-5a4b8d38-b42f-4a77-9fde-b36078c5c2ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23218
73387 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_alert_accum.2321873387
Directory /workspace/38.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/38.alert_handler_esc_intr_timeout.2304505279
Short name T517
Test name
Test status
Simulation time 2624308159 ps
CPU time 58.93 seconds
Started Jul 19 04:49:48 PM PDT 24
Finished Jul 19 04:50:57 PM PDT 24
Peak memory 257100 kb
Host smart-7494493f-7940-42e6-9831-4b21055f96d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23045
05279 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_intr_timeout.2304505279
Directory /workspace/38.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_lpg.924122706
Short name T655
Test name
Test status
Simulation time 151064807422 ps
CPU time 2143.84 seconds
Started Jul 19 04:49:48 PM PDT 24
Finished Jul 19 05:25:42 PM PDT 24
Peak memory 273632 kb
Host smart-5ed46706-cc17-48ad-9c03-25a237e2be31
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=924122706 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg.924122706
Directory /workspace/38.alert_handler_lpg/latest

Test location /workspace/coverage/default/38.alert_handler_lpg_stub_clk.1753301494
Short name T511
Test name
Test status
Simulation time 21461871822 ps
CPU time 1033.02 seconds
Started Jul 19 04:49:49 PM PDT 24
Finished Jul 19 05:07:11 PM PDT 24
Peak memory 272916 kb
Host smart-cd26e28b-9b82-469d-b383-74f711d9d387
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753301494 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg_stub_clk.1753301494
Directory /workspace/38.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/38.alert_handler_random_alerts.285039397
Short name T424
Test name
Test status
Simulation time 3443558910 ps
CPU time 50.86 seconds
Started Jul 19 04:49:47 PM PDT 24
Finished Jul 19 04:50:48 PM PDT 24
Peak memory 256332 kb
Host smart-f49c0be3-bd67-4185-942f-71f3704ac8de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28503
9397 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_alerts.285039397
Directory /workspace/38.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/38.alert_handler_random_classes.1144491477
Short name T107
Test name
Test status
Simulation time 6304154693 ps
CPU time 27.22 seconds
Started Jul 19 04:49:49 PM PDT 24
Finished Jul 19 04:50:26 PM PDT 24
Peak memory 248988 kb
Host smart-cef19e67-4d18-46d1-bfeb-cef09b1e49ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11444
91477 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_classes.1144491477
Directory /workspace/38.alert_handler_random_classes/latest

Test location /workspace/coverage/default/38.alert_handler_sig_int_fail.1852405373
Short name T355
Test name
Test status
Simulation time 784972120 ps
CPU time 54.31 seconds
Started Jul 19 04:49:48 PM PDT 24
Finished Jul 19 04:50:52 PM PDT 24
Peak memory 256780 kb
Host smart-f2147cb6-dbfc-4403-80b5-d894c84ea714
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18524
05373 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_sig_int_fail.1852405373
Directory /workspace/38.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/38.alert_handler_smoke.1748956116
Short name T578
Test name
Test status
Simulation time 290763359 ps
CPU time 27.03 seconds
Started Jul 19 04:49:50 PM PDT 24
Finished Jul 19 04:50:26 PM PDT 24
Peak memory 257148 kb
Host smart-bff8cb07-df92-4aae-83f0-81e2d29858b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17489
56116 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_smoke.1748956116
Directory /workspace/38.alert_handler_smoke/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all.1971806606
Short name T507
Test name
Test status
Simulation time 40860907534 ps
CPU time 2592.68 seconds
Started Jul 19 04:49:49 PM PDT 24
Finished Jul 19 05:33:12 PM PDT 24
Peak memory 289648 kb
Host smart-22655ec9-7972-4c42-9647-4a86b5556732
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971806606 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_ha
ndler_stress_all.1971806606
Directory /workspace/38.alert_handler_stress_all/latest

Test location /workspace/coverage/default/39.alert_handler_entropy.3905011536
Short name T242
Test name
Test status
Simulation time 37193293052 ps
CPU time 1812.18 seconds
Started Jul 19 04:49:57 PM PDT 24
Finished Jul 19 05:20:14 PM PDT 24
Peak memory 289064 kb
Host smart-af80054b-288e-4b04-a235-301156e3232b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905011536 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_entropy.3905011536
Directory /workspace/39.alert_handler_entropy/latest

Test location /workspace/coverage/default/39.alert_handler_esc_alert_accum.14454687
Short name T520
Test name
Test status
Simulation time 184586234 ps
CPU time 26.42 seconds
Started Jul 19 04:49:57 PM PDT 24
Finished Jul 19 04:50:28 PM PDT 24
Peak memory 256488 kb
Host smart-286021f9-9a6e-4983-a554-617d66772e25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14454
687 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_alert_accum.14454687
Directory /workspace/39.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/39.alert_handler_esc_intr_timeout.951802139
Short name T419
Test name
Test status
Simulation time 909226879 ps
CPU time 61.54 seconds
Started Jul 19 04:49:56 PM PDT 24
Finished Jul 19 04:51:03 PM PDT 24
Peak memory 248568 kb
Host smart-1d510cc7-07ee-4cbb-a682-efea14e5fa1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95180
2139 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_intr_timeout.951802139
Directory /workspace/39.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_lpg_stub_clk.141118131
Short name T595
Test name
Test status
Simulation time 15481242879 ps
CPU time 1318.45 seconds
Started Jul 19 04:50:04 PM PDT 24
Finished Jul 19 05:12:05 PM PDT 24
Peak memory 289328 kb
Host smart-115e2791-46ad-4bb2-b922-71b132aa1bef
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141118131 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg_stub_clk.141118131
Directory /workspace/39.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/39.alert_handler_ping_timeout.3575614005
Short name T309
Test name
Test status
Simulation time 7418730506 ps
CPU time 297.22 seconds
Started Jul 19 04:49:57 PM PDT 24
Finished Jul 19 04:54:59 PM PDT 24
Peak memory 249076 kb
Host smart-343cc50e-498d-4aa7-a721-33abbbf6ba2d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575614005 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_ping_timeout.3575614005
Directory /workspace/39.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_random_alerts.3349586858
Short name T243
Test name
Test status
Simulation time 788421442 ps
CPU time 19.19 seconds
Started Jul 19 04:49:57 PM PDT 24
Finished Jul 19 04:50:21 PM PDT 24
Peak memory 248928 kb
Host smart-4f6c7f4f-564f-4759-b4ec-08224cdb550a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33495
86858 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_alerts.3349586858
Directory /workspace/39.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/39.alert_handler_random_classes.2374575842
Short name T381
Test name
Test status
Simulation time 6921782852 ps
CPU time 47.55 seconds
Started Jul 19 04:49:59 PM PDT 24
Finished Jul 19 04:50:50 PM PDT 24
Peak memory 249052 kb
Host smart-e17631cd-8701-43b6-9faf-aadca5f10a4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23745
75842 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_classes.2374575842
Directory /workspace/39.alert_handler_random_classes/latest

Test location /workspace/coverage/default/39.alert_handler_sig_int_fail.3217925133
Short name T275
Test name
Test status
Simulation time 925585986 ps
CPU time 33.18 seconds
Started Jul 19 04:49:54 PM PDT 24
Finished Jul 19 04:50:34 PM PDT 24
Peak memory 256356 kb
Host smart-4ceb2fd9-f206-4911-87ad-c180cf083581
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32179
25133 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_sig_int_fail.3217925133
Directory /workspace/39.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/39.alert_handler_smoke.947804239
Short name T567
Test name
Test status
Simulation time 130950763 ps
CPU time 4.29 seconds
Started Jul 19 04:50:04 PM PDT 24
Finished Jul 19 04:50:10 PM PDT 24
Peak memory 248924 kb
Host smart-6ef237d9-586a-4a87-99e6-fb78e414d96b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94780
4239 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_smoke.947804239
Directory /workspace/39.alert_handler_smoke/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all.4006294324
Short name T656
Test name
Test status
Simulation time 38271864349 ps
CPU time 2289.36 seconds
Started Jul 19 04:49:58 PM PDT 24
Finished Jul 19 05:28:12 PM PDT 24
Peak memory 285108 kb
Host smart-337884b2-b1ab-45ef-ad2f-30f42d0a015b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006294324 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_ha
ndler_stress_all.4006294324
Directory /workspace/39.alert_handler_stress_all/latest

Test location /workspace/coverage/default/4.alert_handler_alert_accum_saturation.508395018
Short name T220
Test name
Test status
Simulation time 131500126 ps
CPU time 3.58 seconds
Started Jul 19 04:48:48 PM PDT 24
Finished Jul 19 04:49:06 PM PDT 24
Peak memory 249228 kb
Host smart-8ceb0a14-f368-474a-8aca-f0298dab5e56
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=508395018 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_alert_accum_saturation.508395018
Directory /workspace/4.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/4.alert_handler_entropy.2317590167
Short name T15
Test name
Test status
Simulation time 17657586205 ps
CPU time 696.31 seconds
Started Jul 19 04:48:40 PM PDT 24
Finished Jul 19 05:00:34 PM PDT 24
Peak memory 265536 kb
Host smart-b0aa2a35-c9dc-4084-9c3d-15fe6d777874
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2317590167 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy.2317590167
Directory /workspace/4.alert_handler_entropy/latest

Test location /workspace/coverage/default/4.alert_handler_entropy_stress.4290024760
Short name T395
Test name
Test status
Simulation time 2511389426 ps
CPU time 33.34 seconds
Started Jul 19 04:48:49 PM PDT 24
Finished Jul 19 04:49:37 PM PDT 24
Peak memory 248880 kb
Host smart-24e8d7fa-66cb-4b5f-b4c4-782fea107dbc
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4290024760 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy_stress.4290024760
Directory /workspace/4.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/4.alert_handler_esc_alert_accum.1218260885
Short name T478
Test name
Test status
Simulation time 2981130671 ps
CPU time 166.79 seconds
Started Jul 19 04:48:39 PM PDT 24
Finished Jul 19 04:51:44 PM PDT 24
Peak memory 256692 kb
Host smart-0742cd49-93dd-4a74-be98-277172e049d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12182
60885 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_alert_accum.1218260885
Directory /workspace/4.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/4.alert_handler_esc_intr_timeout.4093459673
Short name T43
Test name
Test status
Simulation time 741032959 ps
CPU time 13.06 seconds
Started Jul 19 04:48:50 PM PDT 24
Finished Jul 19 04:49:18 PM PDT 24
Peak memory 249308 kb
Host smart-7bff3054-e520-4f8f-bd19-d70debd5aff3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40934
59673 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_intr_timeout.4093459673
Directory /workspace/4.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_lpg.2532236748
Short name T8
Test name
Test status
Simulation time 9837856296 ps
CPU time 1007.37 seconds
Started Jul 19 04:48:52 PM PDT 24
Finished Jul 19 05:05:54 PM PDT 24
Peak memory 273500 kb
Host smart-3fb32562-5181-4e51-8891-93c39ca3fefc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532236748 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg.2532236748
Directory /workspace/4.alert_handler_lpg/latest

Test location /workspace/coverage/default/4.alert_handler_lpg_stub_clk.4132115729
Short name T396
Test name
Test status
Simulation time 87927877450 ps
CPU time 1494.71 seconds
Started Jul 19 04:48:45 PM PDT 24
Finished Jul 19 05:13:56 PM PDT 24
Peak memory 273404 kb
Host smart-1d5676fe-afe2-4f72-9d34-4395336e2087
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132115729 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg_stub_clk.4132115729
Directory /workspace/4.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/4.alert_handler_random_alerts.336246933
Short name T491
Test name
Test status
Simulation time 927012115 ps
CPU time 47.03 seconds
Started Jul 19 04:48:39 PM PDT 24
Finished Jul 19 04:49:44 PM PDT 24
Peak memory 256148 kb
Host smart-cbe07db9-15e3-470a-9efb-4e28936d225e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33624
6933 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_alerts.336246933
Directory /workspace/4.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/4.alert_handler_random_classes.590651966
Short name T92
Test name
Test status
Simulation time 4178798519 ps
CPU time 62.08 seconds
Started Jul 19 04:48:41 PM PDT 24
Finished Jul 19 04:50:00 PM PDT 24
Peak memory 248708 kb
Host smart-c1056b9b-58db-435e-8aea-e39b58386a6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59065
1966 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_classes.590651966
Directory /workspace/4.alert_handler_random_classes/latest

Test location /workspace/coverage/default/4.alert_handler_sec_cm.2867317234
Short name T38
Test name
Test status
Simulation time 685914051 ps
CPU time 21.74 seconds
Started Jul 19 04:48:42 PM PDT 24
Finished Jul 19 04:49:20 PM PDT 24
Peak memory 271908 kb
Host smart-3598eedd-206c-4aa5-a939-477770485054
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2867317234 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sec_cm.2867317234
Directory /workspace/4.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/4.alert_handler_smoke.2157594048
Short name T261
Test name
Test status
Simulation time 332929419 ps
CPU time 29.92 seconds
Started Jul 19 04:48:48 PM PDT 24
Finished Jul 19 04:49:33 PM PDT 24
Peak memory 248956 kb
Host smart-d4bec797-dd31-4527-83ee-237d68dc91a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21575
94048 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_smoke.2157594048
Directory /workspace/4.alert_handler_smoke/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all.4004626202
Short name T708
Test name
Test status
Simulation time 153321214531 ps
CPU time 1567.82 seconds
Started Jul 19 04:48:56 PM PDT 24
Finished Jul 19 05:15:17 PM PDT 24
Peak memory 289104 kb
Host smart-7be04848-6b15-4d8f-ad72-65276f0cc230
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004626202 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_han
dler_stress_all.4004626202
Directory /workspace/4.alert_handler_stress_all/latest

Test location /workspace/coverage/default/40.alert_handler_entropy.1900363430
Short name T82
Test name
Test status
Simulation time 26483167854 ps
CPU time 737.32 seconds
Started Jul 19 04:50:00 PM PDT 24
Finished Jul 19 05:02:21 PM PDT 24
Peak memory 273528 kb
Host smart-137a51c5-69fb-4f66-84c3-0acaee32d023
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900363430 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_entropy.1900363430
Directory /workspace/40.alert_handler_entropy/latest

Test location /workspace/coverage/default/40.alert_handler_esc_alert_accum.1121288332
Short name T193
Test name
Test status
Simulation time 2036458874 ps
CPU time 131.15 seconds
Started Jul 19 04:50:05 PM PDT 24
Finished Jul 19 04:52:18 PM PDT 24
Peak memory 257128 kb
Host smart-bfe074a3-6a87-4834-8a08-22edcc1ef2ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11212
88332 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_alert_accum.1121288332
Directory /workspace/40.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/40.alert_handler_esc_intr_timeout.2543978130
Short name T60
Test name
Test status
Simulation time 599438106 ps
CPU time 11.71 seconds
Started Jul 19 04:49:55 PM PDT 24
Finished Jul 19 04:50:13 PM PDT 24
Peak memory 248464 kb
Host smart-09173d3b-1490-4383-a696-e1255f0f204e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25439
78130 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_intr_timeout.2543978130
Directory /workspace/40.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_lpg.494127262
Short name T337
Test name
Test status
Simulation time 18515762187 ps
CPU time 1485.55 seconds
Started Jul 19 04:49:57 PM PDT 24
Finished Jul 19 05:14:47 PM PDT 24
Peak memory 289456 kb
Host smart-1ab9b73b-d5e1-418c-90b2-d73e2e3e0030
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494127262 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg.494127262
Directory /workspace/40.alert_handler_lpg/latest

Test location /workspace/coverage/default/40.alert_handler_lpg_stub_clk.3195512959
Short name T233
Test name
Test status
Simulation time 35736382729 ps
CPU time 2420.53 seconds
Started Jul 19 04:49:56 PM PDT 24
Finished Jul 19 05:30:22 PM PDT 24
Peak memory 290000 kb
Host smart-036bf048-d5ce-4f93-af5d-7170d81df599
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195512959 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg_stub_clk.3195512959
Directory /workspace/40.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/40.alert_handler_ping_timeout.505092841
Short name T296
Test name
Test status
Simulation time 13376059873 ps
CPU time 135.82 seconds
Started Jul 19 04:49:57 PM PDT 24
Finished Jul 19 04:52:18 PM PDT 24
Peak memory 254648 kb
Host smart-9bf5dc1d-4939-431e-ba6a-3517765cd249
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505092841 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_ping_timeout.505092841
Directory /workspace/40.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_random_alerts.1745464529
Short name T377
Test name
Test status
Simulation time 1753273657 ps
CPU time 57.1 seconds
Started Jul 19 04:49:55 PM PDT 24
Finished Jul 19 04:50:58 PM PDT 24
Peak memory 248920 kb
Host smart-6a19e515-e4de-4e28-b603-8264428fac2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17454
64529 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_alerts.1745464529
Directory /workspace/40.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/40.alert_handler_random_classes.1297783270
Short name T555
Test name
Test status
Simulation time 940839421 ps
CPU time 59.93 seconds
Started Jul 19 04:49:57 PM PDT 24
Finished Jul 19 04:51:02 PM PDT 24
Peak memory 248888 kb
Host smart-4e5c9c36-3f6a-45b7-b207-c04e54a78695
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12977
83270 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_classes.1297783270
Directory /workspace/40.alert_handler_random_classes/latest

Test location /workspace/coverage/default/40.alert_handler_sig_int_fail.3228414533
Short name T99
Test name
Test status
Simulation time 213632849 ps
CPU time 21.37 seconds
Started Jul 19 04:49:55 PM PDT 24
Finished Jul 19 04:50:23 PM PDT 24
Peak memory 256316 kb
Host smart-b3fc91cb-361b-4882-8746-484b14237229
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32284
14533 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_sig_int_fail.3228414533
Directory /workspace/40.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/40.alert_handler_smoke.511669143
Short name T473
Test name
Test status
Simulation time 429853831 ps
CPU time 36.63 seconds
Started Jul 19 04:49:58 PM PDT 24
Finished Jul 19 04:50:39 PM PDT 24
Peak memory 256232 kb
Host smart-f357372a-df97-4acd-8413-858e59a3cbb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51166
9143 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_smoke.511669143
Directory /workspace/40.alert_handler_smoke/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all.3540919933
Short name T288
Test name
Test status
Simulation time 49783892493 ps
CPU time 775.65 seconds
Started Jul 19 04:50:05 PM PDT 24
Finished Jul 19 05:03:03 PM PDT 24
Peak memory 273652 kb
Host smart-934557be-0475-4b7c-a489-ee419f30f3eb
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540919933 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_ha
ndler_stress_all.3540919933
Directory /workspace/40.alert_handler_stress_all/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all_with_rand_reset.2242534982
Short name T236
Test name
Test status
Simulation time 76076282340 ps
CPU time 2302.19 seconds
Started Jul 19 04:49:58 PM PDT 24
Finished Jul 19 05:28:25 PM PDT 24
Peak memory 290108 kb
Host smart-93d642f4-9cba-4a59-81a7-0772b973089c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242534982 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 40.alert_handler_stress_all_with_rand_reset.2242534982
Directory /workspace/40.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.alert_handler_entropy.2843318742
Short name T387
Test name
Test status
Simulation time 181363053563 ps
CPU time 2939.65 seconds
Started Jul 19 04:50:04 PM PDT 24
Finished Jul 19 05:39:07 PM PDT 24
Peak memory 288552 kb
Host smart-ab50a412-0672-401c-b8c0-5ef159f664ae
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843318742 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_entropy.2843318742
Directory /workspace/41.alert_handler_entropy/latest

Test location /workspace/coverage/default/41.alert_handler_esc_alert_accum.3967031345
Short name T561
Test name
Test status
Simulation time 5920530495 ps
CPU time 86.08 seconds
Started Jul 19 04:50:05 PM PDT 24
Finished Jul 19 04:51:33 PM PDT 24
Peak memory 250000 kb
Host smart-daf1e0c0-6f3f-40eb-a14e-cc3e93ead0f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39670
31345 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_alert_accum.3967031345
Directory /workspace/41.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/41.alert_handler_esc_intr_timeout.1387979340
Short name T437
Test name
Test status
Simulation time 2966791357 ps
CPU time 61.08 seconds
Started Jul 19 04:50:04 PM PDT 24
Finished Jul 19 04:51:06 PM PDT 24
Peak memory 248972 kb
Host smart-6ee75aa8-39ac-4fbb-b4f9-207b3c1c3872
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13879
79340 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_intr_timeout.1387979340
Directory /workspace/41.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_lpg.2752590637
Short name T318
Test name
Test status
Simulation time 154437001814 ps
CPU time 1572.7 seconds
Started Jul 19 04:50:02 PM PDT 24
Finished Jul 19 05:16:17 PM PDT 24
Peak memory 272840 kb
Host smart-7b4ae456-2f07-4cf8-bb0c-cc49b5f35ce1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752590637 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg.2752590637
Directory /workspace/41.alert_handler_lpg/latest

Test location /workspace/coverage/default/41.alert_handler_lpg_stub_clk.57236594
Short name T415
Test name
Test status
Simulation time 13989190708 ps
CPU time 1343.66 seconds
Started Jul 19 04:50:13 PM PDT 24
Finished Jul 19 05:12:39 PM PDT 24
Peak memory 281840 kb
Host smart-cdd4e9f0-2c05-45d2-9b9f-6fb704865910
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57236594 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg_stub_clk.57236594
Directory /workspace/41.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/41.alert_handler_random_alerts.3854465543
Short name T444
Test name
Test status
Simulation time 137607010 ps
CPU time 17.65 seconds
Started Jul 19 04:50:04 PM PDT 24
Finished Jul 19 04:50:24 PM PDT 24
Peak memory 256640 kb
Host smart-bc0e672a-b5fb-4053-9e72-490bed021d3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38544
65543 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_alerts.3854465543
Directory /workspace/41.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/41.alert_handler_random_classes.390836174
Short name T490
Test name
Test status
Simulation time 503767003 ps
CPU time 10.2 seconds
Started Jul 19 04:50:05 PM PDT 24
Finished Jul 19 04:50:18 PM PDT 24
Peak memory 248936 kb
Host smart-3561d7ee-27b4-4789-af8e-7b4762749d49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39083
6174 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_classes.390836174
Directory /workspace/41.alert_handler_random_classes/latest

Test location /workspace/coverage/default/41.alert_handler_sig_int_fail.813065962
Short name T667
Test name
Test status
Simulation time 535778289 ps
CPU time 30.93 seconds
Started Jul 19 04:50:13 PM PDT 24
Finished Jul 19 04:50:46 PM PDT 24
Peak memory 248900 kb
Host smart-ae5d710c-268e-4de4-8489-5eb05287a46d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81306
5962 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_sig_int_fail.813065962
Directory /workspace/41.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/41.alert_handler_smoke.2929372988
Short name T433
Test name
Test status
Simulation time 489041485 ps
CPU time 54.36 seconds
Started Jul 19 04:49:56 PM PDT 24
Finished Jul 19 04:50:56 PM PDT 24
Peak memory 248904 kb
Host smart-4a76d8e6-15e9-42b9-9abc-7952df3ccb7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29293
72988 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_smoke.2929372988
Directory /workspace/41.alert_handler_smoke/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all_with_rand_reset.4096542586
Short name T513
Test name
Test status
Simulation time 53100233582 ps
CPU time 5370.38 seconds
Started Jul 19 04:50:13 PM PDT 24
Finished Jul 19 06:19:46 PM PDT 24
Peak memory 354932 kb
Host smart-db571dfa-5d9c-49f9-be82-418f1ea01681
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096542586 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 41.alert_handler_stress_all_with_rand_reset.4096542586
Directory /workspace/41.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.alert_handler_entropy.3749440341
Short name T623
Test name
Test status
Simulation time 133357697235 ps
CPU time 2298.61 seconds
Started Jul 19 04:50:04 PM PDT 24
Finished Jul 19 05:28:24 PM PDT 24
Peak memory 288872 kb
Host smart-75f639f0-0824-48b0-b9f8-63cbbe77a7f7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749440341 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_entropy.3749440341
Directory /workspace/42.alert_handler_entropy/latest

Test location /workspace/coverage/default/42.alert_handler_esc_alert_accum.263005765
Short name T250
Test name
Test status
Simulation time 110546238190 ps
CPU time 303.89 seconds
Started Jul 19 04:50:13 PM PDT 24
Finished Jul 19 04:55:19 PM PDT 24
Peak memory 257236 kb
Host smart-b499380b-f6b4-4b44-9d0a-711b327b2a26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26300
5765 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_alert_accum.263005765
Directory /workspace/42.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/42.alert_handler_esc_intr_timeout.1954897335
Short name T95
Test name
Test status
Simulation time 1506256471 ps
CPU time 28.45 seconds
Started Jul 19 04:50:06 PM PDT 24
Finished Jul 19 04:50:36 PM PDT 24
Peak memory 256632 kb
Host smart-d3e76a18-52f2-4f26-b3c2-3fc2f139e704
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19548
97335 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_intr_timeout.1954897335
Directory /workspace/42.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_lpg.198429951
Short name T661
Test name
Test status
Simulation time 38251282162 ps
CPU time 1041.04 seconds
Started Jul 19 04:50:06 PM PDT 24
Finished Jul 19 05:07:29 PM PDT 24
Peak memory 273648 kb
Host smart-35a5e911-073c-467a-bd01-87923b4958f3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198429951 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg.198429951
Directory /workspace/42.alert_handler_lpg/latest

Test location /workspace/coverage/default/42.alert_handler_lpg_stub_clk.3833504761
Short name T629
Test name
Test status
Simulation time 26760354677 ps
CPU time 2130.11 seconds
Started Jul 19 04:50:06 PM PDT 24
Finished Jul 19 05:25:38 PM PDT 24
Peak memory 289876 kb
Host smart-617d8cfd-35f3-4cf5-ae8c-a7256cc34f8a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833504761 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg_stub_clk.3833504761
Directory /workspace/42.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/42.alert_handler_ping_timeout.4234332538
Short name T4
Test name
Test status
Simulation time 5379356036 ps
CPU time 226.99 seconds
Started Jul 19 04:50:13 PM PDT 24
Finished Jul 19 04:54:02 PM PDT 24
Peak memory 248920 kb
Host smart-fc4533dc-0488-48a5-9974-56cbf13cf544
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234332538 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_ping_timeout.4234332538
Directory /workspace/42.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_random_alerts.2406095690
Short name T696
Test name
Test status
Simulation time 486280953 ps
CPU time 32.59 seconds
Started Jul 19 04:50:07 PM PDT 24
Finished Jul 19 04:50:41 PM PDT 24
Peak memory 256964 kb
Host smart-ce13bb44-2bad-4285-99a9-bfaf1f670352
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24060
95690 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_alerts.2406095690
Directory /workspace/42.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/42.alert_handler_random_classes.3676689733
Short name T357
Test name
Test status
Simulation time 371291689 ps
CPU time 29.55 seconds
Started Jul 19 04:50:05 PM PDT 24
Finished Jul 19 04:50:36 PM PDT 24
Peak memory 248928 kb
Host smart-f4a76049-5385-4fec-87e0-21ab31c5e18a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36766
89733 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_classes.3676689733
Directory /workspace/42.alert_handler_random_classes/latest

Test location /workspace/coverage/default/42.alert_handler_sig_int_fail.1074459317
Short name T522
Test name
Test status
Simulation time 1152364422 ps
CPU time 44.87 seconds
Started Jul 19 04:50:05 PM PDT 24
Finished Jul 19 04:50:53 PM PDT 24
Peak memory 248320 kb
Host smart-2432ba43-34d0-4045-9998-f2312c1c8c5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10744
59317 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_sig_int_fail.1074459317
Directory /workspace/42.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/42.alert_handler_smoke.3834706821
Short name T564
Test name
Test status
Simulation time 807223788 ps
CPU time 52.05 seconds
Started Jul 19 04:50:04 PM PDT 24
Finished Jul 19 04:50:59 PM PDT 24
Peak memory 257132 kb
Host smart-4fb13c1a-ad26-4dfa-9474-221a42c33f76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38347
06821 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_smoke.3834706821
Directory /workspace/42.alert_handler_smoke/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all_with_rand_reset.534464846
Short name T57
Test name
Test status
Simulation time 34199007254 ps
CPU time 3718.69 seconds
Started Jul 19 04:50:05 PM PDT 24
Finished Jul 19 05:52:07 PM PDT 24
Peak memory 322612 kb
Host smart-ea4b9897-987e-4b1a-80af-ba89575b14c2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534464846 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 42.alert_handler_stress_all_with_rand_reset.534464846
Directory /workspace/42.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.alert_handler_entropy.2480021709
Short name T568
Test name
Test status
Simulation time 39085088072 ps
CPU time 1591.09 seconds
Started Jul 19 04:50:12 PM PDT 24
Finished Jul 19 05:16:45 PM PDT 24
Peak memory 289912 kb
Host smart-07e3a2e6-ecb6-466d-a813-01db5a9d2114
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480021709 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_entropy.2480021709
Directory /workspace/43.alert_handler_entropy/latest

Test location /workspace/coverage/default/43.alert_handler_esc_alert_accum.3061094143
Short name T600
Test name
Test status
Simulation time 2529771201 ps
CPU time 74.47 seconds
Started Jul 19 04:50:12 PM PDT 24
Finished Jul 19 04:51:29 PM PDT 24
Peak memory 256672 kb
Host smart-c1992adb-80b1-4df2-9036-91c100c910c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30610
94143 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_alert_accum.3061094143
Directory /workspace/43.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/43.alert_handler_esc_intr_timeout.3253412800
Short name T563
Test name
Test status
Simulation time 780173767 ps
CPU time 50.69 seconds
Started Jul 19 04:50:12 PM PDT 24
Finished Jul 19 04:51:04 PM PDT 24
Peak memory 256672 kb
Host smart-8206da12-d40a-497f-907f-7096a403715c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32534
12800 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_intr_timeout.3253412800
Directory /workspace/43.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_lpg.3902794870
Short name T323
Test name
Test status
Simulation time 133785794539 ps
CPU time 1585.62 seconds
Started Jul 19 04:50:14 PM PDT 24
Finished Jul 19 05:16:41 PM PDT 24
Peak memory 272852 kb
Host smart-8e97c2ef-fa0f-4625-8f80-0657981dcb5e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902794870 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg.3902794870
Directory /workspace/43.alert_handler_lpg/latest

Test location /workspace/coverage/default/43.alert_handler_lpg_stub_clk.3405082347
Short name T484
Test name
Test status
Simulation time 12471013196 ps
CPU time 1205.99 seconds
Started Jul 19 04:50:13 PM PDT 24
Finished Jul 19 05:10:21 PM PDT 24
Peak memory 289660 kb
Host smart-b6d8962c-6fa5-490b-8918-0068d6697e60
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405082347 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg_stub_clk.3405082347
Directory /workspace/43.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/43.alert_handler_ping_timeout.2728257604
Short name T300
Test name
Test status
Simulation time 15741595881 ps
CPU time 166.63 seconds
Started Jul 19 04:50:13 PM PDT 24
Finished Jul 19 04:53:02 PM PDT 24
Peak memory 254616 kb
Host smart-b91a3b72-72f7-4740-86de-b04084ecd732
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728257604 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_ping_timeout.2728257604
Directory /workspace/43.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_random_alerts.2763645340
Short name T225
Test name
Test status
Simulation time 190291911 ps
CPU time 4.16 seconds
Started Jul 19 04:50:14 PM PDT 24
Finished Jul 19 04:50:20 PM PDT 24
Peak memory 240512 kb
Host smart-6a064f6b-d37f-44ec-85e2-eaab124f5c31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27636
45340 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_alerts.2763645340
Directory /workspace/43.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/43.alert_handler_random_classes.4013219607
Short name T528
Test name
Test status
Simulation time 1730891521 ps
CPU time 51.62 seconds
Started Jul 19 04:50:16 PM PDT 24
Finished Jul 19 04:51:09 PM PDT 24
Peak memory 256164 kb
Host smart-d761d1e9-34fe-42d4-8d74-c6002b644300
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40132
19607 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_classes.4013219607
Directory /workspace/43.alert_handler_random_classes/latest

Test location /workspace/coverage/default/43.alert_handler_sig_int_fail.3612002627
Short name T115
Test name
Test status
Simulation time 466346846 ps
CPU time 36.72 seconds
Started Jul 19 04:50:14 PM PDT 24
Finished Jul 19 04:50:53 PM PDT 24
Peak memory 248500 kb
Host smart-d8148a77-e4c8-435f-b8be-5d0ae1ce1869
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36120
02627 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_sig_int_fail.3612002627
Directory /workspace/43.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/43.alert_handler_smoke.2997757809
Short name T384
Test name
Test status
Simulation time 1885909962 ps
CPU time 39.1 seconds
Started Jul 19 04:50:04 PM PDT 24
Finished Jul 19 04:50:44 PM PDT 24
Peak memory 256672 kb
Host smart-a7217ef2-35d8-4d05-8a75-63d822849196
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29977
57809 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_smoke.2997757809
Directory /workspace/43.alert_handler_smoke/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all.3351625291
Short name T669
Test name
Test status
Simulation time 7528472213 ps
CPU time 114.14 seconds
Started Jul 19 04:50:13 PM PDT 24
Finished Jul 19 04:52:10 PM PDT 24
Peak memory 257236 kb
Host smart-20bdf62e-6743-43a8-8ff1-90454c2a0392
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351625291 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_ha
ndler_stress_all.3351625291
Directory /workspace/43.alert_handler_stress_all/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all_with_rand_reset.3838012640
Short name T589
Test name
Test status
Simulation time 24535788019 ps
CPU time 1607.15 seconds
Started Jul 19 04:50:14 PM PDT 24
Finished Jul 19 05:17:03 PM PDT 24
Peak memory 286944 kb
Host smart-0f662c17-2b35-4893-8ebd-929d35ade6da
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838012640 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 43.alert_handler_stress_all_with_rand_reset.3838012640
Directory /workspace/43.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.alert_handler_entropy.2130537915
Short name T450
Test name
Test status
Simulation time 61070084955 ps
CPU time 2098.79 seconds
Started Jul 19 04:50:13 PM PDT 24
Finished Jul 19 05:25:14 PM PDT 24
Peak memory 273588 kb
Host smart-f272065f-16e0-4539-8288-2a2676feb957
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130537915 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_entropy.2130537915
Directory /workspace/44.alert_handler_entropy/latest

Test location /workspace/coverage/default/44.alert_handler_esc_alert_accum.2879231334
Short name T615
Test name
Test status
Simulation time 7774114474 ps
CPU time 120.33 seconds
Started Jul 19 04:50:17 PM PDT 24
Finished Jul 19 04:52:19 PM PDT 24
Peak memory 256936 kb
Host smart-e2362270-94ed-4c58-9700-594e6fe0d1c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28792
31334 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_alert_accum.2879231334
Directory /workspace/44.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/44.alert_handler_esc_intr_timeout.468582066
Short name T547
Test name
Test status
Simulation time 4047197341 ps
CPU time 56.23 seconds
Started Jul 19 04:50:12 PM PDT 24
Finished Jul 19 04:51:10 PM PDT 24
Peak memory 249128 kb
Host smart-76f26df7-fa62-41b5-899d-6bd044d3eb25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46858
2066 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_intr_timeout.468582066
Directory /workspace/44.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_lpg.2185915822
Short name T330
Test name
Test status
Simulation time 51342105916 ps
CPU time 1006.85 seconds
Started Jul 19 04:50:13 PM PDT 24
Finished Jul 19 05:07:02 PM PDT 24
Peak memory 273544 kb
Host smart-76472ec9-1495-48a6-afb1-4ec04beeccb1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185915822 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg.2185915822
Directory /workspace/44.alert_handler_lpg/latest

Test location /workspace/coverage/default/44.alert_handler_lpg_stub_clk.1201120594
Short name T485
Test name
Test status
Simulation time 168534135525 ps
CPU time 2473.76 seconds
Started Jul 19 04:50:14 PM PDT 24
Finished Jul 19 05:31:30 PM PDT 24
Peak memory 289200 kb
Host smart-0efdfa62-2edd-4cf0-a8e2-2d19fea7ad7b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201120594 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg_stub_clk.1201120594
Directory /workspace/44.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/44.alert_handler_ping_timeout.1892311664
Short name T307
Test name
Test status
Simulation time 2359092307 ps
CPU time 108.32 seconds
Started Jul 19 04:50:13 PM PDT 24
Finished Jul 19 04:52:04 PM PDT 24
Peak memory 249024 kb
Host smart-6b7e946c-24f2-4cf5-9e63-53c54c4a23c7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892311664 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_ping_timeout.1892311664
Directory /workspace/44.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_random_alerts.2402182985
Short name T590
Test name
Test status
Simulation time 278694478 ps
CPU time 16.53 seconds
Started Jul 19 04:50:16 PM PDT 24
Finished Jul 19 04:50:34 PM PDT 24
Peak memory 248520 kb
Host smart-c9f5dbdf-e9a1-44f2-b5bb-ede84857066f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24021
82985 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_alerts.2402182985
Directory /workspace/44.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/44.alert_handler_random_classes.3304138286
Short name T388
Test name
Test status
Simulation time 4806647027 ps
CPU time 37.06 seconds
Started Jul 19 04:50:14 PM PDT 24
Finished Jul 19 04:50:53 PM PDT 24
Peak memory 256332 kb
Host smart-b36924a7-8e36-4256-8ee3-3cf00289c877
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33041
38286 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_classes.3304138286
Directory /workspace/44.alert_handler_random_classes/latest

Test location /workspace/coverage/default/44.alert_handler_sig_int_fail.713177883
Short name T63
Test name
Test status
Simulation time 250394298 ps
CPU time 26.75 seconds
Started Jul 19 04:50:12 PM PDT 24
Finished Jul 19 04:50:41 PM PDT 24
Peak memory 248468 kb
Host smart-d4267341-a9a2-4052-b5ac-966e59002b82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71317
7883 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_sig_int_fail.713177883
Directory /workspace/44.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/44.alert_handler_smoke.2516431671
Short name T409
Test name
Test status
Simulation time 416921141 ps
CPU time 38.39 seconds
Started Jul 19 04:50:13 PM PDT 24
Finished Jul 19 04:50:54 PM PDT 24
Peak memory 257104 kb
Host smart-78facda9-aa37-451f-98fd-7f938cfb20b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25164
31671 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_smoke.2516431671
Directory /workspace/44.alert_handler_smoke/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all.1459818992
Short name T635
Test name
Test status
Simulation time 77845865837 ps
CPU time 1409.15 seconds
Started Jul 19 04:50:11 PM PDT 24
Finished Jul 19 05:13:42 PM PDT 24
Peak memory 272944 kb
Host smart-283c3ecc-1904-4e23-901a-18c89bf8e008
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459818992 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_ha
ndler_stress_all.1459818992
Directory /workspace/44.alert_handler_stress_all/latest

Test location /workspace/coverage/default/45.alert_handler_entropy.4127408114
Short name T428
Test name
Test status
Simulation time 38142128469 ps
CPU time 1691.83 seconds
Started Jul 19 04:50:24 PM PDT 24
Finished Jul 19 05:18:38 PM PDT 24
Peak memory 289064 kb
Host smart-83397cfc-31b0-4959-b00e-4465a4392276
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127408114 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_entropy.4127408114
Directory /workspace/45.alert_handler_entropy/latest

Test location /workspace/coverage/default/45.alert_handler_esc_alert_accum.1698988301
Short name T431
Test name
Test status
Simulation time 1285697234 ps
CPU time 117.34 seconds
Started Jul 19 04:50:22 PM PDT 24
Finished Jul 19 04:52:20 PM PDT 24
Peak memory 256652 kb
Host smart-7bf4c508-d9de-4349-88d3-a40510deb8f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16989
88301 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_alert_accum.1698988301
Directory /workspace/45.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/45.alert_handler_esc_intr_timeout.3576764765
Short name T512
Test name
Test status
Simulation time 48691346 ps
CPU time 4.56 seconds
Started Jul 19 04:50:16 PM PDT 24
Finished Jul 19 04:50:22 PM PDT 24
Peak memory 239924 kb
Host smart-18467165-51ab-458a-bcf4-e62172ddb712
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35767
64765 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_intr_timeout.3576764765
Directory /workspace/45.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_lpg.2505450884
Short name T326
Test name
Test status
Simulation time 16664025197 ps
CPU time 1380.56 seconds
Started Jul 19 04:50:23 PM PDT 24
Finished Jul 19 05:13:25 PM PDT 24
Peak memory 289200 kb
Host smart-c4c40b4d-2dd4-465e-a92c-13a3dcc7c832
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505450884 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg.2505450884
Directory /workspace/45.alert_handler_lpg/latest

Test location /workspace/coverage/default/45.alert_handler_lpg_stub_clk.1323497943
Short name T704
Test name
Test status
Simulation time 204839875642 ps
CPU time 1891.06 seconds
Started Jul 19 04:50:22 PM PDT 24
Finished Jul 19 05:21:54 PM PDT 24
Peak memory 281840 kb
Host smart-b2c4e734-eb11-408b-bbee-8d38d0582bdd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1323497943 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg_stub_clk.1323497943
Directory /workspace/45.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/45.alert_handler_ping_timeout.1682571697
Short name T297
Test name
Test status
Simulation time 3838231977 ps
CPU time 156.54 seconds
Started Jul 19 04:50:23 PM PDT 24
Finished Jul 19 04:53:01 PM PDT 24
Peak memory 249036 kb
Host smart-d9b2d1bc-6cb9-4b0f-b8a1-9cb30637b9a7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1682571697 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_ping_timeout.1682571697
Directory /workspace/45.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_random_alerts.3710937146
Short name T709
Test name
Test status
Simulation time 2489556464 ps
CPU time 58.85 seconds
Started Jul 19 04:50:13 PM PDT 24
Finished Jul 19 04:51:14 PM PDT 24
Peak memory 256728 kb
Host smart-a03a75a1-3d08-491d-ad62-cf8f31e380b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37109
37146 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_alerts.3710937146
Directory /workspace/45.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/45.alert_handler_random_classes.427640317
Short name T688
Test name
Test status
Simulation time 738770048 ps
CPU time 44.03 seconds
Started Jul 19 04:50:14 PM PDT 24
Finished Jul 19 04:51:00 PM PDT 24
Peak memory 256620 kb
Host smart-52bc5866-7508-49fa-983e-6398a8f917c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42764
0317 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_classes.427640317
Directory /workspace/45.alert_handler_random_classes/latest

Test location /workspace/coverage/default/45.alert_handler_sig_int_fail.1739948125
Short name T652
Test name
Test status
Simulation time 368202637 ps
CPU time 24.1 seconds
Started Jul 19 04:50:24 PM PDT 24
Finished Jul 19 04:50:50 PM PDT 24
Peak memory 248248 kb
Host smart-f11388f5-5851-4b32-846d-916a9c4ba7c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17399
48125 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_sig_int_fail.1739948125
Directory /workspace/45.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/45.alert_handler_smoke.326576376
Short name T230
Test name
Test status
Simulation time 453144540 ps
CPU time 21.6 seconds
Started Jul 19 04:50:12 PM PDT 24
Finished Jul 19 04:50:34 PM PDT 24
Peak memory 256904 kb
Host smart-75a98626-4a94-4f90-a973-77aa0a111409
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32657
6376 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_smoke.326576376
Directory /workspace/45.alert_handler_smoke/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all_with_rand_reset.3613700400
Short name T287
Test name
Test status
Simulation time 106641454663 ps
CPU time 2931 seconds
Started Jul 19 04:50:25 PM PDT 24
Finished Jul 19 05:39:17 PM PDT 24
Peak memory 305636 kb
Host smart-daa90522-ce4e-4105-8008-0993768d321a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613700400 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 45.alert_handler_stress_all_with_rand_reset.3613700400
Directory /workspace/45.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.alert_handler_entropy.3172535184
Short name T266
Test name
Test status
Simulation time 99889195605 ps
CPU time 1364.78 seconds
Started Jul 19 04:50:24 PM PDT 24
Finished Jul 19 05:13:10 PM PDT 24
Peak memory 288380 kb
Host smart-bf41bfcc-a915-41ea-9d4a-88c38b81646b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172535184 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_entropy.3172535184
Directory /workspace/46.alert_handler_entropy/latest

Test location /workspace/coverage/default/46.alert_handler_esc_alert_accum.1536700801
Short name T2
Test name
Test status
Simulation time 7020100416 ps
CPU time 179.57 seconds
Started Jul 19 04:50:23 PM PDT 24
Finished Jul 19 04:53:24 PM PDT 24
Peak memory 256416 kb
Host smart-257da568-c521-4a95-a13e-279e2fd5966d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15367
00801 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_alert_accum.1536700801
Directory /workspace/46.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/46.alert_handler_esc_intr_timeout.1868145802
Short name T382
Test name
Test status
Simulation time 1329275111 ps
CPU time 8.81 seconds
Started Jul 19 04:50:23 PM PDT 24
Finished Jul 19 04:50:34 PM PDT 24
Peak memory 248904 kb
Host smart-513ada30-3ea6-49f9-9e4d-20272af63833
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18681
45802 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_intr_timeout.1868145802
Directory /workspace/46.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_lpg_stub_clk.1546548286
Short name T660
Test name
Test status
Simulation time 55270888255 ps
CPU time 3455.08 seconds
Started Jul 19 04:50:22 PM PDT 24
Finished Jul 19 05:47:58 PM PDT 24
Peak memory 289776 kb
Host smart-7c8448e1-4b8a-4766-a61a-80710ee2efe9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546548286 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg_stub_clk.1546548286
Directory /workspace/46.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/46.alert_handler_ping_timeout.632677843
Short name T301
Test name
Test status
Simulation time 6911822477 ps
CPU time 170.47 seconds
Started Jul 19 04:50:23 PM PDT 24
Finished Jul 19 04:53:15 PM PDT 24
Peak memory 248904 kb
Host smart-df68689b-3329-442d-87f6-3d5cf0862b2f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632677843 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_ping_timeout.632677843
Directory /workspace/46.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_random_alerts.561032537
Short name T441
Test name
Test status
Simulation time 383559211 ps
CPU time 40.24 seconds
Started Jul 19 04:50:24 PM PDT 24
Finished Jul 19 04:51:06 PM PDT 24
Peak memory 248928 kb
Host smart-5f490540-9220-4e5e-a87f-7fe9da019999
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56103
2537 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_alerts.561032537
Directory /workspace/46.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/46.alert_handler_random_classes.2165061054
Short name T465
Test name
Test status
Simulation time 3055798334 ps
CPU time 37.2 seconds
Started Jul 19 04:50:22 PM PDT 24
Finished Jul 19 04:51:00 PM PDT 24
Peak memory 248812 kb
Host smart-3ff6f087-3a0a-45aa-9d09-7c663788cd62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21650
61054 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_classes.2165061054
Directory /workspace/46.alert_handler_random_classes/latest

Test location /workspace/coverage/default/46.alert_handler_sig_int_fail.992448864
Short name T682
Test name
Test status
Simulation time 1056879357 ps
CPU time 59.15 seconds
Started Jul 19 04:50:25 PM PDT 24
Finished Jul 19 04:51:25 PM PDT 24
Peak memory 248824 kb
Host smart-5293a319-8ba1-4cee-874e-072d61c6c9a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99244
8864 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_sig_int_fail.992448864
Directory /workspace/46.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/46.alert_handler_smoke.3508089867
Short name T372
Test name
Test status
Simulation time 12685528837 ps
CPU time 55.36 seconds
Started Jul 19 04:50:26 PM PDT 24
Finished Jul 19 04:51:22 PM PDT 24
Peak memory 256208 kb
Host smart-d0f7e126-0e84-45f7-bcf6-4f8e904de95d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35080
89867 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_smoke.3508089867
Directory /workspace/46.alert_handler_smoke/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all.3971157894
Short name T584
Test name
Test status
Simulation time 20738546112 ps
CPU time 150.03 seconds
Started Jul 19 04:50:23 PM PDT 24
Finished Jul 19 04:52:54 PM PDT 24
Peak memory 257120 kb
Host smart-1cc14a99-edd2-4625-8b90-e3389e93ad31
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971157894 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_ha
ndler_stress_all.3971157894
Directory /workspace/46.alert_handler_stress_all/latest

Test location /workspace/coverage/default/47.alert_handler_entropy.546493176
Short name T599
Test name
Test status
Simulation time 63653986147 ps
CPU time 1347.6 seconds
Started Jul 19 04:50:36 PM PDT 24
Finished Jul 19 05:13:05 PM PDT 24
Peak memory 287660 kb
Host smart-5922c984-0d8d-483a-b5dd-cb49af6fc65c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546493176 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_entropy.546493176
Directory /workspace/47.alert_handler_entropy/latest

Test location /workspace/coverage/default/47.alert_handler_esc_alert_accum.2585978631
Short name T610
Test name
Test status
Simulation time 2307330051 ps
CPU time 72.27 seconds
Started Jul 19 04:50:34 PM PDT 24
Finished Jul 19 04:51:49 PM PDT 24
Peak memory 256732 kb
Host smart-ba24b6db-88a9-439d-88d9-f7c6c4b9920b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25859
78631 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_alert_accum.2585978631
Directory /workspace/47.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/47.alert_handler_esc_intr_timeout.3422958694
Short name T627
Test name
Test status
Simulation time 1029717696 ps
CPU time 59.32 seconds
Started Jul 19 04:50:25 PM PDT 24
Finished Jul 19 04:51:25 PM PDT 24
Peak memory 248468 kb
Host smart-290e1980-7161-4447-b10c-dbf4b9028b65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34229
58694 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_intr_timeout.3422958694
Directory /workspace/47.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_lpg.484329588
Short name T334
Test name
Test status
Simulation time 24963683010 ps
CPU time 680.11 seconds
Started Jul 19 04:50:34 PM PDT 24
Finished Jul 19 05:01:57 PM PDT 24
Peak memory 272712 kb
Host smart-989e8475-acf8-4dde-9044-22017bd20d38
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484329588 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg.484329588
Directory /workspace/47.alert_handler_lpg/latest

Test location /workspace/coverage/default/47.alert_handler_lpg_stub_clk.1709997993
Short name T407
Test name
Test status
Simulation time 5262911593 ps
CPU time 659.82 seconds
Started Jul 19 04:50:33 PM PDT 24
Finished Jul 19 05:01:35 PM PDT 24
Peak memory 265424 kb
Host smart-cedd12a4-6abb-4248-898e-2092f2cc2b36
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1709997993 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg_stub_clk.1709997993
Directory /workspace/47.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/47.alert_handler_random_alerts.1029004564
Short name T352
Test name
Test status
Simulation time 2449424747 ps
CPU time 28.02 seconds
Started Jul 19 04:50:23 PM PDT 24
Finished Jul 19 04:50:52 PM PDT 24
Peak memory 256300 kb
Host smart-41b9cc6d-dec2-4857-8cfc-a06f5d00728b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10290
04564 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_alerts.1029004564
Directory /workspace/47.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/47.alert_handler_random_classes.3322913009
Short name T430
Test name
Test status
Simulation time 113333325 ps
CPU time 3.95 seconds
Started Jul 19 04:50:24 PM PDT 24
Finished Jul 19 04:50:30 PM PDT 24
Peak memory 240240 kb
Host smart-ac223ccc-ec15-4329-a8bc-6c313b6afa91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33229
13009 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_classes.3322913009
Directory /workspace/47.alert_handler_random_classes/latest

Test location /workspace/coverage/default/47.alert_handler_sig_int_fail.1586501254
Short name T385
Test name
Test status
Simulation time 137030665 ps
CPU time 11.09 seconds
Started Jul 19 04:50:35 PM PDT 24
Finished Jul 19 04:50:48 PM PDT 24
Peak memory 248968 kb
Host smart-ee14e580-2b5f-4005-a7ba-3a7de6cd4894
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15865
01254 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_sig_int_fail.1586501254
Directory /workspace/47.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/47.alert_handler_smoke.2649082016
Short name T348
Test name
Test status
Simulation time 7621574798 ps
CPU time 41.11 seconds
Started Jul 19 04:50:23 PM PDT 24
Finished Jul 19 04:51:05 PM PDT 24
Peak memory 256244 kb
Host smart-105f869b-cb03-4899-8a25-0ae0386dcbfa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26490
82016 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_smoke.2649082016
Directory /workspace/47.alert_handler_smoke/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all.897386254
Short name T118
Test name
Test status
Simulation time 126978534930 ps
CPU time 2070.16 seconds
Started Jul 19 04:50:36 PM PDT 24
Finished Jul 19 05:25:08 PM PDT 24
Peak memory 283988 kb
Host smart-c89fa76f-5ba8-4dd8-b4cb-5740b1e9ff49
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897386254 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_han
dler_stress_all.897386254
Directory /workspace/47.alert_handler_stress_all/latest

Test location /workspace/coverage/default/48.alert_handler_entropy.839059333
Short name T573
Test name
Test status
Simulation time 8982668001 ps
CPU time 879.3 seconds
Started Jul 19 04:50:36 PM PDT 24
Finished Jul 19 05:05:18 PM PDT 24
Peak memory 289644 kb
Host smart-bdc74a70-5f65-4bf8-9fe1-4925d9abacf2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=839059333 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_entropy.839059333
Directory /workspace/48.alert_handler_entropy/latest

Test location /workspace/coverage/default/48.alert_handler_esc_alert_accum.3105962329
Short name T390
Test name
Test status
Simulation time 19331678260 ps
CPU time 259.24 seconds
Started Jul 19 04:50:35 PM PDT 24
Finished Jul 19 04:54:56 PM PDT 24
Peak memory 256524 kb
Host smart-9c2ffdc5-9d3f-46ba-bc82-34145e29e271
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31059
62329 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_alert_accum.3105962329
Directory /workspace/48.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/48.alert_handler_esc_intr_timeout.3038382349
Short name T371
Test name
Test status
Simulation time 1391779152 ps
CPU time 45.24 seconds
Started Jul 19 04:50:35 PM PDT 24
Finished Jul 19 04:51:23 PM PDT 24
Peak memory 257056 kb
Host smart-f4eb416c-483d-41ed-88ff-42ef41f07782
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30383
82349 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_intr_timeout.3038382349
Directory /workspace/48.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_lpg.1937589645
Short name T665
Test name
Test status
Simulation time 14252007237 ps
CPU time 1396.3 seconds
Started Jul 19 04:50:36 PM PDT 24
Finished Jul 19 05:13:55 PM PDT 24
Peak memory 289552 kb
Host smart-7bb8facc-aefd-47cc-a16f-57da46a0a9a3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937589645 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg.1937589645
Directory /workspace/48.alert_handler_lpg/latest

Test location /workspace/coverage/default/48.alert_handler_lpg_stub_clk.2401356393
Short name T265
Test name
Test status
Simulation time 49540062437 ps
CPU time 1101.56 seconds
Started Jul 19 04:50:33 PM PDT 24
Finished Jul 19 05:08:56 PM PDT 24
Peak memory 273624 kb
Host smart-813d9b44-c222-44e8-9a0a-23c6c3554e3d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2401356393 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg_stub_clk.2401356393
Directory /workspace/48.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/48.alert_handler_ping_timeout.2695910775
Short name T306
Test name
Test status
Simulation time 10033706336 ps
CPU time 207.13 seconds
Started Jul 19 04:50:34 PM PDT 24
Finished Jul 19 04:54:03 PM PDT 24
Peak memory 249076 kb
Host smart-d513c7c6-5936-4832-af41-547357aa95f5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695910775 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_ping_timeout.2695910775
Directory /workspace/48.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_random_alerts.3229602632
Short name T596
Test name
Test status
Simulation time 471469206 ps
CPU time 10.63 seconds
Started Jul 19 04:50:37 PM PDT 24
Finished Jul 19 04:50:49 PM PDT 24
Peak memory 248956 kb
Host smart-8a1f405d-5bf0-4459-9e39-edb12e2a7667
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32296
02632 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_alerts.3229602632
Directory /workspace/48.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/48.alert_handler_random_classes.3907948250
Short name T61
Test name
Test status
Simulation time 124782071 ps
CPU time 8.86 seconds
Started Jul 19 04:50:36 PM PDT 24
Finished Jul 19 04:50:47 PM PDT 24
Peak memory 248436 kb
Host smart-0f2f5ff1-2191-4dab-a398-40977638201e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39079
48250 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_classes.3907948250
Directory /workspace/48.alert_handler_random_classes/latest

Test location /workspace/coverage/default/48.alert_handler_sig_int_fail.321868175
Short name T286
Test name
Test status
Simulation time 3003908282 ps
CPU time 45.61 seconds
Started Jul 19 04:50:34 PM PDT 24
Finished Jul 19 04:51:22 PM PDT 24
Peak memory 248976 kb
Host smart-84f6803e-89e2-4248-beba-c92cdd5d60a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32186
8175 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_sig_int_fail.321868175
Directory /workspace/48.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/48.alert_handler_smoke.3660295069
Short name T508
Test name
Test status
Simulation time 1214206566 ps
CPU time 22.21 seconds
Started Jul 19 04:50:38 PM PDT 24
Finished Jul 19 04:51:01 PM PDT 24
Peak memory 255948 kb
Host smart-46e027a7-ee6b-4d9d-b707-5febe823a5d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36602
95069 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_smoke.3660295069
Directory /workspace/48.alert_handler_smoke/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all.717535694
Short name T30
Test name
Test status
Simulation time 40389850230 ps
CPU time 2239.72 seconds
Started Jul 19 04:50:36 PM PDT 24
Finished Jul 19 05:27:58 PM PDT 24
Peak memory 289444 kb
Host smart-3dcf552e-164d-47fa-a5c6-d5fd75b40d1d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717535694 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_han
dler_stress_all.717535694
Directory /workspace/48.alert_handler_stress_all/latest

Test location /workspace/coverage/default/49.alert_handler_entropy.2381007058
Short name T463
Test name
Test status
Simulation time 94356732981 ps
CPU time 1874.61 seconds
Started Jul 19 04:50:34 PM PDT 24
Finished Jul 19 05:21:51 PM PDT 24
Peak memory 284220 kb
Host smart-359cd18e-37c8-4342-ac50-2c974f41d466
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381007058 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_entropy.2381007058
Directory /workspace/49.alert_handler_entropy/latest

Test location /workspace/coverage/default/49.alert_handler_esc_alert_accum.3972650594
Short name T458
Test name
Test status
Simulation time 2776250374 ps
CPU time 52.15 seconds
Started Jul 19 04:50:34 PM PDT 24
Finished Jul 19 04:51:29 PM PDT 24
Peak memory 256748 kb
Host smart-32b61910-eb74-491a-9407-1cfd03e7e07b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39726
50594 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_alert_accum.3972650594
Directory /workspace/49.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/49.alert_handler_esc_intr_timeout.281302537
Short name T556
Test name
Test status
Simulation time 124197174 ps
CPU time 8.55 seconds
Started Jul 19 04:50:35 PM PDT 24
Finished Jul 19 04:50:46 PM PDT 24
Peak memory 252696 kb
Host smart-37befab5-360b-40f8-918a-63709718e34b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28130
2537 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_intr_timeout.281302537
Directory /workspace/49.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_lpg.4176210588
Short name T234
Test name
Test status
Simulation time 15360960857 ps
CPU time 1389.57 seconds
Started Jul 19 04:50:42 PM PDT 24
Finished Jul 19 05:13:54 PM PDT 24
Peak memory 287732 kb
Host smart-c35374c7-a3df-4c16-a10d-16480bfe7772
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176210588 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg.4176210588
Directory /workspace/49.alert_handler_lpg/latest

Test location /workspace/coverage/default/49.alert_handler_lpg_stub_clk.2508367769
Short name T552
Test name
Test status
Simulation time 55764902523 ps
CPU time 2015.84 seconds
Started Jul 19 04:50:42 PM PDT 24
Finished Jul 19 05:24:21 PM PDT 24
Peak memory 290016 kb
Host smart-e16b7b7d-6495-467b-a4df-6ddefa1a46c4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508367769 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg_stub_clk.2508367769
Directory /workspace/49.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/49.alert_handler_ping_timeout.1672254991
Short name T492
Test name
Test status
Simulation time 15172704588 ps
CPU time 166.31 seconds
Started Jul 19 04:50:41 PM PDT 24
Finished Jul 19 04:53:30 PM PDT 24
Peak memory 256044 kb
Host smart-4d00831f-b5dd-4736-a0a2-4fb4f9594cf5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672254991 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_ping_timeout.1672254991
Directory /workspace/49.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_random_alerts.2155607099
Short name T59
Test name
Test status
Simulation time 5890222988 ps
CPU time 61.93 seconds
Started Jul 19 04:50:36 PM PDT 24
Finished Jul 19 04:51:40 PM PDT 24
Peak memory 256868 kb
Host smart-dab4f50b-d46f-4bb1-b823-3ca77cbf6e36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21556
07099 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_alerts.2155607099
Directory /workspace/49.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/49.alert_handler_random_classes.3161989898
Short name T229
Test name
Test status
Simulation time 453703874 ps
CPU time 32.7 seconds
Started Jul 19 04:50:33 PM PDT 24
Finished Jul 19 04:51:07 PM PDT 24
Peak memory 256384 kb
Host smart-91b34cd0-2357-4f9a-90c2-cf2b0265fb6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31619
89898 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_classes.3161989898
Directory /workspace/49.alert_handler_random_classes/latest

Test location /workspace/coverage/default/49.alert_handler_sig_int_fail.3715608118
Short name T276
Test name
Test status
Simulation time 190311292 ps
CPU time 24.1 seconds
Started Jul 19 04:50:41 PM PDT 24
Finished Jul 19 04:51:08 PM PDT 24
Peak memory 249348 kb
Host smart-67624aa7-c6c9-4f19-9051-31f99d659c3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37156
08118 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_sig_int_fail.3715608118
Directory /workspace/49.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/49.alert_handler_smoke.1641824001
Short name T699
Test name
Test status
Simulation time 2859049600 ps
CPU time 41.49 seconds
Started Jul 19 04:50:35 PM PDT 24
Finished Jul 19 04:51:19 PM PDT 24
Peak memory 257044 kb
Host smart-75b3e8d8-d59e-4d51-9950-667f59d7fbd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16418
24001 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_smoke.1641824001
Directory /workspace/49.alert_handler_smoke/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all.780480052
Short name T260
Test name
Test status
Simulation time 774139138814 ps
CPU time 3188.39 seconds
Started Jul 19 04:50:41 PM PDT 24
Finished Jul 19 05:43:53 PM PDT 24
Peak memory 299540 kb
Host smart-6ea8594b-606b-428a-8d2e-67b2ec125211
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780480052 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_han
dler_stress_all.780480052
Directory /workspace/49.alert_handler_stress_all/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all_with_rand_reset.4281025258
Short name T192
Test name
Test status
Simulation time 218674020917 ps
CPU time 3774.11 seconds
Started Jul 19 04:50:39 PM PDT 24
Finished Jul 19 05:53:34 PM PDT 24
Peak memory 316324 kb
Host smart-484fa498-6fe9-4e93-88ba-f66c5ccdca45
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281025258 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 49.alert_handler_stress_all_with_rand_reset.4281025258
Directory /workspace/49.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.alert_handler_alert_accum_saturation.2215380579
Short name T215
Test name
Test status
Simulation time 118552134 ps
CPU time 2.45 seconds
Started Jul 19 04:48:44 PM PDT 24
Finished Jul 19 04:49:03 PM PDT 24
Peak memory 249232 kb
Host smart-942d9020-c735-470e-83d5-d325f1b2f181
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2215380579 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_alert_accum_saturation.2215380579
Directory /workspace/5.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/5.alert_handler_entropy.2250107088
Short name T103
Test name
Test status
Simulation time 29165721353 ps
CPU time 1692.86 seconds
Started Jul 19 04:48:46 PM PDT 24
Finished Jul 19 05:17:15 PM PDT 24
Peak memory 273192 kb
Host smart-64ec4a6d-65a6-40ab-a41f-84554b8e5ea2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250107088 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy.2250107088
Directory /workspace/5.alert_handler_entropy/latest

Test location /workspace/coverage/default/5.alert_handler_entropy_stress.2561565468
Short name T650
Test name
Test status
Simulation time 4703576379 ps
CPU time 20.22 seconds
Started Jul 19 04:48:39 PM PDT 24
Finished Jul 19 04:49:17 PM PDT 24
Peak memory 249072 kb
Host smart-42cc4652-89d1-4dd0-8458-b096bc243152
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2561565468 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy_stress.2561565468
Directory /workspace/5.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/5.alert_handler_esc_alert_accum.264049438
Short name T565
Test name
Test status
Simulation time 4685469281 ps
CPU time 149.26 seconds
Started Jul 19 04:48:48 PM PDT 24
Finished Jul 19 04:51:33 PM PDT 24
Peak memory 256932 kb
Host smart-f1f64072-e4ad-483c-97a7-cd3e5e2a6c78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26404
9438 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_alert_accum.264049438
Directory /workspace/5.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/5.alert_handler_esc_intr_timeout.605982723
Short name T636
Test name
Test status
Simulation time 1028951785 ps
CPU time 16.99 seconds
Started Jul 19 04:48:37 PM PDT 24
Finished Jul 19 04:49:11 PM PDT 24
Peak memory 248944 kb
Host smart-df645e32-73f5-4129-ba19-4b6c4f81ab4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60598
2723 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_intr_timeout.605982723
Directory /workspace/5.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_lpg.764219621
Short name T64
Test name
Test status
Simulation time 9786653109 ps
CPU time 894.84 seconds
Started Jul 19 04:48:50 PM PDT 24
Finished Jul 19 05:04:00 PM PDT 24
Peak memory 282184 kb
Host smart-52b6de7a-29e0-4118-8071-0f7f78db19d0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764219621 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg.764219621
Directory /workspace/5.alert_handler_lpg/latest

Test location /workspace/coverage/default/5.alert_handler_lpg_stub_clk.3609784402
Short name T539
Test name
Test status
Simulation time 29035814989 ps
CPU time 862.21 seconds
Started Jul 19 04:48:39 PM PDT 24
Finished Jul 19 05:03:19 PM PDT 24
Peak memory 273508 kb
Host smart-2b901e9e-2d10-4020-89c1-93659a5ec6df
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609784402 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg_stub_clk.3609784402
Directory /workspace/5.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/5.alert_handler_ping_timeout.1759781652
Short name T505
Test name
Test status
Simulation time 49784448749 ps
CPU time 609.67 seconds
Started Jul 19 04:49:13 PM PDT 24
Finished Jul 19 04:59:33 PM PDT 24
Peak memory 248980 kb
Host smart-26755b74-1ba0-4935-9485-350a3df32e37
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759781652 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_ping_timeout.1759781652
Directory /workspace/5.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_random_alerts.796660606
Short name T223
Test name
Test status
Simulation time 461479623 ps
CPU time 23.06 seconds
Started Jul 19 04:48:47 PM PDT 24
Finished Jul 19 04:49:26 PM PDT 24
Peak memory 256516 kb
Host smart-fe65ea57-6430-479a-b0bc-dc44cd2cefb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79666
0606 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_alerts.796660606
Directory /workspace/5.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/5.alert_handler_random_classes.1999170363
Short name T649
Test name
Test status
Simulation time 2627997879 ps
CPU time 43.44 seconds
Started Jul 19 04:48:52 PM PDT 24
Finished Jul 19 04:49:50 PM PDT 24
Peak memory 248464 kb
Host smart-c8da43ee-26bd-46b9-af65-fe6217e2bc5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19991
70363 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_classes.1999170363
Directory /workspace/5.alert_handler_random_classes/latest

Test location /workspace/coverage/default/5.alert_handler_sig_int_fail.1978620828
Short name T96
Test name
Test status
Simulation time 736871785 ps
CPU time 53.95 seconds
Started Jul 19 04:48:46 PM PDT 24
Finished Jul 19 04:49:56 PM PDT 24
Peak memory 248268 kb
Host smart-5f36fb30-00d0-4d24-b15e-a419a8f41346
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19786
20828 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_sig_int_fail.1978620828
Directory /workspace/5.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/5.alert_handler_smoke.2767825769
Short name T488
Test name
Test status
Simulation time 1095159785 ps
CPU time 63.15 seconds
Started Jul 19 04:48:51 PM PDT 24
Finished Jul 19 04:50:09 PM PDT 24
Peak memory 257080 kb
Host smart-86b79bf6-36b6-4aa7-9ebc-9e83754b3523
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27678
25769 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_smoke.2767825769
Directory /workspace/5.alert_handler_smoke/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all.2512357966
Short name T50
Test name
Test status
Simulation time 12309487552 ps
CPU time 1214.73 seconds
Started Jul 19 04:48:39 PM PDT 24
Finished Jul 19 05:09:12 PM PDT 24
Peak memory 281884 kb
Host smart-d0e2c9e5-89b7-4d87-b8b1-7645bcc7a04d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512357966 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_han
dler_stress_all.2512357966
Directory /workspace/5.alert_handler_stress_all/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all_with_rand_reset.2932601262
Short name T70
Test name
Test status
Simulation time 162551664968 ps
CPU time 5509.85 seconds
Started Jul 19 04:48:48 PM PDT 24
Finished Jul 19 06:20:54 PM PDT 24
Peak memory 322172 kb
Host smart-10534594-aa44-44ee-8a78-27b0023c6670
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932601262 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 5.alert_handler_stress_all_with_rand_reset.2932601262
Directory /workspace/5.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.alert_handler_alert_accum_saturation.2459063669
Short name T218
Test name
Test status
Simulation time 32456757 ps
CPU time 2.35 seconds
Started Jul 19 04:48:51 PM PDT 24
Finished Jul 19 04:49:08 PM PDT 24
Peak memory 249176 kb
Host smart-23ba0162-fbed-4eae-baa4-9c5888f7c611
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2459063669 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_alert_accum_saturation.2459063669
Directory /workspace/6.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/6.alert_handler_entropy.2091952328
Short name T519
Test name
Test status
Simulation time 19708576936 ps
CPU time 1000.36 seconds
Started Jul 19 04:48:50 PM PDT 24
Finished Jul 19 05:05:46 PM PDT 24
Peak memory 273616 kb
Host smart-fad9929e-693b-4c1f-807d-42c38d7aca4a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091952328 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy.2091952328
Directory /workspace/6.alert_handler_entropy/latest

Test location /workspace/coverage/default/6.alert_handler_entropy_stress.2664882527
Short name T684
Test name
Test status
Simulation time 201758632 ps
CPU time 11.43 seconds
Started Jul 19 04:48:51 PM PDT 24
Finished Jul 19 04:49:17 PM PDT 24
Peak memory 248988 kb
Host smart-24a7f1dc-2f46-4933-8c7e-9bad951d8254
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2664882527 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy_stress.2664882527
Directory /workspace/6.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/6.alert_handler_esc_alert_accum.3177351457
Short name T591
Test name
Test status
Simulation time 2749509571 ps
CPU time 175.34 seconds
Started Jul 19 04:48:45 PM PDT 24
Finished Jul 19 04:51:57 PM PDT 24
Peak memory 256272 kb
Host smart-d449fae4-9c69-4a98-be76-6baee856369f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31773
51457 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_alert_accum.3177351457
Directory /workspace/6.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/6.alert_handler_esc_intr_timeout.220073157
Short name T471
Test name
Test status
Simulation time 834099128 ps
CPU time 42.04 seconds
Started Jul 19 04:48:50 PM PDT 24
Finished Jul 19 04:49:47 PM PDT 24
Peak memory 248852 kb
Host smart-834195c1-3ce8-41b9-b598-89105e1b6cd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22007
3157 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_intr_timeout.220073157
Directory /workspace/6.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_lpg.448025513
Short name T1
Test name
Test status
Simulation time 8118825467 ps
CPU time 852.62 seconds
Started Jul 19 04:48:54 PM PDT 24
Finished Jul 19 05:03:20 PM PDT 24
Peak memory 273616 kb
Host smart-e25c3da1-07f6-4c20-99c0-744c97df945a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448025513 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg.448025513
Directory /workspace/6.alert_handler_lpg/latest

Test location /workspace/coverage/default/6.alert_handler_lpg_stub_clk.1452460428
Short name T454
Test name
Test status
Simulation time 58395783118 ps
CPU time 1931.31 seconds
Started Jul 19 04:48:44 PM PDT 24
Finished Jul 19 05:21:12 PM PDT 24
Peak memory 273596 kb
Host smart-1c673051-4041-4e93-a373-b4368952d5c1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452460428 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg_stub_clk.1452460428
Directory /workspace/6.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/6.alert_handler_ping_timeout.582906963
Short name T609
Test name
Test status
Simulation time 14161340833 ps
CPU time 288.36 seconds
Started Jul 19 04:48:52 PM PDT 24
Finished Jul 19 04:53:55 PM PDT 24
Peak memory 248976 kb
Host smart-9cce21b0-01cf-42f5-99de-3cbdb86eec9c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=582906963 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_ping_timeout.582906963
Directory /workspace/6.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_random_alerts.3585317686
Short name T364
Test name
Test status
Simulation time 221156995 ps
CPU time 13.49 seconds
Started Jul 19 04:48:55 PM PDT 24
Finished Jul 19 04:49:23 PM PDT 24
Peak memory 248888 kb
Host smart-c89a48e6-7f0d-4eb8-8f36-9118cdbcb5f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35853
17686 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_alerts.3585317686
Directory /workspace/6.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/6.alert_handler_random_classes.1302022582
Short name T622
Test name
Test status
Simulation time 694240197 ps
CPU time 38.37 seconds
Started Jul 19 04:48:50 PM PDT 24
Finished Jul 19 04:49:44 PM PDT 24
Peak memory 257072 kb
Host smart-0de4c483-8cb8-4ffd-90c1-06212db9bb37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13020
22582 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_classes.1302022582
Directory /workspace/6.alert_handler_random_classes/latest

Test location /workspace/coverage/default/6.alert_handler_sig_int_fail.2237115140
Short name T20
Test name
Test status
Simulation time 1845320505 ps
CPU time 26.57 seconds
Started Jul 19 04:49:05 PM PDT 24
Finished Jul 19 04:49:42 PM PDT 24
Peak memory 248520 kb
Host smart-8520353a-b84b-4325-8f6f-67884bf4f019
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22371
15140 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_sig_int_fail.2237115140
Directory /workspace/6.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/6.alert_handler_smoke.738476108
Short name T676
Test name
Test status
Simulation time 854673267 ps
CPU time 60.97 seconds
Started Jul 19 04:48:55 PM PDT 24
Finished Jul 19 04:50:10 PM PDT 24
Peak memory 256052 kb
Host smart-6e01005f-fba6-4986-a9a1-d428c8777a9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73847
6108 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_smoke.738476108
Directory /workspace/6.alert_handler_smoke/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all.179923267
Short name T677
Test name
Test status
Simulation time 96119753326 ps
CPU time 2568.77 seconds
Started Jul 19 04:48:38 PM PDT 24
Finished Jul 19 05:31:45 PM PDT 24
Peak memory 289628 kb
Host smart-842616ad-08b7-40d5-a40a-2dbcf6ed8a7b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179923267 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_hand
ler_stress_all.179923267
Directory /workspace/6.alert_handler_stress_all/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all_with_rand_reset.2197952403
Short name T182
Test name
Test status
Simulation time 38856969426 ps
CPU time 1129.55 seconds
Started Jul 19 04:48:51 PM PDT 24
Finished Jul 19 05:07:55 PM PDT 24
Peak memory 289440 kb
Host smart-728b1508-0bde-4b9e-b718-14bed235b0b8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197952403 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 6.alert_handler_stress_all_with_rand_reset.2197952403
Directory /workspace/6.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.alert_handler_alert_accum_saturation.3705699557
Short name T211
Test name
Test status
Simulation time 58565796 ps
CPU time 3.2 seconds
Started Jul 19 04:48:48 PM PDT 24
Finished Jul 19 04:49:06 PM PDT 24
Peak memory 249152 kb
Host smart-d4296290-bb4b-4615-9178-ab77e04097ec
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3705699557 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_alert_accum_saturation.3705699557
Directory /workspace/7.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/7.alert_handler_entropy.327289797
Short name T576
Test name
Test status
Simulation time 8150058004 ps
CPU time 626.38 seconds
Started Jul 19 04:48:51 PM PDT 24
Finished Jul 19 04:59:32 PM PDT 24
Peak memory 273680 kb
Host smart-12240608-4e98-4705-9a00-64872eef5cd9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327289797 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy.327289797
Directory /workspace/7.alert_handler_entropy/latest

Test location /workspace/coverage/default/7.alert_handler_entropy_stress.1743432453
Short name T494
Test name
Test status
Simulation time 1847532732 ps
CPU time 14.46 seconds
Started Jul 19 04:48:47 PM PDT 24
Finished Jul 19 04:49:17 PM PDT 24
Peak memory 248992 kb
Host smart-617b5da0-8e97-48c9-975c-0d8cfa40390d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1743432453 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy_stress.1743432453
Directory /workspace/7.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/7.alert_handler_esc_alert_accum.2374401871
Short name T41
Test name
Test status
Simulation time 1583002549 ps
CPU time 127.98 seconds
Started Jul 19 04:48:44 PM PDT 24
Finished Jul 19 04:51:08 PM PDT 24
Peak memory 256700 kb
Host smart-c2b25442-8eb2-481d-b4d0-b690f5125b31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23744
01871 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_alert_accum.2374401871
Directory /workspace/7.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/7.alert_handler_esc_intr_timeout.1321575130
Short name T438
Test name
Test status
Simulation time 691093163 ps
CPU time 37.45 seconds
Started Jul 19 04:48:52 PM PDT 24
Finished Jul 19 04:49:44 PM PDT 24
Peak memory 248948 kb
Host smart-76d1013e-02e8-4a40-9561-0a415975e30e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13215
75130 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_intr_timeout.1321575130
Directory /workspace/7.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_lpg.2462944608
Short name T16
Test name
Test status
Simulation time 49197885386 ps
CPU time 833.28 seconds
Started Jul 19 04:48:57 PM PDT 24
Finished Jul 19 05:03:03 PM PDT 24
Peak memory 273600 kb
Host smart-00df6b9d-affb-44ba-bdf3-aacdc98b1ac8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462944608 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg.2462944608
Directory /workspace/7.alert_handler_lpg/latest

Test location /workspace/coverage/default/7.alert_handler_lpg_stub_clk.3561671600
Short name T443
Test name
Test status
Simulation time 43630284254 ps
CPU time 841.08 seconds
Started Jul 19 04:48:40 PM PDT 24
Finished Jul 19 05:02:59 PM PDT 24
Peak memory 273612 kb
Host smart-17018b77-399a-4e07-ac2d-91b21b26537c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561671600 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg_stub_clk.3561671600
Directory /workspace/7.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/7.alert_handler_ping_timeout.2978695764
Short name T317
Test name
Test status
Simulation time 10125653053 ps
CPU time 419.24 seconds
Started Jul 19 04:48:43 PM PDT 24
Finished Jul 19 04:55:58 PM PDT 24
Peak memory 249004 kb
Host smart-9c8c8fa0-86f0-42bf-9014-af9295845fd4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978695764 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_ping_timeout.2978695764
Directory /workspace/7.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_random_alerts.831697911
Short name T570
Test name
Test status
Simulation time 11103735390 ps
CPU time 32.4 seconds
Started Jul 19 04:48:51 PM PDT 24
Finished Jul 19 04:49:38 PM PDT 24
Peak memory 257080 kb
Host smart-a9dbc71b-7d70-4bc9-af96-764f97860567
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83169
7911 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_alerts.831697911
Directory /workspace/7.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/7.alert_handler_random_classes.234178336
Short name T455
Test name
Test status
Simulation time 215279566 ps
CPU time 20.27 seconds
Started Jul 19 04:48:52 PM PDT 24
Finished Jul 19 04:49:27 PM PDT 24
Peak memory 256716 kb
Host smart-9cb06a73-8fb6-4b81-bc9f-055807a450a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23417
8336 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_classes.234178336
Directory /workspace/7.alert_handler_random_classes/latest

Test location /workspace/coverage/default/7.alert_handler_sig_int_fail.50977899
Short name T280
Test name
Test status
Simulation time 76240763 ps
CPU time 10.16 seconds
Started Jul 19 04:48:49 PM PDT 24
Finished Jul 19 04:49:14 PM PDT 24
Peak memory 248420 kb
Host smart-712c3b58-bd08-4a66-bf9f-42b5552e1ee8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50977
899 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_sig_int_fail.50977899
Directory /workspace/7.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/7.alert_handler_smoke.3692426285
Short name T701
Test name
Test status
Simulation time 2098360219 ps
CPU time 27.06 seconds
Started Jul 19 04:48:43 PM PDT 24
Finished Jul 19 04:49:26 PM PDT 24
Peak memory 257088 kb
Host smart-1380362f-9280-4111-8a2c-e65816f1c02e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36924
26285 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_smoke.3692426285
Directory /workspace/7.alert_handler_smoke/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all_with_rand_reset.2536558587
Short name T111
Test name
Test status
Simulation time 57291476616 ps
CPU time 6974.62 seconds
Started Jul 19 04:48:49 PM PDT 24
Finished Jul 19 06:45:20 PM PDT 24
Peak memory 372112 kb
Host smart-c8373bc3-854c-4c55-8dfa-05be14d358aa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536558587 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 7.alert_handler_stress_all_with_rand_reset.2536558587
Directory /workspace/7.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.alert_handler_alert_accum_saturation.1104393460
Short name T205
Test name
Test status
Simulation time 17664365 ps
CPU time 2.74 seconds
Started Jul 19 04:48:52 PM PDT 24
Finished Jul 19 04:49:09 PM PDT 24
Peak memory 249176 kb
Host smart-27258326-e326-4844-b2f9-aecdb6823ff6
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1104393460 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_alert_accum_saturation.1104393460
Directory /workspace/8.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/8.alert_handler_entropy.1463317814
Short name T412
Test name
Test status
Simulation time 6751241020 ps
CPU time 672.33 seconds
Started Jul 19 04:48:52 PM PDT 24
Finished Jul 19 05:00:19 PM PDT 24
Peak memory 273288 kb
Host smart-153a2ce3-4249-415e-bc1d-50e015cc675a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463317814 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy.1463317814
Directory /workspace/8.alert_handler_entropy/latest

Test location /workspace/coverage/default/8.alert_handler_entropy_stress.3965575380
Short name T695
Test name
Test status
Simulation time 283351494 ps
CPU time 16.03 seconds
Started Jul 19 04:48:58 PM PDT 24
Finished Jul 19 04:49:26 PM PDT 24
Peak memory 248900 kb
Host smart-e3ca318e-c379-4a52-a674-4cda6f5147b7
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3965575380 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy_stress.3965575380
Directory /workspace/8.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/8.alert_handler_esc_alert_accum.1932063322
Short name T421
Test name
Test status
Simulation time 4196465677 ps
CPU time 118 seconds
Started Jul 19 04:49:07 PM PDT 24
Finished Jul 19 04:51:15 PM PDT 24
Peak memory 256800 kb
Host smart-d49896a1-6bbd-43c8-b749-2f1000831dce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19320
63322 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_alert_accum.1932063322
Directory /workspace/8.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/8.alert_handler_esc_intr_timeout.127446634
Short name T535
Test name
Test status
Simulation time 1077520713 ps
CPU time 25.36 seconds
Started Jul 19 04:48:54 PM PDT 24
Finished Jul 19 04:49:33 PM PDT 24
Peak memory 256716 kb
Host smart-de82d02a-0daa-4dfb-b87c-31491fde3b0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12744
6634 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_intr_timeout.127446634
Directory /workspace/8.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_lpg.2087004583
Short name T632
Test name
Test status
Simulation time 9196530419 ps
CPU time 908.41 seconds
Started Jul 19 04:48:46 PM PDT 24
Finished Jul 19 05:04:10 PM PDT 24
Peak memory 273576 kb
Host smart-2d525a15-699d-45a7-8f8f-8ddebff8eb21
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087004583 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg.2087004583
Directory /workspace/8.alert_handler_lpg/latest

Test location /workspace/coverage/default/8.alert_handler_lpg_stub_clk.4276346149
Short name T327
Test name
Test status
Simulation time 55400487364 ps
CPU time 1542.9 seconds
Started Jul 19 04:48:55 PM PDT 24
Finished Jul 19 05:14:52 PM PDT 24
Peak memory 273520 kb
Host smart-7fb4e6d1-6292-47cb-ae84-9e257f72625f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276346149 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg_stub_clk.4276346149
Directory /workspace/8.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/8.alert_handler_ping_timeout.606982744
Short name T694
Test name
Test status
Simulation time 15369372713 ps
CPU time 618.24 seconds
Started Jul 19 04:48:59 PM PDT 24
Finished Jul 19 04:59:29 PM PDT 24
Peak memory 256104 kb
Host smart-47d25c0e-576d-4bb2-89a0-56e9e61ed79c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606982744 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_ping_timeout.606982744
Directory /workspace/8.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_random_alerts.200329372
Short name T706
Test name
Test status
Simulation time 786614959 ps
CPU time 28.66 seconds
Started Jul 19 04:48:43 PM PDT 24
Finished Jul 19 04:49:28 PM PDT 24
Peak memory 248976 kb
Host smart-26c60ee4-c74f-43f0-ae77-c52fdc60c946
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20032
9372 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_alerts.200329372
Directory /workspace/8.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/8.alert_handler_random_classes.749546851
Short name T109
Test name
Test status
Simulation time 1102420566 ps
CPU time 25.38 seconds
Started Jul 19 04:48:40 PM PDT 24
Finished Jul 19 04:49:23 PM PDT 24
Peak memory 256212 kb
Host smart-aa7275dd-e659-433e-b699-afd48562dd1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74954
6851 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_classes.749546851
Directory /workspace/8.alert_handler_random_classes/latest

Test location /workspace/coverage/default/8.alert_handler_sig_int_fail.655175247
Short name T120
Test name
Test status
Simulation time 307725968 ps
CPU time 32.02 seconds
Started Jul 19 04:48:54 PM PDT 24
Finished Jul 19 04:49:40 PM PDT 24
Peak memory 248368 kb
Host smart-7bd7cae3-f548-4914-b36c-9e14a3bb03ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65517
5247 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_sig_int_fail.655175247
Directory /workspace/8.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/8.alert_handler_smoke.432307258
Short name T417
Test name
Test status
Simulation time 147783302 ps
CPU time 4.11 seconds
Started Jul 19 04:48:45 PM PDT 24
Finished Jul 19 04:49:05 PM PDT 24
Peak memory 251880 kb
Host smart-8f0b7a46-a5f1-4c8f-99a3-3643c947b6ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43230
7258 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_smoke.432307258
Directory /workspace/8.alert_handler_smoke/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all.2495269855
Short name T251
Test name
Test status
Simulation time 106240640554 ps
CPU time 3110.65 seconds
Started Jul 19 04:48:53 PM PDT 24
Finished Jul 19 05:40:58 PM PDT 24
Peak memory 289960 kb
Host smart-f91d8432-4c0d-4af5-b003-4301a2e6acaa
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495269855 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_han
dler_stress_all.2495269855
Directory /workspace/8.alert_handler_stress_all/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all_with_rand_reset.1925833119
Short name T27
Test name
Test status
Simulation time 292700952297 ps
CPU time 4464.31 seconds
Started Jul 19 04:48:43 PM PDT 24
Finished Jul 19 06:03:24 PM PDT 24
Peak memory 333692 kb
Host smart-6480cdb8-9f08-4438-81e7-b0e88e0e62fa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925833119 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 8.alert_handler_stress_all_with_rand_reset.1925833119
Directory /workspace/8.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.alert_handler_alert_accum_saturation.593187042
Short name T212
Test name
Test status
Simulation time 23166781 ps
CPU time 2.58 seconds
Started Jul 19 04:48:53 PM PDT 24
Finished Jul 19 04:49:10 PM PDT 24
Peak memory 249252 kb
Host smart-07bfbec7-cf53-4f56-a9ec-8b5d945231eb
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=593187042 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_alert_accum_saturation.593187042
Directory /workspace/9.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/9.alert_handler_entropy.3315895835
Short name T541
Test name
Test status
Simulation time 104539175807 ps
CPU time 3512.41 seconds
Started Jul 19 04:48:51 PM PDT 24
Finished Jul 19 05:47:39 PM PDT 24
Peak memory 290100 kb
Host smart-584359ab-dfca-41f7-a220-b6004893fd2a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315895835 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy.3315895835
Directory /workspace/9.alert_handler_entropy/latest

Test location /workspace/coverage/default/9.alert_handler_entropy_stress.382409577
Short name T558
Test name
Test status
Simulation time 976340223 ps
CPU time 14.88 seconds
Started Jul 19 04:48:49 PM PDT 24
Finished Jul 19 04:49:18 PM PDT 24
Peak memory 248960 kb
Host smart-d10a5404-4872-4ba4-9384-7e843fa5e7bf
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=382409577 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy_stress.382409577
Directory /workspace/9.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/9.alert_handler_esc_alert_accum.1886387090
Short name T393
Test name
Test status
Simulation time 364363266 ps
CPU time 28.68 seconds
Started Jul 19 04:48:56 PM PDT 24
Finished Jul 19 04:49:38 PM PDT 24
Peak memory 256608 kb
Host smart-799bf02d-6ab2-4aaa-8bb8-563f16480f30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18863
87090 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_alert_accum.1886387090
Directory /workspace/9.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/9.alert_handler_esc_intr_timeout.4221693851
Short name T559
Test name
Test status
Simulation time 5787281333 ps
CPU time 53.86 seconds
Started Jul 19 04:48:45 PM PDT 24
Finished Jul 19 04:49:55 PM PDT 24
Peak memory 257156 kb
Host smart-c5c0afc0-dfd2-4e3b-bde5-572babcc571e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42216
93851 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_intr_timeout.4221693851
Directory /workspace/9.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_lpg.610808022
Short name T331
Test name
Test status
Simulation time 18408781020 ps
CPU time 1305.76 seconds
Started Jul 19 04:48:54 PM PDT 24
Finished Jul 19 05:10:54 PM PDT 24
Peak memory 286468 kb
Host smart-b166dffe-a111-4910-8031-741820c4b296
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610808022 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg.610808022
Directory /workspace/9.alert_handler_lpg/latest

Test location /workspace/coverage/default/9.alert_handler_lpg_stub_clk.3153283985
Short name T383
Test name
Test status
Simulation time 49803543031 ps
CPU time 1130.42 seconds
Started Jul 19 04:48:43 PM PDT 24
Finished Jul 19 05:07:50 PM PDT 24
Peak memory 282348 kb
Host smart-a6f4023a-3ab8-4494-8ba2-475ed7e2b1b1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153283985 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg_stub_clk.3153283985
Directory /workspace/9.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/9.alert_handler_ping_timeout.1196752152
Short name T316
Test name
Test status
Simulation time 3276710102 ps
CPU time 141.93 seconds
Started Jul 19 04:48:44 PM PDT 24
Finished Jul 19 04:51:23 PM PDT 24
Peak memory 255228 kb
Host smart-73504fe2-6fe8-450e-a77f-cd487fac3776
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196752152 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_ping_timeout.1196752152
Directory /workspace/9.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_random_alerts.2165673168
Short name T685
Test name
Test status
Simulation time 2088838830 ps
CPU time 19.38 seconds
Started Jul 19 04:48:47 PM PDT 24
Finished Jul 19 04:49:22 PM PDT 24
Peak memory 248792 kb
Host smart-ebff21e0-c953-4434-98c5-bea0e7d181f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21656
73168 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_alerts.2165673168
Directory /workspace/9.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/9.alert_handler_random_classes.2918567794
Short name T674
Test name
Test status
Simulation time 470141558 ps
CPU time 25.86 seconds
Started Jul 19 04:48:57 PM PDT 24
Finished Jul 19 04:49:36 PM PDT 24
Peak memory 256220 kb
Host smart-f0487a23-fdb4-4339-824f-894fb582333d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29185
67794 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_classes.2918567794
Directory /workspace/9.alert_handler_random_classes/latest

Test location /workspace/coverage/default/9.alert_handler_sig_int_fail.4166751984
Short name T413
Test name
Test status
Simulation time 473997516 ps
CPU time 24.45 seconds
Started Jul 19 04:48:48 PM PDT 24
Finished Jul 19 04:49:27 PM PDT 24
Peak memory 248956 kb
Host smart-b0479ac2-8ff0-40aa-b1f9-d29fbc000b3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41667
51984 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_sig_int_fail.4166751984
Directory /workspace/9.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/9.alert_handler_smoke.3563351251
Short name T487
Test name
Test status
Simulation time 530421099 ps
CPU time 19.04 seconds
Started Jul 19 04:48:44 PM PDT 24
Finished Jul 19 04:49:19 PM PDT 24
Peak memory 248876 kb
Host smart-9a856794-84d7-45c0-aa0d-a2349fe27cbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35633
51251 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_smoke.3563351251
Directory /workspace/9.alert_handler_smoke/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all.1014130757
Short name T291
Test name
Test status
Simulation time 122457846213 ps
CPU time 1162.08 seconds
Started Jul 19 04:48:56 PM PDT 24
Finished Jul 19 05:08:32 PM PDT 24
Peak memory 287028 kb
Host smart-a0e67a7c-b204-46b9-a151-05b4b253f908
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014130757 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_han
dler_stress_all.1014130757
Directory /workspace/9.alert_handler_stress_all/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all_with_rand_reset.244232909
Short name T235
Test name
Test status
Simulation time 96150953016 ps
CPU time 2918.94 seconds
Started Jul 19 04:48:52 PM PDT 24
Finished Jul 19 05:37:46 PM PDT 24
Peak memory 306092 kb
Host smart-ca5b1728-d3c1-4d1d-b071-f41af1b8b354
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244232909 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 9.alert_handler_stress_all_with_rand_reset.244232909
Directory /workspace/9.alert_handler_stress_all_with_rand_reset/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%