Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
esc_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	8	0	8	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	65413	1			T4	2		T5	508		T8	7
class_i[0x1]	55733	1			T4	1		T5	78		T17	11
class_i[0x2]	53695	1			T5	2492		T8	5		T12	20
class_i[0x3]	40521	1			T4	2		T8	3		T22	106

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Summary for Variable esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	51968	1			T4	1		T5	811		T8	5
alert[0x1]	55916	1			T4	1		T5	725		T8	5
alert[0x2]	53395	1			T4	2		T5	756		T8	4
alert[0x3]	54083	1			T4	1		T5	786		T8	1

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Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

esc_integrity_fail

215090

1

T4

1

T5

3078

T8

8

esc_ping_fail

272

1

T4

4

T8

7

T12

7

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Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	esc_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	alert[0x0]	51893	1			T5	811		T8	3		T22	16
esc_integrity_fail	alert[0x1]	55840	1			T5	725		T8	3		T22	32
esc_integrity_fail	alert[0x2]	53334	1			T4	1		T5	756		T8	2
esc_integrity_fail	alert[0x3]	54023	1			T5	786		T22	508		T12	4
esc_ping_fail	alert[0x0]	75	1			T4	1		T8	2		T12	2
esc_ping_fail	alert[0x1]	76	1			T4	1		T8	2		T12	1
esc_ping_fail	alert[0x2]	61	1			T4	1		T8	2		T12	2
esc_ping_fail	alert[0x3]	60	1			T4	1		T8	1		T12	2

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Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	class_i[0x0]	65347	1			T5	508		T22	484		T16	149
esc_integrity_fail	class_i[0x1]	55667	1			T4	1		T5	78		T17	11
esc_integrity_fail	class_i[0x2]	53610	1			T5	2492		T8	5		T12	13
esc_integrity_fail	class_i[0x3]	40466	1			T8	3		T22	106		T16	136
esc_ping_fail	class_i[0x0]	66	1			T4	2		T8	7		T55	3
esc_ping_fail	class_i[0x1]	66	1			T55	1		T216	6		T285	7
esc_ping_fail	class_i[0x2]	85	1			T12	7		T55	2		T314	8
esc_ping_fail	class_i[0x3]	55	1			T4	2		T186	6		T55	2