Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
94.44	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	40	3	37	92.50

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
intr_timeout_cnt_cp	10	0	10	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	40	3	37	92.50	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	81	1			T5	1		T16	1		T27	4
class_index[0x1]	56	1			T5	3		T16	2		T24	1
class_index[0x2]	58	1			T5	1		T6	1		T22	1
class_index[0x3]	59	1			T7	1		T5	1		T6	1

---

Summary for Variable intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for intr_timeout_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
intr_timeout_cnt[0]	100	1			T5	2		T16	1		T24	2
intr_timeout_cnt[1]	51	1			T7	1		T5	1		T6	2
intr_timeout_cnt[2]	26	1			T5	1		T16	1		T27	1
intr_timeout_cnt[3]	20	1			T16	2		T244	1		T245	2
intr_timeout_cnt[4]	15	1			T5	1		T72	1		T47	1
intr_timeout_cnt[5]	14	1			T36	1		T75	1		T101	1
intr_timeout_cnt[6]	4	1			T101	2		T246	1		T247	1
intr_timeout_cnt[7]	9	1			T22	1		T100	1		T244	1
intr_timeout_cnt[8]	7	1			T5	1		T24	1		T27	1
intr_timeout_cnt[9]	8	1			T27	1		T101	3		T108	1

---

Summary for Cross class_cnt_cross

Samples crossed: class_index_cp intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	3	37	92.50	3

Automatically Generated Cross Bins for class_cnt_cross

Uncovered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	NUMBER	STATUS
[class_index[0x0]]	[intr_timeout_cnt[6]]	0	1	1
[class_index[0x2]]	[intr_timeout_cnt[6]]	0	1	1
[class_index[0x2]]	[intr_timeout_cnt[9]]	0	1	1

Covered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	intr_timeout_cnt[0]	28	1			T5	1		T67	1		T25	1
class_index[0x0]	intr_timeout_cnt[1]	23	1			T16	1		T27	3		T75	1
class_index[0x0]	intr_timeout_cnt[2]	10	1			T27	1		T68	1		T71	1
class_index[0x0]	intr_timeout_cnt[3]	4	1			T245	1		T248	1		T249	1
class_index[0x0]	intr_timeout_cnt[4]	2	1			T47	1		T250	1		-	-
class_index[0x0]	intr_timeout_cnt[5]	4	1			T248	1		T251	1		T252	1
class_index[0x0]	intr_timeout_cnt[7]	3	1			T244	1		T96	1		T253	1
class_index[0x0]	intr_timeout_cnt[8]	2	1			T254	1		T255	1		-	-
class_index[0x0]	intr_timeout_cnt[9]	5	1			T101	3		T108	1		T92	1
class_index[0x1]	intr_timeout_cnt[0]	18	1			T24	1		T27	1		T69	1
class_index[0x1]	intr_timeout_cnt[1]	12	1			T27	1		T76	1		T78	1
class_index[0x1]	intr_timeout_cnt[2]	7	1			T5	1		T16	1		T254	1
class_index[0x1]	intr_timeout_cnt[3]	3	1			T16	1		T256	1		T113	1
class_index[0x1]	intr_timeout_cnt[4]	5	1			T5	1		T257	1		T113	1
class_index[0x1]	intr_timeout_cnt[5]	5	1			T75	1		T101	1		T245	1
class_index[0x1]	intr_timeout_cnt[6]	1	1			T246	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[7]	1	1			T258	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[8]	2	1			T5	1		T109	1		-	-
class_index[0x1]	intr_timeout_cnt[9]	2	1			T27	1		T253	1		-	-
class_index[0x2]	intr_timeout_cnt[0]	26	1			T16	1		T27	1		T85	3
class_index[0x2]	intr_timeout_cnt[1]	9	1			T5	1		T6	1		T24	1
class_index[0x2]	intr_timeout_cnt[2]	6	1			T71	1		T82	1		T108	1
class_index[0x2]	intr_timeout_cnt[3]	8	1			T16	1		T244	1		T248	1
class_index[0x2]	intr_timeout_cnt[4]	3	1			T72	1		T259	1		T184	1
class_index[0x2]	intr_timeout_cnt[5]	2	1			T255	1		T113	1		-	-
class_index[0x2]	intr_timeout_cnt[7]	3	1			T22	1		T260	1		T225	1
class_index[0x2]	intr_timeout_cnt[8]	1	1			T24	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[0]	28	1			T5	1		T24	1		T39	1
class_index[0x3]	intr_timeout_cnt[1]	7	1			T7	1		T6	1		T105	2
class_index[0x3]	intr_timeout_cnt[2]	3	1			T46	1		T51	1		T261	1
class_index[0x3]	intr_timeout_cnt[3]	5	1			T245	1		T102	1		T262	1
class_index[0x3]	intr_timeout_cnt[4]	5	1			T92	1		T263	1		T259	2
class_index[0x3]	intr_timeout_cnt[5]	3	1			T36	1		T239	1		T258	1
class_index[0x3]	intr_timeout_cnt[6]	3	1			T101	2		T247	1		-	-
class_index[0x3]	intr_timeout_cnt[7]	2	1			T100	1		T264	1		-	-
class_index[0x3]	intr_timeout_cnt[8]	2	1			T27	1		T249	1		-	-
class_index[0x3]	intr_timeout_cnt[9]	1	1			T265	1		-	-		-	-