Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	348688	1			T1	195		T2	19		T3	7
all_values[1]	348688	1			T1	195		T2	19		T3	7
all_values[2]	348688	1			T1	195		T2	19		T3	7
all_values[3]	348688	1			T1	195		T2	19		T3	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

692675

1

T1

397

T2

45

T3

12

auto[1]

702077

1

T1

383

T2

31

T3

16

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

837593

1

T1

392

T2

40

T3

16

auto[1]

557159

1

T1

388

T2

36

T3

12

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	99579	1			T1	44		T2	5		T18	7
all_values[0]	auto[0]	auto[1]	73415	1			T1	44		T2	5		T18	7
all_values[0]	auto[1]	auto[0]	101556	1			T1	54		T2	5		T3	4
all_values[0]	auto[1]	auto[1]	74138	1			T1	53		T2	4		T3	3
all_values[1]	auto[0]	auto[0]	104987	1			T1	52		T2	6		T3	2
all_values[1]	auto[0]	auto[1]	68247	1			T1	51		T2	5		T3	1
all_values[1]	auto[1]	auto[0]	106662	1			T1	46		T2	4		T3	2
all_values[1]	auto[1]	auto[1]	68792	1			T1	46		T2	4		T3	2
all_values[2]	auto[0]	auto[0]	104695	1			T1	56		T2	7		T3	3
all_values[2]	auto[0]	auto[1]	68793	1			T1	55		T2	6		T3	2
all_values[2]	auto[1]	auto[0]	106256	1			T1	42		T2	3		T3	1
all_values[2]	auto[1]	auto[1]	68944	1			T1	42		T2	3		T3	1
all_values[3]	auto[0]	auto[0]	105864	1			T1	48		T2	6		T3	2
all_values[3]	auto[0]	auto[1]	67095	1			T1	47		T2	5		T3	2
all_values[3]	auto[1]	auto[0]	107994	1			T1	50		T2	4		T3	2
all_values[3]	auto[1]	auto[1]	67735	1			T1	50		T2	4		T3	1