Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	4	0	4	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	348688	1			T1	195		T2	19		T3	7
all_pins[1]	348688	1			T1	195		T2	19		T3	7
all_pins[2]	348688	1			T1	195		T2	19		T3	7
all_pins[3]	348688	1			T1	195		T2	19		T3	7

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1115143	1			T1	589		T2	61		T3	21
values[0x1]	279609	1			T1	191		T2	15		T3	7
transitions[0x0=>0x1]	186403	1			T1	121		T2	10		T3	3
transitions[0x1=>0x0]	186660	1			T1	122		T2	10		T3	4

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	274550	1			T1	142		T2	15		T3	4
all_pins[0]	values[0x1]	74138	1			T1	53		T2	4		T3	3
all_pins[0]	transitions[0x0=>0x1]	73475	1			T1	52		T2	4		T3	2
all_pins[0]	transitions[0x1=>0x0]	67329	1			T1	50		T2	4		T3	1
all_pins[1]	values[0x0]	279896	1			T1	149		T2	15		T3	5
all_pins[1]	values[0x1]	68792	1			T1	46		T2	4		T3	2
all_pins[1]	transitions[0x0=>0x1]	37536	1			T1	22		T2	2		T4	7
all_pins[1]	transitions[0x1=>0x0]	42882	1			T1	29		T2	2		T3	1
all_pins[2]	values[0x0]	279744	1			T1	153		T2	16		T3	6
all_pins[2]	values[0x1]	68944	1			T1	42		T2	3		T3	1
all_pins[2]	transitions[0x0=>0x1]	37988	1			T1	21		T2	2		T7	1
all_pins[2]	transitions[0x1=>0x0]	37836	1			T1	25		T2	3		T3	1
all_pins[3]	values[0x0]	280953	1			T1	145		T2	15		T3	6
all_pins[3]	values[0x1]	67735	1			T1	50		T2	4		T3	1
all_pins[3]	transitions[0x0=>0x1]	37404	1			T1	26		T2	2		T3	1
all_pins[3]	transitions[0x1=>0x0]	38613	1			T1	18		T2	1		T3	1