Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
accum_cnt_cp	6	0	6	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	24	0	24	100.00	100	1	1	0

Summary for Variable accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for accum_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
accum_cnt_2000	78351	1			T5	532		T10	212		T17	672
accum_cnt_1000	221460	1			T1	64		T5	2380		T19	31
accum_cnt_100	28985	1			T1	14		T5	311		T19	41
accum_cnt_50	63515	1			T1	14		T2	26		T18	30
accum_cnt_10	186882	1			T1	199		T2	39		T3	18
accum_cnt_0	405392	1			T1	97		T2	7		T3	6

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Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	256908	1			T1	97		T2	18		T3	6
class_index[0x1]	256908	1			T1	97		T2	18		T3	6
class_index[0x2]	256908	1			T1	97		T2	18		T3	6
class_index[0x3]	256908	1			T1	97		T2	18		T3	6

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Summary for Cross class_cnt_cross

Samples crossed: class_index_cp accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for class_cnt_cross

Bins

class_index_cp	accum_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	accum_cnt_2000	22195	1			T10	212		T17	234		T64	583
class_index[0x0]	accum_cnt_1000	66256	1			T5	91		T19	11		T10	374
class_index[0x0]	accum_cnt_100	10066	1			T5	61		T19	22		T22	38
class_index[0x0]	accum_cnt_50	14405	1			T2	8		T18	2		T5	66
class_index[0x0]	accum_cnt_10	49291	1			T1	97		T2	10		T3	2
class_index[0x0]	accum_cnt_0	82853	1			T3	4		T7	4		T4	20
class_index[0x1]	accum_cnt_2000	16193	1			T5	58		T54	39		T25	6
class_index[0x1]	accum_cnt_1000	49948	1			T1	64		T5	874		T22	28
class_index[0x1]	accum_cnt_100	6523	1			T1	14		T5	64		T22	20
class_index[0x1]	accum_cnt_50	18276	1			T1	14		T2	8		T18	11
class_index[0x1]	accum_cnt_10	40406	1			T1	5		T2	6		T3	6
class_index[0x1]	accum_cnt_0	116608	1			T2	4		T7	1		T4	18
class_index[0x2]	accum_cnt_2000	17860	1			T5	324		T94	288		T38	232
class_index[0x2]	accum_cnt_1000	50041	1			T5	420		T16	117		T80	701
class_index[0x2]	accum_cnt_100	5834	1			T5	58		T16	148		T80	154
class_index[0x2]	accum_cnt_50	15313	1			T2	10		T18	17		T5	58
class_index[0x2]	accum_cnt_10	56183	1			T1	97		T2	8		T3	4
class_index[0x2]	accum_cnt_0	99484	1			T3	2		T7	1		T4	25
class_index[0x3]	accum_cnt_2000	22103	1			T5	150		T17	438		T94	249
class_index[0x3]	accum_cnt_1000	55215	1			T5	995		T19	20		T16	321
class_index[0x3]	accum_cnt_100	6562	1			T5	128		T19	19		T22	2
class_index[0x3]	accum_cnt_50	15521	1			T5	101		T19	12		T6	18
class_index[0x3]	accum_cnt_10	41002	1			T2	15		T3	6		T7	2
class_index[0x3]	accum_cnt_0	106447	1			T1	97		T2	3		T7	2