Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	69	0	69	100.00
Crosses	260	0	260	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
alert_cause_cp	65	0	65	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
alert_cause_cross_class_index	260	0	260	100.00	100	1	1	0

Summary for Variable alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	29830	1			T1	50		T2	4		T3	1
alert[0x1]	29724	1			T2	2		T3	2		T18	2
alert[0x2]	29410	1			T1	38		T18	3		T5	321
alert[0x3]	28203	1			T1	40		T2	2		T3	3
alert[0x4]	31707	1			T2	3		T7	1		T18	1
alert[0x5]	30993	1			T1	56		T2	2		T3	2
alert[0x6]	36158	1			T1	49		T2	3		T7	1
alert[0x7]	35894	1			T1	2		T7	1		T18	3
alert[0x8]	36029	1			T1	43		T2	4		T3	3
alert[0x9]	27654	1			T1	46		T7	1		T18	3
alert[0xa]	32602	1			T7	1		T18	7		T5	272
alert[0xb]	28642	1			T1	52		T2	3		T7	1
alert[0xc]	28409	1			T1	39		T7	2		T18	3
alert[0xd]	27833	1			T1	43		T3	3		T18	4
alert[0xe]	28545	1			T2	6		T7	1		T18	5
alert[0xf]	31387	1			T2	3		T3	2		T18	8
alert[0x10]	26669	1			T1	1		T7	1		T18	4
alert[0x11]	31488	1			T2	5		T18	6		T5	78
alert[0x12]	32002	1			T2	4		T3	3		T18	3
alert[0x13]	33718	1			T1	2		T2	4		T3	1
alert[0x14]	31233	1			T1	52		T2	5		T7	1
alert[0x15]	35055	1			T1	41		T3	1		T7	2
alert[0x16]	34201	1			T1	48		T2	4		T3	1
alert[0x17]	30888	1			T3	2		T7	1		T18	4
alert[0x18]	29470	1			T3	2		T7	2		T18	3
alert[0x19]	28233	1			T1	45		T2	3		T3	2
alert[0x1a]	29115	1			T18	2		T5	57		T19	31
alert[0x1b]	29697	1			T1	50		T18	3		T5	105
alert[0x1c]	28751	1			T2	1		T3	2		T7	1
alert[0x1d]	32349	1			T1	42		T2	4		T7	1
alert[0x1e]	27327	1			T1	47		T7	1		T18	6
alert[0x1f]	36452	1			T1	46		T3	1		T18	2
alert[0x20]	29615	1			T1	1		T18	8		T5	29
alert[0x21]	31034	1			T1	49		T3	1		T18	1
alert[0x22]	33715	1			T1	1		T3	1		T7	1
alert[0x23]	27240	1			T18	6		T5	61		T19	2
alert[0x24]	29274	1			T1	50		T3	1		T18	2
alert[0x25]	31338	1			T2	6		T3	1		T18	6
alert[0x26]	30998	1			T1	40		T2	1		T3	3
alert[0x27]	28892	1			T7	2		T18	1		T5	330
alert[0x28]	33959	1			T1	49		T7	1		T18	3
alert[0x29]	28534	1			T1	43		T2	5		T7	1
alert[0x2a]	32025	1			T1	53		T3	2		T7	1
alert[0x2b]	31828	1			T1	46		T2	4		T3	2
alert[0x2c]	33621	1			T1	42		T2	6		T18	3
alert[0x2d]	31624	1			T1	2		T18	5		T5	300
alert[0x2e]	34599	1			T1	50		T3	2		T18	6
alert[0x2f]	30433	1			T1	48		T2	1		T7	3
alert[0x30]	31192	1			T3	2		T18	4		T5	83
alert[0x31]	30988	1			T1	53		T2	3		T7	2
alert[0x32]	30877	1			T2	3		T3	1		T18	3
alert[0x33]	28927	1			T1	2		T2	3		T3	1
alert[0x34]	31297	1			T1	52		T2	2		T18	2
alert[0x35]	28718	1			T2	1		T3	1		T18	1
alert[0x36]	28489	1			T1	40		T18	5		T5	310
alert[0x37]	29086	1			T1	50		T2	4		T18	2
alert[0x38]	30960	1			T1	42		T7	1		T18	4
alert[0x39]	28802	1			T1	1		T2	6		T7	1
alert[0x3a]	30888	1			T2	1		T18	5		T5	98
alert[0x3b]	30124	1			T1	49		T2	5		T7	1
alert[0x3c]	29250	1			T1	45		T2	1		T3	3
alert[0x3d]	31011	1			T1	48		T2	2		T3	1
alert[0x3e]	28608	1			T2	3		T18	4		T5	284
alert[0x3f]	29319	1			T1	47		T2	6		T18	4
alert[0x40]	28954	1			T1	53		T3	2		T7	1

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	580281	1			T1	415		T2	33		T3	9
class_i[0x1]	477962	1			T1	443		T2	26		T3	13
class_i[0x2]	471381	1			T1	512		T2	35		T3	19
class_i[0x3]	466263	1			T1	418		T2	31		T3	14

---

Summary for Cross alert_cause_cross_class_index

Samples crossed: alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	260	0	260	100.00

Automatically Generated Cross Bins for alert_cause_cross_class_index

Bins

alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	class_i[0x0]	9566	1			T18	1		T5	30		T19	3
alert[0x0]	class_i[0x1]	7996	1			T1	50		T3	1		T18	2
alert[0x0]	class_i[0x2]	7054	1			T2	4		T18	1		T5	222
alert[0x0]	class_i[0x3]	5214	1			T18	1		T5	2		T20	1
alert[0x1]	class_i[0x0]	8779	1			T5	2		T20	1		T22	21
alert[0x1]	class_i[0x1]	6027	1			T2	1		T3	2		T18	2
alert[0x1]	class_i[0x2]	7624	1			T2	1		T5	5		T19	3
alert[0x1]	class_i[0x3]	7294	1			T5	26		T20	4		T22	4
alert[0x2]	class_i[0x0]	8472	1			T1	38		T18	1		T5	256
alert[0x2]	class_i[0x1]	8490	1			T5	3		T20	2		T10	1
alert[0x2]	class_i[0x2]	5089	1			T18	1		T5	27		T16	46
alert[0x2]	class_i[0x3]	7359	1			T18	1		T5	35		T19	1
alert[0x3]	class_i[0x0]	7870	1			T1	40		T2	2		T5	228
alert[0x3]	class_i[0x1]	6896	1			T18	1		T5	1		T20	2
alert[0x3]	class_i[0x2]	9287	1			T3	2		T18	1		T5	19
alert[0x3]	class_i[0x3]	4150	1			T3	1		T18	3		T5	23
alert[0x4]	class_i[0x0]	8788	1			T2	2		T7	1		T5	17
alert[0x4]	class_i[0x1]	7061	1			T5	258		T22	12		T10	1
alert[0x4]	class_i[0x2]	6742	1			T5	1		T19	1		T22	2
alert[0x4]	class_i[0x3]	9116	1			T2	1		T18	1		T5	32
alert[0x5]	class_i[0x0]	11215	1			T2	2		T7	1		T5	240
alert[0x5]	class_i[0x1]	7785	1			T1	53		T18	1		T5	1
alert[0x5]	class_i[0x2]	5166	1			T3	2		T18	1		T19	15
alert[0x5]	class_i[0x3]	6827	1			T1	3		T18	1		T5	27
alert[0x6]	class_i[0x0]	10466	1			T1	1		T2	1		T5	6
alert[0x6]	class_i[0x1]	8941	1			T2	1		T7	1		T18	2
alert[0x6]	class_i[0x2]	9326	1			T2	1		T5	1		T19	1
alert[0x6]	class_i[0x3]	7425	1			T1	48		T18	3		T5	21
alert[0x7]	class_i[0x0]	9668	1			T1	1		T5	28		T21	1
alert[0x7]	class_i[0x1]	7485	1			T1	1		T7	1		T18	2
alert[0x7]	class_i[0x2]	8515	1			T18	1		T5	6		T19	1
alert[0x7]	class_i[0x3]	10226	1			T5	63		T20	1		T22	9
alert[0x8]	class_i[0x0]	9847	1			T2	4		T6	7		T22	2
alert[0x8]	class_i[0x1]	8801	1			T1	41		T5	1		T19	2
alert[0x8]	class_i[0x2]	8066	1			T3	3		T5	7		T19	27
alert[0x8]	class_i[0x3]	9315	1			T1	2		T7	1		T18	3
alert[0x9]	class_i[0x0]	6083	1			T7	1		T18	1		T5	53
alert[0x9]	class_i[0x1]	7247	1			T18	2		T5	4		T22	1
alert[0x9]	class_i[0x2]	6721	1			T1	46		T5	45		T19	1
alert[0x9]	class_i[0x3]	7603	1			T5	1		T22	8		T10	1
alert[0xa]	class_i[0x0]	9790	1			T18	1		T5	1		T19	8
alert[0xa]	class_i[0x1]	8816	1			T7	1		T18	1		T5	28
alert[0xa]	class_i[0x2]	6785	1			T18	1		T5	43		T19	2
alert[0xa]	class_i[0x3]	7211	1			T18	4		T5	200		T19	1
alert[0xb]	class_i[0x0]	6690	1			T5	32		T19	1		T6	1
alert[0xb]	class_i[0x1]	6126	1			T1	52		T5	1		T6	1
alert[0xb]	class_i[0x2]	9207	1			T2	3		T7	1		T18	1
alert[0xb]	class_i[0x3]	6619	1			T5	28		T19	2		T10	190
alert[0xc]	class_i[0x0]	7641	1			T7	1		T22	22		T16	62
alert[0xc]	class_i[0x1]	5925	1			T18	1		T5	1		T19	27
alert[0xc]	class_i[0x2]	7688	1			T7	1		T18	2		T5	70
alert[0xc]	class_i[0x3]	7155	1			T1	39		T5	58		T6	6
alert[0xd]	class_i[0x0]	8556	1			T3	1		T19	1		T22	3
alert[0xd]	class_i[0x1]	7529	1			T18	1		T5	2		T19	1
alert[0xd]	class_i[0x2]	5387	1			T1	43		T3	2		T18	1
alert[0xd]	class_i[0x3]	6361	1			T18	2		T5	29		T22	8
alert[0xe]	class_i[0x0]	8794	1			T18	2		T5	18		T19	1
alert[0xe]	class_i[0x1]	6742	1			T18	1		T19	2		T22	4
alert[0xe]	class_i[0x2]	7353	1			T2	6		T7	1		T5	23
alert[0xe]	class_i[0x3]	5656	1			T18	2		T5	3		T20	1
alert[0xf]	class_i[0x0]	11399	1			T18	1		T5	234		T6	1
alert[0xf]	class_i[0x1]	6194	1			T3	1		T18	1		T5	28
alert[0xf]	class_i[0x2]	6507	1			T2	3		T5	4		T20	1
alert[0xf]	class_i[0x3]	7287	1			T3	1		T18	6		T5	35
alert[0x10]	class_i[0x0]	6434	1			T5	4		T19	2		T6	1
alert[0x10]	class_i[0x1]	6709	1			T1	1		T7	1		T18	2
alert[0x10]	class_i[0x2]	6261	1			T5	36		T20	2		T22	1
alert[0x10]	class_i[0x3]	7265	1			T18	2		T5	44		T10	1
alert[0x11]	class_i[0x0]	9301	1			T18	3		T5	4		T20	1
alert[0x11]	class_i[0x1]	8335	1			T5	1		T20	1		T22	1
alert[0x11]	class_i[0x2]	7510	1			T18	2		T5	37		T22	2
alert[0x11]	class_i[0x3]	6342	1			T2	5		T18	1		T5	36
alert[0x12]	class_i[0x0]	10222	1			T18	1		T5	20		T19	15
alert[0x12]	class_i[0x1]	7463	1			T18	1		T5	29		T19	1
alert[0x12]	class_i[0x2]	6167	1			T2	4		T18	1		T5	30
alert[0x12]	class_i[0x3]	8150	1			T3	3		T5	28		T19	2
alert[0x13]	class_i[0x0]	9156	1			T1	1		T18	2		T5	27
alert[0x13]	class_i[0x1]	9168	1			T7	1		T18	1		T5	59
alert[0x13]	class_i[0x2]	9143	1			T1	1		T5	36		T22	13
alert[0x13]	class_i[0x3]	6251	1			T2	4		T3	1		T18	3
alert[0x14]	class_i[0x0]	10687	1			T18	1		T5	59		T22	18
alert[0x14]	class_i[0x1]	7686	1			T5	3		T20	2		T22	17
alert[0x14]	class_i[0x2]	6090	1			T1	52		T18	3		T5	31
alert[0x14]	class_i[0x3]	6770	1			T2	5		T7	1		T5	205
alert[0x15]	class_i[0x0]	10889	1			T1	1		T5	7		T22	2
alert[0x15]	class_i[0x1]	6615	1			T18	3		T5	27		T6	10
alert[0x15]	class_i[0x2]	9714	1			T5	33		T19	1		T9	191
alert[0x15]	class_i[0x3]	7837	1			T1	40		T3	1		T7	2
alert[0x16]	class_i[0x0]	8673	1			T2	1		T5	66		T16	19
alert[0x16]	class_i[0x1]	8665	1			T1	47		T3	1		T18	2
alert[0x16]	class_i[0x2]	9244	1			T1	1		T2	3		T20	1
alert[0x16]	class_i[0x3]	7619	1			T18	1		T19	16		T20	1
alert[0x17]	class_i[0x0]	8295	1			T18	1		T5	8		T19	1
alert[0x17]	class_i[0x1]	7717	1			T18	1		T5	60		T19	24
alert[0x17]	class_i[0x2]	6593	1			T3	2		T7	1		T18	1
alert[0x17]	class_i[0x3]	8283	1			T18	1		T5	28		T16	34
alert[0x18]	class_i[0x0]	11636	1			T3	2		T18	1		T5	213
alert[0x18]	class_i[0x1]	5772	1			T7	2		T18	2		T5	11
alert[0x18]	class_i[0x2]	5428	1			T5	49		T19	1		T6	1
alert[0x18]	class_i[0x3]	6634	1			T5	4		T20	1		T16	1
alert[0x19]	class_i[0x0]	8077	1			T2	2		T5	38		T19	25
alert[0x19]	class_i[0x1]	7214	1			T1	45		T18	1		T19	1
alert[0x19]	class_i[0x2]	6150	1			T18	1		T6	9		T20	3
alert[0x19]	class_i[0x3]	6792	1			T2	1		T3	2		T5	45
alert[0x1a]	class_i[0x0]	10375	1			T5	25		T19	1		T20	1
alert[0x1a]	class_i[0x1]	7145	1			T18	1		T5	3		T19	29
alert[0x1a]	class_i[0x2]	5403	1			T5	2		T19	1		T20	3
alert[0x1a]	class_i[0x3]	6192	1			T18	1		T5	27		T20	1
alert[0x1b]	class_i[0x0]	10394	1			T5	30		T6	8		T22	4
alert[0x1b]	class_i[0x1]	5782	1			T18	1		T5	1		T22	1
alert[0x1b]	class_i[0x2]	5418	1			T1	50		T5	73		T22	24
alert[0x1b]	class_i[0x3]	8103	1			T18	2		T5	1		T19	23
alert[0x1c]	class_i[0x0]	8532	1			T5	6		T6	6		T22	21
alert[0x1c]	class_i[0x1]	5397	1			T3	2		T18	1		T5	30
alert[0x1c]	class_i[0x2]	7893	1			T7	1		T5	32		T20	1
alert[0x1c]	class_i[0x3]	6929	1			T2	1		T18	3		T5	21
alert[0x1d]	class_i[0x0]	7796	1			T1	42		T2	4		T18	2
alert[0x1d]	class_i[0x1]	8687	1			T7	1		T5	251		T22	3
alert[0x1d]	class_i[0x2]	7613	1			T18	1		T27	57		T240	10
alert[0x1d]	class_i[0x3]	8253	1			T18	1		T5	56		T10	1
alert[0x1e]	class_i[0x0]	7361	1			T7	1		T18	1		T5	1
alert[0x1e]	class_i[0x1]	5513	1			T5	2		T20	1		T22	1
alert[0x1e]	class_i[0x2]	6961	1			T1	47		T18	1		T5	38
alert[0x1e]	class_i[0x3]	7492	1			T18	4		T5	29		T19	23
alert[0x1f]	class_i[0x0]	9185	1			T1	1		T18	1		T22	1
alert[0x1f]	class_i[0x1]	8867	1			T18	1		T5	26		T22	36
alert[0x1f]	class_i[0x2]	9551	1			T5	26		T19	1		T22	2
alert[0x1f]	class_i[0x3]	8849	1			T1	45		T3	1		T5	17
alert[0x20]	class_i[0x0]	8149	1			T18	4		T5	25		T19	1
alert[0x20]	class_i[0x1]	4994	1			T1	1		T18	2		T5	1
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alert[0x20]	class_i[0x3]	7658	1			T18	2		T5	3		T20	1
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alert[0x21]	class_i[0x1]	9589	1			T5	32		T19	1		T22	5
alert[0x21]	class_i[0x2]	5316	1			T18	1		T5	51		T19	20
alert[0x21]	class_i[0x3]	7208	1			T3	1		T5	38		T20	1
alert[0x22]	class_i[0x0]	8554	1			T18	1		T5	40		T20	1
alert[0x22]	class_i[0x1]	7927	1			T1	1		T3	1		T5	2
alert[0x22]	class_i[0x2]	7546	1			T7	1		T18	3		T5	31
alert[0x22]	class_i[0x3]	9688	1			T18	1		T5	36		T20	1
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alert[0x23]	class_i[0x1]	6167	1			T18	1		T5	27		T19	1
alert[0x23]	class_i[0x2]	8138	1			T19	1		T9	1		T16	1
alert[0x23]	class_i[0x3]	5552	1			T18	3		T5	3		T6	1
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alert[0x24]	class_i[0x1]	7206	1			T18	1		T5	2		T19	1
alert[0x24]	class_i[0x2]	7697	1			T1	50		T3	1		T5	2
alert[0x24]	class_i[0x3]	6934	1			T5	15		T22	32		T9	2
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alert[0x25]	class_i[0x1]	7938	1			T2	6		T18	3		T5	250
alert[0x25]	class_i[0x2]	6916	1			T5	3		T20	1		T22	2
alert[0x25]	class_i[0x3]	7755	1			T3	1		T18	3		T5	1
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alert[0x29]	class_i[0x3]	6607	1			T1	1		T2	5		T18	1
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alert[0x3a]	class_i[0x0]	7061	1			T18	1		T5	76		T19	33
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alert[0x40]	class_i[0x1]	6372	1			T7	1		T18	3		T5	20
alert[0x40]	class_i[0x2]	6351	1			T18	1		T5	46		T19	1
alert[0x40]	class_i[0x3]	7698	1			T1	53		T5	210		T19	1