Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	71	0	71	100.00
Crosses	138	0	138	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
alert_index_cp	65	0	65	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	130	0	130	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for alert_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	3262	1			T22	4		T17	23		T221	7
alert[0x1]	696	1			T16	2		T27	5		T63	8
alert[0x2]	4063	1			T16	103		T17	486		T27	37
alert[0x3]	9238	1			T4	1		T63	145		T38	19
alert[0x4]	2635	1			T16	66		T17	140		T27	13
alert[0x5]	6067	1			T221	1		T63	153		T53	2
alert[0x6]	13962	1			T5	10		T17	153		T186	1
alert[0x7]	9239	1			T5	8		T8	1		T22	1
alert[0x8]	8007	1			T17	12		T80	1		T27	4
alert[0x9]	9606	1			T16	954		T63	2		T55	1
alert[0xa]	9583	1			T4	1		T5	9		T8	2
alert[0xb]	4133	1			T12	1		T16	311		T17	18
alert[0xc]	3775	1			T8	1		T16	7		T27	1
alert[0xd]	8393	1			T8	1		T12	1		T17	12
alert[0xe]	14355	1			T5	4		T16	3		T17	203
alert[0xf]	4952	1			T4	1		T27	11		T304	1
alert[0x10]	15839	1			T8	1		T16	26		T221	8
alert[0x11]	7927	1			T57	1		T60	4		T71	4
alert[0x12]	5304	1			T8	1		T17	357		T27	18
alert[0x13]	9179	1			T4	1		T16	138		T55	1
alert[0x14]	7022	1			T12	1		T39	34		T294	1
alert[0x15]	9235	1			T4	1		T5	519		T8	1
alert[0x16]	5341	1			T22	4		T17	250		T80	1
alert[0x17]	3153	1			T4	1		T5	12		T8	1
alert[0x18]	4205	1			T5	97		T27	32		T53	2
alert[0x19]	3323	1			T16	47		T11	1		T17	91
alert[0x1a]	5503	1			T12	1		T11	1		T17	60
alert[0x1b]	9292	1			T186	1		T27	9		T53	8
alert[0x1c]	8463	1			T4	1		T8	1		T22	4
alert[0x1d]	4168	1			T5	1		T12	1		T17	27
alert[0x1e]	5120	1			T8	1		T17	5		T186	1
alert[0x1f]	10579	1			T16	2		T27	18		T221	3
alert[0x20]	7018	1			T16	23		T27	4		T63	12
alert[0x21]	2950	1			T16	116		T17	108		T63	1
alert[0x22]	4139	1			T4	1		T5	61		T27	5
alert[0x23]	4622	1			T22	8		T27	78		T38	137
alert[0x24]	3613	1			T5	53		T186	1		T63	53
alert[0x25]	4546	1			T12	1		T63	291		T57	1
alert[0x26]	3742	1			T5	7		T22	1		T16	19
alert[0x27]	9550	1			T5	18		T8	1		T24	2
alert[0x28]	6200	1			T17	821		T80	1		T221	3
alert[0x29]	7200	1			T8	1		T24	1		T186	1
alert[0x2a]	2163	1			T8	1		T16	45		T24	6
alert[0x2b]	15750	1			T5	26		T22	1		T16	81
alert[0x2c]	7456	1			T8	1		T55	1		T38	37
alert[0x2d]	5929	1			T4	1		T17	5		T73	57
alert[0x2e]	3887	1			T25	2		T75	43		T305	188
alert[0x2f]	5518	1			T5	502		T12	1		T16	41
alert[0x30]	5151	1			T5	3		T16	38		T27	6
alert[0x31]	3633	1			T5	24		T12	1		T16	15
alert[0x32]	7543	1			T27	10		T63	57		T53	2
alert[0x33]	5234	1			T5	346		T12	1		T16	12
alert[0x34]	10572	1			T4	1		T5	934		T17	191
alert[0x35]	3909	1			T5	24		T17	76		T186	1
alert[0x36]	3714	1			T16	31		T24	2		T63	2
alert[0x37]	4843	1			T12	1		T16	9		T221	3
alert[0x38]	2577	1			T186	1		T55	1		T304	1
alert[0x39]	3181	1			T17	60		T24	5		T64	8
alert[0x3a]	11790	1			T4	1		T5	115		T17	49
alert[0x3b]	10364	1			T16	26		T186	1		T66	1
alert[0x3c]	13576	1			T4	1		T5	40		T22	18
alert[0x3d]	2295	1			T12	1		T17	42		T27	16
alert[0x3e]	2107	1			T17	6		T221	3		T304	1
alert[0x3f]	4128	1			T5	95		T27	4		T63	129
alert[0x40]	3170	1			T5	10		T17	44		T221	19

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	105075	1			T5	2292		T22	18		T80	3
class_i[0x1]	81284	1			T4	7		T8	14		T22	26
class_i[0x2]	128524	1			T4	1		T5	626		T8	1
class_i[0x3]	102806	1			T4	4		T22	19		T16	1827

---

Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

alert_integrity_fail

417047

1

T5

2918

T22

63

T16

2348

alert_ping_fail

642

1

T4

12

T8

15

T12

13

---

Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	0	130	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	alert_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	alert[0x0]	3251	1			T22	4		T17	23		T221	7
alert_integrity_fail	alert[0x1]	684	1			T16	2		T27	5		T63	8
alert_integrity_fail	alert[0x2]	4056	1			T16	103		T17	486		T27	37
alert_integrity_fail	alert[0x3]	9230	1			T63	145		T38	19		T25	703
alert_integrity_fail	alert[0x4]	2631	1			T16	66		T17	140		T27	13
alert_integrity_fail	alert[0x5]	6060	1			T221	1		T63	153		T53	2
alert_integrity_fail	alert[0x6]	13954	1			T5	10		T17	153		T63	31
alert_integrity_fail	alert[0x7]	9228	1			T5	8		T22	1		T17	2369
alert_integrity_fail	alert[0x8]	7998	1			T17	12		T27	4		T63	150
alert_integrity_fail	alert[0x9]	9595	1			T16	954		T63	2		T38	28
alert_integrity_fail	alert[0xa]	9564	1			T5	9		T17	143		T28	212
alert_integrity_fail	alert[0xb]	4123	1			T16	311		T17	18		T27	3
alert_integrity_fail	alert[0xc]	3755	1			T16	7		T27	1		T221	1
alert_integrity_fail	alert[0xd]	8381	1			T17	12		T63	7		T267	9
alert_integrity_fail	alert[0xe]	14350	1			T5	4		T16	3		T17	203
alert_integrity_fail	alert[0xf]	4945	1			T27	11		T28	2		T283	1
alert_integrity_fail	alert[0x10]	15829	1			T16	26		T221	8		T36	6
alert_integrity_fail	alert[0x11]	7923	1			T60	4		T71	4		T73	73
alert_integrity_fail	alert[0x12]	5298	1			T17	357		T27	18		T221	1
alert_integrity_fail	alert[0x13]	9168	1			T16	138		T38	35		T209	31
alert_integrity_fail	alert[0x14]	7010	1			T39	34		T25	277		T283	1
alert_integrity_fail	alert[0x15]	9227	1			T5	519		T25	52		T73	135
alert_integrity_fail	alert[0x16]	5324	1			T22	4		T17	250		T24	21
alert_integrity_fail	alert[0x17]	3140	1			T5	12		T22	22		T27	63
alert_integrity_fail	alert[0x18]	4196	1			T5	97		T27	32		T53	2
alert_integrity_fail	alert[0x19]	3313	1			T16	47		T17	91		T27	389
alert_integrity_fail	alert[0x1a]	5494	1			T17	60		T27	45		T25	15
alert_integrity_fail	alert[0x1b]	9281	1			T27	9		T53	8		T38	1787
alert_integrity_fail	alert[0x1c]	8453	1			T22	4		T17	38		T24	4
alert_integrity_fail	alert[0x1d]	4154	1			T5	1		T17	27		T27	6
alert_integrity_fail	alert[0x1e]	5115	1			T17	5		T63	20		T39	6
alert_integrity_fail	alert[0x1f]	10560	1			T16	2		T27	18		T221	3
alert_integrity_fail	alert[0x20]	7013	1			T16	23		T27	4		T63	12
alert_integrity_fail	alert[0x21]	2945	1			T16	116		T17	108		T63	1
alert_integrity_fail	alert[0x22]	4125	1			T5	61		T27	5		T63	11
alert_integrity_fail	alert[0x23]	4613	1			T22	8		T27	78		T38	137
alert_integrity_fail	alert[0x24]	3607	1			T5	53		T63	53		T38	24
alert_integrity_fail	alert[0x25]	4540	1			T63	291		T38	16		T267	1
alert_integrity_fail	alert[0x26]	3737	1			T5	7		T22	1		T16	19
alert_integrity_fail	alert[0x27]	9543	1			T5	18		T24	2		T27	33
alert_integrity_fail	alert[0x28]	6175	1			T17	821		T221	3		T38	44
alert_integrity_fail	alert[0x29]	7187	1			T24	1		T53	3		T38	232
alert_integrity_fail	alert[0x2a]	2149	1			T16	45		T24	6		T73	14
alert_integrity_fail	alert[0x2b]	15737	1			T5	26		T22	1		T16	81
alert_integrity_fail	alert[0x2c]	7442	1			T38	37		T267	1		T71	2
alert_integrity_fail	alert[0x2d]	5914	1			T17	5		T73	57		T306	65
alert_integrity_fail	alert[0x2e]	3874	1			T25	2		T75	43		T305	188
alert_integrity_fail	alert[0x2f]	5506	1			T5	502		T16	41		T17	770
alert_integrity_fail	alert[0x30]	5146	1			T5	3		T16	38		T27	6
alert_integrity_fail	alert[0x31]	3623	1			T5	24		T16	15		T17	42
alert_integrity_fail	alert[0x32]	7536	1			T27	10		T63	57		T53	2
alert_integrity_fail	alert[0x33]	5227	1			T5	346		T16	12		T63	64
alert_integrity_fail	alert[0x34]	10563	1			T5	934		T17	191		T27	4
alert_integrity_fail	alert[0x35]	3901	1			T5	24		T17	76		T27	106
alert_integrity_fail	alert[0x36]	3710	1			T16	31		T24	2		T63	2
alert_integrity_fail	alert[0x37]	4831	1			T16	9		T221	3		T38	66
alert_integrity_fail	alert[0x38]	2565	1			T25	12		T241	9		T79	354
alert_integrity_fail	alert[0x39]	3175	1			T17	60		T24	5		T64	8
alert_integrity_fail	alert[0x3a]	11777	1			T5	115		T17	49		T27	5
alert_integrity_fail	alert[0x3b]	10356	1			T16	26		T66	1		T53	1
alert_integrity_fail	alert[0x3c]	13563	1			T5	40		T22	18		T16	233
alert_integrity_fail	alert[0x3d]	2290	1			T17	42		T27	16		T63	9
alert_integrity_fail	alert[0x3e]	2097	1			T17	6		T221	3		T25	46
alert_integrity_fail	alert[0x3f]	4126	1			T5	95		T27	4		T63	129
alert_integrity_fail	alert[0x40]	3164	1			T5	10		T17	44		T221	19
alert_ping_fail	alert[0x0]	11	1			T231	1		T307	1		T308	1
alert_ping_fail	alert[0x1]	12	1			T57	1		T216	1		T309	1
alert_ping_fail	alert[0x2]	7	1			T55	1		T216	1		T231	1
alert_ping_fail	alert[0x3]	8	1			T4	1		T309	1		T308	1
alert_ping_fail	alert[0x4]	4	1			T55	1		T310	1		T311	1
alert_ping_fail	alert[0x5]	7	1			T215	1		T312	1		T313	1
alert_ping_fail	alert[0x6]	8	1			T186	1		T231	2		T308	1
alert_ping_fail	alert[0x7]	11	1			T8	1		T12	1		T314	1
alert_ping_fail	alert[0x8]	9	1			T80	1		T307	1		T315	1
alert_ping_fail	alert[0x9]	11	1			T55	1		T314	1		T316	1
alert_ping_fail	alert[0xa]	19	1			T4	1		T8	2		T304	2
alert_ping_fail	alert[0xb]	10	1			T12	1		T304	1		T316	2
alert_ping_fail	alert[0xc]	20	1			T8	1		T57	1		T216	1
alert_ping_fail	alert[0xd]	12	1			T8	1		T12	1		T55	1
alert_ping_fail	alert[0xe]	5	1			T175	1		T317	1		T318	1
alert_ping_fail	alert[0xf]	7	1			T4	1		T304	1		T215	1
alert_ping_fail	alert[0x10]	10	1			T8	1		T55	1		T57	1
alert_ping_fail	alert[0x11]	4	1			T57	1		T215	1		T317	1
alert_ping_fail	alert[0x12]	6	1			T8	1		T57	1		T216	1
alert_ping_fail	alert[0x13]	11	1			T4	1		T55	1		T304	1
alert_ping_fail	alert[0x14]	12	1			T12	1		T294	1		T319	1
alert_ping_fail	alert[0x15]	8	1			T4	1		T8	1		T231	1
alert_ping_fail	alert[0x16]	17	1			T80	1		T55	1		T216	2
alert_ping_fail	alert[0x17]	13	1			T4	1		T8	1		T11	1
alert_ping_fail	alert[0x18]	9	1			T57	1		T216	1		T285	1
alert_ping_fail	alert[0x19]	10	1			T11	1		T216	1		T309	1
alert_ping_fail	alert[0x1a]	9	1			T12	1		T11	1		T294	1
alert_ping_fail	alert[0x1b]	11	1			T186	1		T310	1		T215	1
alert_ping_fail	alert[0x1c]	10	1			T4	1		T8	1		T12	1
alert_ping_fail	alert[0x1d]	14	1			T12	1		T222	1		T55	1
alert_ping_fail	alert[0x1e]	5	1			T8	1		T186	1		T316	1
alert_ping_fail	alert[0x1f]	19	1			T55	1		T320	2		T321	1
alert_ping_fail	alert[0x20]	5	1			T216	1		T322	1		T323	1
alert_ping_fail	alert[0x21]	5	1			T215	1		T285	1		T324	1
alert_ping_fail	alert[0x22]	14	1			T4	1		T231	1		T325	1
alert_ping_fail	alert[0x23]	9	1			T216	1		T231	1		T285	1
alert_ping_fail	alert[0x24]	6	1			T186	1		T55	1		T57	1
alert_ping_fail	alert[0x25]	6	1			T12	1		T57	1		T304	1
alert_ping_fail	alert[0x26]	5	1			T325	1		T307	1		T326	1
alert_ping_fail	alert[0x27]	7	1			T8	1		T215	1		T314	1
alert_ping_fail	alert[0x28]	25	1			T80	1		T55	1		T294	1
alert_ping_fail	alert[0x29]	13	1			T8	1		T186	1		T55	1
alert_ping_fail	alert[0x2a]	14	1			T8	1		T215	1		T327	1
alert_ping_fail	alert[0x2b]	13	1			T186	1		T55	1		T314	1
alert_ping_fail	alert[0x2c]	14	1			T8	1		T55	1		T310	1
alert_ping_fail	alert[0x2d]	15	1			T4	1		T328	2		T329	1
alert_ping_fail	alert[0x2e]	13	1			T216	1		T330	1		T331	1
alert_ping_fail	alert[0x2f]	12	1			T12	1		T57	1		T231	2
alert_ping_fail	alert[0x30]	5	1			T328	1		T311	1		T307	1
alert_ping_fail	alert[0x31]	10	1			T12	1		T57	1		T231	1
alert_ping_fail	alert[0x32]	7	1			T314	1		T311	1		T331	1
alert_ping_fail	alert[0x33]	7	1			T12	1		T231	1		T307	1
alert_ping_fail	alert[0x34]	9	1			T4	1		T186	1		T304	1
alert_ping_fail	alert[0x35]	8	1			T186	1		T216	1		T316	1
alert_ping_fail	alert[0x36]	4	1			T231	1		T285	1		T332	1
alert_ping_fail	alert[0x37]	12	1			T12	1		T55	1		T57	1
alert_ping_fail	alert[0x38]	12	1			T186	1		T55	1		T304	1
alert_ping_fail	alert[0x39]	6	1			T285	1		T311	1		T333	1
alert_ping_fail	alert[0x3a]	13	1			T4	1		T55	2		T304	2
alert_ping_fail	alert[0x3b]	8	1			T186	1		T215	1		T334	1
alert_ping_fail	alert[0x3c]	13	1			T4	1		T186	1		T310	1
alert_ping_fail	alert[0x3d]	5	1			T12	1		T55	2		T335	1
alert_ping_fail	alert[0x3e]	10	1			T304	1		T231	1		T175	1
alert_ping_fail	alert[0x3f]	2	1			T334	1		T307	1		-	-
alert_ping_fail	alert[0x40]	6	1			T294	1		T330	1		T313	1

---

Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	class_i[0x0]	104870	1			T5	2292		T22	18		T24	41
alert_integrity_fail	class_i[0x1]	81120	1			T22	26		T27	489		T221	12
alert_integrity_fail	class_i[0x2]	128395	1			T5	626		T16	521		T17	6733
alert_integrity_fail	class_i[0x3]	102662	1			T22	19		T16	1827		T35	6
alert_ping_fail	class_i[0x0]	205	1			T80	3		T55	14		T57	1
alert_ping_fail	class_i[0x1]	164	1			T4	7		T8	14		T12	13
alert_ping_fail	class_i[0x2]	129	1			T4	1		T8	1		T11	3
alert_ping_fail	class_i[0x3]	144	1			T4	4		T186	11		T55	2