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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.66 99.99 98.72 100.00 100.00 100.00 99.30 99.60


Total test records in report: 832
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html
T767 /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.882065959 Jul 20 06:40:50 PM PDT 24 Jul 20 06:41:13 PM PDT 24 1868742170 ps
T154 /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.149540003 Jul 20 06:40:54 PM PDT 24 Jul 20 06:41:40 PM PDT 24 1206045147 ps
T146 /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.2813608348 Jul 20 06:40:34 PM PDT 24 Jul 20 06:46:10 PM PDT 24 2539298790 ps
T768 /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.3823665438 Jul 20 06:40:39 PM PDT 24 Jul 20 06:40:50 PM PDT 24 112967175 ps
T769 /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.1045808663 Jul 20 06:40:35 PM PDT 24 Jul 20 06:41:03 PM PDT 24 684507336 ps
T164 /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.3540265981 Jul 20 06:40:35 PM PDT 24 Jul 20 06:41:07 PM PDT 24 325322058 ps
T770 /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.3591062199 Jul 20 06:40:36 PM PDT 24 Jul 20 06:40:47 PM PDT 24 883134903 ps
T771 /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.423198626 Jul 20 06:41:01 PM PDT 24 Jul 20 06:41:03 PM PDT 24 24550397 ps
T772 /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.181771197 Jul 20 06:40:29 PM PDT 24 Jul 20 06:42:57 PM PDT 24 1058785068 ps
T773 /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.3944939281 Jul 20 06:40:58 PM PDT 24 Jul 20 06:41:18 PM PDT 24 261833079 ps
T774 /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.2557729156 Jul 20 06:40:32 PM PDT 24 Jul 20 06:40:45 PM PDT 24 143044185 ps
T775 /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.3777166436 Jul 20 06:40:32 PM PDT 24 Jul 20 06:40:42 PM PDT 24 57601970 ps
T170 /workspace/coverage/cover_reg_top/12.alert_handler_tl_intg_err.1666097580 Jul 20 06:40:33 PM PDT 24 Jul 20 06:41:14 PM PDT 24 5544471238 ps
T776 /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.1772637184 Jul 20 06:40:40 PM PDT 24 Jul 20 06:40:47 PM PDT 24 65736288 ps
T777 /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.3243217334 Jul 20 06:40:32 PM PDT 24 Jul 20 06:40:39 PM PDT 24 56508514 ps
T778 /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.4130785919 Jul 20 06:40:31 PM PDT 24 Jul 20 06:42:51 PM PDT 24 6923078967 ps
T779 /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.3070260308 Jul 20 06:40:36 PM PDT 24 Jul 20 06:40:52 PM PDT 24 241175436 ps
T780 /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.949493927 Jul 20 06:40:33 PM PDT 24 Jul 20 06:40:37 PM PDT 24 12910858 ps
T169 /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.1186951500 Jul 20 06:40:42 PM PDT 24 Jul 20 06:40:48 PM PDT 24 77768702 ps
T781 /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.679644330 Jul 20 06:40:42 PM PDT 24 Jul 20 06:40:52 PM PDT 24 507227466 ps
T782 /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.631827510 Jul 20 06:40:33 PM PDT 24 Jul 20 06:40:56 PM PDT 24 1246472690 ps
T783 /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.3586766172 Jul 20 06:40:24 PM PDT 24 Jul 20 06:40:34 PM PDT 24 864915824 ps
T784 /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.790713493 Jul 20 06:40:36 PM PDT 24 Jul 20 06:40:40 PM PDT 24 16681174 ps
T785 /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.3464259724 Jul 20 06:40:25 PM PDT 24 Jul 20 06:43:21 PM PDT 24 5052457626 ps
T786 /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.179408469 Jul 20 06:40:35 PM PDT 24 Jul 20 06:40:39 PM PDT 24 10115422 ps
T787 /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.2876722123 Jul 20 06:40:36 PM PDT 24 Jul 20 06:40:40 PM PDT 24 13312278 ps
T788 /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.185770610 Jul 20 06:40:37 PM PDT 24 Jul 20 06:40:44 PM PDT 24 93991665 ps
T789 /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.2033027965 Jul 20 06:40:25 PM PDT 24 Jul 20 06:44:37 PM PDT 24 5018614378 ps
T790 /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.1750589893 Jul 20 06:41:08 PM PDT 24 Jul 20 06:41:11 PM PDT 24 11382450 ps
T791 /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.2033651639 Jul 20 06:40:22 PM PDT 24 Jul 20 06:40:27 PM PDT 24 55238611 ps
T357 /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.4165316105 Jul 20 06:40:24 PM PDT 24 Jul 20 06:57:47 PM PDT 24 12624883988 ps
T792 /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.1968007548 Jul 20 06:40:37 PM PDT 24 Jul 20 06:40:46 PM PDT 24 62382884 ps
T159 /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.1242365074 Jul 20 06:40:37 PM PDT 24 Jul 20 06:40:44 PM PDT 24 65731489 ps
T793 /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.1631367405 Jul 20 06:40:59 PM PDT 24 Jul 20 06:41:01 PM PDT 24 6825199 ps
T145 /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.1910868705 Jul 20 06:40:44 PM PDT 24 Jul 20 06:45:18 PM PDT 24 9158953765 ps
T794 /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.501625591 Jul 20 06:40:35 PM PDT 24 Jul 20 06:40:51 PM PDT 24 352118123 ps
T795 /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.583577613 Jul 20 06:40:47 PM PDT 24 Jul 20 06:41:24 PM PDT 24 956972233 ps
T796 /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.2140697579 Jul 20 06:40:34 PM PDT 24 Jul 20 06:40:56 PM PDT 24 983763798 ps
T157 /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.4104041991 Jul 20 06:40:39 PM PDT 24 Jul 20 06:41:43 PM PDT 24 1806378517 ps
T797 /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.2333467707 Jul 20 06:40:36 PM PDT 24 Jul 20 06:51:16 PM PDT 24 15428549466 ps
T358 /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.292625725 Jul 20 06:40:35 PM PDT 24 Jul 20 06:46:39 PM PDT 24 6020367634 ps
T798 /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.4206340662 Jul 20 06:40:56 PM PDT 24 Jul 20 06:40:59 PM PDT 24 50800990 ps
T799 /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.1613354068 Jul 20 06:40:54 PM PDT 24 Jul 20 06:40:57 PM PDT 24 6803850 ps
T800 /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.8355593 Jul 20 06:40:41 PM PDT 24 Jul 20 06:40:44 PM PDT 24 12244892 ps
T801 /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.190987109 Jul 20 06:40:32 PM PDT 24 Jul 20 06:40:34 PM PDT 24 8948028 ps
T147 /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.2044608683 Jul 20 06:41:03 PM PDT 24 Jul 20 06:44:55 PM PDT 24 1654047615 ps
T802 /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.642521961 Jul 20 06:40:34 PM PDT 24 Jul 20 06:40:45 PM PDT 24 153760153 ps
T803 /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.3015237441 Jul 20 06:40:26 PM PDT 24 Jul 20 06:40:28 PM PDT 24 8552409 ps
T804 /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.2206591108 Jul 20 06:40:32 PM PDT 24 Jul 20 06:40:49 PM PDT 24 242581666 ps
T805 /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.4087615861 Jul 20 06:40:51 PM PDT 24 Jul 20 06:40:55 PM PDT 24 15667082 ps
T806 /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.737538070 Jul 20 06:40:43 PM PDT 24 Jul 20 06:40:51 PM PDT 24 146391088 ps
T160 /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.2828154475 Jul 20 06:40:27 PM PDT 24 Jul 20 06:40:50 PM PDT 24 1220913891 ps
T807 /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.231378353 Jul 20 06:40:53 PM PDT 24 Jul 20 06:40:56 PM PDT 24 19202027 ps
T808 /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.3003559211 Jul 20 06:40:54 PM PDT 24 Jul 20 06:40:57 PM PDT 24 8254391 ps
T809 /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.1810871306 Jul 20 06:40:48 PM PDT 24 Jul 20 06:42:18 PM PDT 24 1526081763 ps
T810 /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.1257730497 Jul 20 06:40:34 PM PDT 24 Jul 20 06:40:42 PM PDT 24 28861084 ps
T811 /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.4106479478 Jul 20 06:40:42 PM PDT 24 Jul 20 06:40:59 PM PDT 24 680899829 ps
T812 /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.1634897589 Jul 20 06:40:34 PM PDT 24 Jul 20 06:40:51 PM PDT 24 843684768 ps
T813 /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.1080589734 Jul 20 06:40:49 PM PDT 24 Jul 20 06:40:51 PM PDT 24 10134486 ps
T140 /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.811881786 Jul 20 06:40:33 PM PDT 24 Jul 20 06:45:20 PM PDT 24 2956343639 ps
T814 /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.1639017320 Jul 20 06:40:36 PM PDT 24 Jul 20 06:40:51 PM PDT 24 130757581 ps
T360 /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.1365772516 Jul 20 06:40:49 PM PDT 24 Jul 20 06:57:14 PM PDT 24 49716615633 ps
T815 /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.1731436052 Jul 20 06:40:34 PM PDT 24 Jul 20 06:40:40 PM PDT 24 111665320 ps
T816 /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.3912212408 Jul 20 06:41:00 PM PDT 24 Jul 20 06:41:02 PM PDT 24 9632628 ps
T817 /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.4225909886 Jul 20 06:40:24 PM PDT 24 Jul 20 06:40:27 PM PDT 24 126797043 ps
T818 /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.2068529597 Jul 20 06:40:31 PM PDT 24 Jul 20 06:40:36 PM PDT 24 192915171 ps
T819 /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.2284230934 Jul 20 06:40:33 PM PDT 24 Jul 20 06:40:48 PM PDT 24 311763383 ps
T820 /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.415240963 Jul 20 06:41:06 PM PDT 24 Jul 20 06:41:08 PM PDT 24 8755731 ps
T821 /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.4260260364 Jul 20 06:40:27 PM PDT 24 Jul 20 06:43:16 PM PDT 24 2263656033 ps
T822 /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.1160485907 Jul 20 06:40:33 PM PDT 24 Jul 20 06:40:42 PM PDT 24 37213631 ps
T823 /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.2766761977 Jul 20 06:40:40 PM PDT 24 Jul 20 06:40:43 PM PDT 24 12358530 ps
T359 /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.1080706247 Jul 20 06:40:34 PM PDT 24 Jul 20 06:46:39 PM PDT 24 4441343960 ps
T824 /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.1215884833 Jul 20 06:40:55 PM PDT 24 Jul 20 06:41:01 PM PDT 24 100220240 ps
T825 /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.3777689229 Jul 20 06:40:40 PM PDT 24 Jul 20 06:40:56 PM PDT 24 97195422 ps
T826 /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.3983488655 Jul 20 06:40:50 PM PDT 24 Jul 20 06:40:53 PM PDT 24 42279320 ps
T827 /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.3714465885 Jul 20 06:40:27 PM PDT 24 Jul 20 06:40:51 PM PDT 24 1185143670 ps
T828 /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.3194718070 Jul 20 06:40:40 PM PDT 24 Jul 20 06:41:03 PM PDT 24 971810338 ps
T137 /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.498645383 Jul 20 06:40:25 PM PDT 24 Jul 20 06:47:19 PM PDT 24 2160169690 ps
T829 /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.396114157 Jul 20 06:40:18 PM PDT 24 Jul 20 06:40:30 PM PDT 24 83212801 ps
T830 /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.933457401 Jul 20 06:40:26 PM PDT 24 Jul 20 06:43:21 PM PDT 24 5828872929 ps
T831 /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.1726792365 Jul 20 06:40:35 PM PDT 24 Jul 20 06:41:06 PM PDT 24 1443751597 ps
T832 /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.2691578932 Jul 20 06:40:38 PM PDT 24 Jul 20 06:40:51 PM PDT 24 133105371 ps

Test location /workspace/coverage/default/44.alert_handler_stress_all_with_rand_reset.41156120
Short name T5
Test name
Test status
Simulation time 331850178269 ps
CPU time 5296.02 seconds
Started Jul 20 06:43:09 PM PDT 24
Finished Jul 20 08:11:26 PM PDT 24
Peak memory 322964 kb
Host smart-77e79711-b56f-4203-ba45-26770379a29c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41156120 -assert nopostproc +UVM_TESTNAME=alert_
handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 44.alert_handler_stress_all_with_rand_reset.41156120
Directory /workspace/44.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.alert_handler_sec_cm.4176697753
Short name T14
Test name
Test status
Simulation time 836947115 ps
CPU time 14.94 seconds
Started Jul 20 06:41:05 PM PDT 24
Finished Jul 20 06:41:20 PM PDT 24
Peak memory 267032 kb
Host smart-74a90761-2201-4a9d-8b2f-36cb4fee03f1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4176697753 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sec_cm.4176697753
Directory /workspace/3.alert_handler_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.1449129541
Short name T148
Test name
Test status
Simulation time 2494171382 ps
CPU time 86.29 seconds
Started Jul 20 06:40:39 PM PDT 24
Finished Jul 20 06:42:07 PM PDT 24
Peak memory 240720 kb
Host smart-0f374027-50d4-41b4-8de4-f70f98657b57
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1449129541 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_intg_err.1449129541
Directory /workspace/14.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/7.alert_handler_entropy_stress.466025059
Short name T56
Test name
Test status
Simulation time 456860268 ps
CPU time 24.97 seconds
Started Jul 20 06:41:07 PM PDT 24
Finished Jul 20 06:41:33 PM PDT 24
Peak memory 248976 kb
Host smart-3a3559b7-fd61-4208-a113-a3722ebdc855
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=466025059 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy_stress.466025059
Directory /workspace/7.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all_with_rand_reset.73819703
Short name T45
Test name
Test status
Simulation time 205738596399 ps
CPU time 3528.31 seconds
Started Jul 20 06:43:19 PM PDT 24
Finished Jul 20 07:42:08 PM PDT 24
Peak memory 305748 kb
Host smart-f1f25ac3-a2a6-4f2a-b095-ed2bf184b0fe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73819703 -assert nopostproc +UVM_TESTNAME=alert_
handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 47.alert_handler_stress_all_with_rand_reset.73819703
Directory /workspace/47.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all_with_rand_reset.2062134285
Short name T262
Test name
Test status
Simulation time 158296543781 ps
CPU time 2534.61 seconds
Started Jul 20 06:42:42 PM PDT 24
Finished Jul 20 07:24:59 PM PDT 24
Peak memory 290128 kb
Host smart-01bcc2e1-b26a-45c1-aedb-1dcfab555eb3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062134285 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.alert_handler_stress_all_with_rand_reset.2062134285
Directory /workspace/39.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.233351228
Short name T135
Test name
Test status
Simulation time 5857811638 ps
CPU time 191.89 seconds
Started Jul 20 06:40:35 PM PDT 24
Finished Jul 20 06:43:50 PM PDT 24
Peak memory 265616 kb
Host smart-25cdfbd0-0c88-4bbb-be58-c63e364ca00c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=233351228 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shadow_reg_erro
rs.233351228
Directory /workspace/11.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/40.alert_handler_lpg.1987064798
Short name T23
Test name
Test status
Simulation time 41522294121 ps
CPU time 2513.27 seconds
Started Jul 20 06:42:53 PM PDT 24
Finished Jul 20 07:24:47 PM PDT 24
Peak memory 283364 kb
Host smart-a8a99127-9ebe-4b4d-b4a2-c8404903f91d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987064798 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg.1987064798
Directory /workspace/40.alert_handler_lpg/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all_with_rand_reset.1563448646
Short name T16
Test name
Test status
Simulation time 41522688237 ps
CPU time 2813.01 seconds
Started Jul 20 06:41:39 PM PDT 24
Finished Jul 20 07:28:33 PM PDT 24
Peak memory 300860 kb
Host smart-5ba55d72-dbd5-41f2-adbb-a23353e22440
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563448646 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 19.alert_handler_stress_all_with_rand_reset.1563448646
Directory /workspace/19.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.1955088705
Short name T130
Test name
Test status
Simulation time 4462355828 ps
CPU time 628.86 seconds
Started Jul 20 06:40:25 PM PDT 24
Finished Jul 20 06:50:55 PM PDT 24
Peak memory 265564 kb
Host smart-d1d37ba0-ce50-4b48-94d3-887aa93cec9d
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955088705 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.alert_handler_shadow_reg_errors_with_csr_rw.1955088705
Directory /workspace/4.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all_with_rand_reset.1315821792
Short name T98
Test name
Test status
Simulation time 99505623572 ps
CPU time 3296.31 seconds
Started Jul 20 06:41:06 PM PDT 24
Finished Jul 20 07:36:03 PM PDT 24
Peak memory 306204 kb
Host smart-f4d947d4-ed40-4616-acae-cf2c7a606cfc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315821792 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.alert_handler_stress_all_with_rand_reset.1315821792
Directory /workspace/2.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.alert_handler_ping_timeout.1883290225
Short name T12
Test name
Test status
Simulation time 7380851334 ps
CPU time 315.34 seconds
Started Jul 20 06:41:38 PM PDT 24
Finished Jul 20 06:46:54 PM PDT 24
Peak memory 247976 kb
Host smart-61315418-bc38-48dc-a91a-5619af8f2b8c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1883290225 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_ping_timeout.1883290225
Directory /workspace/19.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.170238981
Short name T116
Test name
Test status
Simulation time 6711603262 ps
CPU time 218.26 seconds
Started Jul 20 06:40:39 PM PDT 24
Finished Jul 20 06:44:19 PM PDT 24
Peak memory 265620 kb
Host smart-26baa713-527e-476c-93dd-26190d0d2cbd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=170238981 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shadow_reg_error
s.170238981
Directory /workspace/9.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all.2063027315
Short name T25
Test name
Test status
Simulation time 43696779274 ps
CPU time 2616.11 seconds
Started Jul 20 06:42:27 PM PDT 24
Finished Jul 20 07:26:04 PM PDT 24
Peak memory 288028 kb
Host smart-4b3c8fb5-039f-4fa7-901d-a1301f282aa0
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063027315 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_ha
ndler_stress_all.2063027315
Directory /workspace/34.alert_handler_stress_all/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all_with_rand_reset.2578211733
Short name T49
Test name
Test status
Simulation time 273302053801 ps
CPU time 4079.48 seconds
Started Jul 20 06:42:13 PM PDT 24
Finished Jul 20 07:50:14 PM PDT 24
Peak memory 337884 kb
Host smart-8d426d6f-6d89-4caa-8f59-1a72ec47fbf9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578211733 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 31.alert_handler_stress_all_with_rand_reset.2578211733
Directory /workspace/31.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.alert_handler_ping_timeout.2118472146
Short name T55
Test name
Test status
Simulation time 108023281557 ps
CPU time 592.97 seconds
Started Jul 20 06:42:13 PM PDT 24
Finished Jul 20 06:52:07 PM PDT 24
Peak memory 255932 kb
Host smart-8ff0fa7e-bde3-41ba-a2f4-0ad6540a6b28
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2118472146 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_ping_timeout.2118472146
Directory /workspace/30.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_lpg.2434999744
Short name T300
Test name
Test status
Simulation time 52111066113 ps
CPU time 3046.3 seconds
Started Jul 20 06:42:28 PM PDT 24
Finished Jul 20 07:33:16 PM PDT 24
Peak memory 289372 kb
Host smart-8440ceed-bca5-45d0-a7fa-e13a44dd20f3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434999744 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg.2434999744
Directory /workspace/35.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.328505115
Short name T119
Test name
Test status
Simulation time 6295489464 ps
CPU time 202 seconds
Started Jul 20 06:40:33 PM PDT 24
Finished Jul 20 06:43:56 PM PDT 24
Peak memory 265580 kb
Host smart-f223f29e-855d-411d-b3cd-1e0b1720cf0b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=328505115 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shadow_reg_error
s.328505115
Directory /workspace/5.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.599462930
Short name T354
Test name
Test status
Simulation time 11942320 ps
CPU time 1.3 seconds
Started Jul 20 06:40:47 PM PDT 24
Finished Jul 20 06:40:49 PM PDT 24
Peak memory 236912 kb
Host smart-57648469-4d22-4475-8881-bfac6ff776e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=599462930 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.alert_handler_intr_test.599462930
Directory /workspace/40.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.3782028365
Short name T139
Test name
Test status
Simulation time 49365815121 ps
CPU time 1069.89 seconds
Started Jul 20 06:40:33 PM PDT 24
Finished Jul 20 06:58:26 PM PDT 24
Peak memory 265556 kb
Host smart-df0e5594-84f3-4e50-a517-47416a7e925f
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782028365 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 10.alert_handler_shadow_reg_errors_with_csr_rw.3782028365
Directory /workspace/10.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/14.alert_handler_entropy.2153619632
Short name T305
Test name
Test status
Simulation time 278977674439 ps
CPU time 2044.42 seconds
Started Jul 20 06:41:31 PM PDT 24
Finished Jul 20 07:15:37 PM PDT 24
Peak memory 288648 kb
Host smart-56e88aa2-403d-4230-82b2-e2c23237b66d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153619632 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy.2153619632
Directory /workspace/14.alert_handler_entropy/latest

Test location /workspace/coverage/default/38.alert_handler_lpg.4288301698
Short name T11
Test name
Test status
Simulation time 29479673130 ps
CPU time 1699.65 seconds
Started Jul 20 06:42:38 PM PDT 24
Finished Jul 20 07:10:58 PM PDT 24
Peak memory 272888 kb
Host smart-47862ef3-959c-420b-9bff-adf5591e940b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288301698 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg.4288301698
Directory /workspace/38.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.2333467707
Short name T797
Test name
Test status
Simulation time 15428549466 ps
CPU time 637.06 seconds
Started Jul 20 06:40:36 PM PDT 24
Finished Jul 20 06:51:16 PM PDT 24
Peak memory 266588 kb
Host smart-629389f8-f000-4874-8e17-13e4264c07ce
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333467707 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 15.alert_handler_shadow_reg_errors_with_csr_rw.2333467707
Directory /workspace/15.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/41.alert_handler_ping_timeout.3591667282
Short name T4
Test name
Test status
Simulation time 16019860729 ps
CPU time 329.99 seconds
Started Jul 20 06:42:52 PM PDT 24
Finished Jul 20 06:48:23 PM PDT 24
Peak memory 255768 kb
Host smart-a1e57260-f756-4f91-9fa4-84c02771d626
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591667282 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_ping_timeout.3591667282
Directory /workspace/41.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all_with_rand_reset.2912990931
Short name T27
Test name
Test status
Simulation time 281557463527 ps
CPU time 4120.97 seconds
Started Jul 20 06:41:58 PM PDT 24
Finished Jul 20 07:50:40 PM PDT 24
Peak memory 306288 kb
Host smart-737f4ead-b5fc-4ec7-bbb2-0f0ee6e9a3ea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912990931 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 25.alert_handler_stress_all_with_rand_reset.2912990931
Directory /workspace/25.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.1776548920
Short name T127
Test name
Test status
Simulation time 28940262706 ps
CPU time 1107.67 seconds
Started Jul 20 06:40:38 PM PDT 24
Finished Jul 20 06:59:08 PM PDT 24
Peak memory 265760 kb
Host smart-709676e5-743b-44c5-99f8-dd906842fa12
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776548920 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 13.alert_handler_shadow_reg_errors_with_csr_rw.1776548920
Directory /workspace/13.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/29.alert_handler_ping_timeout.1186113436
Short name T231
Test name
Test status
Simulation time 33186955069 ps
CPU time 719.18 seconds
Started Jul 20 06:42:11 PM PDT 24
Finished Jul 20 06:54:12 PM PDT 24
Peak memory 248944 kb
Host smart-87006f9a-7de6-4e2d-a4fd-c8d8082df901
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1186113436 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_ping_timeout.1186113436
Directory /workspace/29.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_lpg.3142757255
Short name T347
Test name
Test status
Simulation time 178491383555 ps
CPU time 2693.37 seconds
Started Jul 20 06:41:45 PM PDT 24
Finished Jul 20 07:26:39 PM PDT 24
Peak memory 289416 kb
Host smart-0695bf72-3aa1-44cd-8c69-8a2e71fe3a1d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142757255 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg.3142757255
Directory /workspace/21.alert_handler_lpg/latest

Test location /workspace/coverage/default/7.alert_handler_entropy.3789476310
Short name T28
Test name
Test status
Simulation time 56007266091 ps
CPU time 1844.58 seconds
Started Jul 20 06:41:09 PM PDT 24
Finished Jul 20 07:11:56 PM PDT 24
Peak memory 271588 kb
Host smart-ad162131-3dd6-4c28-bfc9-087e6075b25a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789476310 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy.3789476310
Directory /workspace/7.alert_handler_entropy/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.811881786
Short name T140
Test name
Test status
Simulation time 2956343639 ps
CPU time 285.57 seconds
Started Jul 20 06:40:33 PM PDT 24
Finished Jul 20 06:45:20 PM PDT 24
Peak memory 265588 kb
Host smart-2260cf5a-b397-4e6a-944b-7086942d1d36
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=811881786 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shadow_reg_error
s.811881786
Directory /workspace/0.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all.873912644
Short name T258
Test name
Test status
Simulation time 10021573674 ps
CPU time 921.21 seconds
Started Jul 20 06:42:20 PM PDT 24
Finished Jul 20 06:57:43 PM PDT 24
Peak memory 283928 kb
Host smart-ebfd8c42-8d91-4448-a1c1-3f4d6e2524f8
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873912644 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_han
dler_stress_all.873912644
Directory /workspace/32.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.3182547182
Short name T153
Test name
Test status
Simulation time 25377804 ps
CPU time 1.49 seconds
Started Jul 20 06:40:56 PM PDT 24
Finished Jul 20 06:40:59 PM PDT 24
Peak memory 236820 kb
Host smart-43f8966b-38e4-4b3e-bc31-60b6abbae1b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3182547182 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.alert_handler_intr_test.3182547182
Directory /workspace/48.alert_handler_intr_test/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all.3149185043
Short name T101
Test name
Test status
Simulation time 43538181557 ps
CPU time 2411.49 seconds
Started Jul 20 06:40:51 PM PDT 24
Finished Jul 20 07:21:05 PM PDT 24
Peak memory 281916 kb
Host smart-a12ffefc-fbf5-4274-b2cd-005fb4020f53
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149185043 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_han
dler_stress_all.3149185043
Directory /workspace/1.alert_handler_stress_all/latest

Test location /workspace/coverage/default/14.alert_handler_lpg.2356699122
Short name T340
Test name
Test status
Simulation time 40425721638 ps
CPU time 2329.95 seconds
Started Jul 20 06:41:30 PM PDT 24
Finished Jul 20 07:20:21 PM PDT 24
Peak memory 288092 kb
Host smart-a03481fc-ab20-4dfd-92dc-6f06b7b5aab6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356699122 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg.2356699122
Directory /workspace/14.alert_handler_lpg/latest

Test location /workspace/coverage/default/23.alert_handler_ping_timeout.3865234011
Short name T333
Test name
Test status
Simulation time 49650657794 ps
CPU time 533.5 seconds
Started Jul 20 06:41:54 PM PDT 24
Finished Jul 20 06:50:48 PM PDT 24
Peak memory 249052 kb
Host smart-9aee3328-8ad9-4534-a497-fb3fad696a96
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865234011 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_ping_timeout.3865234011
Directory /workspace/23.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_ping_timeout.2386049447
Short name T215
Test name
Test status
Simulation time 88911774615 ps
CPU time 362.26 seconds
Started Jul 20 06:42:19 PM PDT 24
Finished Jul 20 06:48:22 PM PDT 24
Peak memory 249112 kb
Host smart-129c31a6-ac06-4be5-a591-f7904a02c158
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386049447 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_ping_timeout.2386049447
Directory /workspace/34.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.3489478376
Short name T131
Test name
Test status
Simulation time 4491204488 ps
CPU time 360.84 seconds
Started Jul 20 06:40:39 PM PDT 24
Finished Jul 20 06:46:41 PM PDT 24
Peak memory 265744 kb
Host smart-4153aa71-7238-49e7-b7ea-4a3df6b2de03
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3489478376 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shadow_reg_erro
rs.3489478376
Directory /workspace/4.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.1746405764
Short name T156
Test name
Test status
Simulation time 953179062 ps
CPU time 73.1 seconds
Started Jul 20 06:40:32 PM PDT 24
Finished Jul 20 06:41:46 PM PDT 24
Peak memory 240700 kb
Host smart-f6b68c62-01bf-4e2d-a283-8affbb5af2a9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1746405764 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_intg_err.1746405764
Directory /workspace/7.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/18.alert_handler_lpg.4205258500
Short name T80
Test name
Test status
Simulation time 114226837183 ps
CPU time 1784.79 seconds
Started Jul 20 06:41:35 PM PDT 24
Finished Jul 20 07:11:20 PM PDT 24
Peak memory 273588 kb
Host smart-7d633844-4a65-4903-a55c-d692f46a4f94
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205258500 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg.4205258500
Directory /workspace/18.alert_handler_lpg/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all.1827748091
Short name T248
Test name
Test status
Simulation time 46275082318 ps
CPU time 2721.03 seconds
Started Jul 20 06:41:40 PM PDT 24
Finished Jul 20 07:27:02 PM PDT 24
Peak memory 288944 kb
Host smart-bab48ad3-f9b2-4b0c-ae6e-e696dedbb385
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827748091 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_ha
ndler_stress_all.1827748091
Directory /workspace/21.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.3464601604
Short name T118
Test name
Test status
Simulation time 6258594699 ps
CPU time 227.96 seconds
Started Jul 20 06:40:39 PM PDT 24
Finished Jul 20 06:44:29 PM PDT 24
Peak memory 271868 kb
Host smart-2a34eb50-a292-460b-bf5c-369cb32f5751
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3464601604 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shadow_reg_err
ors.3464601604
Directory /workspace/17.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/33.alert_handler_ping_timeout.3500510679
Short name T307
Test name
Test status
Simulation time 59287498435 ps
CPU time 549.08 seconds
Started Jul 20 06:42:29 PM PDT 24
Finished Jul 20 06:51:40 PM PDT 24
Peak memory 249020 kb
Host smart-91d7ed2a-cf72-45e4-88c4-40f46c8313ba
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500510679 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_ping_timeout.3500510679
Directory /workspace/33.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.2545211503
Short name T161
Test name
Test status
Simulation time 334983822 ps
CPU time 14.55 seconds
Started Jul 20 06:40:55 PM PDT 24
Finished Jul 20 06:41:11 PM PDT 24
Peak memory 237760 kb
Host smart-e6b9f501-3b73-4dc7-8a7a-80c35c3ce4d6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2545211503 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_intg_err.2545211503
Directory /workspace/17.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.3077314893
Short name T143
Test name
Test status
Simulation time 4688380988 ps
CPU time 688.37 seconds
Started Jul 20 06:40:26 PM PDT 24
Finished Jul 20 06:51:55 PM PDT 24
Peak memory 265588 kb
Host smart-cb137321-6f90-42a4-96b8-52a5c8cf5307
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077314893 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.alert_handler_shadow_reg_errors_with_csr_rw.3077314893
Directory /workspace/3.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/23.alert_handler_lpg.1979232727
Short name T338
Test name
Test status
Simulation time 68569696855 ps
CPU time 1659.19 seconds
Started Jul 20 06:41:50 PM PDT 24
Finished Jul 20 07:09:30 PM PDT 24
Peak memory 289364 kb
Host smart-fb01c52e-8430-4c21-a72b-49c50334e734
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1979232727 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg.1979232727
Directory /workspace/23.alert_handler_lpg/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all.664781754
Short name T255
Test name
Test status
Simulation time 525000504981 ps
CPU time 2273.07 seconds
Started Jul 20 06:42:11 PM PDT 24
Finished Jul 20 07:20:05 PM PDT 24
Peak memory 273792 kb
Host smart-7240db3f-e1e2-465e-9802-d14cbe4ea428
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664781754 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_han
dler_stress_all.664781754
Directory /workspace/31.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.1065730039
Short name T133
Test name
Test status
Simulation time 16593321476 ps
CPU time 326.38 seconds
Started Jul 20 06:40:22 PM PDT 24
Finished Jul 20 06:45:49 PM PDT 24
Peak memory 273004 kb
Host smart-6b4ac72a-ac6e-4650-bc72-2e604e1cd8c4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1065730039 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shadow_reg_erro
rs.1065730039
Directory /workspace/1.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/0.alert_handler_alert_accum_saturation.3637760408
Short name T177
Test name
Test status
Simulation time 53592727 ps
CPU time 2.6 seconds
Started Jul 20 06:41:09 PM PDT 24
Finished Jul 20 06:41:14 PM PDT 24
Peak memory 249100 kb
Host smart-aed9d98c-c3cf-4565-a75d-1f106436ddd1
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3637760408 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_alert_accum_saturation.3637760408
Directory /workspace/0.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/1.alert_handler_alert_accum_saturation.4269618178
Short name T203
Test name
Test status
Simulation time 35895135 ps
CPU time 2.36 seconds
Started Jul 20 06:41:05 PM PDT 24
Finished Jul 20 06:41:08 PM PDT 24
Peak memory 249128 kb
Host smart-8c811dcd-07d9-4806-b415-cf413fc06200
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4269618178 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_alert_accum_saturation.4269618178
Directory /workspace/1.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/11.alert_handler_alert_accum_saturation.206959090
Short name T190
Test name
Test status
Simulation time 49813100 ps
CPU time 2.68 seconds
Started Jul 20 06:41:25 PM PDT 24
Finished Jul 20 06:41:30 PM PDT 24
Peak memory 249244 kb
Host smart-be1ef51d-df52-42a8-a2c3-cfffb990a225
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=206959090 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_alert_accum_saturation.206959090
Directory /workspace/11.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all_with_rand_reset.3506423261
Short name T276
Test name
Test status
Simulation time 37187673383 ps
CPU time 3334.33 seconds
Started Jul 20 06:41:19 PM PDT 24
Finished Jul 20 07:36:54 PM PDT 24
Peak memory 302504 kb
Host smart-063ce216-46b0-4d32-8280-ee51feb25beb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506423261 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 10.alert_handler_stress_all_with_rand_reset.3506423261
Directory /workspace/10.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.alert_handler_lpg.2575532522
Short name T350
Test name
Test status
Simulation time 81436912325 ps
CPU time 2572.93 seconds
Started Jul 20 06:41:12 PM PDT 24
Finished Jul 20 07:24:06 PM PDT 24
Peak memory 290048 kb
Host smart-76bbffd8-61e7-4ddc-b7c8-cae3bdae519f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575532522 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg.2575532522
Directory /workspace/11.alert_handler_lpg/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all_with_rand_reset.3718489416
Short name T82
Test name
Test status
Simulation time 248562033928 ps
CPU time 4188.8 seconds
Started Jul 20 06:41:25 PM PDT 24
Finished Jul 20 07:51:16 PM PDT 24
Peak memory 306520 kb
Host smart-d0032ec4-0e95-4087-a9eb-6e0a6d514603
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718489416 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 11.alert_handler_stress_all_with_rand_reset.3718489416
Directory /workspace/11.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.alert_handler_lpg_stub_clk.1467133544
Short name T234
Test name
Test status
Simulation time 9342230568 ps
CPU time 1154.72 seconds
Started Jul 20 06:41:32 PM PDT 24
Finished Jul 20 07:00:48 PM PDT 24
Peak memory 287496 kb
Host smart-55110f50-43b7-416d-9936-5e1516602e41
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467133544 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg_stub_clk.1467133544
Directory /workspace/17.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all.4239386667
Short name T259
Test name
Test status
Simulation time 95449626253 ps
CPU time 2918.56 seconds
Started Jul 20 06:41:41 PM PDT 24
Finished Jul 20 07:30:20 PM PDT 24
Peak memory 289408 kb
Host smart-83261aee-8e49-4210-b56c-f543501d5bbf
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239386667 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_ha
ndler_stress_all.4239386667
Directory /workspace/22.alert_handler_stress_all/latest

Test location /workspace/coverage/default/43.alert_handler_ping_timeout.1550130483
Short name T323
Test name
Test status
Simulation time 9762189721 ps
CPU time 402.43 seconds
Started Jul 20 06:42:59 PM PDT 24
Finished Jul 20 06:49:42 PM PDT 24
Peak memory 249088 kb
Host smart-d0061028-e6e1-4121-ad81-cc01eea26834
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550130483 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_ping_timeout.1550130483
Directory /workspace/43.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.3960714292
Short name T128
Test name
Test status
Simulation time 19827621986 ps
CPU time 353.52 seconds
Started Jul 20 06:40:35 PM PDT 24
Finished Jul 20 06:46:31 PM PDT 24
Peak memory 265592 kb
Host smart-4a170811-005d-4157-a267-04a4ee26c63b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3960714292 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shadow_reg_erro
rs.3960714292
Directory /workspace/3.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all_with_rand_reset.2063825628
Short name T24
Test name
Test status
Simulation time 79439290965 ps
CPU time 1566.06 seconds
Started Jul 20 06:41:09 PM PDT 24
Finished Jul 20 07:07:17 PM PDT 24
Peak memory 290108 kb
Host smart-475fdd19-7362-4dc3-9b62-6eeb67f04851
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063825628 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 8.alert_handler_stress_all_with_rand_reset.2063825628
Directory /workspace/8.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.871238355
Short name T122
Test name
Test status
Simulation time 55703013723 ps
CPU time 877.62 seconds
Started Jul 20 06:41:02 PM PDT 24
Finished Jul 20 06:55:40 PM PDT 24
Peak memory 265680 kb
Host smart-0fe37854-10c1-4c00-8a75-a936f510b9a1
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871238355 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 19.alert_handler_shadow_reg_errors_with_csr_rw.871238355
Directory /workspace/19.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.4165316105
Short name T357
Test name
Test status
Simulation time 12624883988 ps
CPU time 1042.35 seconds
Started Jul 20 06:40:24 PM PDT 24
Finished Jul 20 06:57:47 PM PDT 24
Peak memory 265440 kb
Host smart-0c48c170-bc23-4a19-a4d6-0d16cb0ffb2a
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165316105 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.alert_handler_shadow_reg_errors_with_csr_rw.4165316105
Directory /workspace/0.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/0.alert_handler_random_classes.4175159392
Short name T543
Test name
Test status
Simulation time 1030254568 ps
CPU time 62.16 seconds
Started Jul 20 06:41:07 PM PDT 24
Finished Jul 20 06:42:10 PM PDT 24
Peak memory 256728 kb
Host smart-6ce7e263-6d7c-4458-885c-a4a443c07f55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41751
59392 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_classes.4175159392
Directory /workspace/0.alert_handler_random_classes/latest

Test location /workspace/coverage/default/1.alert_handler_random_classes.1293551829
Short name T293
Test name
Test status
Simulation time 545317739 ps
CPU time 34.56 seconds
Started Jul 20 06:41:02 PM PDT 24
Finished Jul 20 06:41:37 PM PDT 24
Peak memory 248528 kb
Host smart-6f0974f3-1421-46f5-a70e-4ba0b9895bcf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12935
51829 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_classes.1293551829
Directory /workspace/1.alert_handler_random_classes/latest

Test location /workspace/coverage/default/1.alert_handler_sig_int_fail.3185119678
Short name T246
Test name
Test status
Simulation time 460703555 ps
CPU time 31.22 seconds
Started Jul 20 06:40:54 PM PDT 24
Finished Jul 20 06:41:27 PM PDT 24
Peak memory 248952 kb
Host smart-fc3d615f-5243-4142-a3cc-efd9c8e75861
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31851
19678 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sig_int_fail.3185119678
Directory /workspace/1.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all_with_rand_reset.243878190
Short name T96
Test name
Test status
Simulation time 6046092742 ps
CPU time 120 seconds
Started Jul 20 06:41:06 PM PDT 24
Finished Jul 20 06:43:07 PM PDT 24
Peak memory 265468 kb
Host smart-67c1ec62-b87e-407c-affa-35dfda4485fd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243878190 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 1.alert_handler_stress_all_with_rand_reset.243878190
Directory /workspace/1.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all.2317220943
Short name T22
Test name
Test status
Simulation time 15324404212 ps
CPU time 342.74 seconds
Started Jul 20 06:42:42 PM PDT 24
Finished Jul 20 06:48:27 PM PDT 24
Peak memory 264888 kb
Host smart-974ad2dd-0d00-4220-8d34-e324699694fd
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317220943 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_ha
ndler_stress_all.2317220943
Directory /workspace/13.alert_handler_stress_all/latest

Test location /workspace/coverage/default/18.alert_handler_entropy.836668776
Short name T290
Test name
Test status
Simulation time 108783146650 ps
CPU time 1531.73 seconds
Started Jul 20 06:41:31 PM PDT 24
Finished Jul 20 07:07:04 PM PDT 24
Peak memory 273208 kb
Host smart-1854ada9-cd7b-4eda-a474-230ce297c732
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836668776 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy.836668776
Directory /workspace/18.alert_handler_entropy/latest

Test location /workspace/coverage/default/18.alert_handler_ping_timeout.2157242136
Short name T318
Test name
Test status
Simulation time 16586416929 ps
CPU time 170.17 seconds
Started Jul 20 06:41:31 PM PDT 24
Finished Jul 20 06:44:23 PM PDT 24
Peak memory 249260 kb
Host smart-1e24a194-e998-4633-a33c-3882cf08afaa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157242136 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_ping_timeout.2157242136
Directory /workspace/18.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_sig_int_fail.3569639822
Short name T100
Test name
Test status
Simulation time 551583032 ps
CPU time 35.52 seconds
Started Jul 20 06:40:53 PM PDT 24
Finished Jul 20 06:41:31 PM PDT 24
Peak memory 249000 kb
Host smart-887d3e05-d15f-4460-8a7c-8f9658fbec20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35696
39822 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sig_int_fail.3569639822
Directory /workspace/2.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all.806259606
Short name T299
Test name
Test status
Simulation time 14129863005 ps
CPU time 1263.39 seconds
Started Jul 20 06:40:55 PM PDT 24
Finished Jul 20 07:02:00 PM PDT 24
Peak memory 289732 kb
Host smart-ae96ea6f-0ee9-4b68-b0bd-f559c422f706
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806259606 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_hand
ler_stress_all.806259606
Directory /workspace/2.alert_handler_stress_all/latest

Test location /workspace/coverage/default/22.alert_handler_random_alerts.1888043087
Short name T297
Test name
Test status
Simulation time 4666706540 ps
CPU time 59.95 seconds
Started Jul 20 06:41:41 PM PDT 24
Finished Jul 20 06:42:42 PM PDT 24
Peak memory 256308 kb
Host smart-054d2e68-59ce-442a-b539-1b03fa0dd8a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18880
43087 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_alerts.1888043087
Directory /workspace/22.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all.2107225582
Short name T47
Test name
Test status
Simulation time 19103017249 ps
CPU time 1109.65 seconds
Started Jul 20 06:42:09 PM PDT 24
Finished Jul 20 07:00:40 PM PDT 24
Peak memory 265408 kb
Host smart-4870a408-b828-4da4-b78d-62d88dcbded3
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107225582 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_ha
ndler_stress_all.2107225582
Directory /workspace/28.alert_handler_stress_all/latest

Test location /workspace/coverage/default/29.alert_handler_lpg.3080150069
Short name T593
Test name
Test status
Simulation time 83024388097 ps
CPU time 2590.4 seconds
Started Jul 20 06:42:11 PM PDT 24
Finished Jul 20 07:25:23 PM PDT 24
Peak memory 281792 kb
Host smart-211bcd09-9eff-43b5-928f-1718d2f6b9eb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3080150069 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg.3080150069
Directory /workspace/29.alert_handler_lpg/latest

Test location /workspace/coverage/default/32.alert_handler_lpg.4141158096
Short name T683
Test name
Test status
Simulation time 9370791001 ps
CPU time 758.94 seconds
Started Jul 20 06:42:23 PM PDT 24
Finished Jul 20 06:55:03 PM PDT 24
Peak memory 266372 kb
Host smart-4c41de21-dd19-4cd9-b574-604239836b9d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141158096 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg.4141158096
Directory /workspace/32.alert_handler_lpg/latest

Test location /workspace/coverage/default/32.alert_handler_sig_int_fail.1789657074
Short name T261
Test name
Test status
Simulation time 484083157 ps
CPU time 22.34 seconds
Started Jul 20 06:42:21 PM PDT 24
Finished Jul 20 06:42:44 PM PDT 24
Peak memory 248264 kb
Host smart-4e8144bc-6eec-4819-9624-01ba0c0bcd52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17896
57074 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_sig_int_fail.1789657074
Directory /workspace/32.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/37.alert_handler_lpg.3483882168
Short name T279
Test name
Test status
Simulation time 89238770157 ps
CPU time 2477.88 seconds
Started Jul 20 06:42:34 PM PDT 24
Finished Jul 20 07:23:53 PM PDT 24
Peak memory 283312 kb
Host smart-9f7efa4f-46f7-447b-8a82-c4a33168f75f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483882168 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg.3483882168
Directory /workspace/37.alert_handler_lpg/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all.2111983033
Short name T265
Test name
Test status
Simulation time 3261585472 ps
CPU time 180.81 seconds
Started Jul 20 06:43:05 PM PDT 24
Finished Jul 20 06:46:07 PM PDT 24
Peak memory 257160 kb
Host smart-483f2205-8217-4ab3-b608-9dacbacb79c8
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111983033 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_ha
ndler_stress_all.2111983033
Directory /workspace/43.alert_handler_stress_all/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all_with_rand_reset.649277459
Short name T102
Test name
Test status
Simulation time 91183740332 ps
CPU time 6205.51 seconds
Started Jul 20 06:43:14 PM PDT 24
Finished Jul 20 08:26:41 PM PDT 24
Peak memory 320752 kb
Host smart-0516ab61-5260-434e-b6f9-e12a894a5709
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649277459 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 45.alert_handler_stress_all_with_rand_reset.649277459
Directory /workspace/45.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.3388645503
Short name T149
Test name
Test status
Simulation time 236115235 ps
CPU time 4.59 seconds
Started Jul 20 06:40:44 PM PDT 24
Finished Jul 20 06:40:50 PM PDT 24
Peak memory 237696 kb
Host smart-a2333b82-0701-4abb-9cdb-5f6dd6d746b0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3388645503 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_intg_err.3388645503
Directory /workspace/10.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.2338704551
Short name T167
Test name
Test status
Simulation time 888838436 ps
CPU time 32.04 seconds
Started Jul 20 06:40:41 PM PDT 24
Finished Jul 20 06:41:15 PM PDT 24
Peak memory 237764 kb
Host smart-4453e358-d32a-49ae-85a5-9dab9301adba
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2338704551 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_intg_err.2338704551
Directory /workspace/13.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.3619361294
Short name T162
Test name
Test status
Simulation time 295353216 ps
CPU time 20.28 seconds
Started Jul 20 06:41:02 PM PDT 24
Finished Jul 20 06:41:23 PM PDT 24
Peak memory 239796 kb
Host smart-4e322155-1065-400f-8efa-b09e80803506
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3619361294 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_intg_err.3619361294
Directory /workspace/18.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.1242365074
Short name T159
Test name
Test status
Simulation time 65731489 ps
CPU time 4.72 seconds
Started Jul 20 06:40:37 PM PDT 24
Finished Jul 20 06:40:44 PM PDT 24
Peak memory 238000 kb
Host smart-61515706-0799-4043-a11c-d465d1ea4571
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1242365074 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_intg_err.1242365074
Directory /workspace/4.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.3540265981
Short name T164
Test name
Test status
Simulation time 325322058 ps
CPU time 29.44 seconds
Started Jul 20 06:40:35 PM PDT 24
Finished Jul 20 06:41:07 PM PDT 24
Peak memory 237676 kb
Host smart-fbf9ef0b-096d-4117-b08d-e43990b3f01a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3540265981 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_intg_err.3540265981
Directory /workspace/0.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.2198097203
Short name T123
Test name
Test status
Simulation time 4411696159 ps
CPU time 337.76 seconds
Started Jul 20 06:40:35 PM PDT 24
Finished Jul 20 06:46:15 PM PDT 24
Peak memory 272416 kb
Host smart-1b53fb84-69ad-453f-b201-f58286305190
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2198097203 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shadow_reg_err
ors.2198097203
Directory /workspace/12.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.840108278
Short name T155
Test name
Test status
Simulation time 1783293142 ps
CPU time 32.41 seconds
Started Jul 20 06:40:15 PM PDT 24
Finished Jul 20 06:40:48 PM PDT 24
Peak memory 246228 kb
Host smart-29c9a4bb-59b2-4125-9ce1-b2f17d09642a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=840108278 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_intg_err.840108278
Directory /workspace/2.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.2103303911
Short name T158
Test name
Test status
Simulation time 123402263 ps
CPU time 6.84 seconds
Started Jul 20 06:40:34 PM PDT 24
Finished Jul 20 06:40:43 PM PDT 24
Peak memory 237776 kb
Host smart-d86758e5-bf6a-4b1e-b4b3-cd2e64675634
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2103303911 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_intg_err.2103303911
Directory /workspace/8.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.4104041991
Short name T157
Test name
Test status
Simulation time 1806378517 ps
CPU time 62.47 seconds
Started Jul 20 06:40:39 PM PDT 24
Finished Jul 20 06:41:43 PM PDT 24
Peak memory 240620 kb
Host smart-9db9474b-34ef-49d9-abce-9f9f272c6d14
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4104041991 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_intg_err.4104041991
Directory /workspace/11.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.149540003
Short name T154
Test name
Test status
Simulation time 1206045147 ps
CPU time 44.82 seconds
Started Jul 20 06:40:54 PM PDT 24
Finished Jul 20 06:41:40 PM PDT 24
Peak memory 240680 kb
Host smart-4671ed73-f421-4cdb-8331-002add75832c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=149540003 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_intg_err.149540003
Directory /workspace/16.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.2828154475
Short name T160
Test name
Test status
Simulation time 1220913891 ps
CPU time 22.57 seconds
Started Jul 20 06:40:27 PM PDT 24
Finished Jul 20 06:40:50 PM PDT 24
Peak memory 240672 kb
Host smart-232a2dc0-172d-462b-9a17-13c9cd2b8d90
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2828154475 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_intg_err.2828154475
Directory /workspace/3.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.3136324318
Short name T163
Test name
Test status
Simulation time 28147133 ps
CPU time 2.68 seconds
Started Jul 20 06:40:27 PM PDT 24
Finished Jul 20 06:40:31 PM PDT 24
Peak memory 237488 kb
Host smart-e46082a8-44bc-4572-9064-e7498b73452d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3136324318 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_intg_err.3136324318
Directory /workspace/5.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.800366303
Short name T150
Test name
Test status
Simulation time 37057900 ps
CPU time 2.98 seconds
Started Jul 20 06:40:27 PM PDT 24
Finished Jul 20 06:40:31 PM PDT 24
Peak memory 238424 kb
Host smart-0de3469f-dcb8-4d5b-816f-30a9d6f6eb3f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=800366303 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_intg_err.800366303
Directory /workspace/6.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.1186951500
Short name T169
Test name
Test status
Simulation time 77768702 ps
CPU time 4.67 seconds
Started Jul 20 06:40:42 PM PDT 24
Finished Jul 20 06:40:48 PM PDT 24
Peak memory 237736 kb
Host smart-f0c1194d-815e-4214-9598-83308b90f5c8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1186951500 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_intg_err.1186951500
Directory /workspace/9.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.181771197
Short name T772
Test name
Test status
Simulation time 1058785068 ps
CPU time 147.53 seconds
Started Jul 20 06:40:29 PM PDT 24
Finished Jul 20 06:42:57 PM PDT 24
Peak memory 240584 kb
Host smart-70eee51f-d27b-4b40-9194-95af8a7d26d9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=181771197 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_aliasing.181771197
Directory /workspace/0.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.1466347265
Short name T180
Test name
Test status
Simulation time 1705336494 ps
CPU time 242.37 seconds
Started Jul 20 06:40:32 PM PDT 24
Finished Jul 20 06:44:35 PM PDT 24
Peak memory 237768 kb
Host smart-bdef52ee-ab6d-448c-ac03-d57bc9ed6fe4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1466347265 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_bit_bash.1466347265
Directory /workspace/0.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.2429380261
Short name T747
Test name
Test status
Simulation time 497115061 ps
CPU time 11.52 seconds
Started Jul 20 06:40:26 PM PDT 24
Finished Jul 20 06:40:38 PM PDT 24
Peak memory 240696 kb
Host smart-03b232da-e8a9-4723-9fc0-0b1a92875069
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2429380261 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_hw_reset.2429380261
Directory /workspace/0.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.1645106049
Short name T166
Test name
Test status
Simulation time 398727068 ps
CPU time 8.83 seconds
Started Jul 20 06:40:31 PM PDT 24
Finished Jul 20 06:40:41 PM PDT 24
Peak memory 239952 kb
Host smart-de6e9b35-d34c-41f6-be43-341cd3e45f4d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645106049 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 0.alert_handler_csr_mem_rw_with_rand_reset.1645106049
Directory /workspace/0.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.2033651639
Short name T791
Test name
Test status
Simulation time 55238611 ps
CPU time 4.84 seconds
Started Jul 20 06:40:22 PM PDT 24
Finished Jul 20 06:40:27 PM PDT 24
Peak memory 240704 kb
Host smart-970ade61-e21a-4b2d-addc-fa0603cada6d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2033651639 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_rw.2033651639
Directory /workspace/0.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.2218865649
Short name T766
Test name
Test status
Simulation time 9452831 ps
CPU time 1.61 seconds
Started Jul 20 06:40:38 PM PDT 24
Finished Jul 20 06:40:41 PM PDT 24
Peak memory 236816 kb
Host smart-59575b3d-ccbf-4149-8a46-1608bc9bc617
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2218865649 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_intr_test.2218865649
Directory /workspace/0.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.1676698316
Short name T758
Test name
Test status
Simulation time 173971054 ps
CPU time 26.61 seconds
Started Jul 20 06:40:22 PM PDT 24
Finished Jul 20 06:40:49 PM PDT 24
Peak memory 248864 kb
Host smart-ff7041d9-8ad2-405e-a90b-0dbbd9298c27
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1676698316 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_same_csr_out
standing.1676698316
Directory /workspace/0.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.3105613366
Short name T760
Test name
Test status
Simulation time 83005581 ps
CPU time 9.93 seconds
Started Jul 20 06:40:18 PM PDT 24
Finished Jul 20 06:40:29 PM PDT 24
Peak memory 248096 kb
Host smart-b2a20beb-5a7a-40f7-bac0-f403e02c875f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3105613366 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_errors.3105613366
Directory /workspace/0.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.4130785919
Short name T778
Test name
Test status
Simulation time 6923078967 ps
CPU time 138.77 seconds
Started Jul 20 06:40:31 PM PDT 24
Finished Jul 20 06:42:51 PM PDT 24
Peak memory 240464 kb
Host smart-dca58322-e46f-417d-b11e-080bad31d2a9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4130785919 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_aliasing.4130785919
Directory /workspace/1.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.161812962
Short name T738
Test name
Test status
Simulation time 29619007590 ps
CPU time 462.15 seconds
Started Jul 20 06:40:33 PM PDT 24
Finished Jul 20 06:48:18 PM PDT 24
Peak memory 236844 kb
Host smart-b0a37c21-5a02-473c-b418-c0f2578fc8e5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=161812962 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_bit_bash.161812962
Directory /workspace/1.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.1731436052
Short name T815
Test name
Test status
Simulation time 111665320 ps
CPU time 3.98 seconds
Started Jul 20 06:40:34 PM PDT 24
Finished Jul 20 06:40:40 PM PDT 24
Peak memory 240688 kb
Host smart-369206c0-6a7d-43b2-b0a2-c5b70c0e6578
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1731436052 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_hw_reset.1731436052
Directory /workspace/1.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.2426605686
Short name T720
Test name
Test status
Simulation time 214831591 ps
CPU time 7.32 seconds
Started Jul 20 06:40:24 PM PDT 24
Finished Jul 20 06:40:32 PM PDT 24
Peak memory 240992 kb
Host smart-aaac5914-b666-46a7-905a-5ad3099ca366
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426605686 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 1.alert_handler_csr_mem_rw_with_rand_reset.2426605686
Directory /workspace/1.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.1160485907
Short name T822
Test name
Test status
Simulation time 37213631 ps
CPU time 6.63 seconds
Started Jul 20 06:40:33 PM PDT 24
Finished Jul 20 06:40:42 PM PDT 24
Peak memory 237756 kb
Host smart-a28fb244-c25e-43d7-bc1d-672d5328303d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1160485907 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_rw.1160485907
Directory /workspace/1.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.278067636
Short name T355
Test name
Test status
Simulation time 12650523 ps
CPU time 1.4 seconds
Started Jul 20 06:40:19 PM PDT 24
Finished Jul 20 06:40:21 PM PDT 24
Peak memory 237764 kb
Host smart-6ffaa8ac-4db7-4753-b74a-69b97715d1b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=278067636 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_intr_test.278067636
Directory /workspace/1.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.631827510
Short name T782
Test name
Test status
Simulation time 1246472690 ps
CPU time 21.99 seconds
Started Jul 20 06:40:33 PM PDT 24
Finished Jul 20 06:40:56 PM PDT 24
Peak memory 245020 kb
Host smart-9b62668b-5984-405c-ac66-1960baf543eb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=631827510 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_same_csr_outs
tanding.631827510
Directory /workspace/1.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.1080706247
Short name T359
Test name
Test status
Simulation time 4441343960 ps
CPU time 362.67 seconds
Started Jul 20 06:40:34 PM PDT 24
Finished Jul 20 06:46:39 PM PDT 24
Peak memory 265572 kb
Host smart-e2c4bf79-d4bb-4be9-95bc-c57265fa3dec
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080706247 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.alert_handler_shadow_reg_errors_with_csr_rw.1080706247
Directory /workspace/1.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.396114157
Short name T829
Test name
Test status
Simulation time 83212801 ps
CPU time 11.29 seconds
Started Jul 20 06:40:18 PM PDT 24
Finished Jul 20 06:40:30 PM PDT 24
Peak memory 252152 kb
Host smart-864253b5-f36a-4c3f-98da-59e7e7008eda
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=396114157 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_errors.396114157
Directory /workspace/1.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.4225909886
Short name T817
Test name
Test status
Simulation time 126797043 ps
CPU time 2.57 seconds
Started Jul 20 06:40:24 PM PDT 24
Finished Jul 20 06:40:27 PM PDT 24
Peak memory 237868 kb
Host smart-7eba62c7-9f6b-4bd9-b054-a5d1775df4d9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4225909886 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_intg_err.4225909886
Directory /workspace/1.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.1968007548
Short name T792
Test name
Test status
Simulation time 62382884 ps
CPU time 6.37 seconds
Started Jul 20 06:40:37 PM PDT 24
Finished Jul 20 06:40:46 PM PDT 24
Peak memory 252628 kb
Host smart-c1cd2954-2420-4516-8304-f0b8d92ab3e1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968007548 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 10.alert_handler_csr_mem_rw_with_rand_reset.1968007548
Directory /workspace/10.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.1772637184
Short name T776
Test name
Test status
Simulation time 65736288 ps
CPU time 5.28 seconds
Started Jul 20 06:40:40 PM PDT 24
Finished Jul 20 06:40:47 PM PDT 24
Peak memory 236808 kb
Host smart-2e888862-cd27-4e43-86b0-cc7c50f31a77
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1772637184 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_csr_rw.1772637184
Directory /workspace/10.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.179408469
Short name T786
Test name
Test status
Simulation time 10115422 ps
CPU time 1.21 seconds
Started Jul 20 06:40:35 PM PDT 24
Finished Jul 20 06:40:39 PM PDT 24
Peak memory 235836 kb
Host smart-3124958f-0489-409c-a3b1-018b96eb9ced
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=179408469 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_intr_test.179408469
Directory /workspace/10.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.3194718070
Short name T828
Test name
Test status
Simulation time 971810338 ps
CPU time 21.79 seconds
Started Jul 20 06:40:40 PM PDT 24
Finished Jul 20 06:41:03 PM PDT 24
Peak memory 245388 kb
Host smart-29287351-cfd4-45ce-a38d-2af068f7c9eb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3194718070 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_same_csr_ou
tstanding.3194718070
Directory /workspace/10.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.2044608683
Short name T147
Test name
Test status
Simulation time 1654047615 ps
CPU time 230.39 seconds
Started Jul 20 06:41:03 PM PDT 24
Finished Jul 20 06:44:55 PM PDT 24
Peak memory 271668 kb
Host smart-dc92f84b-9ef5-46cb-bea2-22b13beea548
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2044608683 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shadow_reg_err
ors.2044608683
Directory /workspace/10.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.156664055
Short name T755
Test name
Test status
Simulation time 113014251 ps
CPU time 8.47 seconds
Started Jul 20 06:40:35 PM PDT 24
Finished Jul 20 06:40:46 PM PDT 24
Peak memory 252988 kb
Host smart-90c68222-87d4-479f-8fd5-e3fcf29b6884
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=156664055 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_errors.156664055
Directory /workspace/10.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.4106479478
Short name T811
Test name
Test status
Simulation time 680899829 ps
CPU time 15.67 seconds
Started Jul 20 06:40:42 PM PDT 24
Finished Jul 20 06:40:59 PM PDT 24
Peak memory 256984 kb
Host smart-4acc47c8-0721-4adb-8a3d-9dda33950cd5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106479478 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 11.alert_handler_csr_mem_rw_with_rand_reset.4106479478
Directory /workspace/11.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.3591062199
Short name T770
Test name
Test status
Simulation time 883134903 ps
CPU time 8.04 seconds
Started Jul 20 06:40:36 PM PDT 24
Finished Jul 20 06:40:47 PM PDT 24
Peak memory 240716 kb
Host smart-08ef52ac-978a-4c7d-b481-2363ced280c1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3591062199 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_csr_rw.3591062199
Directory /workspace/11.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.190987109
Short name T801
Test name
Test status
Simulation time 8948028 ps
CPU time 1.3 seconds
Started Jul 20 06:40:32 PM PDT 24
Finished Jul 20 06:40:34 PM PDT 24
Peak memory 236864 kb
Host smart-1270be8b-4b4d-4838-bb0d-f8c49b27b4f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=190987109 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_intr_test.190987109
Directory /workspace/11.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.3251817889
Short name T168
Test name
Test status
Simulation time 105267130 ps
CPU time 10.88 seconds
Started Jul 20 06:40:33 PM PDT 24
Finished Jul 20 06:40:45 PM PDT 24
Peak memory 245108 kb
Host smart-dadd9731-96e6-46d7-9709-a55adb12382f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3251817889 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_same_csr_ou
tstanding.3251817889
Directory /workspace/11.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.3969230052
Short name T144
Test name
Test status
Simulation time 18328257373 ps
CPU time 1231.48 seconds
Started Jul 20 06:40:36 PM PDT 24
Finished Jul 20 07:01:11 PM PDT 24
Peak memory 273736 kb
Host smart-3566321a-fe03-4f05-bbd9-5345a160ae3b
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969230052 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 11.alert_handler_shadow_reg_errors_with_csr_rw.3969230052
Directory /workspace/11.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.1411931649
Short name T734
Test name
Test status
Simulation time 203596214 ps
CPU time 7.71 seconds
Started Jul 20 06:40:34 PM PDT 24
Finished Jul 20 06:40:44 PM PDT 24
Peak memory 248956 kb
Host smart-71be2998-356e-4d33-ab56-996f28f22350
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1411931649 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_errors.1411931649
Directory /workspace/11.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.560740273
Short name T736
Test name
Test status
Simulation time 31209727 ps
CPU time 4.78 seconds
Started Jul 20 06:40:37 PM PDT 24
Finished Jul 20 06:40:44 PM PDT 24
Peak memory 241484 kb
Host smart-9db04dbd-e53d-487c-a4d2-037b54748b10
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560740273 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 12.alert_handler_csr_mem_rw_with_rand_reset.560740273
Directory /workspace/12.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.2362770181
Short name T181
Test name
Test status
Simulation time 35372100 ps
CPU time 5.51 seconds
Started Jul 20 06:40:35 PM PDT 24
Finished Jul 20 06:40:43 PM PDT 24
Peak memory 237752 kb
Host smart-241b1d04-dd3b-4f88-a4d3-6e4d6be3bd69
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2362770181 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_csr_rw.2362770181
Directory /workspace/12.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.360186645
Short name T711
Test name
Test status
Simulation time 35521757 ps
CPU time 1.52 seconds
Started Jul 20 06:40:38 PM PDT 24
Finished Jul 20 06:40:41 PM PDT 24
Peak memory 236680 kb
Host smart-897c419d-074d-4d91-a859-7c0125a5dc3c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=360186645 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_intr_test.360186645
Directory /workspace/12.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.3480397263
Short name T719
Test name
Test status
Simulation time 3253038171 ps
CPU time 43.29 seconds
Started Jul 20 06:40:33 PM PDT 24
Finished Jul 20 06:41:19 PM PDT 24
Peak memory 245984 kb
Host smart-8730f566-405d-485a-b710-abb13f990fc9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3480397263 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_same_csr_ou
tstanding.3480397263
Directory /workspace/12.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.908938075
Short name T115
Test name
Test status
Simulation time 8144291788 ps
CPU time 378.3 seconds
Started Jul 20 06:40:36 PM PDT 24
Finished Jul 20 06:46:57 PM PDT 24
Peak memory 265552 kb
Host smart-955b5094-7f72-44fa-b27d-257c0b7682ac
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908938075 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 12.alert_handler_shadow_reg_errors_with_csr_rw.908938075
Directory /workspace/12.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.147414480
Short name T236
Test name
Test status
Simulation time 550710620 ps
CPU time 17.27 seconds
Started Jul 20 06:40:40 PM PDT 24
Finished Jul 20 06:40:59 PM PDT 24
Peak memory 249008 kb
Host smart-6cf1ba3d-5c7a-4b2b-b6b1-c94ef0fa4493
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=147414480 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_errors.147414480
Directory /workspace/12.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_intg_err.1666097580
Short name T170
Test name
Test status
Simulation time 5544471238 ps
CPU time 39.19 seconds
Started Jul 20 06:40:33 PM PDT 24
Finished Jul 20 06:41:14 PM PDT 24
Peak memory 246120 kb
Host smart-e92c1f7d-e4fe-4cae-8990-bc296a1df4ef
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1666097580 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_intg_err.1666097580
Directory /workspace/12.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.642521961
Short name T802
Test name
Test status
Simulation time 153760153 ps
CPU time 7.94 seconds
Started Jul 20 06:40:34 PM PDT 24
Finished Jul 20 06:40:45 PM PDT 24
Peak memory 241072 kb
Host smart-51498520-080b-4da7-9951-2e6246a6cc07
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642521961 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 13.alert_handler_csr_mem_rw_with_rand_reset.642521961
Directory /workspace/13.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.185770610
Short name T788
Test name
Test status
Simulation time 93991665 ps
CPU time 4.96 seconds
Started Jul 20 06:40:37 PM PDT 24
Finished Jul 20 06:40:44 PM PDT 24
Peak memory 237756 kb
Host smart-cb8fef2f-b289-43fe-8484-69fad5cc2176
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=185770610 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_csr_rw.185770610
Directory /workspace/13.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.349655401
Short name T725
Test name
Test status
Simulation time 14879309 ps
CPU time 1.3 seconds
Started Jul 20 06:40:41 PM PDT 24
Finished Jul 20 06:40:43 PM PDT 24
Peak memory 237716 kb
Host smart-4f622c13-558c-452b-9bde-8ae398a3e532
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=349655401 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_intr_test.349655401
Directory /workspace/13.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.1622305846
Short name T748
Test name
Test status
Simulation time 99427457 ps
CPU time 13.79 seconds
Started Jul 20 06:40:39 PM PDT 24
Finished Jul 20 06:40:54 PM PDT 24
Peak memory 245948 kb
Host smart-42af8e12-a6f6-4d2b-9909-e5b7b45ea823
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1622305846 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_same_csr_ou
tstanding.1622305846
Directory /workspace/13.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.645122186
Short name T136
Test name
Test status
Simulation time 1960002002 ps
CPU time 130.08 seconds
Started Jul 20 06:40:35 PM PDT 24
Finished Jul 20 06:42:48 PM PDT 24
Peak memory 265548 kb
Host smart-712739e1-3de8-4b41-a578-bb0b7cd4279e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=645122186 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shadow_reg_erro
rs.645122186
Directory /workspace/13.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.3261174023
Short name T713
Test name
Test status
Simulation time 1315623912 ps
CPU time 29.81 seconds
Started Jul 20 06:40:33 PM PDT 24
Finished Jul 20 06:41:05 PM PDT 24
Peak memory 249092 kb
Host smart-ec64b945-6bd0-4ff5-8434-7d34f6864713
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3261174023 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_errors.3261174023
Directory /workspace/13.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.3070260308
Short name T779
Test name
Test status
Simulation time 241175436 ps
CPU time 13.22 seconds
Started Jul 20 06:40:36 PM PDT 24
Finished Jul 20 06:40:52 PM PDT 24
Peak memory 249968 kb
Host smart-2445ee0d-066f-4822-8222-43d41f8af53c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070260308 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 14.alert_handler_csr_mem_rw_with_rand_reset.3070260308
Directory /workspace/14.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.2691578932
Short name T832
Test name
Test status
Simulation time 133105371 ps
CPU time 11.05 seconds
Started Jul 20 06:40:38 PM PDT 24
Finished Jul 20 06:40:51 PM PDT 24
Peak memory 237756 kb
Host smart-9b563b78-78ea-4db2-bec4-a4f92c10ff64
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2691578932 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_csr_rw.2691578932
Directory /workspace/14.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.324619354
Short name T746
Test name
Test status
Simulation time 11044060 ps
CPU time 1.66 seconds
Started Jul 20 06:40:40 PM PDT 24
Finished Jul 20 06:40:43 PM PDT 24
Peak memory 235368 kb
Host smart-ff6a78c5-cc34-4ccb-952c-615addcda71b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=324619354 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_intr_test.324619354
Directory /workspace/14.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.501625591
Short name T794
Test name
Test status
Simulation time 352118123 ps
CPU time 13.67 seconds
Started Jul 20 06:40:35 PM PDT 24
Finished Jul 20 06:40:51 PM PDT 24
Peak memory 245964 kb
Host smart-f9480984-9248-4577-ad9b-abece795dd14
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=501625591 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_same_csr_out
standing.501625591
Directory /workspace/14.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.806143825
Short name T121
Test name
Test status
Simulation time 975253351 ps
CPU time 103.94 seconds
Started Jul 20 06:40:33 PM PDT 24
Finished Jul 20 06:42:20 PM PDT 24
Peak memory 257352 kb
Host smart-d95ae271-0ee6-4c42-9a37-394317ce3ad9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=806143825 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shadow_reg_erro
rs.806143825
Directory /workspace/14.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.495424310
Short name T142
Test name
Test status
Simulation time 8861924641 ps
CPU time 778.85 seconds
Started Jul 20 06:40:40 PM PDT 24
Finished Jul 20 06:53:40 PM PDT 24
Peak memory 265792 kb
Host smart-67615e51-f156-4895-8bb3-0ef18a9a8533
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495424310 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 14.alert_handler_shadow_reg_errors_with_csr_rw.495424310
Directory /workspace/14.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.1453700651
Short name T717
Test name
Test status
Simulation time 1056276821 ps
CPU time 9.81 seconds
Started Jul 20 06:40:39 PM PDT 24
Finished Jul 20 06:40:51 PM PDT 24
Peak memory 248156 kb
Host smart-90f1e3f8-c691-4e3b-8434-9039e2efe3ca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1453700651 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_errors.1453700651
Directory /workspace/14.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.3847380473
Short name T714
Test name
Test status
Simulation time 136447471 ps
CPU time 11.78 seconds
Started Jul 20 06:40:45 PM PDT 24
Finished Jul 20 06:40:57 PM PDT 24
Peak memory 248952 kb
Host smart-daa9c0e0-9785-48c5-8398-1b693babbd6d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847380473 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 15.alert_handler_csr_mem_rw_with_rand_reset.3847380473
Directory /workspace/15.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.796414697
Short name T361
Test name
Test status
Simulation time 169676128 ps
CPU time 4.7 seconds
Started Jul 20 06:40:47 PM PDT 24
Finished Jul 20 06:40:52 PM PDT 24
Peak memory 237756 kb
Host smart-3130b5ee-02f5-4515-b128-7c07e6dbba3a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=796414697 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_csr_rw.796414697
Directory /workspace/15.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.2766761977
Short name T823
Test name
Test status
Simulation time 12358530 ps
CPU time 1.31 seconds
Started Jul 20 06:40:40 PM PDT 24
Finished Jul 20 06:40:43 PM PDT 24
Peak memory 236812 kb
Host smart-7aa01e82-074a-44ac-8960-4b829f66907f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2766761977 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_intr_test.2766761977
Directory /workspace/15.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.2340243369
Short name T183
Test name
Test status
Simulation time 492551555 ps
CPU time 37.46 seconds
Started Jul 20 06:40:43 PM PDT 24
Finished Jul 20 06:41:21 PM PDT 24
Peak memory 248896 kb
Host smart-6ad9e5a2-980a-44bd-8536-05e2cacb7dcf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2340243369 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_same_csr_ou
tstanding.2340243369
Directory /workspace/15.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.2561359193
Short name T120
Test name
Test status
Simulation time 6272266094 ps
CPU time 195.08 seconds
Started Jul 20 06:40:49 PM PDT 24
Finished Jul 20 06:44:05 PM PDT 24
Peak memory 265584 kb
Host smart-d53da44a-2c2a-4819-bfb5-a859d6834236
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2561359193 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shadow_reg_err
ors.2561359193
Directory /workspace/15.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.4283958881
Short name T712
Test name
Test status
Simulation time 87329213 ps
CPU time 7.07 seconds
Started Jul 20 06:40:52 PM PDT 24
Finished Jul 20 06:41:01 PM PDT 24
Peak memory 249992 kb
Host smart-8f983234-a6e9-4c17-8d2c-9174d3fb8615
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4283958881 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_errors.4283958881
Directory /workspace/15.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.2765106141
Short name T243
Test name
Test status
Simulation time 3539549858 ps
CPU time 75.73 seconds
Started Jul 20 06:40:56 PM PDT 24
Finished Jul 20 06:42:14 PM PDT 24
Peak memory 240740 kb
Host smart-09a0be02-9ca6-4110-a8b4-41c96f112886
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2765106141 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_intg_err.2765106141
Directory /workspace/15.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.725584770
Short name T715
Test name
Test status
Simulation time 31196082 ps
CPU time 5.48 seconds
Started Jul 20 06:40:41 PM PDT 24
Finished Jul 20 06:40:48 PM PDT 24
Peak memory 240572 kb
Host smart-244b6b66-7fcc-413a-91bc-2041db17b2cc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725584770 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 16.alert_handler_csr_mem_rw_with_rand_reset.725584770
Directory /workspace/16.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.287908180
Short name T763
Test name
Test status
Simulation time 23105214 ps
CPU time 3.65 seconds
Started Jul 20 06:40:41 PM PDT 24
Finished Jul 20 06:40:47 PM PDT 24
Peak memory 236800 kb
Host smart-f27ec21e-68c2-4563-9769-fcc602dc5e29
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=287908180 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_csr_rw.287908180
Directory /workspace/16.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.8355593
Short name T800
Test name
Test status
Simulation time 12244892 ps
CPU time 1.45 seconds
Started Jul 20 06:40:41 PM PDT 24
Finished Jul 20 06:40:44 PM PDT 24
Peak memory 237772 kb
Host smart-ff67f226-33dd-45e9-8876-0900629580ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=8355593 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_intr_test.8355593
Directory /workspace/16.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.2292932838
Short name T762
Test name
Test status
Simulation time 329110761 ps
CPU time 25.23 seconds
Started Jul 20 06:40:47 PM PDT 24
Finished Jul 20 06:41:13 PM PDT 24
Peak memory 245936 kb
Host smart-dcb9a23f-fb0f-4c74-8802-c1deb301c051
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2292932838 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_same_csr_ou
tstanding.2292932838
Directory /workspace/16.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.1910868705
Short name T145
Test name
Test status
Simulation time 9158953765 ps
CPU time 272.99 seconds
Started Jul 20 06:40:44 PM PDT 24
Finished Jul 20 06:45:18 PM PDT 24
Peak memory 272248 kb
Host smart-21bb5c61-3821-4151-9bf5-bbd371c71778
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1910868705 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shadow_reg_err
ors.1910868705
Directory /workspace/16.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.3845496761
Short name T134
Test name
Test status
Simulation time 4621934039 ps
CPU time 611.83 seconds
Started Jul 20 06:40:41 PM PDT 24
Finished Jul 20 06:50:55 PM PDT 24
Peak memory 265616 kb
Host smart-4f84fcfa-5de8-43d2-843f-b9b870ac5312
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845496761 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 16.alert_handler_shadow_reg_errors_with_csr_rw.3845496761
Directory /workspace/16.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.2289475474
Short name T227
Test name
Test status
Simulation time 1728724770 ps
CPU time 31.98 seconds
Started Jul 20 06:40:43 PM PDT 24
Finished Jul 20 06:41:16 PM PDT 24
Peak memory 251928 kb
Host smart-ff2028d6-75c3-48e6-97af-fc325c08d534
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2289475474 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_errors.2289475474
Directory /workspace/16.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.737538070
Short name T806
Test name
Test status
Simulation time 146391088 ps
CPU time 7.52 seconds
Started Jul 20 06:40:43 PM PDT 24
Finished Jul 20 06:40:51 PM PDT 24
Peak memory 240832 kb
Host smart-6a740b41-e4ff-4e22-9bf3-d7072b475c23
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737538070 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 17.alert_handler_csr_mem_rw_with_rand_reset.737538070
Directory /workspace/17.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.679644330
Short name T781
Test name
Test status
Simulation time 507227466 ps
CPU time 9.16 seconds
Started Jul 20 06:40:42 PM PDT 24
Finished Jul 20 06:40:52 PM PDT 24
Peak memory 236792 kb
Host smart-26b2a366-20c6-4df5-b42c-c06470333d11
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=679644330 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_csr_rw.679644330
Directory /workspace/17.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.4206340662
Short name T798
Test name
Test status
Simulation time 50800990 ps
CPU time 1.39 seconds
Started Jul 20 06:40:56 PM PDT 24
Finished Jul 20 06:40:59 PM PDT 24
Peak memory 236676 kb
Host smart-f726e9cc-bc67-434a-af7d-e4345331404d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4206340662 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_intr_test.4206340662
Directory /workspace/17.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.3206399735
Short name T765
Test name
Test status
Simulation time 601998511 ps
CPU time 39.14 seconds
Started Jul 20 06:40:41 PM PDT 24
Finished Jul 20 06:41:22 PM PDT 24
Peak memory 244996 kb
Host smart-b5037d4d-b1e7-4aa9-b96a-8219841d12a1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3206399735 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_same_csr_ou
tstanding.3206399735
Directory /workspace/17.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.3022666664
Short name T126
Test name
Test status
Simulation time 4496682942 ps
CPU time 649.1 seconds
Started Jul 20 06:40:52 PM PDT 24
Finished Jul 20 06:51:43 PM PDT 24
Peak memory 265620 kb
Host smart-38d68ab6-d093-48bf-86a7-d70010d2dbf3
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022666664 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 17.alert_handler_shadow_reg_errors_with_csr_rw.3022666664
Directory /workspace/17.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.702369427
Short name T751
Test name
Test status
Simulation time 345859632 ps
CPU time 11.77 seconds
Started Jul 20 06:40:41 PM PDT 24
Finished Jul 20 06:40:54 PM PDT 24
Peak memory 253336 kb
Host smart-3ed85799-477b-4bfb-8488-a44457283173
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=702369427 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_errors.702369427
Directory /workspace/17.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.3943036564
Short name T710
Test name
Test status
Simulation time 113908958 ps
CPU time 5.47 seconds
Started Jul 20 06:40:58 PM PDT 24
Finished Jul 20 06:41:05 PM PDT 24
Peak memory 240888 kb
Host smart-61b59a37-7c41-4265-883f-a0da033a53f6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943036564 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 18.alert_handler_csr_mem_rw_with_rand_reset.3943036564
Directory /workspace/18.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.2590754418
Short name T754
Test name
Test status
Simulation time 20170647 ps
CPU time 2.98 seconds
Started Jul 20 06:40:46 PM PDT 24
Finished Jul 20 06:40:49 PM PDT 24
Peak memory 236840 kb
Host smart-25cb5945-88ee-45dd-9f39-9537d9a2f3da
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2590754418 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_csr_rw.2590754418
Directory /workspace/18.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.1301426639
Short name T353
Test name
Test status
Simulation time 9600025 ps
CPU time 1.62 seconds
Started Jul 20 06:40:51 PM PDT 24
Finished Jul 20 06:40:55 PM PDT 24
Peak memory 237716 kb
Host smart-3cb9a9a0-5faa-4b03-ad04-00cc55c2f75b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1301426639 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_intr_test.1301426639
Directory /workspace/18.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.3944939281
Short name T773
Test name
Test status
Simulation time 261833079 ps
CPU time 18.86 seconds
Started Jul 20 06:40:58 PM PDT 24
Finished Jul 20 06:41:18 PM PDT 24
Peak memory 240672 kb
Host smart-74464fc7-4ba7-4588-95e5-04550826ae6c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3944939281 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_same_csr_ou
tstanding.3944939281
Directory /workspace/18.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.1810871306
Short name T809
Test name
Test status
Simulation time 1526081763 ps
CPU time 89.27 seconds
Started Jul 20 06:40:48 PM PDT 24
Finished Jul 20 06:42:18 PM PDT 24
Peak memory 265548 kb
Host smart-cda90cb7-4f4f-44df-a76e-7f21035fdd57
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1810871306 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shadow_reg_err
ors.1810871306
Directory /workspace/18.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.1365772516
Short name T360
Test name
Test status
Simulation time 49716615633 ps
CPU time 983.92 seconds
Started Jul 20 06:40:49 PM PDT 24
Finished Jul 20 06:57:14 PM PDT 24
Peak memory 265560 kb
Host smart-01ac53fd-7e1b-48de-9d17-fe5719117607
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365772516 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 18.alert_handler_shadow_reg_errors_with_csr_rw.1365772516
Directory /workspace/18.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.2274100962
Short name T756
Test name
Test status
Simulation time 584752402 ps
CPU time 10.76 seconds
Started Jul 20 06:41:03 PM PDT 24
Finished Jul 20 06:41:14 PM PDT 24
Peak memory 254396 kb
Host smart-b0d12fd8-0c75-4620-ae05-257105fe1a6b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2274100962 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_errors.2274100962
Directory /workspace/18.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.1368741535
Short name T750
Test name
Test status
Simulation time 580854355 ps
CPU time 8.83 seconds
Started Jul 20 06:41:18 PM PDT 24
Finished Jul 20 06:41:27 PM PDT 24
Peak memory 240712 kb
Host smart-2efe5c9c-bce3-415a-b0a1-98a81a91c101
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368741535 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 19.alert_handler_csr_mem_rw_with_rand_reset.1368741535
Directory /workspace/19.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.1215884833
Short name T824
Test name
Test status
Simulation time 100220240 ps
CPU time 3.95 seconds
Started Jul 20 06:40:55 PM PDT 24
Finished Jul 20 06:41:01 PM PDT 24
Peak memory 237760 kb
Host smart-ab347f23-20fc-4ee6-b91c-c70a0e811d0c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1215884833 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_csr_rw.1215884833
Directory /workspace/19.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.3983488655
Short name T826
Test name
Test status
Simulation time 42279320 ps
CPU time 1.48 seconds
Started Jul 20 06:40:50 PM PDT 24
Finished Jul 20 06:40:53 PM PDT 24
Peak memory 237780 kb
Host smart-f7fbb89d-d163-49fd-b875-103e3a6afd25
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3983488655 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_intr_test.3983488655
Directory /workspace/19.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.882065959
Short name T767
Test name
Test status
Simulation time 1868742170 ps
CPU time 21.06 seconds
Started Jul 20 06:40:50 PM PDT 24
Finished Jul 20 06:41:13 PM PDT 24
Peak memory 245832 kb
Host smart-eda62a14-b3b1-4daa-adeb-57ec0d2023f0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=882065959 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_same_csr_out
standing.882065959
Directory /workspace/19.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.3431643681
Short name T141
Test name
Test status
Simulation time 2479333736 ps
CPU time 178.46 seconds
Started Jul 20 06:40:56 PM PDT 24
Finished Jul 20 06:43:56 PM PDT 24
Peak memory 257384 kb
Host smart-33fb011f-79f5-4480-bd49-b8e374fccdf2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3431643681 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shadow_reg_err
ors.3431643681
Directory /workspace/19.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.682804447
Short name T708
Test name
Test status
Simulation time 205439233 ps
CPU time 12.83 seconds
Started Jul 20 06:41:15 PM PDT 24
Finished Jul 20 06:41:28 PM PDT 24
Peak memory 253576 kb
Host smart-0c64f212-12ee-4b5e-94e3-236e90e13533
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=682804447 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_errors.682804447
Directory /workspace/19.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.583577613
Short name T795
Test name
Test status
Simulation time 956972233 ps
CPU time 36.6 seconds
Started Jul 20 06:40:47 PM PDT 24
Finished Jul 20 06:41:24 PM PDT 24
Peak memory 248904 kb
Host smart-81c7a6b0-acc3-47a9-be7d-f004ac3bcb48
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=583577613 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_intg_err.583577613
Directory /workspace/19.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.3464259724
Short name T785
Test name
Test status
Simulation time 5052457626 ps
CPU time 175.83 seconds
Started Jul 20 06:40:25 PM PDT 24
Finished Jul 20 06:43:21 PM PDT 24
Peak memory 240752 kb
Host smart-3d8cb22a-fae3-4426-9fe6-ccb96408de7e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3464259724 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_aliasing.3464259724
Directory /workspace/2.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.2961101230
Short name T718
Test name
Test status
Simulation time 23752356013 ps
CPU time 416.21 seconds
Started Jul 20 06:40:33 PM PDT 24
Finished Jul 20 06:47:31 PM PDT 24
Peak memory 240752 kb
Host smart-e428d314-7c27-48ab-a978-3213c3b61fd9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2961101230 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_bit_bash.2961101230
Directory /workspace/2.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.3586766172
Short name T783
Test name
Test status
Simulation time 864915824 ps
CPU time 9.54 seconds
Started Jul 20 06:40:24 PM PDT 24
Finished Jul 20 06:40:34 PM PDT 24
Peak memory 249144 kb
Host smart-a90939e2-17ff-40a1-a5d1-1036f0a01c01
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3586766172 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_hw_reset.3586766172
Directory /workspace/2.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.1634897589
Short name T812
Test name
Test status
Simulation time 843684768 ps
CPU time 14.66 seconds
Started Jul 20 06:40:34 PM PDT 24
Finished Jul 20 06:40:51 PM PDT 24
Peak memory 252236 kb
Host smart-6c856fc6-7f6f-4a44-92c3-2bf19df42fb4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634897589 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 2.alert_handler_csr_mem_rw_with_rand_reset.1634897589
Directory /workspace/2.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.3959139421
Short name T742
Test name
Test status
Simulation time 243770283 ps
CPU time 9.49 seconds
Started Jul 20 06:40:36 PM PDT 24
Finished Jul 20 06:40:48 PM PDT 24
Peak memory 237756 kb
Host smart-2b5f885f-acf3-4d1b-aac8-206465e25400
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3959139421 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_rw.3959139421
Directory /workspace/2.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.1872612072
Short name T743
Test name
Test status
Simulation time 8426727 ps
CPU time 1.55 seconds
Started Jul 20 06:40:21 PM PDT 24
Finished Jul 20 06:40:24 PM PDT 24
Peak memory 236824 kb
Host smart-14da7fcb-46d2-4eb7-90b9-7779fa68ed8b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1872612072 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_intr_test.1872612072
Directory /workspace/2.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.1056241913
Short name T731
Test name
Test status
Simulation time 745662183 ps
CPU time 23.87 seconds
Started Jul 20 06:40:27 PM PDT 24
Finished Jul 20 06:40:52 PM PDT 24
Peak memory 248872 kb
Host smart-b86e36a6-99b3-4011-a502-c2f7bbc5eb92
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1056241913 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_same_csr_out
standing.1056241913
Directory /workspace/2.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.933457401
Short name T830
Test name
Test status
Simulation time 5828872929 ps
CPU time 174.58 seconds
Started Jul 20 06:40:26 PM PDT 24
Finished Jul 20 06:43:21 PM PDT 24
Peak memory 265764 kb
Host smart-45ba0a20-6830-49eb-bb8f-68cbdbd3fdd9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=933457401 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shadow_reg_error
s.933457401
Directory /workspace/2.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.1746783208
Short name T129
Test name
Test status
Simulation time 25986817595 ps
CPU time 1039.2 seconds
Started Jul 20 06:40:31 PM PDT 24
Finished Jul 20 06:57:52 PM PDT 24
Peak memory 265256 kb
Host smart-cdeae373-8146-4ebb-b2b4-75f8cd108b20
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746783208 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.alert_handler_shadow_reg_errors_with_csr_rw.1746783208
Directory /workspace/2.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.3777166436
Short name T775
Test name
Test status
Simulation time 57601970 ps
CPU time 8.89 seconds
Started Jul 20 06:40:32 PM PDT 24
Finished Jul 20 06:40:42 PM PDT 24
Peak memory 248264 kb
Host smart-26664d7e-f4d2-4a10-a6be-5357cca9a5cd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3777166436 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_errors.3777166436
Directory /workspace/2.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.423198626
Short name T771
Test name
Test status
Simulation time 24550397 ps
CPU time 1.36 seconds
Started Jul 20 06:41:01 PM PDT 24
Finished Jul 20 06:41:03 PM PDT 24
Peak memory 237756 kb
Host smart-5a92b71f-d51f-4c76-bd96-1611cc59ab10
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=423198626 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.alert_handler_intr_test.423198626
Directory /workspace/20.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.231378353
Short name T807
Test name
Test status
Simulation time 19202027 ps
CPU time 1.37 seconds
Started Jul 20 06:40:53 PM PDT 24
Finished Jul 20 06:40:56 PM PDT 24
Peak memory 237772 kb
Host smart-faf8b882-6b4e-42b7-befe-932e8a6c2d2a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=231378353 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.alert_handler_intr_test.231378353
Directory /workspace/21.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.4272635672
Short name T745
Test name
Test status
Simulation time 18409896 ps
CPU time 1.53 seconds
Started Jul 20 06:40:50 PM PDT 24
Finished Jul 20 06:40:55 PM PDT 24
Peak memory 235560 kb
Host smart-73ee8c82-166e-43ff-a30b-73033993e008
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4272635672 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.alert_handler_intr_test.4272635672
Directory /workspace/22.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.1429713179
Short name T730
Test name
Test status
Simulation time 25093119 ps
CPU time 2.01 seconds
Started Jul 20 06:40:51 PM PDT 24
Finished Jul 20 06:40:55 PM PDT 24
Peak memory 237760 kb
Host smart-073ef06c-de88-439e-a999-12fd371e4704
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1429713179 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.alert_handler_intr_test.1429713179
Directory /workspace/23.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.1860814231
Short name T740
Test name
Test status
Simulation time 34736779 ps
CPU time 1.4 seconds
Started Jul 20 06:40:54 PM PDT 24
Finished Jul 20 06:40:57 PM PDT 24
Peak memory 237628 kb
Host smart-27a1228b-bfdd-456e-9747-ac1b1974166c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1860814231 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.alert_handler_intr_test.1860814231
Directory /workspace/24.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.1613354068
Short name T799
Test name
Test status
Simulation time 6803850 ps
CPU time 1.68 seconds
Started Jul 20 06:40:54 PM PDT 24
Finished Jul 20 06:40:57 PM PDT 24
Peak memory 236812 kb
Host smart-d9ab46fb-1914-4f79-85b5-09d518c8e59f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1613354068 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.alert_handler_intr_test.1613354068
Directory /workspace/25.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.2993579516
Short name T735
Test name
Test status
Simulation time 11351287 ps
CPU time 1.35 seconds
Started Jul 20 06:40:49 PM PDT 24
Finished Jul 20 06:40:51 PM PDT 24
Peak memory 237628 kb
Host smart-4c07e524-ec7f-4c74-995b-16386038cb0e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2993579516 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.alert_handler_intr_test.2993579516
Directory /workspace/26.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.963951109
Short name T729
Test name
Test status
Simulation time 11373781 ps
CPU time 1.38 seconds
Started Jul 20 06:40:49 PM PDT 24
Finished Jul 20 06:40:52 PM PDT 24
Peak memory 235840 kb
Host smart-f3a53d3f-1fee-4501-b767-3edf3837ee11
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=963951109 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.alert_handler_intr_test.963951109
Directory /workspace/27.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.415240963
Short name T820
Test name
Test status
Simulation time 8755731 ps
CPU time 1.56 seconds
Started Jul 20 06:41:06 PM PDT 24
Finished Jul 20 06:41:08 PM PDT 24
Peak memory 237760 kb
Host smart-949a2bfc-e153-4b49-b3ef-b36a995ceab2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=415240963 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.alert_handler_intr_test.415240963
Directory /workspace/28.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.4109659355
Short name T741
Test name
Test status
Simulation time 7832008 ps
CPU time 1.37 seconds
Started Jul 20 06:40:50 PM PDT 24
Finished Jul 20 06:40:54 PM PDT 24
Peak memory 236824 kb
Host smart-3ac65666-2585-4665-9f0c-e329cebaad5d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4109659355 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.alert_handler_intr_test.4109659355
Directory /workspace/29.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.2033027965
Short name T789
Test name
Test status
Simulation time 5018614378 ps
CPU time 250.51 seconds
Started Jul 20 06:40:25 PM PDT 24
Finished Jul 20 06:44:37 PM PDT 24
Peak memory 241140 kb
Host smart-a61cc2dd-1757-4b3f-b05d-c703bb31e69b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2033027965 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_aliasing.2033027965
Directory /workspace/3.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.392866551
Short name T759
Test name
Test status
Simulation time 15140799445 ps
CPU time 469.32 seconds
Started Jul 20 06:40:24 PM PDT 24
Finished Jul 20 06:48:14 PM PDT 24
Peak memory 236864 kb
Host smart-6d1015e8-c9fd-4fc5-babc-aeb68c2e0a22
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=392866551 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_bit_bash.392866551
Directory /workspace/3.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.1837913793
Short name T218
Test name
Test status
Simulation time 1610478066 ps
CPU time 8.5 seconds
Started Jul 20 06:40:26 PM PDT 24
Finished Jul 20 06:40:36 PM PDT 24
Peak memory 240676 kb
Host smart-5f5ceb95-cb52-4889-9a59-c93ac2ce1c02
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1837913793 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_hw_reset.1837913793
Directory /workspace/3.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.2560318608
Short name T726
Test name
Test status
Simulation time 1829540823 ps
CPU time 9.57 seconds
Started Jul 20 06:40:34 PM PDT 24
Finished Jul 20 06:40:46 PM PDT 24
Peak memory 238028 kb
Host smart-a83e0f05-2738-4689-b486-be506f29fc03
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560318608 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 3.alert_handler_csr_mem_rw_with_rand_reset.2560318608
Directory /workspace/3.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.2247296348
Short name T724
Test name
Test status
Simulation time 65759578 ps
CPU time 3.34 seconds
Started Jul 20 06:40:37 PM PDT 24
Finished Jul 20 06:40:42 PM PDT 24
Peak memory 240700 kb
Host smart-a72f4d31-5e58-4f9c-b043-aa8afe96039d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2247296348 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_rw.2247296348
Directory /workspace/3.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.3015237441
Short name T803
Test name
Test status
Simulation time 8552409 ps
CPU time 1.41 seconds
Started Jul 20 06:40:26 PM PDT 24
Finished Jul 20 06:40:28 PM PDT 24
Peak memory 237768 kb
Host smart-461bca2e-a591-4d1b-8e5b-e720a5c0c0a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3015237441 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_intr_test.3015237441
Directory /workspace/3.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.528868792
Short name T182
Test name
Test status
Simulation time 1107207159 ps
CPU time 24.44 seconds
Started Jul 20 06:40:37 PM PDT 24
Finished Jul 20 06:41:04 PM PDT 24
Peak memory 245980 kb
Host smart-eb5b276c-329e-41e8-be5a-1c4a9b7a6ad6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=528868792 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_same_csr_outs
tanding.528868792
Directory /workspace/3.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.685655234
Short name T709
Test name
Test status
Simulation time 568332724 ps
CPU time 12.36 seconds
Started Jul 20 06:40:37 PM PDT 24
Finished Jul 20 06:40:52 PM PDT 24
Peak memory 247852 kb
Host smart-f357da5d-b6c7-4a38-8207-c9aa7b5346e7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=685655234 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_errors.685655234
Directory /workspace/3.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.1750589893
Short name T790
Test name
Test status
Simulation time 11382450 ps
CPU time 1.25 seconds
Started Jul 20 06:41:08 PM PDT 24
Finished Jul 20 06:41:11 PM PDT 24
Peak memory 236768 kb
Host smart-884a6ab4-3dad-43c3-bbd2-7a53def03164
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1750589893 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.alert_handler_intr_test.1750589893
Directory /workspace/30.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.2234124672
Short name T356
Test name
Test status
Simulation time 9789467 ps
CPU time 1.35 seconds
Started Jul 20 06:40:58 PM PDT 24
Finished Jul 20 06:41:01 PM PDT 24
Peak memory 237764 kb
Host smart-2bd9ab59-eeb3-49c7-9312-9fc70c7ac819
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2234124672 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.alert_handler_intr_test.2234124672
Directory /workspace/31.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.4023216993
Short name T737
Test name
Test status
Simulation time 13938287 ps
CPU time 1.29 seconds
Started Jul 20 06:41:04 PM PDT 24
Finished Jul 20 06:41:06 PM PDT 24
Peak memory 237716 kb
Host smart-d633fa3a-78b6-4708-b0eb-cc958a0642fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4023216993 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.alert_handler_intr_test.4023216993
Directory /workspace/32.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.alert_handler_intr_test.3857187589
Short name T761
Test name
Test status
Simulation time 19324368 ps
CPU time 1.95 seconds
Started Jul 20 06:41:06 PM PDT 24
Finished Jul 20 06:41:09 PM PDT 24
Peak memory 237760 kb
Host smart-6c214301-1282-4721-9223-a1a556400793
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3857187589 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.alert_handler_intr_test.3857187589
Directory /workspace/33.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.4087615861
Short name T805
Test name
Test status
Simulation time 15667082 ps
CPU time 1.83 seconds
Started Jul 20 06:40:51 PM PDT 24
Finished Jul 20 06:40:55 PM PDT 24
Peak memory 237776 kb
Host smart-a15c7c47-ea55-4553-9b52-4b1b17b602ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4087615861 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.alert_handler_intr_test.4087615861
Directory /workspace/34.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.1290282243
Short name T722
Test name
Test status
Simulation time 53372246 ps
CPU time 1.44 seconds
Started Jul 20 06:41:06 PM PDT 24
Finished Jul 20 06:41:09 PM PDT 24
Peak memory 236808 kb
Host smart-cedcb30f-1068-41c0-bb83-2961ec412d59
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1290282243 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.alert_handler_intr_test.1290282243
Directory /workspace/35.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.1080589734
Short name T813
Test name
Test status
Simulation time 10134486 ps
CPU time 1.38 seconds
Started Jul 20 06:40:49 PM PDT 24
Finished Jul 20 06:40:51 PM PDT 24
Peak memory 235752 kb
Host smart-c13de59b-e728-4127-bdbb-5391ba480d20
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1080589734 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.alert_handler_intr_test.1080589734
Directory /workspace/36.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.3175446017
Short name T219
Test name
Test status
Simulation time 10778604 ps
CPU time 1.69 seconds
Started Jul 20 06:40:49 PM PDT 24
Finished Jul 20 06:40:51 PM PDT 24
Peak memory 235740 kb
Host smart-108d7d39-8e22-42a3-9dbf-1d2abd2a7a7f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3175446017 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.alert_handler_intr_test.3175446017
Directory /workspace/37.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.3912212408
Short name T816
Test name
Test status
Simulation time 9632628 ps
CPU time 1.6 seconds
Started Jul 20 06:41:00 PM PDT 24
Finished Jul 20 06:41:02 PM PDT 24
Peak memory 236832 kb
Host smart-f70344b7-d559-491b-8110-672e468fdf71
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3912212408 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.alert_handler_intr_test.3912212408
Directory /workspace/38.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.1782731162
Short name T352
Test name
Test status
Simulation time 8924003 ps
CPU time 1.6 seconds
Started Jul 20 06:40:51 PM PDT 24
Finished Jul 20 06:40:55 PM PDT 24
Peak memory 236784 kb
Host smart-d7a330c8-3d12-43de-94b1-6e85cdbaaeb7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1782731162 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.alert_handler_intr_test.1782731162
Directory /workspace/39.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.4260260364
Short name T821
Test name
Test status
Simulation time 2263656033 ps
CPU time 168.11 seconds
Started Jul 20 06:40:27 PM PDT 24
Finished Jul 20 06:43:16 PM PDT 24
Peak memory 240756 kb
Host smart-7190a0a1-0e5d-4dae-ba36-2259db493e42
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4260260364 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_aliasing.4260260364
Directory /workspace/4.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.3454387294
Short name T165
Test name
Test status
Simulation time 1637446762 ps
CPU time 112.89 seconds
Started Jul 20 06:40:34 PM PDT 24
Finished Jul 20 06:42:29 PM PDT 24
Peak memory 240704 kb
Host smart-0bf4d2b0-721b-4f6c-82c3-4d708ba91928
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3454387294 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_bit_bash.3454387294
Directory /workspace/4.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.2944633008
Short name T716
Test name
Test status
Simulation time 198771919 ps
CPU time 5.89 seconds
Started Jul 20 06:40:38 PM PDT 24
Finished Jul 20 06:40:46 PM PDT 24
Peak memory 248892 kb
Host smart-8c2bdd8c-b22d-4bbc-817e-973e0306f2aa
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2944633008 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_hw_reset.2944633008
Directory /workspace/4.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.1639017320
Short name T814
Test name
Test status
Simulation time 130757581 ps
CPU time 12.2 seconds
Started Jul 20 06:40:36 PM PDT 24
Finished Jul 20 06:40:51 PM PDT 24
Peak memory 257160 kb
Host smart-ba35594d-8894-4995-b51f-7fbab43d5a33
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639017320 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 4.alert_handler_csr_mem_rw_with_rand_reset.1639017320
Directory /workspace/4.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.2068529597
Short name T818
Test name
Test status
Simulation time 192915171 ps
CPU time 4.81 seconds
Started Jul 20 06:40:31 PM PDT 24
Finished Jul 20 06:40:36 PM PDT 24
Peak memory 239652 kb
Host smart-5be190dd-ad88-40a6-afc7-b10353198ccf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2068529597 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_rw.2068529597
Directory /workspace/4.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.2876722123
Short name T787
Test name
Test status
Simulation time 13312278 ps
CPU time 1.39 seconds
Started Jul 20 06:40:36 PM PDT 24
Finished Jul 20 06:40:40 PM PDT 24
Peak memory 235848 kb
Host smart-e86b5ceb-fe3c-4e4f-8ced-a7ad3f0caeb4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2876722123 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_intr_test.2876722123
Directory /workspace/4.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.3714465885
Short name T827
Test name
Test status
Simulation time 1185143670 ps
CPU time 22.83 seconds
Started Jul 20 06:40:27 PM PDT 24
Finished Jul 20 06:40:51 PM PDT 24
Peak memory 245008 kb
Host smart-72cd627b-c822-4e42-8d4a-1913f8c69b48
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3714465885 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_same_csr_out
standing.3714465885
Directory /workspace/4.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.279356156
Short name T757
Test name
Test status
Simulation time 801369710 ps
CPU time 12.03 seconds
Started Jul 20 06:40:35 PM PDT 24
Finished Jul 20 06:40:50 PM PDT 24
Peak memory 253700 kb
Host smart-2a586616-3b8b-49c1-8c35-05dbf9e326db
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=279356156 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_errors.279356156
Directory /workspace/4.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.3148022890
Short name T151
Test name
Test status
Simulation time 10068422 ps
CPU time 1.38 seconds
Started Jul 20 06:40:51 PM PDT 24
Finished Jul 20 06:40:55 PM PDT 24
Peak memory 237772 kb
Host smart-22d3fbc8-722b-4547-8554-ef7309141fcd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3148022890 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.alert_handler_intr_test.3148022890
Directory /workspace/41.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.3530436087
Short name T217
Test name
Test status
Simulation time 10426292 ps
CPU time 1.42 seconds
Started Jul 20 06:40:50 PM PDT 24
Finished Jul 20 06:40:55 PM PDT 24
Peak memory 236700 kb
Host smart-7f1e647a-bd02-4899-8adf-84fcd5be16aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3530436087 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.alert_handler_intr_test.3530436087
Directory /workspace/42.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.1631367405
Short name T793
Test name
Test status
Simulation time 6825199 ps
CPU time 1.58 seconds
Started Jul 20 06:40:59 PM PDT 24
Finished Jul 20 06:41:01 PM PDT 24
Peak memory 237772 kb
Host smart-9bfe5a04-d213-4fda-b47d-507d256f8402
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1631367405 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.alert_handler_intr_test.1631367405
Directory /workspace/43.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.834891517
Short name T732
Test name
Test status
Simulation time 15464452 ps
CPU time 1.85 seconds
Started Jul 20 06:41:16 PM PDT 24
Finished Jul 20 06:41:18 PM PDT 24
Peak memory 236724 kb
Host smart-42908a9b-eb85-4e1f-9328-fa0d7ed6fca7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=834891517 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.alert_handler_intr_test.834891517
Directory /workspace/44.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.3003559211
Short name T808
Test name
Test status
Simulation time 8254391 ps
CPU time 1.51 seconds
Started Jul 20 06:40:54 PM PDT 24
Finished Jul 20 06:40:57 PM PDT 24
Peak memory 235868 kb
Host smart-a69edfc3-3d27-4e5a-bc9a-f15aad4ddb09
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3003559211 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.alert_handler_intr_test.3003559211
Directory /workspace/45.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.1180768034
Short name T764
Test name
Test status
Simulation time 20172461 ps
CPU time 1.46 seconds
Started Jul 20 06:40:47 PM PDT 24
Finished Jul 20 06:40:50 PM PDT 24
Peak memory 237700 kb
Host smart-5362a2f3-486b-489f-810c-80b3d853c094
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1180768034 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.alert_handler_intr_test.1180768034
Directory /workspace/46.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.2049827752
Short name T152
Test name
Test status
Simulation time 9140641 ps
CPU time 1.51 seconds
Started Jul 20 06:41:16 PM PDT 24
Finished Jul 20 06:41:18 PM PDT 24
Peak memory 237760 kb
Host smart-2abc2176-431c-4912-bc1a-2cc333ffacab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2049827752 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.alert_handler_intr_test.2049827752
Directory /workspace/47.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.4249030431
Short name T728
Test name
Test status
Simulation time 7727136 ps
CPU time 1.45 seconds
Started Jul 20 06:40:50 PM PDT 24
Finished Jul 20 06:40:53 PM PDT 24
Peak memory 235836 kb
Host smart-573306d2-6c2d-4d0b-ad07-7e5bd8e386cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4249030431 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.alert_handler_intr_test.4249030431
Directory /workspace/49.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.3823665438
Short name T768
Test name
Test status
Simulation time 112967175 ps
CPU time 9.81 seconds
Started Jul 20 06:40:39 PM PDT 24
Finished Jul 20 06:40:50 PM PDT 24
Peak memory 241440 kb
Host smart-ce4e43f3-8519-4e02-83ee-f264aee9e3f7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823665438 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 5.alert_handler_csr_mem_rw_with_rand_reset.3823665438
Directory /workspace/5.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.1826367697
Short name T727
Test name
Test status
Simulation time 61172562 ps
CPU time 5.32 seconds
Started Jul 20 06:40:27 PM PDT 24
Finished Jul 20 06:40:33 PM PDT 24
Peak memory 240692 kb
Host smart-f6e4931a-0102-4da5-9ab2-1f8821ff3caa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1826367697 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_csr_rw.1826367697
Directory /workspace/5.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.801902298
Short name T753
Test name
Test status
Simulation time 26805080 ps
CPU time 1.47 seconds
Started Jul 20 06:40:25 PM PDT 24
Finished Jul 20 06:40:27 PM PDT 24
Peak memory 236872 kb
Host smart-5027608b-848c-487b-93da-82f3897926f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=801902298 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_intr_test.801902298
Directory /workspace/5.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.468742173
Short name T744
Test name
Test status
Simulation time 348358906 ps
CPU time 13.89 seconds
Started Jul 20 06:40:27 PM PDT 24
Finished Jul 20 06:40:42 PM PDT 24
Peak memory 245964 kb
Host smart-c19fee59-efc8-4cd4-a6a0-18b28e9ef9f9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=468742173 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_same_csr_outs
tanding.468742173
Directory /workspace/5.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.498645383
Short name T137
Test name
Test status
Simulation time 2160169690 ps
CPU time 413.72 seconds
Started Jul 20 06:40:25 PM PDT 24
Finished Jul 20 06:47:19 PM PDT 24
Peak memory 265540 kb
Host smart-a68be005-fa45-487f-a6c8-26ea923e847e
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498645383 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.alert_handler_shadow_reg_errors_with_csr_rw.498645383
Directory /workspace/5.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.2206591108
Short name T804
Test name
Test status
Simulation time 242581666 ps
CPU time 15.45 seconds
Started Jul 20 06:40:32 PM PDT 24
Finished Jul 20 06:40:49 PM PDT 24
Peak memory 249064 kb
Host smart-85346315-bafc-448b-9aab-2ecbd0dd79df
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2206591108 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_errors.2206591108
Directory /workspace/5.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.1300689597
Short name T752
Test name
Test status
Simulation time 98774287 ps
CPU time 9.8 seconds
Started Jul 20 06:40:29 PM PDT 24
Finished Jul 20 06:40:39 PM PDT 24
Peak memory 238824 kb
Host smart-f2398e24-b1ad-4294-969d-c2f7720b06e6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300689597 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 6.alert_handler_csr_mem_rw_with_rand_reset.1300689597
Directory /workspace/6.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.3213404417
Short name T179
Test name
Test status
Simulation time 196871708 ps
CPU time 10.99 seconds
Started Jul 20 06:40:39 PM PDT 24
Finished Jul 20 06:40:52 PM PDT 24
Peak memory 237656 kb
Host smart-ee16bcb6-c555-4037-80bd-b412ac7ab554
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3213404417 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_csr_rw.3213404417
Directory /workspace/6.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.1473564399
Short name T733
Test name
Test status
Simulation time 11582346 ps
CPU time 1.41 seconds
Started Jul 20 06:40:38 PM PDT 24
Finished Jul 20 06:40:41 PM PDT 24
Peak memory 236820 kb
Host smart-37c000d4-c907-4a8e-80c0-04487996ace5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1473564399 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_intr_test.1473564399
Directory /workspace/6.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.2140697579
Short name T796
Test name
Test status
Simulation time 983763798 ps
CPU time 19.33 seconds
Started Jul 20 06:40:34 PM PDT 24
Finished Jul 20 06:40:56 PM PDT 24
Peak memory 245036 kb
Host smart-14a458aa-3941-4a8c-9d40-f9ab3234b66b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2140697579 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_same_csr_out
standing.2140697579
Directory /workspace/6.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.2730409708
Short name T124
Test name
Test status
Simulation time 9644880860 ps
CPU time 211.93 seconds
Started Jul 20 06:40:36 PM PDT 24
Finished Jul 20 06:44:11 PM PDT 24
Peak memory 265580 kb
Host smart-7bb3a34b-3130-4f37-89e9-d00b052fcbce
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2730409708 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shadow_reg_erro
rs.2730409708
Directory /workspace/6.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.4053662193
Short name T117
Test name
Test status
Simulation time 18576364965 ps
CPU time 364.06 seconds
Started Jul 20 06:40:35 PM PDT 24
Finished Jul 20 06:46:42 PM PDT 24
Peak memory 265776 kb
Host smart-905f7a1b-e1b3-4828-986b-615aaa380970
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053662193 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.alert_handler_shadow_reg_errors_with_csr_rw.4053662193
Directory /workspace/6.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.1257730497
Short name T810
Test name
Test status
Simulation time 28861084 ps
CPU time 4.96 seconds
Started Jul 20 06:40:34 PM PDT 24
Finished Jul 20 06:40:42 PM PDT 24
Peak memory 252612 kb
Host smart-45ff8360-9a6d-4f1a-9468-229316f47db4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1257730497 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_errors.1257730497
Directory /workspace/6.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.3243217334
Short name T777
Test name
Test status
Simulation time 56508514 ps
CPU time 5.65 seconds
Started Jul 20 06:40:32 PM PDT 24
Finished Jul 20 06:40:39 PM PDT 24
Peak memory 240748 kb
Host smart-8d9d70b9-a3a0-41ab-8609-929805b7846f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243217334 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 7.alert_handler_csr_mem_rw_with_rand_reset.3243217334
Directory /workspace/7.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.515216754
Short name T185
Test name
Test status
Simulation time 183922259 ps
CPU time 4.46 seconds
Started Jul 20 06:40:34 PM PDT 24
Finished Jul 20 06:40:41 PM PDT 24
Peak memory 236940 kb
Host smart-af26c862-5379-4cf0-813d-3819fbd194f2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=515216754 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_csr_rw.515216754
Directory /workspace/7.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.949493927
Short name T780
Test name
Test status
Simulation time 12910858 ps
CPU time 1.35 seconds
Started Jul 20 06:40:33 PM PDT 24
Finished Jul 20 06:40:37 PM PDT 24
Peak memory 236808 kb
Host smart-ce626622-a275-448c-8834-e08d4ca6725b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=949493927 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_intr_test.949493927
Directory /workspace/7.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.3777689229
Short name T825
Test name
Test status
Simulation time 97195422 ps
CPU time 13.56 seconds
Started Jul 20 06:40:40 PM PDT 24
Finished Jul 20 06:40:56 PM PDT 24
Peak memory 248848 kb
Host smart-7a3e2370-42e2-48b4-b560-f40fa2549591
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3777689229 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_same_csr_out
standing.3777689229
Directory /workspace/7.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.3995908020
Short name T125
Test name
Test status
Simulation time 10683852761 ps
CPU time 333.12 seconds
Started Jul 20 06:40:32 PM PDT 24
Finished Jul 20 06:46:07 PM PDT 24
Peak memory 272404 kb
Host smart-7a2e2d18-98aa-4940-9c6a-b7f74a0dec50
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3995908020 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shadow_reg_erro
rs.3995908020
Directory /workspace/7.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.3532672187
Short name T138
Test name
Test status
Simulation time 2281922580 ps
CPU time 390.85 seconds
Started Jul 20 06:40:26 PM PDT 24
Finished Jul 20 06:46:57 PM PDT 24
Peak memory 265564 kb
Host smart-132ae90b-12b9-468d-a86d-016abe216bf6
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532672187 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.alert_handler_shadow_reg_errors_with_csr_rw.3532672187
Directory /workspace/7.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.3735192508
Short name T723
Test name
Test status
Simulation time 755329458 ps
CPU time 11.56 seconds
Started Jul 20 06:40:34 PM PDT 24
Finished Jul 20 06:40:48 PM PDT 24
Peak memory 252372 kb
Host smart-09e1ebb6-28ee-4629-bc06-9da217ca33da
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3735192508 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_errors.3735192508
Directory /workspace/7.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.3186296308
Short name T739
Test name
Test status
Simulation time 537286999 ps
CPU time 13.25 seconds
Started Jul 20 06:40:35 PM PDT 24
Finished Jul 20 06:40:51 PM PDT 24
Peak memory 240548 kb
Host smart-c88bd82a-1628-4f39-acc6-ed1ec751a309
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186296308 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 8.alert_handler_csr_mem_rw_with_rand_reset.3186296308
Directory /workspace/8.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.2351911609
Short name T178
Test name
Test status
Simulation time 38377850 ps
CPU time 6.95 seconds
Started Jul 20 06:40:32 PM PDT 24
Finished Jul 20 06:40:40 PM PDT 24
Peak memory 237744 kb
Host smart-0798da1e-f597-4cbe-9690-46ec4706e6d8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2351911609 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_csr_rw.2351911609
Directory /workspace/8.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.841260635
Short name T749
Test name
Test status
Simulation time 18166110 ps
CPU time 1.56 seconds
Started Jul 20 06:40:36 PM PDT 24
Finished Jul 20 06:40:40 PM PDT 24
Peak memory 237760 kb
Host smart-baf5be6b-fb06-472b-a7e8-989df1592c47
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=841260635 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_intr_test.841260635
Directory /workspace/8.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.1045808663
Short name T769
Test name
Test status
Simulation time 684507336 ps
CPU time 25.35 seconds
Started Jul 20 06:40:35 PM PDT 24
Finished Jul 20 06:41:03 PM PDT 24
Peak memory 245968 kb
Host smart-43db60c3-99ea-4dac-a7a8-8e1512ffcb17
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1045808663 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_same_csr_out
standing.1045808663
Directory /workspace/8.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.1916917302
Short name T132
Test name
Test status
Simulation time 5786349210 ps
CPU time 210.76 seconds
Started Jul 20 06:40:41 PM PDT 24
Finished Jul 20 06:44:14 PM PDT 24
Peak memory 265604 kb
Host smart-bf557fae-2791-46c4-a274-fe7d330253ff
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1916917302 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shadow_reg_erro
rs.1916917302
Directory /workspace/8.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.292625725
Short name T358
Test name
Test status
Simulation time 6020367634 ps
CPU time 361.63 seconds
Started Jul 20 06:40:35 PM PDT 24
Finished Jul 20 06:46:39 PM PDT 24
Peak memory 265224 kb
Host smart-5ff3da0c-f150-454b-af7f-8a6adc14e877
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292625725 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.alert_handler_shadow_reg_errors_with_csr_rw.292625725
Directory /workspace/8.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.2284230934
Short name T819
Test name
Test status
Simulation time 311763383 ps
CPU time 12.37 seconds
Started Jul 20 06:40:33 PM PDT 24
Finished Jul 20 06:40:48 PM PDT 24
Peak memory 247512 kb
Host smart-82a38ed7-c27e-4a9e-b6f6-3b46cc04b75a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2284230934 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_errors.2284230934
Directory /workspace/8.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.2557729156
Short name T774
Test name
Test status
Simulation time 143044185 ps
CPU time 12.05 seconds
Started Jul 20 06:40:32 PM PDT 24
Finished Jul 20 06:40:45 PM PDT 24
Peak memory 251000 kb
Host smart-d4322142-3971-47a1-ba2d-7d55772ed8b5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557729156 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 9.alert_handler_csr_mem_rw_with_rand_reset.2557729156
Directory /workspace/9.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.20520256
Short name T721
Test name
Test status
Simulation time 49477578 ps
CPU time 4.66 seconds
Started Jul 20 06:40:41 PM PDT 24
Finished Jul 20 06:40:47 PM PDT 24
Peak memory 237716 kb
Host smart-c60c084c-d0f0-45a7-9aec-408b81d48671
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=20520256 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_csr_rw.20520256
Directory /workspace/9.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.790713493
Short name T784
Test name
Test status
Simulation time 16681174 ps
CPU time 1.82 seconds
Started Jul 20 06:40:36 PM PDT 24
Finished Jul 20 06:40:40 PM PDT 24
Peak memory 237760 kb
Host smart-7f777e57-f4e8-46f0-a6ea-99c7e710a801
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=790713493 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_intr_test.790713493
Directory /workspace/9.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.1726792365
Short name T831
Test name
Test status
Simulation time 1443751597 ps
CPU time 27.62 seconds
Started Jul 20 06:40:35 PM PDT 24
Finished Jul 20 06:41:06 PM PDT 24
Peak memory 240680 kb
Host smart-1310257d-0654-40a1-a4fc-8dc91e0c9d8a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1726792365 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_same_csr_out
standing.1726792365
Directory /workspace/9.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.2813608348
Short name T146
Test name
Test status
Simulation time 2539298790 ps
CPU time 332.87 seconds
Started Jul 20 06:40:34 PM PDT 24
Finished Jul 20 06:46:10 PM PDT 24
Peak memory 269764 kb
Host smart-3369daa1-f144-496d-bedb-91470719a24d
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813608348 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.alert_handler_shadow_reg_errors_with_csr_rw.2813608348
Directory /workspace/9.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.4240108487
Short name T235
Test name
Test status
Simulation time 766849588 ps
CPU time 13.28 seconds
Started Jul 20 06:40:35 PM PDT 24
Finished Jul 20 06:40:51 PM PDT 24
Peak memory 254956 kb
Host smart-aaeff30c-c4be-4f16-a350-3af7f6a06514
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4240108487 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_errors.4240108487
Directory /workspace/9.alert_handler_tl_errors/latest

Test location /workspace/coverage/default/0.alert_handler_entropy.2365165627
Short name T514
Test name
Test status
Simulation time 13410987516 ps
CPU time 1187.13 seconds
Started Jul 20 06:40:54 PM PDT 24
Finished Jul 20 07:00:43 PM PDT 24
Peak memory 283804 kb
Host smart-cebb56ce-a3cd-4b32-8df0-c53cbbe423cc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365165627 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy.2365165627
Directory /workspace/0.alert_handler_entropy/latest

Test location /workspace/coverage/default/0.alert_handler_entropy_stress.2729391098
Short name T537
Test name
Test status
Simulation time 3182181295 ps
CPU time 35.73 seconds
Started Jul 20 06:41:08 PM PDT 24
Finished Jul 20 06:41:46 PM PDT 24
Peak memory 248952 kb
Host smart-3c16e6c1-e40e-4f86-97ea-ac762ba1c6dd
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2729391098 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy_stress.2729391098
Directory /workspace/0.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/0.alert_handler_esc_alert_accum.3274101201
Short name T565
Test name
Test status
Simulation time 6808778299 ps
CPU time 92.91 seconds
Started Jul 20 06:41:13 PM PDT 24
Finished Jul 20 06:42:46 PM PDT 24
Peak memory 257244 kb
Host smart-dbe9fd71-5601-4da9-a1be-47e797522ebe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32741
01201 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_alert_accum.3274101201
Directory /workspace/0.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/0.alert_handler_esc_intr_timeout.785547035
Short name T590
Test name
Test status
Simulation time 138810456 ps
CPU time 13.27 seconds
Started Jul 20 06:40:54 PM PDT 24
Finished Jul 20 06:41:09 PM PDT 24
Peak memory 248952 kb
Host smart-5ac41330-9265-4692-afe5-5f3bf87ce318
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78554
7035 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_intr_timeout.785547035
Directory /workspace/0.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_lpg.4084386327
Short name T576
Test name
Test status
Simulation time 15297313416 ps
CPU time 1287.14 seconds
Started Jul 20 06:41:08 PM PDT 24
Finished Jul 20 07:02:38 PM PDT 24
Peak memory 284236 kb
Host smart-5cc3a9d1-108f-48f8-8b65-d23ba5c60f5e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4084386327 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg.4084386327
Directory /workspace/0.alert_handler_lpg/latest

Test location /workspace/coverage/default/0.alert_handler_lpg_stub_clk.422498002
Short name T634
Test name
Test status
Simulation time 14793083469 ps
CPU time 1268.79 seconds
Started Jul 20 06:40:51 PM PDT 24
Finished Jul 20 07:02:02 PM PDT 24
Peak memory 289820 kb
Host smart-20c24015-ca7b-42f6-9158-f7496e7e8d24
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422498002 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg_stub_clk.422498002
Directory /workspace/0.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/0.alert_handler_ping_timeout.291342160
Short name T316
Test name
Test status
Simulation time 8026010185 ps
CPU time 325.4 seconds
Started Jul 20 06:40:58 PM PDT 24
Finished Jul 20 06:46:25 PM PDT 24
Peak memory 249004 kb
Host smart-66db792c-a085-432a-ab19-16460d7bc8ee
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291342160 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_ping_timeout.291342160
Directory /workspace/0.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_random_alerts.3958164725
Short name T529
Test name
Test status
Simulation time 815231651 ps
CPU time 45.16 seconds
Started Jul 20 06:41:08 PM PDT 24
Finished Jul 20 06:41:55 PM PDT 24
Peak memory 256340 kb
Host smart-e18db7df-3de2-41a4-876f-bdb4c08d2313
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39581
64725 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_alerts.3958164725
Directory /workspace/0.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/0.alert_handler_sec_cm.3093684056
Short name T13
Test name
Test status
Simulation time 801171857 ps
CPU time 11.76 seconds
Started Jul 20 06:40:50 PM PDT 24
Finished Jul 20 06:41:05 PM PDT 24
Peak memory 272308 kb
Host smart-604902b9-f80a-49ce-a60a-e49baae6bcf8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3093684056 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sec_cm.3093684056
Directory /workspace/0.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/0.alert_handler_sig_int_fail.70485778
Short name T675
Test name
Test status
Simulation time 12899082688 ps
CPU time 46.03 seconds
Started Jul 20 06:40:50 PM PDT 24
Finished Jul 20 06:41:37 PM PDT 24
Peak memory 256580 kb
Host smart-4272497d-f60c-482b-8261-04d93bc8a109
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70485
778 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sig_int_fail.70485778
Directory /workspace/0.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/0.alert_handler_smoke.4172629171
Short name T377
Test name
Test status
Simulation time 171858773 ps
CPU time 10.39 seconds
Started Jul 20 06:41:06 PM PDT 24
Finished Jul 20 06:41:17 PM PDT 24
Peak memory 248920 kb
Host smart-9c619486-8d59-4941-996c-6f73ecf58844
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41726
29171 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_smoke.4172629171
Directory /workspace/0.alert_handler_smoke/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all.2866320141
Short name T83
Test name
Test status
Simulation time 59514831954 ps
CPU time 1247.39 seconds
Started Jul 20 06:41:11 PM PDT 24
Finished Jul 20 07:02:00 PM PDT 24
Peak memory 290028 kb
Host smart-1e35a5ee-584a-44a9-a4cc-c4e54c416743
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866320141 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_han
dler_stress_all.2866320141
Directory /workspace/0.alert_handler_stress_all/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all_with_rand_reset.1026556737
Short name T223
Test name
Test status
Simulation time 16806580795 ps
CPU time 1011.77 seconds
Started Jul 20 06:41:15 PM PDT 24
Finished Jul 20 06:58:07 PM PDT 24
Peak memory 271872 kb
Host smart-70661d04-3372-48ab-ae13-4a08b049b7fd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026556737 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.alert_handler_stress_all_with_rand_reset.1026556737
Directory /workspace/0.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.alert_handler_entropy.17762744
Short name T63
Test name
Test status
Simulation time 170263769557 ps
CPU time 1071.72 seconds
Started Jul 20 06:41:09 PM PDT 24
Finished Jul 20 06:59:02 PM PDT 24
Peak memory 273308 kb
Host smart-fba9eb89-c553-4cba-b347-6918f5d15aba
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17762744 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy.17762744
Directory /workspace/1.alert_handler_entropy/latest

Test location /workspace/coverage/default/1.alert_handler_entropy_stress.2838161426
Short name T539
Test name
Test status
Simulation time 4909024046 ps
CPU time 53.47 seconds
Started Jul 20 06:40:52 PM PDT 24
Finished Jul 20 06:41:47 PM PDT 24
Peak memory 249096 kb
Host smart-39172396-c39e-4e76-92f7-f213e11d0caf
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2838161426 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy_stress.2838161426
Directory /workspace/1.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/1.alert_handler_esc_alert_accum.3588003161
Short name T437
Test name
Test status
Simulation time 2008029719 ps
CPU time 130.65 seconds
Started Jul 20 06:41:03 PM PDT 24
Finished Jul 20 06:43:14 PM PDT 24
Peak memory 256468 kb
Host smart-48b9ee25-608c-423a-b75a-19b58a19c899
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35880
03161 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_alert_accum.3588003161
Directory /workspace/1.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/1.alert_handler_esc_intr_timeout.3334646938
Short name T69
Test name
Test status
Simulation time 1443472359 ps
CPU time 21.11 seconds
Started Jul 20 06:40:49 PM PDT 24
Finished Jul 20 06:41:12 PM PDT 24
Peak memory 248996 kb
Host smart-700a5f50-77e4-4c20-8ee8-96cc774823e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33346
46938 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_intr_timeout.3334646938
Directory /workspace/1.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_lpg.1305915574
Short name T302
Test name
Test status
Simulation time 13202453017 ps
CPU time 1445.38 seconds
Started Jul 20 06:40:51 PM PDT 24
Finished Jul 20 07:04:59 PM PDT 24
Peak memory 288624 kb
Host smart-f52f1832-193b-46d1-a9c9-c38fc8f5ebc5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305915574 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg.1305915574
Directory /workspace/1.alert_handler_lpg/latest

Test location /workspace/coverage/default/1.alert_handler_lpg_stub_clk.2765984897
Short name T622
Test name
Test status
Simulation time 10533068976 ps
CPU time 988.5 seconds
Started Jul 20 06:40:51 PM PDT 24
Finished Jul 20 06:57:22 PM PDT 24
Peak memory 272600 kb
Host smart-57fedd75-4c4a-447b-aa9d-b4c5a0819269
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765984897 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg_stub_clk.2765984897
Directory /workspace/1.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/1.alert_handler_ping_timeout.3224898941
Short name T315
Test name
Test status
Simulation time 3064190413 ps
CPU time 121.84 seconds
Started Jul 20 06:41:05 PM PDT 24
Finished Jul 20 06:43:08 PM PDT 24
Peak memory 248964 kb
Host smart-567dbc46-2b2a-4215-a7b6-ad2f85e92ec6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224898941 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_ping_timeout.3224898941
Directory /workspace/1.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_random_alerts.2098618600
Short name T497
Test name
Test status
Simulation time 451581967 ps
CPU time 18.13 seconds
Started Jul 20 06:40:51 PM PDT 24
Finished Jul 20 06:41:12 PM PDT 24
Peak memory 248924 kb
Host smart-0d5f2e95-338d-4909-b9a5-38856c3b749a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20986
18600 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_alerts.2098618600
Directory /workspace/1.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/1.alert_handler_sec_cm.3632632397
Short name T15
Test name
Test status
Simulation time 1662087322 ps
CPU time 27.17 seconds
Started Jul 20 06:41:11 PM PDT 24
Finished Jul 20 06:41:40 PM PDT 24
Peak memory 270308 kb
Host smart-c7b67adb-2216-4d1a-a4b2-7f09addc3263
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3632632397 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sec_cm.3632632397
Directory /workspace/1.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/1.alert_handler_smoke.2083471066
Short name T403
Test name
Test status
Simulation time 983700230 ps
CPU time 22.94 seconds
Started Jul 20 06:41:20 PM PDT 24
Finished Jul 20 06:41:44 PM PDT 24
Peak memory 256900 kb
Host smart-0dd2f171-b670-4f3b-b05a-ba5bdc59d810
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20834
71066 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_smoke.2083471066
Directory /workspace/1.alert_handler_smoke/latest

Test location /workspace/coverage/default/10.alert_handler_alert_accum_saturation.2520506652
Short name T188
Test name
Test status
Simulation time 15467246 ps
CPU time 2.99 seconds
Started Jul 20 06:41:11 PM PDT 24
Finished Jul 20 06:41:16 PM PDT 24
Peak memory 249164 kb
Host smart-476a7c19-732b-4d50-a874-eae07b966c79
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2520506652 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_alert_accum_saturation.2520506652
Directory /workspace/10.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/10.alert_handler_entropy.1502444126
Short name T698
Test name
Test status
Simulation time 9876090081 ps
CPU time 898.82 seconds
Started Jul 20 06:41:13 PM PDT 24
Finished Jul 20 06:56:13 PM PDT 24
Peak memory 273660 kb
Host smart-8baa486d-d6a5-4522-820f-55385cf45414
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502444126 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy.1502444126
Directory /workspace/10.alert_handler_entropy/latest

Test location /workspace/coverage/default/10.alert_handler_entropy_stress.1899578886
Short name T568
Test name
Test status
Simulation time 2672184978 ps
CPU time 30.32 seconds
Started Jul 20 06:41:25 PM PDT 24
Finished Jul 20 06:41:57 PM PDT 24
Peak memory 249072 kb
Host smart-726f3f00-c2e6-4740-bf22-6a9a6a0879d5
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1899578886 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy_stress.1899578886
Directory /workspace/10.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/10.alert_handler_esc_alert_accum.2584788005
Short name T384
Test name
Test status
Simulation time 2709880066 ps
CPU time 96.81 seconds
Started Jul 20 06:41:14 PM PDT 24
Finished Jul 20 06:42:51 PM PDT 24
Peak memory 257244 kb
Host smart-f94b5bd7-2d68-48c4-90e3-4124dd161dd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25847
88005 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_alert_accum.2584788005
Directory /workspace/10.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/10.alert_handler_esc_intr_timeout.583666106
Short name T566
Test name
Test status
Simulation time 1063604092 ps
CPU time 34.68 seconds
Started Jul 20 06:41:24 PM PDT 24
Finished Jul 20 06:42:00 PM PDT 24
Peak memory 256372 kb
Host smart-322ecf84-7181-407d-8881-a10406275116
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58366
6106 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_intr_timeout.583666106
Directory /workspace/10.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_lpg.1470117894
Short name T671
Test name
Test status
Simulation time 167303861757 ps
CPU time 2280.2 seconds
Started Jul 20 06:41:12 PM PDT 24
Finished Jul 20 07:19:13 PM PDT 24
Peak memory 281784 kb
Host smart-72864672-eddf-48ac-926b-8d43a8342301
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470117894 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg.1470117894
Directory /workspace/10.alert_handler_lpg/latest

Test location /workspace/coverage/default/10.alert_handler_lpg_stub_clk.3597664314
Short name T413
Test name
Test status
Simulation time 27129482184 ps
CPU time 1485.43 seconds
Started Jul 20 06:41:13 PM PDT 24
Finished Jul 20 07:05:59 PM PDT 24
Peak memory 273260 kb
Host smart-0f0c76df-ab1c-4da1-a53b-23abfd770af0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597664314 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg_stub_clk.3597664314
Directory /workspace/10.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/10.alert_handler_ping_timeout.3551297352
Short name T611
Test name
Test status
Simulation time 45016586155 ps
CPU time 535.93 seconds
Started Jul 20 06:41:14 PM PDT 24
Finished Jul 20 06:50:11 PM PDT 24
Peak memory 249088 kb
Host smart-5ad26db3-ed07-40a7-9496-22714411887f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551297352 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_ping_timeout.3551297352
Directory /workspace/10.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_random_alerts.3706477764
Short name T424
Test name
Test status
Simulation time 3765296130 ps
CPU time 36.97 seconds
Started Jul 20 06:41:07 PM PDT 24
Finished Jul 20 06:41:45 PM PDT 24
Peak memory 257060 kb
Host smart-e8cc5bbc-1365-40dc-8949-86c0a9c5a0ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37064
77764 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_alerts.3706477764
Directory /workspace/10.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/10.alert_handler_random_classes.1998258737
Short name T18
Test name
Test status
Simulation time 2376148950 ps
CPU time 56.52 seconds
Started Jul 20 06:41:08 PM PDT 24
Finished Jul 20 06:42:06 PM PDT 24
Peak memory 248912 kb
Host smart-b4a91f7a-2201-4819-a858-73373890e522
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19982
58737 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_classes.1998258737
Directory /workspace/10.alert_handler_random_classes/latest

Test location /workspace/coverage/default/10.alert_handler_sig_int_fail.1281954809
Short name T267
Test name
Test status
Simulation time 625719304 ps
CPU time 44.77 seconds
Started Jul 20 06:41:25 PM PDT 24
Finished Jul 20 06:42:11 PM PDT 24
Peak memory 255852 kb
Host smart-71c1c72d-a0dc-4bda-af1b-36c67aebe8ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12819
54809 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_sig_int_fail.1281954809
Directory /workspace/10.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/10.alert_handler_smoke.3429402859
Short name T534
Test name
Test status
Simulation time 131893433 ps
CPU time 8.84 seconds
Started Jul 20 06:41:03 PM PDT 24
Finished Jul 20 06:41:13 PM PDT 24
Peak memory 251756 kb
Host smart-a34e891e-417e-437c-beca-ac21dcd3b276
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34294
02859 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_smoke.3429402859
Directory /workspace/10.alert_handler_smoke/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all.803199081
Short name T435
Test name
Test status
Simulation time 28242955022 ps
CPU time 1451.83 seconds
Started Jul 20 06:41:26 PM PDT 24
Finished Jul 20 07:05:39 PM PDT 24
Peak memory 289816 kb
Host smart-61a09023-f7ed-4a21-98b5-2d6824ce1c4a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803199081 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_han
dler_stress_all.803199081
Directory /workspace/10.alert_handler_stress_all/latest

Test location /workspace/coverage/default/11.alert_handler_entropy.3308771140
Short name T477
Test name
Test status
Simulation time 179016250486 ps
CPU time 2723.07 seconds
Started Jul 20 06:41:17 PM PDT 24
Finished Jul 20 07:26:41 PM PDT 24
Peak memory 289896 kb
Host smart-4ca31322-21ff-44d5-bdc8-ff59adfbeae8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3308771140 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy.3308771140
Directory /workspace/11.alert_handler_entropy/latest

Test location /workspace/coverage/default/11.alert_handler_entropy_stress.1149640677
Short name T444
Test name
Test status
Simulation time 530973284 ps
CPU time 8.59 seconds
Started Jul 20 06:41:25 PM PDT 24
Finished Jul 20 06:41:35 PM PDT 24
Peak memory 248980 kb
Host smart-da2650eb-0c12-4f5b-83f5-6c605e25a3a7
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1149640677 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy_stress.1149640677
Directory /workspace/11.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/11.alert_handler_esc_alert_accum.2808483608
Short name T210
Test name
Test status
Simulation time 6925778771 ps
CPU time 106.13 seconds
Started Jul 20 06:41:13 PM PDT 24
Finished Jul 20 06:43:00 PM PDT 24
Peak memory 255836 kb
Host smart-d353392b-edf4-47ad-86ec-9e9e4822e915
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28084
83608 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_alert_accum.2808483608
Directory /workspace/11.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/11.alert_handler_esc_intr_timeout.911513186
Short name T232
Test name
Test status
Simulation time 5010904282 ps
CPU time 39.9 seconds
Started Jul 20 06:41:24 PM PDT 24
Finished Jul 20 06:42:05 PM PDT 24
Peak memory 248736 kb
Host smart-2fc9caf8-8771-4a97-8618-41226cff0500
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91151
3186 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_intr_timeout.911513186
Directory /workspace/11.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_lpg_stub_clk.2789506397
Short name T485
Test name
Test status
Simulation time 19386994327 ps
CPU time 1051.59 seconds
Started Jul 20 06:41:22 PM PDT 24
Finished Jul 20 06:58:54 PM PDT 24
Peak memory 273448 kb
Host smart-4359ccf6-7116-46d0-ae40-d4571c84a08e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789506397 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg_stub_clk.2789506397
Directory /workspace/11.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/11.alert_handler_ping_timeout.1874220572
Short name T670
Test name
Test status
Simulation time 30391030471 ps
CPU time 596.22 seconds
Started Jul 20 06:41:27 PM PDT 24
Finished Jul 20 06:51:25 PM PDT 24
Peak memory 255828 kb
Host smart-974c7d25-d390-40f2-b7cc-a0f2d187e745
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874220572 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_ping_timeout.1874220572
Directory /workspace/11.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_random_alerts.2309858910
Short name T367
Test name
Test status
Simulation time 447217409 ps
CPU time 33.39 seconds
Started Jul 20 06:41:14 PM PDT 24
Finished Jul 20 06:41:48 PM PDT 24
Peak memory 256396 kb
Host smart-047892c1-d136-428b-9edd-e60d78083958
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23098
58910 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_alerts.2309858910
Directory /workspace/11.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/11.alert_handler_random_classes.1173289580
Short name T443
Test name
Test status
Simulation time 6898497541 ps
CPU time 60.8 seconds
Started Jul 20 06:41:21 PM PDT 24
Finished Jul 20 06:42:23 PM PDT 24
Peak memory 248720 kb
Host smart-a442f0ff-f2ec-497e-a880-f65b0e7caf72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11732
89580 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_classes.1173289580
Directory /workspace/11.alert_handler_random_classes/latest

Test location /workspace/coverage/default/11.alert_handler_sig_int_fail.143966245
Short name T563
Test name
Test status
Simulation time 744311689 ps
CPU time 19.33 seconds
Started Jul 20 06:41:13 PM PDT 24
Finished Jul 20 06:41:33 PM PDT 24
Peak memory 256708 kb
Host smart-91873098-6bd2-46ee-92e1-c45ad0273c0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14396
6245 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_sig_int_fail.143966245
Directory /workspace/11.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/11.alert_handler_smoke.1824768866
Short name T585
Test name
Test status
Simulation time 69369205 ps
CPU time 8.78 seconds
Started Jul 20 06:41:22 PM PDT 24
Finished Jul 20 06:41:32 PM PDT 24
Peak memory 254004 kb
Host smart-cc51258e-424d-47a3-97d1-817547cace4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18247
68866 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_smoke.1824768866
Directory /workspace/11.alert_handler_smoke/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all.3751532442
Short name T621
Test name
Test status
Simulation time 34490549637 ps
CPU time 175.83 seconds
Started Jul 20 06:41:25 PM PDT 24
Finished Jul 20 06:44:22 PM PDT 24
Peak memory 257304 kb
Host smart-a1993909-1ac6-43ea-a73f-2a9f174f7e1b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751532442 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_ha
ndler_stress_all.3751532442
Directory /workspace/11.alert_handler_stress_all/latest

Test location /workspace/coverage/default/12.alert_handler_alert_accum_saturation.1483886160
Short name T191
Test name
Test status
Simulation time 46639156 ps
CPU time 4.02 seconds
Started Jul 20 06:41:22 PM PDT 24
Finished Jul 20 06:41:28 PM PDT 24
Peak memory 249216 kb
Host smart-b6e4e343-7762-45e6-8982-1b1d263d534a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1483886160 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_alert_accum_saturation.1483886160
Directory /workspace/12.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/12.alert_handler_entropy.900778703
Short name T688
Test name
Test status
Simulation time 9617883376 ps
CPU time 863.66 seconds
Started Jul 20 06:41:22 PM PDT 24
Finished Jul 20 06:55:47 PM PDT 24
Peak memory 273544 kb
Host smart-1ec60cbf-bc48-42ce-b25c-a98b54989894
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900778703 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy.900778703
Directory /workspace/12.alert_handler_entropy/latest

Test location /workspace/coverage/default/12.alert_handler_entropy_stress.3537207195
Short name T527
Test name
Test status
Simulation time 2072442154 ps
CPU time 24.42 seconds
Started Jul 20 06:41:27 PM PDT 24
Finished Jul 20 06:41:52 PM PDT 24
Peak memory 248976 kb
Host smart-17df358c-7125-47a1-ae62-3b8616ec0962
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3537207195 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy_stress.3537207195
Directory /workspace/12.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/12.alert_handler_esc_alert_accum.3297417629
Short name T1
Test name
Test status
Simulation time 5934230101 ps
CPU time 326.62 seconds
Started Jul 20 06:41:24 PM PDT 24
Finished Jul 20 06:46:52 PM PDT 24
Peak memory 257260 kb
Host smart-3e8d15f2-3cee-4bde-986d-1cd47469cb3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32974
17629 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_alert_accum.3297417629
Directory /workspace/12.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/12.alert_handler_esc_intr_timeout.250775579
Short name T411
Test name
Test status
Simulation time 1959548693 ps
CPU time 39.47 seconds
Started Jul 20 06:41:30 PM PDT 24
Finished Jul 20 06:42:11 PM PDT 24
Peak memory 248924 kb
Host smart-fe6d3a23-3ad4-4255-83b4-a039aa4e4986
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25077
5579 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_intr_timeout.250775579
Directory /workspace/12.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_lpg.576022277
Short name T319
Test name
Test status
Simulation time 28474651130 ps
CPU time 1858.92 seconds
Started Jul 20 06:41:28 PM PDT 24
Finished Jul 20 07:12:28 PM PDT 24
Peak memory 272988 kb
Host smart-18bb7000-3e28-408c-be6a-088ecf0bcd02
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576022277 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg.576022277
Directory /workspace/12.alert_handler_lpg/latest

Test location /workspace/coverage/default/12.alert_handler_lpg_stub_clk.1692627119
Short name T471
Test name
Test status
Simulation time 148646320499 ps
CPU time 2009.07 seconds
Started Jul 20 06:41:27 PM PDT 24
Finished Jul 20 07:14:57 PM PDT 24
Peak memory 273600 kb
Host smart-3ecfb728-f117-4ce2-b18c-e43a0019b60c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1692627119 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg_stub_clk.1692627119
Directory /workspace/12.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/12.alert_handler_ping_timeout.1000140347
Short name T560
Test name
Test status
Simulation time 25009223495 ps
CPU time 259.74 seconds
Started Jul 20 06:41:27 PM PDT 24
Finished Jul 20 06:45:48 PM PDT 24
Peak memory 249116 kb
Host smart-e390f46d-0160-4ad4-9f86-b09bc78c33c5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000140347 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_ping_timeout.1000140347
Directory /workspace/12.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_random_alerts.146170394
Short name T291
Test name
Test status
Simulation time 660069683 ps
CPU time 43.41 seconds
Started Jul 20 06:41:23 PM PDT 24
Finished Jul 20 06:42:07 PM PDT 24
Peak memory 256608 kb
Host smart-a57e7fe0-99d1-4ad7-9bd1-6fc4b440f39e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14617
0394 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_alerts.146170394
Directory /workspace/12.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/12.alert_handler_random_classes.3068756788
Short name T575
Test name
Test status
Simulation time 3262677192 ps
CPU time 58.02 seconds
Started Jul 20 06:41:25 PM PDT 24
Finished Jul 20 06:42:24 PM PDT 24
Peak memory 249556 kb
Host smart-53f83d7a-9bca-4c11-bcf2-2c4951a6a599
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30687
56788 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_classes.3068756788
Directory /workspace/12.alert_handler_random_classes/latest

Test location /workspace/coverage/default/12.alert_handler_sig_int_fail.3773389199
Short name T407
Test name
Test status
Simulation time 127268429 ps
CPU time 6.45 seconds
Started Jul 20 06:41:27 PM PDT 24
Finished Jul 20 06:41:35 PM PDT 24
Peak memory 240800 kb
Host smart-b114cc21-6707-4ca0-8b0c-0c4041be6bfa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37733
89199 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_sig_int_fail.3773389199
Directory /workspace/12.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/12.alert_handler_smoke.2475576038
Short name T33
Test name
Test status
Simulation time 20099492 ps
CPU time 2.74 seconds
Started Jul 20 06:42:42 PM PDT 24
Finished Jul 20 06:42:46 PM PDT 24
Peak memory 250428 kb
Host smart-33bf23a8-d519-4413-9e04-a1a7aaac2ce5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24755
76038 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_smoke.2475576038
Directory /workspace/12.alert_handler_smoke/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all.3270776978
Short name T273
Test name
Test status
Simulation time 1628321350 ps
CPU time 149.39 seconds
Started Jul 20 06:41:25 PM PDT 24
Finished Jul 20 06:43:56 PM PDT 24
Peak memory 256224 kb
Host smart-e2071f07-88c8-456c-b786-f746b2f237a0
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270776978 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_ha
ndler_stress_all.3270776978
Directory /workspace/12.alert_handler_stress_all/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all_with_rand_reset.2113992500
Short name T277
Test name
Test status
Simulation time 40323921595 ps
CPU time 3060.09 seconds
Started Jul 20 06:41:27 PM PDT 24
Finished Jul 20 07:32:28 PM PDT 24
Peak memory 306284 kb
Host smart-4211747e-fa28-4f2a-be43-17fc43d07823
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113992500 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.alert_handler_stress_all_with_rand_reset.2113992500
Directory /workspace/12.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.alert_handler_alert_accum_saturation.2327369348
Short name T195
Test name
Test status
Simulation time 18029970 ps
CPU time 2.77 seconds
Started Jul 20 06:41:28 PM PDT 24
Finished Jul 20 06:41:32 PM PDT 24
Peak memory 249272 kb
Host smart-1e2c9ca7-cd6d-4f69-9d4b-2d5456bd10ac
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2327369348 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_alert_accum_saturation.2327369348
Directory /workspace/13.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/13.alert_handler_entropy.2520248293
Short name T42
Test name
Test status
Simulation time 19797538161 ps
CPU time 1693.12 seconds
Started Jul 20 06:41:25 PM PDT 24
Finished Jul 20 07:09:40 PM PDT 24
Peak memory 289216 kb
Host smart-5a5ca194-8a66-42b9-96fe-16bb508e9e60
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520248293 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy.2520248293
Directory /workspace/13.alert_handler_entropy/latest

Test location /workspace/coverage/default/13.alert_handler_entropy_stress.2984926522
Short name T499
Test name
Test status
Simulation time 446466791 ps
CPU time 14.5 seconds
Started Jul 20 06:41:25 PM PDT 24
Finished Jul 20 06:41:41 PM PDT 24
Peak memory 248924 kb
Host smart-8dd006a7-fcdb-4e5e-b44d-c1954d64d2b1
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2984926522 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy_stress.2984926522
Directory /workspace/13.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/13.alert_handler_esc_alert_accum.1035893423
Short name T433
Test name
Test status
Simulation time 15969667018 ps
CPU time 222.25 seconds
Started Jul 20 06:41:22 PM PDT 24
Finished Jul 20 06:45:06 PM PDT 24
Peak memory 251100 kb
Host smart-dd94ccb0-5160-493d-a3a6-a2f7f3fb4d39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10358
93423 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_alert_accum.1035893423
Directory /workspace/13.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/13.alert_handler_esc_intr_timeout.2161664933
Short name T502
Test name
Test status
Simulation time 908723511 ps
CPU time 62.64 seconds
Started Jul 20 06:41:23 PM PDT 24
Finished Jul 20 06:42:27 PM PDT 24
Peak memory 248932 kb
Host smart-7c2a0edb-5db5-42c7-87af-315f56c30f19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21616
64933 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_intr_timeout.2161664933
Directory /workspace/13.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_lpg.27995231
Short name T531
Test name
Test status
Simulation time 30664112122 ps
CPU time 1275 seconds
Started Jul 20 06:41:27 PM PDT 24
Finished Jul 20 07:02:44 PM PDT 24
Peak memory 286324 kb
Host smart-51370f56-5af4-4887-bb95-b00c666fca87
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27995231 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg.27995231
Directory /workspace/13.alert_handler_lpg/latest

Test location /workspace/coverage/default/13.alert_handler_lpg_stub_clk.596934534
Short name T408
Test name
Test status
Simulation time 89472484258 ps
CPU time 1692.25 seconds
Started Jul 20 06:41:28 PM PDT 24
Finished Jul 20 07:09:42 PM PDT 24
Peak memory 273020 kb
Host smart-8620832f-4bc4-4cc0-a6fa-0c0faeff2f77
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=596934534 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg_stub_clk.596934534
Directory /workspace/13.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/13.alert_handler_ping_timeout.1125598115
Short name T314
Test name
Test status
Simulation time 64612019539 ps
CPU time 326.02 seconds
Started Jul 20 06:41:27 PM PDT 24
Finished Jul 20 06:46:54 PM PDT 24
Peak memory 257248 kb
Host smart-2a1293fb-fc1e-45eb-86fa-aff256cca5e0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1125598115 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_ping_timeout.1125598115
Directory /workspace/13.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_random_alerts.1107471717
Short name T372
Test name
Test status
Simulation time 94583688 ps
CPU time 12.44 seconds
Started Jul 20 06:41:24 PM PDT 24
Finished Jul 20 06:41:38 PM PDT 24
Peak memory 249024 kb
Host smart-18fdc595-4008-4f53-9477-b8389a1301fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11074
71717 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_alerts.1107471717
Directory /workspace/13.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/13.alert_handler_random_classes.561865067
Short name T616
Test name
Test status
Simulation time 779578741 ps
CPU time 22.61 seconds
Started Jul 20 06:41:26 PM PDT 24
Finished Jul 20 06:41:50 PM PDT 24
Peak memory 248516 kb
Host smart-d5276cff-4d92-4cb6-a41a-7a8ad56775b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56186
5067 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_classes.561865067
Directory /workspace/13.alert_handler_random_classes/latest

Test location /workspace/coverage/default/13.alert_handler_sig_int_fail.2588457559
Short name T445
Test name
Test status
Simulation time 522994859 ps
CPU time 38.5 seconds
Started Jul 20 06:41:24 PM PDT 24
Finished Jul 20 06:42:05 PM PDT 24
Peak memory 257152 kb
Host smart-9c2b3924-e517-4853-af1a-998c18d19f47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25884
57559 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_sig_int_fail.2588457559
Directory /workspace/13.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/13.alert_handler_smoke.1122167014
Short name T501
Test name
Test status
Simulation time 4782937644 ps
CPU time 64.49 seconds
Started Jul 20 06:41:23 PM PDT 24
Finished Jul 20 06:42:29 PM PDT 24
Peak memory 257220 kb
Host smart-5d766c5f-ba30-4169-958e-df0602df542c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11221
67014 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_smoke.1122167014
Directory /workspace/13.alert_handler_smoke/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all_with_rand_reset.780428247
Short name T224
Test name
Test status
Simulation time 181025225725 ps
CPU time 4744.67 seconds
Started Jul 20 06:41:27 PM PDT 24
Finished Jul 20 08:00:34 PM PDT 24
Peak memory 317120 kb
Host smart-04ce4671-3908-40a7-b4e4-a5511215b1d7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780428247 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 13.alert_handler_stress_all_with_rand_reset.780428247
Directory /workspace/13.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.alert_handler_alert_accum_saturation.1481885911
Short name T200
Test name
Test status
Simulation time 126591320 ps
CPU time 3.55 seconds
Started Jul 20 06:41:31 PM PDT 24
Finished Jul 20 06:41:35 PM PDT 24
Peak memory 249236 kb
Host smart-6b32176e-de67-493a-ad9a-be89a87eabe7
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1481885911 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_alert_accum_saturation.1481885911
Directory /workspace/14.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/14.alert_handler_entropy_stress.1628887163
Short name T579
Test name
Test status
Simulation time 914222704 ps
CPU time 13.19 seconds
Started Jul 20 06:41:37 PM PDT 24
Finished Jul 20 06:41:52 PM PDT 24
Peak memory 248984 kb
Host smart-a8854174-76bb-4523-9097-7a4e5ff96045
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1628887163 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy_stress.1628887163
Directory /workspace/14.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/14.alert_handler_esc_alert_accum.1626515023
Short name T589
Test name
Test status
Simulation time 8458133170 ps
CPU time 275.29 seconds
Started Jul 20 06:41:28 PM PDT 24
Finished Jul 20 06:46:04 PM PDT 24
Peak memory 257244 kb
Host smart-dd8f567a-5429-4b1e-9b45-84c2d6d67fce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16265
15023 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_alert_accum.1626515023
Directory /workspace/14.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/14.alert_handler_esc_intr_timeout.1630959911
Short name T78
Test name
Test status
Simulation time 1063816377 ps
CPU time 44.55 seconds
Started Jul 20 06:41:24 PM PDT 24
Finished Jul 20 06:42:11 PM PDT 24
Peak memory 249008 kb
Host smart-409bb519-baa9-4003-a83a-780a7c4ad694
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16309
59911 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_intr_timeout.1630959911
Directory /workspace/14.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_lpg_stub_clk.1269839527
Short name T412
Test name
Test status
Simulation time 59064926386 ps
CPU time 1816.2 seconds
Started Jul 20 06:41:30 PM PDT 24
Finished Jul 20 07:11:47 PM PDT 24
Peak memory 281832 kb
Host smart-37f45c6d-62bb-4f07-be41-03fe1fdd867d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269839527 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg_stub_clk.1269839527
Directory /workspace/14.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/14.alert_handler_ping_timeout.36565812
Short name T335
Test name
Test status
Simulation time 3852681085 ps
CPU time 155.48 seconds
Started Jul 20 06:41:32 PM PDT 24
Finished Jul 20 06:44:08 PM PDT 24
Peak memory 248844 kb
Host smart-7e1bcdf9-7e02-4448-82e7-c54bb2f91277
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36565812 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_ping_timeout.36565812
Directory /workspace/14.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_random_alerts.3418507104
Short name T463
Test name
Test status
Simulation time 236454140 ps
CPU time 27.93 seconds
Started Jul 20 06:41:26 PM PDT 24
Finished Jul 20 06:41:56 PM PDT 24
Peak memory 256412 kb
Host smart-0680fe02-66f3-4cbd-b03b-5da1fd5d38d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34185
07104 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_alerts.3418507104
Directory /workspace/14.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/14.alert_handler_random_classes.771318125
Short name T81
Test name
Test status
Simulation time 849519554 ps
CPU time 31.82 seconds
Started Jul 20 06:41:25 PM PDT 24
Finished Jul 20 06:41:58 PM PDT 24
Peak memory 256408 kb
Host smart-1a5e3e1c-eea6-4fcc-ae8f-4786170e0af3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77131
8125 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_classes.771318125
Directory /workspace/14.alert_handler_random_classes/latest

Test location /workspace/coverage/default/14.alert_handler_sig_int_fail.4261689864
Short name T453
Test name
Test status
Simulation time 657018805 ps
CPU time 17.86 seconds
Started Jul 20 06:41:34 PM PDT 24
Finished Jul 20 06:41:52 PM PDT 24
Peak memory 256168 kb
Host smart-0df94ee6-76a1-43e2-90f9-6eb9af826c49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42616
89864 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_sig_int_fail.4261689864
Directory /workspace/14.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/14.alert_handler_smoke.1356887958
Short name T59
Test name
Test status
Simulation time 172768228 ps
CPU time 16.97 seconds
Started Jul 20 06:41:22 PM PDT 24
Finished Jul 20 06:41:39 PM PDT 24
Peak memory 256688 kb
Host smart-2e83ed8c-fbca-45c6-8b83-3f7f25a951d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13568
87958 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_smoke.1356887958
Directory /workspace/14.alert_handler_smoke/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all.3713328997
Short name T672
Test name
Test status
Simulation time 16485867066 ps
CPU time 1165.04 seconds
Started Jul 20 06:42:43 PM PDT 24
Finished Jul 20 07:02:09 PM PDT 24
Peak memory 289684 kb
Host smart-c03c2724-0080-4304-b6af-53583dcd419c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713328997 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_ha
ndler_stress_all.3713328997
Directory /workspace/14.alert_handler_stress_all/latest

Test location /workspace/coverage/default/15.alert_handler_alert_accum_saturation.2319633465
Short name T172
Test name
Test status
Simulation time 91033870 ps
CPU time 4.57 seconds
Started Jul 20 06:41:34 PM PDT 24
Finished Jul 20 06:41:40 PM PDT 24
Peak memory 249208 kb
Host smart-afec6fd6-4634-4da8-a90e-6f75527079e9
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2319633465 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_alert_accum_saturation.2319633465
Directory /workspace/15.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/15.alert_handler_entropy.3312159789
Short name T466
Test name
Test status
Simulation time 18443219822 ps
CPU time 851.56 seconds
Started Jul 20 06:42:42 PM PDT 24
Finished Jul 20 06:56:55 PM PDT 24
Peak memory 288632 kb
Host smart-f2285b8b-e3b9-4a81-a24e-682904fa8299
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312159789 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy.3312159789
Directory /workspace/15.alert_handler_entropy/latest

Test location /workspace/coverage/default/15.alert_handler_entropy_stress.2136015201
Short name T206
Test name
Test status
Simulation time 4653124834 ps
CPU time 23.48 seconds
Started Jul 20 06:41:32 PM PDT 24
Finished Jul 20 06:41:57 PM PDT 24
Peak memory 249120 kb
Host smart-d720c17f-cbf8-4be8-90d4-182b23833565
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2136015201 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy_stress.2136015201
Directory /workspace/15.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/15.alert_handler_esc_alert_accum.1811408761
Short name T366
Test name
Test status
Simulation time 10362970492 ps
CPU time 331.7 seconds
Started Jul 20 06:41:38 PM PDT 24
Finished Jul 20 06:47:11 PM PDT 24
Peak memory 256592 kb
Host smart-fc6dfb50-e8f4-48fc-afb3-7f159401c8d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18114
08761 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_alert_accum.1811408761
Directory /workspace/15.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/15.alert_handler_esc_intr_timeout.1786039254
Short name T674
Test name
Test status
Simulation time 43134101 ps
CPU time 4.04 seconds
Started Jul 20 06:41:30 PM PDT 24
Finished Jul 20 06:41:35 PM PDT 24
Peak memory 248992 kb
Host smart-2629ae87-1a6b-4b38-945b-5e40f3f40f3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17860
39254 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_intr_timeout.1786039254
Directory /workspace/15.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_lpg.595032604
Short name T699
Test name
Test status
Simulation time 121519147367 ps
CPU time 3412.58 seconds
Started Jul 20 06:41:37 PM PDT 24
Finished Jul 20 07:38:31 PM PDT 24
Peak memory 289348 kb
Host smart-e2ecd723-9bc2-4250-adcb-500a408acc1f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=595032604 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg.595032604
Directory /workspace/15.alert_handler_lpg/latest

Test location /workspace/coverage/default/15.alert_handler_lpg_stub_clk.3709022033
Short name T482
Test name
Test status
Simulation time 16796456298 ps
CPU time 1096.72 seconds
Started Jul 20 06:41:40 PM PDT 24
Finished Jul 20 06:59:58 PM PDT 24
Peak memory 273504 kb
Host smart-cb4b8c59-bdc6-4692-9b24-328e3cc78480
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709022033 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg_stub_clk.3709022033
Directory /workspace/15.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/15.alert_handler_ping_timeout.1763424010
Short name T334
Test name
Test status
Simulation time 5289914554 ps
CPU time 156.57 seconds
Started Jul 20 06:41:34 PM PDT 24
Finished Jul 20 06:44:11 PM PDT 24
Peak memory 249016 kb
Host smart-3f147169-f366-4bde-946d-e3189ee64a50
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763424010 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_ping_timeout.1763424010
Directory /workspace/15.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_random_alerts.1201132399
Short name T515
Test name
Test status
Simulation time 1645485384 ps
CPU time 29.98 seconds
Started Jul 20 06:41:31 PM PDT 24
Finished Jul 20 06:42:02 PM PDT 24
Peak memory 256464 kb
Host smart-d77f2b7a-b098-437b-a640-c3aa1bb56277
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12011
32399 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_alerts.1201132399
Directory /workspace/15.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/15.alert_handler_random_classes.184572283
Short name T397
Test name
Test status
Simulation time 1240352177 ps
CPU time 12.88 seconds
Started Jul 20 06:41:31 PM PDT 24
Finished Jul 20 06:41:45 PM PDT 24
Peak memory 253832 kb
Host smart-0b9a202b-45e4-4a0d-bae5-ddaea1f7f265
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18457
2283 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_classes.184572283
Directory /workspace/15.alert_handler_random_classes/latest

Test location /workspace/coverage/default/15.alert_handler_sig_int_fail.1431244619
Short name T60
Test name
Test status
Simulation time 958248031 ps
CPU time 35.08 seconds
Started Jul 20 06:41:29 PM PDT 24
Finished Jul 20 06:42:05 PM PDT 24
Peak memory 248892 kb
Host smart-f76b6a31-834e-4b7e-89f2-18f3d37ac062
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14312
44619 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_sig_int_fail.1431244619
Directory /workspace/15.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/15.alert_handler_smoke.1928880800
Short name T409
Test name
Test status
Simulation time 182847120 ps
CPU time 5.75 seconds
Started Jul 20 06:41:32 PM PDT 24
Finished Jul 20 06:41:39 PM PDT 24
Peak memory 251660 kb
Host smart-9a73700b-814e-4a3c-99d3-00ac57d49835
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19288
80800 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_smoke.1928880800
Directory /workspace/15.alert_handler_smoke/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all.3564797068
Short name T242
Test name
Test status
Simulation time 5625777552 ps
CPU time 529.8 seconds
Started Jul 20 06:41:27 PM PDT 24
Finished Jul 20 06:50:18 PM PDT 24
Peak memory 273608 kb
Host smart-ba177ea4-16aa-4028-83dd-3aa6996a115d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564797068 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_ha
ndler_stress_all.3564797068
Directory /workspace/15.alert_handler_stress_all/latest

Test location /workspace/coverage/default/16.alert_handler_alert_accum_saturation.2478102914
Short name T199
Test name
Test status
Simulation time 48238961 ps
CPU time 2.88 seconds
Started Jul 20 06:41:34 PM PDT 24
Finished Jul 20 06:41:37 PM PDT 24
Peak memory 249208 kb
Host smart-940a6b0f-d153-4d41-a69e-0879dc97f27c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2478102914 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_alert_accum_saturation.2478102914
Directory /workspace/16.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/16.alert_handler_entropy.4196760765
Short name T558
Test name
Test status
Simulation time 232319498390 ps
CPU time 3431.78 seconds
Started Jul 20 06:41:29 PM PDT 24
Finished Jul 20 07:38:42 PM PDT 24
Peak memory 289688 kb
Host smart-dfedcf96-223e-4a74-8b67-7aa46913dff7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196760765 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy.4196760765
Directory /workspace/16.alert_handler_entropy/latest

Test location /workspace/coverage/default/16.alert_handler_entropy_stress.1576003120
Short name T689
Test name
Test status
Simulation time 124068507 ps
CPU time 8.79 seconds
Started Jul 20 06:41:33 PM PDT 24
Finished Jul 20 06:41:43 PM PDT 24
Peak memory 249000 kb
Host smart-be6ca1c4-93f8-4700-a536-ad44fda69183
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1576003120 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy_stress.1576003120
Directory /workspace/16.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/16.alert_handler_esc_alert_accum.614062308
Short name T656
Test name
Test status
Simulation time 6397587005 ps
CPU time 179.22 seconds
Started Jul 20 06:41:29 PM PDT 24
Finished Jul 20 06:44:29 PM PDT 24
Peak memory 257308 kb
Host smart-8008809b-6a4d-4cbe-a3a1-dcc7b08e4e2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61406
2308 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_alert_accum.614062308
Directory /workspace/16.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/16.alert_handler_esc_intr_timeout.1289742070
Short name T380
Test name
Test status
Simulation time 316034296 ps
CPU time 11.59 seconds
Started Jul 20 06:41:40 PM PDT 24
Finished Jul 20 06:41:52 PM PDT 24
Peak memory 248948 kb
Host smart-b0f24dba-feb5-4a81-9a02-676fa91285d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12897
42070 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_intr_timeout.1289742070
Directory /workspace/16.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_lpg.2175283387
Short name T697
Test name
Test status
Simulation time 25463547900 ps
CPU time 1415.25 seconds
Started Jul 20 06:41:29 PM PDT 24
Finished Jul 20 07:05:05 PM PDT 24
Peak memory 286580 kb
Host smart-5b378cc8-8e03-43f9-acac-2b0d39bc5085
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175283387 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg.2175283387
Directory /workspace/16.alert_handler_lpg/latest

Test location /workspace/coverage/default/16.alert_handler_lpg_stub_clk.3816973408
Short name T112
Test name
Test status
Simulation time 99426419748 ps
CPU time 2539.62 seconds
Started Jul 20 06:41:28 PM PDT 24
Finished Jul 20 07:23:49 PM PDT 24
Peak memory 289848 kb
Host smart-9b8130c2-0628-435d-a46b-bf17fb5aed17
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3816973408 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg_stub_clk.3816973408
Directory /workspace/16.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/16.alert_handler_ping_timeout.3985611792
Short name T308
Test name
Test status
Simulation time 26214681613 ps
CPU time 158.87 seconds
Started Jul 20 06:41:30 PM PDT 24
Finished Jul 20 06:44:09 PM PDT 24
Peak memory 249080 kb
Host smart-06137ed0-bbfc-4bf9-8483-520a5bb375c0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985611792 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_ping_timeout.3985611792
Directory /workspace/16.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_random_alerts.2618706708
Short name T381
Test name
Test status
Simulation time 319359740 ps
CPU time 19.76 seconds
Started Jul 20 06:41:34 PM PDT 24
Finished Jul 20 06:41:54 PM PDT 24
Peak memory 248956 kb
Host smart-3ed7e76c-6846-4728-a1ae-45a99d19ad38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26187
06708 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_alerts.2618706708
Directory /workspace/16.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/16.alert_handler_random_classes.674036314
Short name T382
Test name
Test status
Simulation time 869782636 ps
CPU time 59.26 seconds
Started Jul 20 06:41:40 PM PDT 24
Finished Jul 20 06:42:40 PM PDT 24
Peak memory 256620 kb
Host smart-bae8f83b-1b3f-4e4b-8d34-d90c24987602
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67403
6314 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_classes.674036314
Directory /workspace/16.alert_handler_random_classes/latest

Test location /workspace/coverage/default/16.alert_handler_sig_int_fail.2128066593
Short name T586
Test name
Test status
Simulation time 624070367 ps
CPU time 45.42 seconds
Started Jul 20 06:41:32 PM PDT 24
Finished Jul 20 06:42:19 PM PDT 24
Peak memory 248888 kb
Host smart-eabfaa6f-96b1-4880-b622-22883cea4a50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21280
66593 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_sig_int_fail.2128066593
Directory /workspace/16.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/16.alert_handler_smoke.1578737117
Short name T373
Test name
Test status
Simulation time 1104104948 ps
CPU time 22.18 seconds
Started Jul 20 06:41:31 PM PDT 24
Finished Jul 20 06:41:54 PM PDT 24
Peak memory 256964 kb
Host smart-12dacc69-59a7-4a70-8e1c-94477eb6b942
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15787
37117 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_smoke.1578737117
Directory /workspace/16.alert_handler_smoke/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all.1845245309
Short name T557
Test name
Test status
Simulation time 18416038888 ps
CPU time 850.08 seconds
Started Jul 20 06:41:35 PM PDT 24
Finished Jul 20 06:55:46 PM PDT 24
Peak memory 289956 kb
Host smart-f6cdc655-dde3-4f52-aa4e-d202016a9e41
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845245309 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_ha
ndler_stress_all.1845245309
Directory /workspace/16.alert_handler_stress_all/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all_with_rand_reset.2514003478
Short name T690
Test name
Test status
Simulation time 302229710040 ps
CPU time 5662.83 seconds
Started Jul 20 06:41:35 PM PDT 24
Finished Jul 20 08:16:00 PM PDT 24
Peak memory 333232 kb
Host smart-32b780c9-c829-4dcf-b095-d014a94ae81e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514003478 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 16.alert_handler_stress_all_with_rand_reset.2514003478
Directory /workspace/16.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.alert_handler_alert_accum_saturation.2999928695
Short name T201
Test name
Test status
Simulation time 55730262 ps
CPU time 4.47 seconds
Started Jul 20 06:41:32 PM PDT 24
Finished Jul 20 06:41:37 PM PDT 24
Peak memory 249192 kb
Host smart-0ad57e6c-b3db-4316-96ba-50f4b2710bed
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2999928695 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_alert_accum_saturation.2999928695
Directory /workspace/17.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/17.alert_handler_entropy.577206042
Short name T103
Test name
Test status
Simulation time 87844574448 ps
CPU time 1058.65 seconds
Started Jul 20 06:41:40 PM PDT 24
Finished Jul 20 06:59:19 PM PDT 24
Peak memory 273072 kb
Host smart-2a4d374b-3440-448c-97fa-4c3ee6d18244
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577206042 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy.577206042
Directory /workspace/17.alert_handler_entropy/latest

Test location /workspace/coverage/default/17.alert_handler_entropy_stress.1006851645
Short name T610
Test name
Test status
Simulation time 2095359667 ps
CPU time 24.14 seconds
Started Jul 20 06:41:28 PM PDT 24
Finished Jul 20 06:41:54 PM PDT 24
Peak memory 248996 kb
Host smart-3ed4d9c7-a539-4dcd-a213-08344e077479
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1006851645 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy_stress.1006851645
Directory /workspace/17.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/17.alert_handler_esc_alert_accum.2760302682
Short name T500
Test name
Test status
Simulation time 656379767 ps
CPU time 47.79 seconds
Started Jul 20 06:41:29 PM PDT 24
Finished Jul 20 06:42:18 PM PDT 24
Peak memory 256468 kb
Host smart-7e735272-d7e1-41ee-807f-259cfc951b85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27603
02682 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_alert_accum.2760302682
Directory /workspace/17.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/17.alert_handler_esc_intr_timeout.1699346296
Short name T451
Test name
Test status
Simulation time 255905675 ps
CPU time 15.43 seconds
Started Jul 20 06:41:34 PM PDT 24
Finished Jul 20 06:41:51 PM PDT 24
Peak memory 248524 kb
Host smart-05cb8007-b803-4f95-9e76-ddc8b9ca1a42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16993
46296 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_intr_timeout.1699346296
Directory /workspace/17.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_lpg.3152216665
Short name T510
Test name
Test status
Simulation time 77328904912 ps
CPU time 1243.74 seconds
Started Jul 20 06:41:30 PM PDT 24
Finished Jul 20 07:02:15 PM PDT 24
Peak memory 273620 kb
Host smart-35801a32-62c8-4197-8bce-6b21276fee9b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152216665 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg.3152216665
Directory /workspace/17.alert_handler_lpg/latest

Test location /workspace/coverage/default/17.alert_handler_ping_timeout.3011765283
Short name T625
Test name
Test status
Simulation time 50194767008 ps
CPU time 548.45 seconds
Started Jul 20 06:41:32 PM PDT 24
Finished Jul 20 06:50:42 PM PDT 24
Peak memory 249076 kb
Host smart-2515117b-d339-4d16-baad-96e0dcd5546f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011765283 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_ping_timeout.3011765283
Directory /workspace/17.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_random_alerts.1806458946
Short name T480
Test name
Test status
Simulation time 1403926881 ps
CPU time 38.08 seconds
Started Jul 20 06:41:33 PM PDT 24
Finished Jul 20 06:42:12 PM PDT 24
Peak memory 256408 kb
Host smart-c1b72a69-5429-4471-af3e-9df977b8850c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18064
58946 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_alerts.1806458946
Directory /workspace/17.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/17.alert_handler_random_classes.247287062
Short name T594
Test name
Test status
Simulation time 291849088 ps
CPU time 15.34 seconds
Started Jul 20 06:41:35 PM PDT 24
Finished Jul 20 06:41:51 PM PDT 24
Peak memory 256240 kb
Host smart-24598af4-2782-4e0a-a75c-22ec21cddc40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24728
7062 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_classes.247287062
Directory /workspace/17.alert_handler_random_classes/latest

Test location /workspace/coverage/default/17.alert_handler_sig_int_fail.2665249016
Short name T77
Test name
Test status
Simulation time 2082357669 ps
CPU time 58.39 seconds
Started Jul 20 06:41:37 PM PDT 24
Finished Jul 20 06:42:37 PM PDT 24
Peak memory 248700 kb
Host smart-0037531b-22d1-4cf2-a76f-55a9c6533474
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26652
49016 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_sig_int_fail.2665249016
Directory /workspace/17.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/17.alert_handler_smoke.2549173258
Short name T421
Test name
Test status
Simulation time 783746956 ps
CPU time 30.19 seconds
Started Jul 20 06:41:32 PM PDT 24
Finished Jul 20 06:42:03 PM PDT 24
Peak memory 256888 kb
Host smart-3a17c641-d626-400b-9afd-813f73a338c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25491
73258 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_smoke.2549173258
Directory /workspace/17.alert_handler_smoke/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all.1302865498
Short name T109
Test name
Test status
Simulation time 41145080956 ps
CPU time 2546.52 seconds
Started Jul 20 06:41:37 PM PDT 24
Finished Jul 20 07:24:04 PM PDT 24
Peak memory 285668 kb
Host smart-54cd89dc-c79e-412e-9594-0e4bce0df68f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302865498 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_ha
ndler_stress_all.1302865498
Directory /workspace/17.alert_handler_stress_all/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all_with_rand_reset.2008195374
Short name T549
Test name
Test status
Simulation time 18778321293 ps
CPU time 1274.42 seconds
Started Jul 20 06:41:29 PM PDT 24
Finished Jul 20 07:02:44 PM PDT 24
Peak memory 273456 kb
Host smart-d947b540-b56f-4f43-9fef-d4a976718bf2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008195374 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 17.alert_handler_stress_all_with_rand_reset.2008195374
Directory /workspace/17.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.alert_handler_alert_accum_saturation.3990761886
Short name T202
Test name
Test status
Simulation time 66384344 ps
CPU time 3.72 seconds
Started Jul 20 06:41:40 PM PDT 24
Finished Jul 20 06:41:44 PM PDT 24
Peak memory 249240 kb
Host smart-d2f4272d-fcc4-408b-a65d-2cef194af06c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3990761886 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_alert_accum_saturation.3990761886
Directory /workspace/18.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/18.alert_handler_entropy_stress.314344598
Short name T544
Test name
Test status
Simulation time 240457406 ps
CPU time 12.67 seconds
Started Jul 20 06:41:28 PM PDT 24
Finished Jul 20 06:41:42 PM PDT 24
Peak memory 249000 kb
Host smart-bd7e61fd-2772-4a19-966e-912baae4c0ab
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=314344598 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy_stress.314344598
Directory /workspace/18.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/18.alert_handler_esc_alert_accum.2461228018
Short name T427
Test name
Test status
Simulation time 565554555 ps
CPU time 54.26 seconds
Started Jul 20 06:41:32 PM PDT 24
Finished Jul 20 06:42:28 PM PDT 24
Peak memory 256736 kb
Host smart-189cb21c-ef37-4e8d-8f9e-71aebd990338
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24612
28018 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_alert_accum.2461228018
Directory /workspace/18.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/18.alert_handler_esc_intr_timeout.4272887518
Short name T389
Test name
Test status
Simulation time 359105606 ps
CPU time 10.15 seconds
Started Jul 20 06:41:31 PM PDT 24
Finished Jul 20 06:41:43 PM PDT 24
Peak memory 248356 kb
Host smart-89904763-921a-4021-ac74-cbd48b2e5c25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42728
87518 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_intr_timeout.4272887518
Directory /workspace/18.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_lpg_stub_clk.3614580486
Short name T205
Test name
Test status
Simulation time 191319571986 ps
CPU time 1265.84 seconds
Started Jul 20 06:41:32 PM PDT 24
Finished Jul 20 07:02:39 PM PDT 24
Peak memory 273592 kb
Host smart-f69c340a-3869-4d95-9193-679cf0929e28
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3614580486 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg_stub_clk.3614580486
Directory /workspace/18.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/18.alert_handler_random_alerts.602587716
Short name T682
Test name
Test status
Simulation time 691157980 ps
CPU time 5.93 seconds
Started Jul 20 06:41:31 PM PDT 24
Finished Jul 20 06:41:37 PM PDT 24
Peak memory 248996 kb
Host smart-3d06bbc3-0544-4047-acb7-710aa9595af5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60258
7716 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_alerts.602587716
Directory /workspace/18.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/18.alert_handler_random_classes.3058563985
Short name T405
Test name
Test status
Simulation time 111772201 ps
CPU time 18.34 seconds
Started Jul 20 06:41:28 PM PDT 24
Finished Jul 20 06:41:47 PM PDT 24
Peak memory 248936 kb
Host smart-01b8975d-9f6f-4acc-9731-db398c469e3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30585
63985 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_classes.3058563985
Directory /workspace/18.alert_handler_random_classes/latest

Test location /workspace/coverage/default/18.alert_handler_sig_int_fail.1418274183
Short name T263
Test name
Test status
Simulation time 2033064050 ps
CPU time 17.2 seconds
Started Jul 20 06:41:32 PM PDT 24
Finished Jul 20 06:41:50 PM PDT 24
Peak memory 255640 kb
Host smart-a0cdc4aa-4eff-40cc-a054-eedd655ebd47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14182
74183 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_sig_int_fail.1418274183
Directory /workspace/18.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/18.alert_handler_smoke.2641867459
Short name T271
Test name
Test status
Simulation time 604286296 ps
CPU time 36.06 seconds
Started Jul 20 06:41:33 PM PDT 24
Finished Jul 20 06:42:10 PM PDT 24
Peak memory 256924 kb
Host smart-b17d772c-95b3-4bb2-80eb-6096dc0c2f57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26418
67459 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_smoke.2641867459
Directory /workspace/18.alert_handler_smoke/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all.3656254870
Short name T237
Test name
Test status
Simulation time 3525303504 ps
CPU time 87.1 seconds
Started Jul 20 06:41:29 PM PDT 24
Finished Jul 20 06:42:57 PM PDT 24
Peak memory 257264 kb
Host smart-f86274dc-8263-423c-81ff-cf12a8e60bf8
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656254870 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_ha
ndler_stress_all.3656254870
Directory /workspace/18.alert_handler_stress_all/latest

Test location /workspace/coverage/default/19.alert_handler_alert_accum_saturation.2676355170
Short name T189
Test name
Test status
Simulation time 30289875 ps
CPU time 3.71 seconds
Started Jul 20 06:41:38 PM PDT 24
Finished Jul 20 06:41:43 PM PDT 24
Peak memory 249180 kb
Host smart-de46ef0c-8843-421f-bed5-0ef915864cc4
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2676355170 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_alert_accum_saturation.2676355170
Directory /workspace/19.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/19.alert_handler_entropy.2469830711
Short name T66
Test name
Test status
Simulation time 89781079559 ps
CPU time 2643.36 seconds
Started Jul 20 06:41:35 PM PDT 24
Finished Jul 20 07:25:40 PM PDT 24
Peak memory 284668 kb
Host smart-0e631689-be30-46c6-9f13-2cd9a6e586f1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469830711 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy.2469830711
Directory /workspace/19.alert_handler_entropy/latest

Test location /workspace/coverage/default/19.alert_handler_entropy_stress.669958628
Short name T229
Test name
Test status
Simulation time 4208324504 ps
CPU time 49.27 seconds
Started Jul 20 06:41:45 PM PDT 24
Finished Jul 20 06:42:35 PM PDT 24
Peak memory 249044 kb
Host smart-8b14fe5f-ecd1-440a-bc2c-421371c32f64
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=669958628 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy_stress.669958628
Directory /workspace/19.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/19.alert_handler_esc_alert_accum.2162997137
Short name T457
Test name
Test status
Simulation time 2493801375 ps
CPU time 75.7 seconds
Started Jul 20 06:41:35 PM PDT 24
Finished Jul 20 06:42:52 PM PDT 24
Peak memory 256812 kb
Host smart-7e8b0dca-d934-45a9-b391-cf23d80944d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21629
97137 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_alert_accum.2162997137
Directory /workspace/19.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/19.alert_handler_esc_intr_timeout.867181964
Short name T67
Test name
Test status
Simulation time 3628602591 ps
CPU time 54.61 seconds
Started Jul 20 06:41:35 PM PDT 24
Finished Jul 20 06:42:30 PM PDT 24
Peak memory 249624 kb
Host smart-8f617432-ce56-414c-adfe-48589d26a47f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86718
1964 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_intr_timeout.867181964
Directory /workspace/19.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_lpg.2461890630
Short name T342
Test name
Test status
Simulation time 9373690735 ps
CPU time 790.5 seconds
Started Jul 20 06:41:36 PM PDT 24
Finished Jul 20 06:54:47 PM PDT 24
Peak memory 272348 kb
Host smart-ecb481ae-ed1c-4fc7-b674-70fe8340a508
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2461890630 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg.2461890630
Directory /workspace/19.alert_handler_lpg/latest

Test location /workspace/coverage/default/19.alert_handler_lpg_stub_clk.1929812982
Short name T393
Test name
Test status
Simulation time 41344965005 ps
CPU time 2390.38 seconds
Started Jul 20 06:41:45 PM PDT 24
Finished Jul 20 07:21:36 PM PDT 24
Peak memory 286352 kb
Host smart-d4b0dcc9-3826-47fc-83ab-cd6d7137c22d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929812982 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg_stub_clk.1929812982
Directory /workspace/19.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/19.alert_handler_random_alerts.2611244751
Short name T401
Test name
Test status
Simulation time 514067491 ps
CPU time 32.05 seconds
Started Jul 20 06:41:36 PM PDT 24
Finished Jul 20 06:42:09 PM PDT 24
Peak memory 256516 kb
Host smart-400c04f0-26e6-4436-9250-c1d865ecfd3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26112
44751 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_alerts.2611244751
Directory /workspace/19.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/19.alert_handler_random_classes.3130417212
Short name T90
Test name
Test status
Simulation time 1332910809 ps
CPU time 30.37 seconds
Started Jul 20 06:41:38 PM PDT 24
Finished Jul 20 06:42:09 PM PDT 24
Peak memory 248540 kb
Host smart-fc343d98-5ad0-4ab8-80d6-034183edb44f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31304
17212 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_classes.3130417212
Directory /workspace/19.alert_handler_random_classes/latest

Test location /workspace/coverage/default/19.alert_handler_sig_int_fail.501552168
Short name T53
Test name
Test status
Simulation time 974780658 ps
CPU time 32.9 seconds
Started Jul 20 06:41:35 PM PDT 24
Finished Jul 20 06:42:08 PM PDT 24
Peak memory 248936 kb
Host smart-5daea81a-5110-4f2a-b05e-3c94d4dc1403
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50155
2168 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_sig_int_fail.501552168
Directory /workspace/19.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/19.alert_handler_smoke.3261182436
Short name T572
Test name
Test status
Simulation time 3542165798 ps
CPU time 65.3 seconds
Started Jul 20 06:41:39 PM PDT 24
Finished Jul 20 06:42:45 PM PDT 24
Peak memory 257232 kb
Host smart-503ec0af-f384-42b0-8944-fa8f71555bbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32611
82436 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_smoke.3261182436
Directory /workspace/19.alert_handler_smoke/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all.1047165071
Short name T75
Test name
Test status
Simulation time 69863713403 ps
CPU time 1671.24 seconds
Started Jul 20 06:41:35 PM PDT 24
Finished Jul 20 07:09:28 PM PDT 24
Peak memory 298332 kb
Host smart-784b4ba3-e541-456e-ba6c-a0fcc97a0dbd
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047165071 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_ha
ndler_stress_all.1047165071
Directory /workspace/19.alert_handler_stress_all/latest

Test location /workspace/coverage/default/2.alert_handler_alert_accum_saturation.2737873366
Short name T194
Test name
Test status
Simulation time 37761504 ps
CPU time 2.4 seconds
Started Jul 20 06:41:00 PM PDT 24
Finished Jul 20 06:41:03 PM PDT 24
Peak memory 249368 kb
Host smart-14510348-d9e5-4015-9193-cda0806c6bb5
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2737873366 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_alert_accum_saturation.2737873366
Directory /workspace/2.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/2.alert_handler_entropy.1032901593
Short name T479
Test name
Test status
Simulation time 32509676457 ps
CPU time 648.66 seconds
Started Jul 20 06:41:08 PM PDT 24
Finished Jul 20 06:51:59 PM PDT 24
Peak memory 265436 kb
Host smart-a1a109cc-e9bd-44c8-95df-684d23dca672
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1032901593 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy.1032901593
Directory /workspace/2.alert_handler_entropy/latest

Test location /workspace/coverage/default/2.alert_handler_entropy_stress.2295394000
Short name T171
Test name
Test status
Simulation time 5250979208 ps
CPU time 56.5 seconds
Started Jul 20 06:41:11 PM PDT 24
Finished Jul 20 06:42:09 PM PDT 24
Peak memory 249084 kb
Host smart-970438f9-31ac-42bb-8820-7eae2ff3e209
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2295394000 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy_stress.2295394000
Directory /workspace/2.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/2.alert_handler_esc_alert_accum.2036557389
Short name T214
Test name
Test status
Simulation time 5304689063 ps
CPU time 125.66 seconds
Started Jul 20 06:41:10 PM PDT 24
Finished Jul 20 06:43:18 PM PDT 24
Peak memory 256808 kb
Host smart-80840bfa-00d8-4470-8557-ef8441138416
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20365
57389 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_alert_accum.2036557389
Directory /workspace/2.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/2.alert_handler_esc_intr_timeout.3674064274
Short name T385
Test name
Test status
Simulation time 212113867 ps
CPU time 5.37 seconds
Started Jul 20 06:40:54 PM PDT 24
Finished Jul 20 06:41:01 PM PDT 24
Peak memory 248588 kb
Host smart-c33c7f3b-6606-493e-b158-4b5f08dfea31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36740
64274 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_intr_timeout.3674064274
Directory /workspace/2.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_lpg.3054351930
Short name T439
Test name
Test status
Simulation time 42503770717 ps
CPU time 987.77 seconds
Started Jul 20 06:41:22 PM PDT 24
Finished Jul 20 06:57:51 PM PDT 24
Peak memory 273616 kb
Host smart-48d96f43-3e68-4cbc-9472-e081c7628c12
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054351930 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg.3054351930
Directory /workspace/2.alert_handler_lpg/latest

Test location /workspace/coverage/default/2.alert_handler_lpg_stub_clk.1895287231
Short name T436
Test name
Test status
Simulation time 18860233000 ps
CPU time 889.99 seconds
Started Jul 20 06:41:02 PM PDT 24
Finished Jul 20 06:55:53 PM PDT 24
Peak memory 271068 kb
Host smart-cea7805b-755c-4490-84d9-a4bd3a5c00c7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895287231 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg_stub_clk.1895287231
Directory /workspace/2.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/2.alert_handler_ping_timeout.2252856851
Short name T556
Test name
Test status
Simulation time 9243299563 ps
CPU time 184.78 seconds
Started Jul 20 06:40:59 PM PDT 24
Finished Jul 20 06:44:05 PM PDT 24
Peak memory 249036 kb
Host smart-bdfafd52-7ed6-47a8-8ad0-30ecf3246795
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2252856851 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_ping_timeout.2252856851
Directory /workspace/2.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_random_alerts.2809949838
Short name T623
Test name
Test status
Simulation time 124082476 ps
CPU time 15.06 seconds
Started Jul 20 06:40:53 PM PDT 24
Finished Jul 20 06:41:10 PM PDT 24
Peak memory 256448 kb
Host smart-55baafb7-2966-4db7-8e75-833680421414
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28099
49838 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_alerts.2809949838
Directory /workspace/2.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/2.alert_handler_random_classes.779255581
Short name T278
Test name
Test status
Simulation time 446210865 ps
CPU time 11.87 seconds
Started Jul 20 06:40:54 PM PDT 24
Finished Jul 20 06:41:07 PM PDT 24
Peak memory 249336 kb
Host smart-4b281a1f-9f27-4474-8ee2-2937b000847b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77925
5581 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_classes.779255581
Directory /workspace/2.alert_handler_random_classes/latest

Test location /workspace/coverage/default/2.alert_handler_sec_cm.1599287182
Short name T30
Test name
Test status
Simulation time 209933117 ps
CPU time 14.14 seconds
Started Jul 20 06:40:56 PM PDT 24
Finished Jul 20 06:41:11 PM PDT 24
Peak memory 270708 kb
Host smart-9c24bd68-2a86-477e-bac9-48ecfa682448
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1599287182 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sec_cm.1599287182
Directory /workspace/2.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/2.alert_handler_smoke.1642685632
Short name T378
Test name
Test status
Simulation time 149134698 ps
CPU time 17.03 seconds
Started Jul 20 06:41:08 PM PDT 24
Finished Jul 20 06:41:25 PM PDT 24
Peak memory 248984 kb
Host smart-e8396735-9771-49b2-91ac-89336eb09318
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16426
85632 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_smoke.1642685632
Directory /workspace/2.alert_handler_smoke/latest

Test location /workspace/coverage/default/20.alert_handler_entropy.933440935
Short name T571
Test name
Test status
Simulation time 15019286148 ps
CPU time 1162.23 seconds
Started Jul 20 06:41:46 PM PDT 24
Finished Jul 20 07:01:09 PM PDT 24
Peak memory 286240 kb
Host smart-b3ebeb56-7e8e-44fd-b886-e53b9866c771
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933440935 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_entropy.933440935
Directory /workspace/20.alert_handler_entropy/latest

Test location /workspace/coverage/default/20.alert_handler_esc_alert_accum.2479537447
Short name T369
Test name
Test status
Simulation time 1397951978 ps
CPU time 85.97 seconds
Started Jul 20 06:41:42 PM PDT 24
Finished Jul 20 06:43:08 PM PDT 24
Peak memory 256576 kb
Host smart-9133bf7c-f004-4ae8-bcf2-59d0e96e868d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24795
37447 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_alert_accum.2479537447
Directory /workspace/20.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/20.alert_handler_esc_intr_timeout.4159299661
Short name T650
Test name
Test status
Simulation time 546455118 ps
CPU time 26.99 seconds
Started Jul 20 06:41:36 PM PDT 24
Finished Jul 20 06:42:04 PM PDT 24
Peak memory 248764 kb
Host smart-fd4c9183-c733-4201-a2eb-b4b20a20f75e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41592
99661 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_intr_timeout.4159299661
Directory /workspace/20.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_lpg.2996394236
Short name T345
Test name
Test status
Simulation time 22033865538 ps
CPU time 1292.8 seconds
Started Jul 20 06:41:43 PM PDT 24
Finished Jul 20 07:03:16 PM PDT 24
Peak memory 265440 kb
Host smart-75de79ff-246b-4ec5-a80b-2b039decf719
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996394236 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg.2996394236
Directory /workspace/20.alert_handler_lpg/latest

Test location /workspace/coverage/default/20.alert_handler_lpg_stub_clk.1184731077
Short name T266
Test name
Test status
Simulation time 52383095715 ps
CPU time 3014.44 seconds
Started Jul 20 06:41:38 PM PDT 24
Finished Jul 20 07:31:54 PM PDT 24
Peak memory 289868 kb
Host smart-99639656-046b-4fd7-8dc6-7b235812f55c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184731077 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg_stub_clk.1184731077
Directory /workspace/20.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/20.alert_handler_ping_timeout.3975096481
Short name T304
Test name
Test status
Simulation time 15737852483 ps
CPU time 325.04 seconds
Started Jul 20 06:41:38 PM PDT 24
Finished Jul 20 06:47:04 PM PDT 24
Peak memory 248976 kb
Host smart-6ab755ea-16b2-422e-b4b7-f4146589c6a3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975096481 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_ping_timeout.3975096481
Directory /workspace/20.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_random_alerts.492857085
Short name T612
Test name
Test status
Simulation time 602476666 ps
CPU time 18.72 seconds
Started Jul 20 06:41:37 PM PDT 24
Finished Jul 20 06:41:56 PM PDT 24
Peak memory 249016 kb
Host smart-a0c2d1db-b612-4554-9ecf-cd209c18f09c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49285
7085 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_alerts.492857085
Directory /workspace/20.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/20.alert_handler_random_classes.1292730370
Short name T667
Test name
Test status
Simulation time 490351401 ps
CPU time 21.45 seconds
Started Jul 20 06:41:36 PM PDT 24
Finished Jul 20 06:41:59 PM PDT 24
Peak memory 248676 kb
Host smart-43c08738-ea00-41d5-b1dd-11b88d102322
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12927
30370 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_classes.1292730370
Directory /workspace/20.alert_handler_random_classes/latest

Test location /workspace/coverage/default/20.alert_handler_sig_int_fail.1478466024
Short name T490
Test name
Test status
Simulation time 1212312010 ps
CPU time 25.85 seconds
Started Jul 20 06:41:36 PM PDT 24
Finished Jul 20 06:42:02 PM PDT 24
Peak memory 248932 kb
Host smart-4b38e7af-8216-4e7b-b93e-8c7d3d5f7959
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14784
66024 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_sig_int_fail.1478466024
Directory /workspace/20.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/20.alert_handler_smoke.1922096174
Short name T540
Test name
Test status
Simulation time 1450794061 ps
CPU time 49.56 seconds
Started Jul 20 06:41:39 PM PDT 24
Finished Jul 20 06:42:29 PM PDT 24
Peak memory 257136 kb
Host smart-10b0cdeb-31ac-475d-8827-de4042abf904
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19220
96174 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_smoke.1922096174
Directory /workspace/20.alert_handler_smoke/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all.967983702
Short name T254
Test name
Test status
Simulation time 17022155742 ps
CPU time 1459.38 seconds
Started Jul 20 06:41:36 PM PDT 24
Finished Jul 20 07:05:56 PM PDT 24
Peak memory 289700 kb
Host smart-2d01ca1a-c6e7-4c7e-957c-1cdc74dbcb52
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967983702 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_han
dler_stress_all.967983702
Directory /workspace/20.alert_handler_stress_all/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all_with_rand_reset.2292272597
Short name T26
Test name
Test status
Simulation time 264793335432 ps
CPU time 3277.84 seconds
Started Jul 20 06:41:36 PM PDT 24
Finished Jul 20 07:36:15 PM PDT 24
Peak memory 289636 kb
Host smart-7b2e2923-5876-4240-8d76-eeccac652b57
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292272597 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 20.alert_handler_stress_all_with_rand_reset.2292272597
Directory /workspace/20.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.alert_handler_entropy.1810230809
Short name T410
Test name
Test status
Simulation time 19369855441 ps
CPU time 1090.01 seconds
Started Jul 20 06:41:45 PM PDT 24
Finished Jul 20 06:59:56 PM PDT 24
Peak memory 282688 kb
Host smart-45a16833-bd7c-4418-b3b2-3e1dc04283b1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810230809 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_entropy.1810230809
Directory /workspace/21.alert_handler_entropy/latest

Test location /workspace/coverage/default/21.alert_handler_esc_alert_accum.1106903620
Short name T240
Test name
Test status
Simulation time 1666417627 ps
CPU time 32.78 seconds
Started Jul 20 06:41:42 PM PDT 24
Finished Jul 20 06:42:15 PM PDT 24
Peak memory 257184 kb
Host smart-2d11923b-02b6-46e3-b854-2cc1720c57b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11069
03620 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_alert_accum.1106903620
Directory /workspace/21.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/21.alert_handler_esc_intr_timeout.2493644674
Short name T70
Test name
Test status
Simulation time 873457191 ps
CPU time 45.21 seconds
Started Jul 20 06:41:38 PM PDT 24
Finished Jul 20 06:42:24 PM PDT 24
Peak memory 256092 kb
Host smart-f64a41cd-1f8d-4d27-9a22-63918439b47c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24936
44674 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_intr_timeout.2493644674
Directory /workspace/21.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_lpg_stub_clk.602576491
Short name T281
Test name
Test status
Simulation time 33574931500 ps
CPU time 1099.14 seconds
Started Jul 20 06:41:42 PM PDT 24
Finished Jul 20 07:00:02 PM PDT 24
Peak memory 289104 kb
Host smart-591f4e9e-1502-4a87-a342-8795fd50bf3a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602576491 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg_stub_clk.602576491
Directory /workspace/21.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/21.alert_handler_ping_timeout.3507389863
Short name T702
Test name
Test status
Simulation time 5632884220 ps
CPU time 247.81 seconds
Started Jul 20 06:41:44 PM PDT 24
Finished Jul 20 06:45:52 PM PDT 24
Peak memory 249116 kb
Host smart-15354fae-3e50-4dbe-975b-092c450d9d32
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507389863 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_ping_timeout.3507389863
Directory /workspace/21.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_random_alerts.1827563046
Short name T570
Test name
Test status
Simulation time 2665429464 ps
CPU time 20.8 seconds
Started Jul 20 06:41:40 PM PDT 24
Finished Jul 20 06:42:01 PM PDT 24
Peak memory 257108 kb
Host smart-46ae9bc7-f4af-4732-a97f-eb79d3216d7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18275
63046 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_alerts.1827563046
Directory /workspace/21.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/21.alert_handler_random_classes.901212787
Short name T204
Test name
Test status
Simulation time 483627921 ps
CPU time 29.48 seconds
Started Jul 20 06:41:38 PM PDT 24
Finished Jul 20 06:42:08 PM PDT 24
Peak memory 248924 kb
Host smart-53e5cc22-284a-44ab-8bdc-4e170f0c978d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90121
2787 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_classes.901212787
Directory /workspace/21.alert_handler_random_classes/latest

Test location /workspace/coverage/default/21.alert_handler_sig_int_fail.1968514356
Short name T249
Test name
Test status
Simulation time 4537918674 ps
CPU time 76.05 seconds
Started Jul 20 06:41:37 PM PDT 24
Finished Jul 20 06:42:54 PM PDT 24
Peak memory 248844 kb
Host smart-0cdad357-b990-4ce1-99cf-4ea0cdf5eacb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19685
14356 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_sig_int_fail.1968514356
Directory /workspace/21.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/21.alert_handler_smoke.86358083
Short name T678
Test name
Test status
Simulation time 327344491 ps
CPU time 8.52 seconds
Started Jul 20 06:41:35 PM PDT 24
Finished Jul 20 06:41:45 PM PDT 24
Peak memory 249464 kb
Host smart-7dcef52f-3a0b-4ed0-baaf-f6ef9e816e4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86358
083 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_smoke.86358083
Directory /workspace/21.alert_handler_smoke/latest

Test location /workspace/coverage/default/22.alert_handler_entropy.2971136672
Short name T64
Test name
Test status
Simulation time 175213578942 ps
CPU time 1136.24 seconds
Started Jul 20 06:41:45 PM PDT 24
Finished Jul 20 07:00:42 PM PDT 24
Peak memory 289052 kb
Host smart-874cc7ee-06d8-4ce2-b848-7e94f198d692
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971136672 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_entropy.2971136672
Directory /workspace/22.alert_handler_entropy/latest

Test location /workspace/coverage/default/22.alert_handler_esc_alert_accum.3246673638
Short name T564
Test name
Test status
Simulation time 2412106278 ps
CPU time 47.09 seconds
Started Jul 20 06:41:43 PM PDT 24
Finished Jul 20 06:42:31 PM PDT 24
Peak memory 257252 kb
Host smart-bde4e29a-b76a-4f9f-9c1d-a736e7e091db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32466
73638 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_alert_accum.3246673638
Directory /workspace/22.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/22.alert_handler_esc_intr_timeout.3241679735
Short name T469
Test name
Test status
Simulation time 1336407012 ps
CPU time 37.32 seconds
Started Jul 20 06:41:44 PM PDT 24
Finished Jul 20 06:42:22 PM PDT 24
Peak memory 256728 kb
Host smart-ea83ec9f-5eb5-4a9a-a0f5-9cddc2fe3854
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32416
79735 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_intr_timeout.3241679735
Directory /workspace/22.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_lpg.464354541
Short name T639
Test name
Test status
Simulation time 50723278840 ps
CPU time 2507.02 seconds
Started Jul 20 06:41:43 PM PDT 24
Finished Jul 20 07:23:31 PM PDT 24
Peak memory 286976 kb
Host smart-801095be-509a-435a-bab3-d219eddfaaea
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464354541 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg.464354541
Directory /workspace/22.alert_handler_lpg/latest

Test location /workspace/coverage/default/22.alert_handler_lpg_stub_clk.3673764912
Short name T95
Test name
Test status
Simulation time 45595208004 ps
CPU time 2802.52 seconds
Started Jul 20 06:41:45 PM PDT 24
Finished Jul 20 07:28:29 PM PDT 24
Peak memory 281964 kb
Host smart-f4b1e7fb-85f8-4edc-a112-da4087d40c63
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673764912 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg_stub_clk.3673764912
Directory /workspace/22.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/22.alert_handler_ping_timeout.453351984
Short name T325
Test name
Test status
Simulation time 8117466991 ps
CPU time 169.7 seconds
Started Jul 20 06:41:46 PM PDT 24
Finished Jul 20 06:44:36 PM PDT 24
Peak memory 248908 kb
Host smart-de5cffc8-3296-4682-85e9-9f3e60f86e95
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453351984 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_ping_timeout.453351984
Directory /workspace/22.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_random_classes.153541242
Short name T390
Test name
Test status
Simulation time 1511264855 ps
CPU time 27.64 seconds
Started Jul 20 06:41:42 PM PDT 24
Finished Jul 20 06:42:11 PM PDT 24
Peak memory 255532 kb
Host smart-86e7db16-1da0-4b05-a69d-fad5887cbe51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15354
1242 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_classes.153541242
Directory /workspace/22.alert_handler_random_classes/latest

Test location /workspace/coverage/default/22.alert_handler_sig_int_fail.606223781
Short name T555
Test name
Test status
Simulation time 905050337 ps
CPU time 50.49 seconds
Started Jul 20 06:41:44 PM PDT 24
Finished Jul 20 06:42:35 PM PDT 24
Peak memory 257208 kb
Host smart-99ca9b1c-2cb9-42a1-a763-d0df46b2c425
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60622
3781 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_sig_int_fail.606223781
Directory /workspace/22.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/22.alert_handler_smoke.2898197827
Short name T608
Test name
Test status
Simulation time 1186372389 ps
CPU time 22.52 seconds
Started Jul 20 06:41:42 PM PDT 24
Finished Jul 20 06:42:06 PM PDT 24
Peak memory 256888 kb
Host smart-b03eb7a2-85a3-4c70-b4b9-8e2ad0c9a9f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28981
97827 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_smoke.2898197827
Directory /workspace/22.alert_handler_smoke/latest

Test location /workspace/coverage/default/23.alert_handler_entropy.2641627746
Short name T473
Test name
Test status
Simulation time 20203242060 ps
CPU time 1351.84 seconds
Started Jul 20 06:41:54 PM PDT 24
Finished Jul 20 07:04:26 PM PDT 24
Peak memory 272568 kb
Host smart-43c9842d-9e44-4152-a32c-044eec36f3f3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641627746 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_entropy.2641627746
Directory /workspace/23.alert_handler_entropy/latest

Test location /workspace/coverage/default/23.alert_handler_esc_alert_accum.70790033
Short name T535
Test name
Test status
Simulation time 1958899827 ps
CPU time 179.51 seconds
Started Jul 20 06:41:45 PM PDT 24
Finished Jul 20 06:44:46 PM PDT 24
Peak memory 257304 kb
Host smart-a99e2af2-d4ce-4ba7-975c-81557091d91c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70790
033 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_alert_accum.70790033
Directory /workspace/23.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/23.alert_handler_esc_intr_timeout.1781231038
Short name T434
Test name
Test status
Simulation time 301755158 ps
CPU time 20.34 seconds
Started Jul 20 06:41:43 PM PDT 24
Finished Jul 20 06:42:04 PM PDT 24
Peak memory 248948 kb
Host smart-3973b10e-6b1c-4b3e-b1cd-c123841a2312
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17812
31038 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_intr_timeout.1781231038
Directory /workspace/23.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_lpg_stub_clk.3745059959
Short name T488
Test name
Test status
Simulation time 180325790746 ps
CPU time 1771.05 seconds
Started Jul 20 06:41:49 PM PDT 24
Finished Jul 20 07:11:21 PM PDT 24
Peak memory 273560 kb
Host smart-bf21a19f-83db-4ecc-babe-3e47bab31462
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745059959 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg_stub_clk.3745059959
Directory /workspace/23.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/23.alert_handler_random_alerts.4076053657
Short name T693
Test name
Test status
Simulation time 3457292022 ps
CPU time 24.47 seconds
Started Jul 20 06:41:44 PM PDT 24
Finished Jul 20 06:42:09 PM PDT 24
Peak memory 256564 kb
Host smart-7733b0ea-95c2-4b9e-9fb7-c8a52ebf5fea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40760
53657 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_alerts.4076053657
Directory /workspace/23.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/23.alert_handler_random_classes.2037302235
Short name T533
Test name
Test status
Simulation time 816615173 ps
CPU time 63.61 seconds
Started Jul 20 06:41:44 PM PDT 24
Finished Jul 20 06:42:48 PM PDT 24
Peak memory 248508 kb
Host smart-4b9066da-a227-4098-84d3-3ea333c570a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20373
02235 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_classes.2037302235
Directory /workspace/23.alert_handler_random_classes/latest

Test location /workspace/coverage/default/23.alert_handler_sig_int_fail.2061111178
Short name T472
Test name
Test status
Simulation time 759006174 ps
CPU time 56.27 seconds
Started Jul 20 06:41:51 PM PDT 24
Finished Jul 20 06:42:48 PM PDT 24
Peak memory 256440 kb
Host smart-902e27ef-194c-45e7-ac53-2fe94fce16ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20611
11178 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_sig_int_fail.2061111178
Directory /workspace/23.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/23.alert_handler_smoke.991379754
Short name T370
Test name
Test status
Simulation time 1381974208 ps
CPU time 21.86 seconds
Started Jul 20 06:41:45 PM PDT 24
Finished Jul 20 06:42:07 PM PDT 24
Peak memory 257088 kb
Host smart-d649bb7f-e922-4ea7-8941-8fa62bda2a14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99137
9754 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_smoke.991379754
Directory /workspace/23.alert_handler_smoke/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all.1663528739
Short name T37
Test name
Test status
Simulation time 36111911350 ps
CPU time 1966.36 seconds
Started Jul 20 06:41:50 PM PDT 24
Finished Jul 20 07:14:36 PM PDT 24
Peak memory 283492 kb
Host smart-5bd95b29-d164-4762-af8e-afb95db56954
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663528739 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_ha
ndler_stress_all.1663528739
Directory /workspace/23.alert_handler_stress_all/latest

Test location /workspace/coverage/default/24.alert_handler_entropy.1586413126
Short name T580
Test name
Test status
Simulation time 38081558018 ps
CPU time 1400.49 seconds
Started Jul 20 06:41:51 PM PDT 24
Finished Jul 20 07:05:12 PM PDT 24
Peak memory 289812 kb
Host smart-6ce11caf-0296-4828-b97f-5992e13be81e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586413126 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_entropy.1586413126
Directory /workspace/24.alert_handler_entropy/latest

Test location /workspace/coverage/default/24.alert_handler_esc_alert_accum.352390560
Short name T429
Test name
Test status
Simulation time 6295299026 ps
CPU time 205.68 seconds
Started Jul 20 06:41:52 PM PDT 24
Finished Jul 20 06:45:18 PM PDT 24
Peak memory 256804 kb
Host smart-355e0d6a-1e05-4df2-8aed-ad83ce1f2849
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35239
0560 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_alert_accum.352390560
Directory /workspace/24.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/24.alert_handler_esc_intr_timeout.2742191660
Short name T661
Test name
Test status
Simulation time 521846133 ps
CPU time 16.78 seconds
Started Jul 20 06:41:51 PM PDT 24
Finished Jul 20 06:42:08 PM PDT 24
Peak memory 248480 kb
Host smart-059bd1ea-0551-4883-83b9-e08021ac9a42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27421
91660 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_intr_timeout.2742191660
Directory /workspace/24.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_lpg.2636958911
Short name T647
Test name
Test status
Simulation time 26316718521 ps
CPU time 1018.94 seconds
Started Jul 20 06:41:53 PM PDT 24
Finished Jul 20 06:58:52 PM PDT 24
Peak memory 273696 kb
Host smart-0ab3d76e-a90e-4c0f-a76a-da8b21e758a1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636958911 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg.2636958911
Directory /workspace/24.alert_handler_lpg/latest

Test location /workspace/coverage/default/24.alert_handler_lpg_stub_clk.2962010545
Short name T233
Test name
Test status
Simulation time 48480711611 ps
CPU time 2812.47 seconds
Started Jul 20 06:41:49 PM PDT 24
Finished Jul 20 07:28:42 PM PDT 24
Peak memory 288268 kb
Host smart-a6b3582e-0351-41b2-b3f6-5338888eb528
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962010545 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg_stub_clk.2962010545
Directory /workspace/24.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/24.alert_handler_ping_timeout.1965138454
Short name T331
Test name
Test status
Simulation time 18663778608 ps
CPU time 203.5 seconds
Started Jul 20 06:41:52 PM PDT 24
Finished Jul 20 06:45:16 PM PDT 24
Peak memory 249084 kb
Host smart-f6dc2fa4-7c53-4fb9-9db8-81c4347701cb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965138454 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_ping_timeout.1965138454
Directory /workspace/24.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_random_alerts.2624422168
Short name T676
Test name
Test status
Simulation time 2217410448 ps
CPU time 43.35 seconds
Started Jul 20 06:41:51 PM PDT 24
Finished Jul 20 06:42:35 PM PDT 24
Peak memory 256608 kb
Host smart-7b772e96-a9bd-42d7-bc63-160eab180410
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26244
22168 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_alerts.2624422168
Directory /workspace/24.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/24.alert_handler_random_classes.995181318
Short name T618
Test name
Test status
Simulation time 2676543742 ps
CPU time 55.32 seconds
Started Jul 20 06:41:52 PM PDT 24
Finished Jul 20 06:42:48 PM PDT 24
Peak memory 256804 kb
Host smart-d4121cb3-1702-4df3-ad24-593e48e84ed0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99518
1318 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_classes.995181318
Directory /workspace/24.alert_handler_random_classes/latest

Test location /workspace/coverage/default/24.alert_handler_sig_int_fail.2963732510
Short name T71
Test name
Test status
Simulation time 1841298724 ps
CPU time 17.74 seconds
Started Jul 20 06:41:52 PM PDT 24
Finished Jul 20 06:42:10 PM PDT 24
Peak memory 257148 kb
Host smart-9df3b5f1-be8c-4edd-a293-7ae38f68fbc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29637
32510 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_sig_int_fail.2963732510
Directory /workspace/24.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/24.alert_handler_smoke.500851164
Short name T29
Test name
Test status
Simulation time 519373855 ps
CPU time 38.47 seconds
Started Jul 20 06:41:58 PM PDT 24
Finished Jul 20 06:42:37 PM PDT 24
Peak memory 248932 kb
Host smart-70bf09b1-50cd-49d0-874d-d5bfd96fe5d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50085
1164 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_smoke.500851164
Directory /workspace/24.alert_handler_smoke/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all.319236583
Short name T588
Test name
Test status
Simulation time 47454618245 ps
CPU time 1549.54 seconds
Started Jul 20 06:41:55 PM PDT 24
Finished Jul 20 07:07:45 PM PDT 24
Peak memory 273396 kb
Host smart-544f0448-9ff3-4af2-af5f-2728adb02c45
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319236583 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_han
dler_stress_all.319236583
Directory /workspace/24.alert_handler_stress_all/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all_with_rand_reset.3709601079
Short name T226
Test name
Test status
Simulation time 117703893201 ps
CPU time 3388.38 seconds
Started Jul 20 06:41:52 PM PDT 24
Finished Jul 20 07:38:21 PM PDT 24
Peak memory 306008 kb
Host smart-fbcadc28-5b1a-4010-b2c0-27cd770ba429
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709601079 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 24.alert_handler_stress_all_with_rand_reset.3709601079
Directory /workspace/24.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.alert_handler_entropy.2025257930
Short name T270
Test name
Test status
Simulation time 39282427383 ps
CPU time 1848.5 seconds
Started Jul 20 06:41:58 PM PDT 24
Finished Jul 20 07:12:47 PM PDT 24
Peak memory 289372 kb
Host smart-c2312a15-97ae-41da-8fd0-ed7b90e57cb9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025257930 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_entropy.2025257930
Directory /workspace/25.alert_handler_entropy/latest

Test location /workspace/coverage/default/25.alert_handler_esc_alert_accum.1366017052
Short name T599
Test name
Test status
Simulation time 23113144516 ps
CPU time 302.85 seconds
Started Jul 20 06:41:51 PM PDT 24
Finished Jul 20 06:46:54 PM PDT 24
Peak memory 257224 kb
Host smart-570e9815-0fb5-4414-ab26-08e04f76a57b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13660
17052 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_alert_accum.1366017052
Directory /workspace/25.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/25.alert_handler_esc_intr_timeout.1811095238
Short name T388
Test name
Test status
Simulation time 845669518 ps
CPU time 37.78 seconds
Started Jul 20 06:41:51 PM PDT 24
Finished Jul 20 06:42:30 PM PDT 24
Peak memory 249604 kb
Host smart-81458a79-bde6-488d-be0c-3f65066727f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18110
95238 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_intr_timeout.1811095238
Directory /workspace/25.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_lpg.1731118108
Short name T341
Test name
Test status
Simulation time 64673642654 ps
CPU time 1437.31 seconds
Started Jul 20 06:42:01 PM PDT 24
Finished Jul 20 07:05:59 PM PDT 24
Peak memory 289448 kb
Host smart-bde40bb8-5e54-4c89-9dc6-becfc20bda9d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731118108 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg.1731118108
Directory /workspace/25.alert_handler_lpg/latest

Test location /workspace/coverage/default/25.alert_handler_lpg_stub_clk.2220213569
Short name T351
Test name
Test status
Simulation time 76400738841 ps
CPU time 2652.63 seconds
Started Jul 20 06:42:09 PM PDT 24
Finished Jul 20 07:26:22 PM PDT 24
Peak memory 290020 kb
Host smart-e3414cec-8c57-420a-b7e1-936aeb35536c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2220213569 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg_stub_clk.2220213569
Directory /workspace/25.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/25.alert_handler_ping_timeout.1061605178
Short name T186
Test name
Test status
Simulation time 30859800127 ps
CPU time 353.32 seconds
Started Jul 20 06:42:11 PM PDT 24
Finished Jul 20 06:48:05 PM PDT 24
Peak memory 256020 kb
Host smart-43b4e1c2-b1fd-4f31-8aaa-f06c7ce0c23a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061605178 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_ping_timeout.1061605178
Directory /workspace/25.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_random_alerts.3007749896
Short name T461
Test name
Test status
Simulation time 55022271 ps
CPU time 3.43 seconds
Started Jul 20 06:41:51 PM PDT 24
Finished Jul 20 06:41:55 PM PDT 24
Peak memory 240728 kb
Host smart-e637e3e5-d9ea-4e8b-b242-20ee84050439
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30077
49896 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_alerts.3007749896
Directory /workspace/25.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/25.alert_handler_random_classes.202132514
Short name T298
Test name
Test status
Simulation time 666085565 ps
CPU time 41.79 seconds
Started Jul 20 06:41:50 PM PDT 24
Finished Jul 20 06:42:33 PM PDT 24
Peak memory 256240 kb
Host smart-169361a8-4825-48fc-b56c-1bd75645de13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20213
2514 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_classes.202132514
Directory /workspace/25.alert_handler_random_classes/latest

Test location /workspace/coverage/default/25.alert_handler_sig_int_fail.2533768124
Short name T48
Test name
Test status
Simulation time 524610064 ps
CPU time 25.03 seconds
Started Jul 20 06:41:57 PM PDT 24
Finished Jul 20 06:42:22 PM PDT 24
Peak memory 248556 kb
Host smart-386ec3b9-07e1-477b-b0cd-042f0e299947
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25337
68124 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_sig_int_fail.2533768124
Directory /workspace/25.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/25.alert_handler_smoke.2718744929
Short name T383
Test name
Test status
Simulation time 95388255 ps
CPU time 11.44 seconds
Started Jul 20 06:41:50 PM PDT 24
Finished Jul 20 06:42:02 PM PDT 24
Peak memory 256040 kb
Host smart-199e2380-e55b-44db-b0cf-ef1a04640a78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27187
44929 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_smoke.2718744929
Directory /workspace/25.alert_handler_smoke/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all.289734790
Short name T251
Test name
Test status
Simulation time 137492894317 ps
CPU time 512.22 seconds
Started Jul 20 06:42:10 PM PDT 24
Finished Jul 20 06:50:43 PM PDT 24
Peak memory 265532 kb
Host smart-5f9dd79e-b7a6-4228-b4bd-ec14f5ff7ba3
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289734790 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_han
dler_stress_all.289734790
Directory /workspace/25.alert_handler_stress_all/latest

Test location /workspace/coverage/default/26.alert_handler_entropy.962088448
Short name T89
Test name
Test status
Simulation time 34155482553 ps
CPU time 2154.11 seconds
Started Jul 20 06:41:57 PM PDT 24
Finished Jul 20 07:17:52 PM PDT 24
Peak memory 289740 kb
Host smart-b714a794-82eb-48f5-adb4-795d8598adf9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962088448 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_entropy.962088448
Directory /workspace/26.alert_handler_entropy/latest

Test location /workspace/coverage/default/26.alert_handler_esc_alert_accum.3760212674
Short name T665
Test name
Test status
Simulation time 7811682202 ps
CPU time 115.86 seconds
Started Jul 20 06:42:01 PM PDT 24
Finished Jul 20 06:43:57 PM PDT 24
Peak memory 256792 kb
Host smart-7ee1f88d-9dab-4e85-8353-754f7c4ceaee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37602
12674 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_alert_accum.3760212674
Directory /workspace/26.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/26.alert_handler_esc_intr_timeout.229962171
Short name T462
Test name
Test status
Simulation time 999039964 ps
CPU time 56.74 seconds
Started Jul 20 06:42:11 PM PDT 24
Finished Jul 20 06:43:09 PM PDT 24
Peak memory 248856 kb
Host smart-53b6f2a3-de93-4362-829d-282d60c7b5aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22996
2171 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_intr_timeout.229962171
Directory /workspace/26.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_lpg.2653542065
Short name T532
Test name
Test status
Simulation time 418999990448 ps
CPU time 1242.07 seconds
Started Jul 20 06:42:00 PM PDT 24
Finished Jul 20 07:02:43 PM PDT 24
Peak memory 273548 kb
Host smart-73afb991-7423-491c-89e7-a242b02c38c3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2653542065 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg.2653542065
Directory /workspace/26.alert_handler_lpg/latest

Test location /workspace/coverage/default/26.alert_handler_lpg_stub_clk.943619076
Short name T212
Test name
Test status
Simulation time 11956359786 ps
CPU time 1144.36 seconds
Started Jul 20 06:43:03 PM PDT 24
Finished Jul 20 07:02:08 PM PDT 24
Peak memory 289840 kb
Host smart-719a7746-d59c-4431-9b84-a1c16ffd9686
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943619076 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg_stub_clk.943619076
Directory /workspace/26.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/26.alert_handler_ping_timeout.2556405063
Short name T310
Test name
Test status
Simulation time 5413829406 ps
CPU time 164.45 seconds
Started Jul 20 06:42:13 PM PDT 24
Finished Jul 20 06:44:59 PM PDT 24
Peak memory 248928 kb
Host smart-7960dd2c-54f1-4e29-b21f-3ef6ff55d071
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556405063 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_ping_timeout.2556405063
Directory /workspace/26.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_random_alerts.1828724856
Short name T494
Test name
Test status
Simulation time 256782065 ps
CPU time 9.18 seconds
Started Jul 20 06:42:12 PM PDT 24
Finished Jul 20 06:42:22 PM PDT 24
Peak memory 248956 kb
Host smart-e320befe-05ed-429c-9a71-16ba7d03cc0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18287
24856 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_alerts.1828724856
Directory /workspace/26.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/26.alert_handler_random_classes.3013877952
Short name T292
Test name
Test status
Simulation time 3574362006 ps
CPU time 62.74 seconds
Started Jul 20 06:41:58 PM PDT 24
Finished Jul 20 06:43:01 PM PDT 24
Peak memory 248768 kb
Host smart-008da755-1397-4b49-9b27-c32e72f44cd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30138
77952 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_classes.3013877952
Directory /workspace/26.alert_handler_random_classes/latest

Test location /workspace/coverage/default/26.alert_handler_sig_int_fail.1934300827
Short name T550
Test name
Test status
Simulation time 770415858 ps
CPU time 21.89 seconds
Started Jul 20 06:42:11 PM PDT 24
Finished Jul 20 06:42:34 PM PDT 24
Peak memory 256448 kb
Host smart-a20be99b-68c3-49d4-aac5-c56bdf329b81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19343
00827 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_sig_int_fail.1934300827
Directory /workspace/26.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/26.alert_handler_smoke.2499437448
Short name T554
Test name
Test status
Simulation time 499551792 ps
CPU time 13.28 seconds
Started Jul 20 06:42:00 PM PDT 24
Finished Jul 20 06:42:14 PM PDT 24
Peak memory 256208 kb
Host smart-11e6c88e-db1b-4e8c-aa48-6f4028e41d97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24994
37448 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_smoke.2499437448
Directory /workspace/26.alert_handler_smoke/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all.1702238994
Short name T275
Test name
Test status
Simulation time 163100825488 ps
CPU time 2605.07 seconds
Started Jul 20 06:42:10 PM PDT 24
Finished Jul 20 07:25:36 PM PDT 24
Peak memory 289472 kb
Host smart-ab398e6e-8784-40f0-a72f-44ef0dd0c002
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702238994 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_ha
ndler_stress_all.1702238994
Directory /workspace/26.alert_handler_stress_all/latest

Test location /workspace/coverage/default/27.alert_handler_entropy.2214846180
Short name T441
Test name
Test status
Simulation time 71198561314 ps
CPU time 1457.22 seconds
Started Jul 20 06:42:13 PM PDT 24
Finished Jul 20 07:06:31 PM PDT 24
Peak memory 273664 kb
Host smart-7bbe878d-fbc2-4f28-88c4-b23698aca5a0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214846180 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_entropy.2214846180
Directory /workspace/27.alert_handler_entropy/latest

Test location /workspace/coverage/default/27.alert_handler_esc_alert_accum.3281405857
Short name T417
Test name
Test status
Simulation time 15441269690 ps
CPU time 256.43 seconds
Started Jul 20 06:41:59 PM PDT 24
Finished Jul 20 06:46:15 PM PDT 24
Peak memory 256632 kb
Host smart-9985cdf9-578c-4bee-9057-9b963fb8a4bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32814
05857 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_alert_accum.3281405857
Directory /workspace/27.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/27.alert_handler_esc_intr_timeout.1568297509
Short name T2
Test name
Test status
Simulation time 166664876 ps
CPU time 20.15 seconds
Started Jul 20 06:41:59 PM PDT 24
Finished Jul 20 06:42:20 PM PDT 24
Peak memory 248932 kb
Host smart-bbb1680a-6a6a-4dee-8839-9f854baf8476
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15682
97509 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_intr_timeout.1568297509
Directory /workspace/27.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_lpg.3405506475
Short name T595
Test name
Test status
Simulation time 171931786384 ps
CPU time 2262.34 seconds
Started Jul 20 06:42:00 PM PDT 24
Finished Jul 20 07:19:43 PM PDT 24
Peak memory 282880 kb
Host smart-4f4f951c-c296-47da-9ada-0446178fcb4c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405506475 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg.3405506475
Directory /workspace/27.alert_handler_lpg/latest

Test location /workspace/coverage/default/27.alert_handler_lpg_stub_clk.2503374288
Short name T9
Test name
Test status
Simulation time 57872498669 ps
CPU time 1036.67 seconds
Started Jul 20 06:42:00 PM PDT 24
Finished Jul 20 06:59:17 PM PDT 24
Peak memory 265652 kb
Host smart-fb80f215-b92a-4de8-9fec-e1535eef65a9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2503374288 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg_stub_clk.2503374288
Directory /workspace/27.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/27.alert_handler_ping_timeout.467405992
Short name T662
Test name
Test status
Simulation time 14387727928 ps
CPU time 594.97 seconds
Started Jul 20 06:42:09 PM PDT 24
Finished Jul 20 06:52:06 PM PDT 24
Peak memory 257296 kb
Host smart-6081c528-0c9a-4c6c-9d2e-e1a31967d96e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=467405992 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_ping_timeout.467405992
Directory /workspace/27.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_random_alerts.2374474040
Short name T207
Test name
Test status
Simulation time 423960235 ps
CPU time 26.98 seconds
Started Jul 20 06:42:13 PM PDT 24
Finished Jul 20 06:42:41 PM PDT 24
Peak memory 256196 kb
Host smart-078d59d7-5eb4-4ea2-81b0-76609ed17d9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23744
74040 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_alerts.2374474040
Directory /workspace/27.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/27.alert_handler_random_classes.1291667842
Short name T34
Test name
Test status
Simulation time 212616432 ps
CPU time 23.46 seconds
Started Jul 20 06:42:10 PM PDT 24
Finished Jul 20 06:42:34 PM PDT 24
Peak memory 248540 kb
Host smart-cb1eadcc-05f7-4407-a79e-ec20adc27b80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12916
67842 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_classes.1291667842
Directory /workspace/27.alert_handler_random_classes/latest

Test location /workspace/coverage/default/27.alert_handler_sig_int_fail.2576846940
Short name T598
Test name
Test status
Simulation time 986350741 ps
CPU time 32.84 seconds
Started Jul 20 06:42:08 PM PDT 24
Finished Jul 20 06:42:41 PM PDT 24
Peak memory 257156 kb
Host smart-e1bb25cd-df62-4182-af1a-847f879362ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25768
46940 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_sig_int_fail.2576846940
Directory /workspace/27.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/27.alert_handler_smoke.2274985865
Short name T456
Test name
Test status
Simulation time 4482906698 ps
CPU time 34.51 seconds
Started Jul 20 06:42:10 PM PDT 24
Finished Jul 20 06:42:46 PM PDT 24
Peak memory 256948 kb
Host smart-4698601a-b263-4fbb-bc8c-d447b158c10d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22749
85865 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_smoke.2274985865
Directory /workspace/27.alert_handler_smoke/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all.2523537805
Short name T607
Test name
Test status
Simulation time 16644145060 ps
CPU time 226.18 seconds
Started Jul 20 06:42:10 PM PDT 24
Finished Jul 20 06:45:57 PM PDT 24
Peak memory 257308 kb
Host smart-f4cb9d99-77cc-46b4-b771-404a2df9cc89
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523537805 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_ha
ndler_stress_all.2523537805
Directory /workspace/27.alert_handler_stress_all/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all_with_rand_reset.1219812458
Short name T108
Test name
Test status
Simulation time 106864847824 ps
CPU time 3210.1 seconds
Started Jul 20 06:41:59 PM PDT 24
Finished Jul 20 07:35:30 PM PDT 24
Peak memory 305864 kb
Host smart-3fdb3a88-6be4-4cf8-8d90-ca754e4d3827
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219812458 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.alert_handler_stress_all_with_rand_reset.1219812458
Directory /workspace/27.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.alert_handler_entropy.2212277402
Short name T677
Test name
Test status
Simulation time 90522852182 ps
CPU time 1521.25 seconds
Started Jul 20 06:42:11 PM PDT 24
Finished Jul 20 07:07:34 PM PDT 24
Peak memory 273716 kb
Host smart-4662a10b-5b6f-46e0-972f-e44665e40ce4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212277402 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_entropy.2212277402
Directory /workspace/28.alert_handler_entropy/latest

Test location /workspace/coverage/default/28.alert_handler_esc_alert_accum.2661054894
Short name T423
Test name
Test status
Simulation time 5355606269 ps
CPU time 167.86 seconds
Started Jul 20 06:42:11 PM PDT 24
Finished Jul 20 06:45:00 PM PDT 24
Peak memory 256732 kb
Host smart-93fdeedf-4244-47b4-b69f-1bbe57bccdea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26610
54894 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_alert_accum.2661054894
Directory /workspace/28.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/28.alert_handler_esc_intr_timeout.3550371077
Short name T521
Test name
Test status
Simulation time 850459329 ps
CPU time 64.19 seconds
Started Jul 20 06:42:13 PM PDT 24
Finished Jul 20 06:43:18 PM PDT 24
Peak memory 256728 kb
Host smart-c524323a-a771-42a9-ac3b-d2be6439c7b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35503
71077 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_intr_timeout.3550371077
Directory /workspace/28.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_lpg.3363847906
Short name T587
Test name
Test status
Simulation time 94656261727 ps
CPU time 2041 seconds
Started Jul 20 06:42:11 PM PDT 24
Finished Jul 20 07:16:13 PM PDT 24
Peak memory 281788 kb
Host smart-0a198799-b6ce-4d63-8f96-98eaab477d39
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363847906 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg.3363847906
Directory /workspace/28.alert_handler_lpg/latest

Test location /workspace/coverage/default/28.alert_handler_lpg_stub_clk.1292886181
Short name T10
Test name
Test status
Simulation time 47062917235 ps
CPU time 1311.19 seconds
Started Jul 20 06:42:12 PM PDT 24
Finished Jul 20 07:04:04 PM PDT 24
Peak memory 273032 kb
Host smart-c1d7a135-4486-4564-8816-6374a939d88f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292886181 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg_stub_clk.1292886181
Directory /workspace/28.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/28.alert_handler_ping_timeout.1051327080
Short name T326
Test name
Test status
Simulation time 14210775390 ps
CPU time 587.55 seconds
Started Jul 20 06:42:11 PM PDT 24
Finished Jul 20 06:52:00 PM PDT 24
Peak memory 256128 kb
Host smart-6ff40409-f4d3-40c3-9b27-a24d6881a257
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051327080 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_ping_timeout.1051327080
Directory /workspace/28.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_random_alerts.2209237164
Short name T470
Test name
Test status
Simulation time 227735953 ps
CPU time 9.66 seconds
Started Jul 20 06:42:09 PM PDT 24
Finished Jul 20 06:42:20 PM PDT 24
Peak memory 248928 kb
Host smart-e565e773-638e-42a8-b3d7-42d68fda2706
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22092
37164 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_alerts.2209237164
Directory /workspace/28.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/28.alert_handler_random_classes.1901029400
Short name T363
Test name
Test status
Simulation time 2324753703 ps
CPU time 67.4 seconds
Started Jul 20 06:42:11 PM PDT 24
Finished Jul 20 06:43:20 PM PDT 24
Peak memory 248780 kb
Host smart-df4555b9-4b91-46c7-bc9a-a40b3773e532
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19010
29400 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_classes.1901029400
Directory /workspace/28.alert_handler_random_classes/latest

Test location /workspace/coverage/default/28.alert_handler_sig_int_fail.3720249480
Short name T286
Test name
Test status
Simulation time 639380871 ps
CPU time 46.41 seconds
Started Jul 20 06:42:10 PM PDT 24
Finished Jul 20 06:42:57 PM PDT 24
Peak memory 248960 kb
Host smart-9cfedf6b-bae7-4067-a681-402f1154888f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37202
49480 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_sig_int_fail.3720249480
Directory /workspace/28.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/28.alert_handler_smoke.4059490960
Short name T486
Test name
Test status
Simulation time 1585141543 ps
CPU time 59.85 seconds
Started Jul 20 06:42:09 PM PDT 24
Finished Jul 20 06:43:09 PM PDT 24
Peak memory 257104 kb
Host smart-46b8f771-9405-4a53-af39-c69d5227d554
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40594
90960 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_smoke.4059490960
Directory /workspace/28.alert_handler_smoke/latest

Test location /workspace/coverage/default/29.alert_handler_entropy.3474552324
Short name T84
Test name
Test status
Simulation time 20854392304 ps
CPU time 1006.42 seconds
Started Jul 20 06:42:11 PM PDT 24
Finished Jul 20 06:58:59 PM PDT 24
Peak memory 289188 kb
Host smart-a0595194-2141-4e7e-8bea-21aa0d1c4c0e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3474552324 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_entropy.3474552324
Directory /workspace/29.alert_handler_entropy/latest

Test location /workspace/coverage/default/29.alert_handler_esc_alert_accum.3931080849
Short name T481
Test name
Test status
Simulation time 1297845409 ps
CPU time 76.51 seconds
Started Jul 20 06:42:12 PM PDT 24
Finished Jul 20 06:43:30 PM PDT 24
Peak memory 256704 kb
Host smart-1c10c1f8-9f5c-41ef-a2ab-af4e374ebfeb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39310
80849 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_alert_accum.3931080849
Directory /workspace/29.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/29.alert_handler_esc_intr_timeout.493448573
Short name T438
Test name
Test status
Simulation time 447633571 ps
CPU time 27.11 seconds
Started Jul 20 06:42:10 PM PDT 24
Finished Jul 20 06:42:38 PM PDT 24
Peak memory 248600 kb
Host smart-a328e0d3-5200-48ee-ab20-1f1f42779c45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49344
8573 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_intr_timeout.493448573
Directory /workspace/29.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_lpg_stub_clk.3194412547
Short name T110
Test name
Test status
Simulation time 73296046082 ps
CPU time 1452.45 seconds
Started Jul 20 06:42:12 PM PDT 24
Finished Jul 20 07:06:26 PM PDT 24
Peak memory 289988 kb
Host smart-d86f9c8d-1f9d-4822-a105-935657f413db
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3194412547 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg_stub_clk.3194412547
Directory /workspace/29.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/29.alert_handler_random_alerts.2458369898
Short name T425
Test name
Test status
Simulation time 5548904136 ps
CPU time 74.14 seconds
Started Jul 20 06:42:13 PM PDT 24
Finished Jul 20 06:43:29 PM PDT 24
Peak memory 257276 kb
Host smart-09d32de0-be4b-41bb-8c10-6581ad79faa1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24583
69898 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_alerts.2458369898
Directory /workspace/29.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/29.alert_handler_random_classes.3602277287
Short name T637
Test name
Test status
Simulation time 289924264 ps
CPU time 20.11 seconds
Started Jul 20 06:42:08 PM PDT 24
Finished Jul 20 06:42:28 PM PDT 24
Peak memory 248560 kb
Host smart-877d08ba-19a2-413e-b83f-1019315786c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36022
77287 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_classes.3602277287
Directory /workspace/29.alert_handler_random_classes/latest

Test location /workspace/coverage/default/29.alert_handler_sig_int_fail.2151202483
Short name T256
Test name
Test status
Simulation time 181855579 ps
CPU time 15.31 seconds
Started Jul 20 06:42:10 PM PDT 24
Finished Jul 20 06:42:26 PM PDT 24
Peak memory 248516 kb
Host smart-b0505870-663d-467d-8d49-7b7b1d444506
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21512
02483 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_sig_int_fail.2151202483
Directory /workspace/29.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/29.alert_handler_smoke.2717869640
Short name T387
Test name
Test status
Simulation time 1128085587 ps
CPU time 66.16 seconds
Started Jul 20 06:42:12 PM PDT 24
Finished Jul 20 06:43:19 PM PDT 24
Peak memory 257124 kb
Host smart-e7b27b07-23ae-4e04-8065-6ff4d6d77831
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27178
69640 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_smoke.2717869640
Directory /workspace/29.alert_handler_smoke/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all.4288493729
Short name T289
Test name
Test status
Simulation time 62033747106 ps
CPU time 3699.42 seconds
Started Jul 20 06:42:09 PM PDT 24
Finished Jul 20 07:43:49 PM PDT 24
Peak memory 306244 kb
Host smart-84ba5d23-4077-4869-becf-7520ae7102e0
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288493729 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_ha
ndler_stress_all.4288493729
Directory /workspace/29.alert_handler_stress_all/latest

Test location /workspace/coverage/default/3.alert_handler_alert_accum_saturation.1368398595
Short name T32
Test name
Test status
Simulation time 13690632 ps
CPU time 2.58 seconds
Started Jul 20 06:41:08 PM PDT 24
Finished Jul 20 06:41:11 PM PDT 24
Peak memory 249216 kb
Host smart-dbcb5c20-101a-4b77-9281-3a7f548c3708
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1368398595 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_alert_accum_saturation.1368398595
Directory /workspace/3.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/3.alert_handler_entropy.2979947646
Short name T522
Test name
Test status
Simulation time 18845537600 ps
CPU time 1180.09 seconds
Started Jul 20 06:41:08 PM PDT 24
Finished Jul 20 07:00:50 PM PDT 24
Peak memory 272932 kb
Host smart-763f4f0e-a8bf-4e6b-9515-b8ea5b04f4a0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979947646 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy.2979947646
Directory /workspace/3.alert_handler_entropy/latest

Test location /workspace/coverage/default/3.alert_handler_entropy_stress.1839855271
Short name T379
Test name
Test status
Simulation time 186735625 ps
CPU time 10.59 seconds
Started Jul 20 06:40:55 PM PDT 24
Finished Jul 20 06:41:07 PM PDT 24
Peak memory 248904 kb
Host smart-86a74cb9-5373-44ae-bb22-008a9b58ae58
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1839855271 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy_stress.1839855271
Directory /workspace/3.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/3.alert_handler_esc_alert_accum.3774844277
Short name T19
Test name
Test status
Simulation time 1045749291 ps
CPU time 114.43 seconds
Started Jul 20 06:41:21 PM PDT 24
Finished Jul 20 06:43:16 PM PDT 24
Peak memory 257136 kb
Host smart-e7701a11-35af-4006-b31d-bf365d3de0b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37748
44277 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_alert_accum.3774844277
Directory /workspace/3.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/3.alert_handler_esc_intr_timeout.2814102687
Short name T76
Test name
Test status
Simulation time 476689051 ps
CPU time 26.08 seconds
Started Jul 20 06:40:56 PM PDT 24
Finished Jul 20 06:41:23 PM PDT 24
Peak memory 257356 kb
Host smart-c997a296-6547-4df6-ae0f-654638752304
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28141
02687 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_intr_timeout.2814102687
Directory /workspace/3.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_lpg.1458146540
Short name T339
Test name
Test status
Simulation time 20117747506 ps
CPU time 983.95 seconds
Started Jul 20 06:40:59 PM PDT 24
Finished Jul 20 06:57:24 PM PDT 24
Peak memory 273604 kb
Host smart-0f61c47c-e2f4-4726-8a95-2823f97dfd3f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458146540 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg.1458146540
Directory /workspace/3.alert_handler_lpg/latest

Test location /workspace/coverage/default/3.alert_handler_lpg_stub_clk.129424555
Short name T343
Test name
Test status
Simulation time 36127232236 ps
CPU time 2187.26 seconds
Started Jul 20 06:41:13 PM PDT 24
Finished Jul 20 07:17:41 PM PDT 24
Peak memory 282732 kb
Host smart-4b6d0662-273f-410e-bd05-5add5e9500a3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129424555 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg_stub_clk.129424555
Directory /workspace/3.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/3.alert_handler_ping_timeout.3314098982
Short name T216
Test name
Test status
Simulation time 11907238780 ps
CPU time 474.7 seconds
Started Jul 20 06:41:18 PM PDT 24
Finished Jul 20 06:49:13 PM PDT 24
Peak memory 249108 kb
Host smart-98c476c0-a3e7-4c52-ae95-30d8d75dd9e1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314098982 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_ping_timeout.3314098982
Directory /workspace/3.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_random_alerts.3817821402
Short name T492
Test name
Test status
Simulation time 1104486680 ps
CPU time 6.06 seconds
Started Jul 20 06:40:56 PM PDT 24
Finished Jul 20 06:41:04 PM PDT 24
Peak memory 248996 kb
Host smart-4f058e01-3c12-45b8-bc9b-0b80cd669163
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38178
21402 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_alerts.3817821402
Directory /workspace/3.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/3.alert_handler_random_classes.2502042758
Short name T174
Test name
Test status
Simulation time 428751207 ps
CPU time 17.39 seconds
Started Jul 20 06:42:26 PM PDT 24
Finished Jul 20 06:42:44 PM PDT 24
Peak memory 249108 kb
Host smart-bd7bc443-751c-46f5-b806-ba78229497cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25020
42758 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_classes.2502042758
Directory /workspace/3.alert_handler_random_classes/latest

Test location /workspace/coverage/default/3.alert_handler_sig_int_fail.1563092917
Short name T257
Test name
Test status
Simulation time 548679168 ps
CPU time 16.67 seconds
Started Jul 20 06:41:08 PM PDT 24
Finished Jul 20 06:41:26 PM PDT 24
Peak memory 248548 kb
Host smart-6e3d99da-7334-44e0-bbf8-85862022d5a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15630
92917 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sig_int_fail.1563092917
Directory /workspace/3.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/3.alert_handler_smoke.122336224
Short name T483
Test name
Test status
Simulation time 333439847 ps
CPU time 22.32 seconds
Started Jul 20 06:40:56 PM PDT 24
Finished Jul 20 06:41:20 PM PDT 24
Peak memory 257132 kb
Host smart-79fe82f1-c4a5-4268-9845-2aecae4cfa8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12233
6224 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_smoke.122336224
Directory /workspace/3.alert_handler_smoke/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all.2670884215
Short name T38
Test name
Test status
Simulation time 51254151085 ps
CPU time 1478.31 seconds
Started Jul 20 06:40:58 PM PDT 24
Finished Jul 20 07:05:38 PM PDT 24
Peak memory 289380 kb
Host smart-ed95044d-20d4-4786-b017-c428c3d82ada
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670884215 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_han
dler_stress_all.2670884215
Directory /workspace/3.alert_handler_stress_all/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all_with_rand_reset.2555099722
Short name T253
Test name
Test status
Simulation time 59140367623 ps
CPU time 4030.97 seconds
Started Jul 20 06:42:15 PM PDT 24
Finished Jul 20 07:49:28 PM PDT 24
Peak memory 304616 kb
Host smart-2437483f-8250-464f-8882-c154be1d273b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555099722 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.alert_handler_stress_all_with_rand_reset.2555099722
Directory /workspace/3.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.alert_handler_entropy.1000993059
Short name T269
Test name
Test status
Simulation time 68169582818 ps
CPU time 707.93 seconds
Started Jul 20 06:42:18 PM PDT 24
Finished Jul 20 06:54:07 PM PDT 24
Peak memory 265440 kb
Host smart-50aebe34-d80c-4a21-953d-36fb000640b5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000993059 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_entropy.1000993059
Directory /workspace/30.alert_handler_entropy/latest

Test location /workspace/coverage/default/30.alert_handler_esc_alert_accum.1276440564
Short name T287
Test name
Test status
Simulation time 3107154016 ps
CPU time 196.89 seconds
Started Jul 20 06:42:13 PM PDT 24
Finished Jul 20 06:45:31 PM PDT 24
Peak memory 256780 kb
Host smart-9f5b2afe-d66d-4526-9f5a-268fe8caa0cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12764
40564 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_alert_accum.1276440564
Directory /workspace/30.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/30.alert_handler_esc_intr_timeout.2687943087
Short name T685
Test name
Test status
Simulation time 6639603908 ps
CPU time 49.72 seconds
Started Jul 20 06:42:13 PM PDT 24
Finished Jul 20 06:43:04 PM PDT 24
Peak memory 256344 kb
Host smart-92c50085-bc27-4a05-9072-90402aa4255a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26879
43087 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_intr_timeout.2687943087
Directory /workspace/30.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_lpg.2223047681
Short name T176
Test name
Test status
Simulation time 87454208958 ps
CPU time 2592.13 seconds
Started Jul 20 06:42:14 PM PDT 24
Finished Jul 20 07:25:27 PM PDT 24
Peak memory 289988 kb
Host smart-08b4883c-d134-4758-8038-b9efee104e76
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2223047681 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg.2223047681
Directory /workspace/30.alert_handler_lpg/latest

Test location /workspace/coverage/default/30.alert_handler_lpg_stub_clk.4249529319
Short name T601
Test name
Test status
Simulation time 45935385776 ps
CPU time 2663.14 seconds
Started Jul 20 06:42:13 PM PDT 24
Finished Jul 20 07:26:38 PM PDT 24
Peak memory 289808 kb
Host smart-26b01abe-1e7f-4ba5-96a7-031cc5ec7b57
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4249529319 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg_stub_clk.4249529319
Directory /workspace/30.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/30.alert_handler_random_alerts.1789970301
Short name T559
Test name
Test status
Simulation time 1280526616 ps
CPU time 76.35 seconds
Started Jul 20 06:42:12 PM PDT 24
Finished Jul 20 06:43:30 PM PDT 24
Peak memory 256640 kb
Host smart-1716c340-0485-412c-af8c-b5e035339807
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17899
70301 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_alerts.1789970301
Directory /workspace/30.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/30.alert_handler_random_classes.1536542701
Short name T552
Test name
Test status
Simulation time 1132562042 ps
CPU time 60.9 seconds
Started Jul 20 06:42:13 PM PDT 24
Finished Jul 20 06:43:16 PM PDT 24
Peak memory 256720 kb
Host smart-b8a0d946-07ce-4981-9661-8ae73cb32013
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15365
42701 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_classes.1536542701
Directory /workspace/30.alert_handler_random_classes/latest

Test location /workspace/coverage/default/30.alert_handler_sig_int_fail.78550814
Short name T221
Test name
Test status
Simulation time 990745539 ps
CPU time 60.15 seconds
Started Jul 20 06:42:17 PM PDT 24
Finished Jul 20 06:43:18 PM PDT 24
Peak memory 256952 kb
Host smart-9d839d3b-37cc-43a7-8efb-bce864418cfc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78550
814 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_sig_int_fail.78550814
Directory /workspace/30.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/30.alert_handler_smoke.843240828
Short name T638
Test name
Test status
Simulation time 554569061 ps
CPU time 37.72 seconds
Started Jul 20 06:42:18 PM PDT 24
Finished Jul 20 06:42:57 PM PDT 24
Peak memory 256240 kb
Host smart-fa192482-4783-4650-98ce-554049811b75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84324
0828 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_smoke.843240828
Directory /workspace/30.alert_handler_smoke/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all.724484595
Short name T88
Test name
Test status
Simulation time 55885101414 ps
CPU time 1732.51 seconds
Started Jul 20 06:42:11 PM PDT 24
Finished Jul 20 07:11:05 PM PDT 24
Peak memory 284276 kb
Host smart-88417f1a-9256-444f-9111-877ea19a90a9
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724484595 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_han
dler_stress_all.724484595
Directory /workspace/30.alert_handler_stress_all/latest

Test location /workspace/coverage/default/31.alert_handler_entropy.3616111952
Short name T663
Test name
Test status
Simulation time 13589470685 ps
CPU time 1270.42 seconds
Started Jul 20 06:42:18 PM PDT 24
Finished Jul 20 07:03:29 PM PDT 24
Peak memory 289680 kb
Host smart-165be4a9-be5d-482d-b5e6-5208e162cacc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3616111952 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_entropy.3616111952
Directory /workspace/31.alert_handler_entropy/latest

Test location /workspace/coverage/default/31.alert_handler_esc_alert_accum.926952000
Short name T476
Test name
Test status
Simulation time 304612104 ps
CPU time 20.7 seconds
Started Jul 20 06:42:18 PM PDT 24
Finished Jul 20 06:42:39 PM PDT 24
Peak memory 256312 kb
Host smart-b70f55e2-f42d-4a8c-acbd-6c69bcf6f68e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92695
2000 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_alert_accum.926952000
Directory /workspace/31.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/31.alert_handler_esc_intr_timeout.1237592691
Short name T464
Test name
Test status
Simulation time 1016925192 ps
CPU time 38.05 seconds
Started Jul 20 06:42:14 PM PDT 24
Finished Jul 20 06:42:53 PM PDT 24
Peak memory 248760 kb
Host smart-8becb124-e37d-4a77-b3e7-f1df581b6094
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12375
92691 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_intr_timeout.1237592691
Directory /workspace/31.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_lpg.2971056091
Short name T701
Test name
Test status
Simulation time 67989481515 ps
CPU time 1929.19 seconds
Started Jul 20 06:42:17 PM PDT 24
Finished Jul 20 07:14:26 PM PDT 24
Peak memory 272972 kb
Host smart-a41af658-1d57-4630-b3da-4173decee9fd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971056091 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg.2971056091
Directory /workspace/31.alert_handler_lpg/latest

Test location /workspace/coverage/default/31.alert_handler_lpg_stub_clk.3472525844
Short name T431
Test name
Test status
Simulation time 130909436170 ps
CPU time 1717 seconds
Started Jul 20 06:42:11 PM PDT 24
Finished Jul 20 07:10:49 PM PDT 24
Peak memory 273676 kb
Host smart-969a5713-2abb-4bcb-b1bb-cd7e7146beaf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472525844 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg_stub_clk.3472525844
Directory /workspace/31.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/31.alert_handler_ping_timeout.3058785503
Short name T309
Test name
Test status
Simulation time 2152005887 ps
CPU time 88.78 seconds
Started Jul 20 06:42:13 PM PDT 24
Finished Jul 20 06:43:43 PM PDT 24
Peak memory 249060 kb
Host smart-a91c9ada-e263-491d-9929-9694e2564761
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058785503 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_ping_timeout.3058785503
Directory /workspace/31.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_random_alerts.4059721297
Short name T653
Test name
Test status
Simulation time 1073328315 ps
CPU time 10.46 seconds
Started Jul 20 06:42:18 PM PDT 24
Finished Jul 20 06:42:29 PM PDT 24
Peak memory 248900 kb
Host smart-5671cdb2-98b5-4ee9-bf74-9979d1f809c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40597
21297 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_alerts.4059721297
Directory /workspace/31.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/31.alert_handler_random_classes.1506767516
Short name T508
Test name
Test status
Simulation time 1295358712 ps
CPU time 37.84 seconds
Started Jul 20 06:42:15 PM PDT 24
Finished Jul 20 06:42:54 PM PDT 24
Peak memory 249536 kb
Host smart-ecb6c1f4-0574-4a53-bf73-18d0250e8595
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15067
67516 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_classes.1506767516
Directory /workspace/31.alert_handler_random_classes/latest

Test location /workspace/coverage/default/31.alert_handler_sig_int_fail.3930754621
Short name T245
Test name
Test status
Simulation time 878158412 ps
CPU time 30.6 seconds
Started Jul 20 06:42:18 PM PDT 24
Finished Jul 20 06:42:49 PM PDT 24
Peak memory 249504 kb
Host smart-94b8ad7a-3c88-4eaa-a056-485448851a4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39307
54621 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_sig_int_fail.3930754621
Directory /workspace/31.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/31.alert_handler_smoke.1356657236
Short name T468
Test name
Test status
Simulation time 473881832 ps
CPU time 30.49 seconds
Started Jul 20 06:42:15 PM PDT 24
Finished Jul 20 06:42:46 PM PDT 24
Peak memory 257052 kb
Host smart-c9b79f05-b9df-4f78-aec1-34bfc2de59a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13566
57236 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_smoke.1356657236
Directory /workspace/31.alert_handler_smoke/latest

Test location /workspace/coverage/default/32.alert_handler_entropy.1024635578
Short name T106
Test name
Test status
Simulation time 174201402387 ps
CPU time 2958.46 seconds
Started Jul 20 06:42:23 PM PDT 24
Finished Jul 20 07:31:43 PM PDT 24
Peak memory 290032 kb
Host smart-843145dd-782c-4321-97b4-074adea3d618
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024635578 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_entropy.1024635578
Directory /workspace/32.alert_handler_entropy/latest

Test location /workspace/coverage/default/32.alert_handler_esc_alert_accum.810576127
Short name T430
Test name
Test status
Simulation time 1536383580 ps
CPU time 28.26 seconds
Started Jul 20 06:42:29 PM PDT 24
Finished Jul 20 06:42:59 PM PDT 24
Peak memory 256628 kb
Host smart-5e8e1190-6a85-49cb-b7b6-2117e625498d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81057
6127 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_alert_accum.810576127
Directory /workspace/32.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/32.alert_handler_esc_intr_timeout.1237837083
Short name T602
Test name
Test status
Simulation time 847901872 ps
CPU time 20 seconds
Started Jul 20 06:42:23 PM PDT 24
Finished Jul 20 06:42:44 PM PDT 24
Peak memory 256552 kb
Host smart-efe5b24c-8692-4932-9e66-5b93e8e547a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12378
37083 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_intr_timeout.1237837083
Directory /workspace/32.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_lpg_stub_clk.3028899865
Short name T87
Test name
Test status
Simulation time 11166234129 ps
CPU time 1083.27 seconds
Started Jul 20 06:42:21 PM PDT 24
Finished Jul 20 07:00:25 PM PDT 24
Peak memory 289464 kb
Host smart-f3bfe6ea-d49a-4b2c-909c-eedf1fe2f9ee
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028899865 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg_stub_clk.3028899865
Directory /workspace/32.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/32.alert_handler_ping_timeout.4248271113
Short name T614
Test name
Test status
Simulation time 21757029788 ps
CPU time 149.26 seconds
Started Jul 20 06:42:22 PM PDT 24
Finished Jul 20 06:44:52 PM PDT 24
Peak memory 249116 kb
Host smart-e368b130-a8d0-46ce-ab96-6b2828dd16ae
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248271113 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_ping_timeout.4248271113
Directory /workspace/32.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_random_alerts.3230057161
Short name T592
Test name
Test status
Simulation time 1377087487 ps
CPU time 72.8 seconds
Started Jul 20 06:42:22 PM PDT 24
Finished Jul 20 06:43:36 PM PDT 24
Peak memory 256252 kb
Host smart-31a29321-535e-4bf2-98a1-7d17adcfbd6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32300
57161 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_alerts.3230057161
Directory /workspace/32.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/32.alert_handler_random_classes.2644133414
Short name T20
Test name
Test status
Simulation time 129903609 ps
CPU time 19.59 seconds
Started Jul 20 06:42:22 PM PDT 24
Finished Jul 20 06:42:42 PM PDT 24
Peak memory 256720 kb
Host smart-808d2095-21d5-42cf-9b01-de584eaf33cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26441
33414 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_classes.2644133414
Directory /workspace/32.alert_handler_random_classes/latest

Test location /workspace/coverage/default/32.alert_handler_smoke.3803893055
Short name T528
Test name
Test status
Simulation time 624403861 ps
CPU time 44.01 seconds
Started Jul 20 06:42:13 PM PDT 24
Finished Jul 20 06:42:58 PM PDT 24
Peak memory 256716 kb
Host smart-31599852-0285-4ff5-95d4-cdb50399c4f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38038
93055 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_smoke.3803893055
Directory /workspace/32.alert_handler_smoke/latest

Test location /workspace/coverage/default/33.alert_handler_entropy.2698775072
Short name T657
Test name
Test status
Simulation time 28873675837 ps
CPU time 2030.5 seconds
Started Jul 20 06:42:20 PM PDT 24
Finished Jul 20 07:16:12 PM PDT 24
Peak memory 289872 kb
Host smart-d9aa4241-a3da-491d-948c-3087f2d742f2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2698775072 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_entropy.2698775072
Directory /workspace/33.alert_handler_entropy/latest

Test location /workspace/coverage/default/33.alert_handler_esc_alert_accum.1677490710
Short name T541
Test name
Test status
Simulation time 3186236255 ps
CPU time 23.55 seconds
Started Jul 20 06:42:24 PM PDT 24
Finished Jul 20 06:42:48 PM PDT 24
Peak memory 256524 kb
Host smart-fb33e4c7-15c9-4a19-ad04-8c3786dbf975
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16774
90710 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_alert_accum.1677490710
Directory /workspace/33.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/33.alert_handler_esc_intr_timeout.421392774
Short name T402
Test name
Test status
Simulation time 874439359 ps
CPU time 61.12 seconds
Started Jul 20 06:42:21 PM PDT 24
Finished Jul 20 06:43:23 PM PDT 24
Peak memory 257172 kb
Host smart-f985f3f4-3ee6-44af-8dc5-e663a9855395
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42139
2774 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_intr_timeout.421392774
Directory /workspace/33.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_lpg.2049625228
Short name T321
Test name
Test status
Simulation time 30899142448 ps
CPU time 1622.97 seconds
Started Jul 20 06:42:21 PM PDT 24
Finished Jul 20 07:09:25 PM PDT 24
Peak memory 265424 kb
Host smart-7f531430-0bea-4119-a117-de67088baf60
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049625228 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg.2049625228
Directory /workspace/33.alert_handler_lpg/latest

Test location /workspace/coverage/default/33.alert_handler_lpg_stub_clk.1022941508
Short name T629
Test name
Test status
Simulation time 28342746897 ps
CPU time 1622.16 seconds
Started Jul 20 06:42:23 PM PDT 24
Finished Jul 20 07:09:26 PM PDT 24
Peak memory 273356 kb
Host smart-5f4b677e-62fb-4027-97b6-c961da228ab1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1022941508 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg_stub_clk.1022941508
Directory /workspace/33.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/33.alert_handler_random_alerts.2870191796
Short name T414
Test name
Test status
Simulation time 1909778030 ps
CPU time 60.53 seconds
Started Jul 20 06:42:23 PM PDT 24
Finished Jul 20 06:43:24 PM PDT 24
Peak memory 255620 kb
Host smart-09eb0bff-12d5-4c18-8412-1e22bcb5d019
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28701
91796 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_alerts.2870191796
Directory /workspace/33.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/33.alert_handler_random_classes.868808983
Short name T40
Test name
Test status
Simulation time 2754979431 ps
CPU time 54.37 seconds
Started Jul 20 06:42:29 PM PDT 24
Finished Jul 20 06:43:25 PM PDT 24
Peak memory 257172 kb
Host smart-31c92b3b-29ab-404c-aea8-562b38170960
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86880
8983 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_classes.868808983
Directory /workspace/33.alert_handler_random_classes/latest

Test location /workspace/coverage/default/33.alert_handler_sig_int_fail.3371323185
Short name T422
Test name
Test status
Simulation time 994196407 ps
CPU time 31.06 seconds
Started Jul 20 06:42:23 PM PDT 24
Finished Jul 20 06:42:55 PM PDT 24
Peak memory 249028 kb
Host smart-e408428d-c70c-447c-b608-12a2e56d3dff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33713
23185 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_sig_int_fail.3371323185
Directory /workspace/33.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/33.alert_handler_smoke.2258625439
Short name T496
Test name
Test status
Simulation time 49266228 ps
CPU time 4.82 seconds
Started Jul 20 06:42:21 PM PDT 24
Finished Jul 20 06:42:27 PM PDT 24
Peak memory 251984 kb
Host smart-a4a4a4cd-e555-4c9c-a741-14559cc45288
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22586
25439 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_smoke.2258625439
Directory /workspace/33.alert_handler_smoke/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all.2573740562
Short name T50
Test name
Test status
Simulation time 130527664195 ps
CPU time 1114.02 seconds
Started Jul 20 06:42:22 PM PDT 24
Finished Jul 20 07:00:57 PM PDT 24
Peak memory 289496 kb
Host smart-987d737c-146c-4063-8744-46c98777b3fa
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573740562 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_ha
ndler_stress_all.2573740562
Directory /workspace/33.alert_handler_stress_all/latest

Test location /workspace/coverage/default/34.alert_handler_entropy.1443285107
Short name T649
Test name
Test status
Simulation time 37857453224 ps
CPU time 1170.72 seconds
Started Jul 20 06:42:21 PM PDT 24
Finished Jul 20 07:01:52 PM PDT 24
Peak memory 272860 kb
Host smart-425084ee-a995-41b4-a183-e118668b827c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443285107 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_entropy.1443285107
Directory /workspace/34.alert_handler_entropy/latest

Test location /workspace/coverage/default/34.alert_handler_esc_alert_accum.2790116859
Short name T548
Test name
Test status
Simulation time 5011794756 ps
CPU time 202.34 seconds
Started Jul 20 06:42:20 PM PDT 24
Finished Jul 20 06:45:44 PM PDT 24
Peak memory 251196 kb
Host smart-ecafc0f3-4432-4c5a-b471-8f76981d33f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27901
16859 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_alert_accum.2790116859
Directory /workspace/34.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/34.alert_handler_esc_intr_timeout.3913612227
Short name T504
Test name
Test status
Simulation time 2864568464 ps
CPU time 57.68 seconds
Started Jul 20 06:42:22 PM PDT 24
Finished Jul 20 06:43:20 PM PDT 24
Peak memory 256944 kb
Host smart-16ccdbed-cf4b-498e-b7f2-363ebba13afd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39136
12227 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_intr_timeout.3913612227
Directory /workspace/34.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_lpg.3323753524
Short name T328
Test name
Test status
Simulation time 221744161389 ps
CPU time 3175.4 seconds
Started Jul 20 06:42:22 PM PDT 24
Finished Jul 20 07:35:18 PM PDT 24
Peak memory 288572 kb
Host smart-6bfd965f-bd79-44ea-8403-d606ecc79948
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323753524 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg.3323753524
Directory /workspace/34.alert_handler_lpg/latest

Test location /workspace/coverage/default/34.alert_handler_lpg_stub_clk.691600754
Short name T577
Test name
Test status
Simulation time 77804791909 ps
CPU time 1031.8 seconds
Started Jul 20 06:42:22 PM PDT 24
Finished Jul 20 06:59:35 PM PDT 24
Peak memory 272700 kb
Host smart-ffce3dae-667c-49f1-a93b-7817d299da3c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691600754 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg_stub_clk.691600754
Directory /workspace/34.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/34.alert_handler_random_alerts.1035000914
Short name T562
Test name
Test status
Simulation time 2144236547 ps
CPU time 19.69 seconds
Started Jul 20 06:42:22 PM PDT 24
Finished Jul 20 06:42:43 PM PDT 24
Peak memory 255312 kb
Host smart-d3cd3bfe-efee-418b-883e-45eba59d370a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10350
00914 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_alerts.1035000914
Directory /workspace/34.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/34.alert_handler_random_classes.740675467
Short name T3
Test name
Test status
Simulation time 187233488 ps
CPU time 12.16 seconds
Started Jul 20 06:42:23 PM PDT 24
Finished Jul 20 06:42:36 PM PDT 24
Peak memory 248508 kb
Host smart-9b4aeeda-a951-4602-8351-280aa8271980
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74067
5467 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_classes.740675467
Directory /workspace/34.alert_handler_random_classes/latest

Test location /workspace/coverage/default/34.alert_handler_sig_int_fail.768763269
Short name T578
Test name
Test status
Simulation time 674075941 ps
CPU time 41.5 seconds
Started Jul 20 06:42:22 PM PDT 24
Finished Jul 20 06:43:05 PM PDT 24
Peak memory 249992 kb
Host smart-c329cfc8-b7d8-4641-a9b5-c9e883d24e79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76876
3269 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_sig_int_fail.768763269
Directory /workspace/34.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/34.alert_handler_smoke.205944287
Short name T448
Test name
Test status
Simulation time 3869225498 ps
CPU time 52.14 seconds
Started Jul 20 06:42:29 PM PDT 24
Finished Jul 20 06:43:23 PM PDT 24
Peak memory 249288 kb
Host smart-7433f8dd-2512-47c3-a1a0-62ea350649c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20594
4287 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_smoke.205944287
Directory /workspace/34.alert_handler_smoke/latest

Test location /workspace/coverage/default/35.alert_handler_entropy.1558965005
Short name T547
Test name
Test status
Simulation time 63012584344 ps
CPU time 2398.22 seconds
Started Jul 20 06:42:27 PM PDT 24
Finished Jul 20 07:22:26 PM PDT 24
Peak memory 289752 kb
Host smart-38fbdbfa-c36f-4ddd-89c9-7f98c420a505
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558965005 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_entropy.1558965005
Directory /workspace/35.alert_handler_entropy/latest

Test location /workspace/coverage/default/35.alert_handler_esc_alert_accum.2329735464
Short name T230
Test name
Test status
Simulation time 1503784252 ps
CPU time 75.97 seconds
Started Jul 20 06:42:30 PM PDT 24
Finished Jul 20 06:43:47 PM PDT 24
Peak memory 257192 kb
Host smart-4fda86f5-13ac-49e3-8d87-f8412fea5720
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23297
35464 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_alert_accum.2329735464
Directory /workspace/35.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/35.alert_handler_esc_intr_timeout.2764684394
Short name T605
Test name
Test status
Simulation time 1162051090 ps
CPU time 37.52 seconds
Started Jul 20 06:42:30 PM PDT 24
Finished Jul 20 06:43:08 PM PDT 24
Peak memory 256376 kb
Host smart-255af0c8-c2f1-4e31-af83-d172e42ce580
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27646
84394 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_intr_timeout.2764684394
Directory /workspace/35.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_lpg_stub_clk.660683912
Short name T395
Test name
Test status
Simulation time 14582309778 ps
CPU time 1371.5 seconds
Started Jul 20 06:42:29 PM PDT 24
Finished Jul 20 07:05:21 PM PDT 24
Peak memory 283512 kb
Host smart-30742c9d-0056-4816-87af-b6a7b554604a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660683912 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg_stub_clk.660683912
Directory /workspace/35.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/35.alert_handler_ping_timeout.3714771005
Short name T619
Test name
Test status
Simulation time 21234647021 ps
CPU time 362.83 seconds
Started Jul 20 06:42:28 PM PDT 24
Finished Jul 20 06:48:32 PM PDT 24
Peak memory 257244 kb
Host smart-e3ca1754-022b-4e9f-b28d-a90d31793259
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714771005 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_ping_timeout.3714771005
Directory /workspace/35.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_random_alerts.747925686
Short name T107
Test name
Test status
Simulation time 2489334567 ps
CPU time 34.24 seconds
Started Jul 20 06:42:30 PM PDT 24
Finished Jul 20 06:43:05 PM PDT 24
Peak memory 256644 kb
Host smart-cf22124f-3748-4c13-a0c0-6d2248657c78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74792
5686 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_alerts.747925686
Directory /workspace/35.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/35.alert_handler_random_classes.2205071724
Short name T668
Test name
Test status
Simulation time 1069586820 ps
CPU time 20.74 seconds
Started Jul 20 06:42:27 PM PDT 24
Finished Jul 20 06:42:49 PM PDT 24
Peak memory 256320 kb
Host smart-abafd91d-9c86-4bd8-98ad-1acbbe6ca9e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22050
71724 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_classes.2205071724
Directory /workspace/35.alert_handler_random_classes/latest

Test location /workspace/coverage/default/35.alert_handler_sig_int_fail.1958068728
Short name T250
Test name
Test status
Simulation time 723365087 ps
CPU time 25.66 seconds
Started Jul 20 06:42:31 PM PDT 24
Finished Jul 20 06:42:57 PM PDT 24
Peak memory 248560 kb
Host smart-455ccc2a-60c1-46a6-9707-e589a6092ace
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19580
68728 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_sig_int_fail.1958068728
Directory /workspace/35.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/35.alert_handler_smoke.2813761910
Short name T173
Test name
Test status
Simulation time 1239848033 ps
CPU time 36.34 seconds
Started Jul 20 06:42:29 PM PDT 24
Finished Jul 20 06:43:07 PM PDT 24
Peak memory 257144 kb
Host smart-a13a9ca9-4e22-49c8-8c20-dded5c3f4e72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28137
61910 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_smoke.2813761910
Directory /workspace/35.alert_handler_smoke/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all.2923284522
Short name T651
Test name
Test status
Simulation time 18357165669 ps
CPU time 1056.3 seconds
Started Jul 20 06:42:30 PM PDT 24
Finished Jul 20 07:00:08 PM PDT 24
Peak memory 289744 kb
Host smart-93b60e81-3a67-4889-803a-42877b42960b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923284522 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_ha
ndler_stress_all.2923284522
Directory /workspace/35.alert_handler_stress_all/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all_with_rand_reset.161137864
Short name T695
Test name
Test status
Simulation time 1193604622170 ps
CPU time 9302.38 seconds
Started Jul 20 06:42:28 PM PDT 24
Finished Jul 20 09:17:32 PM PDT 24
Peak memory 370324 kb
Host smart-a647f34f-7085-4a54-aa89-3281f5453600
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161137864 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 35.alert_handler_stress_all_with_rand_reset.161137864
Directory /workspace/35.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.alert_handler_entropy.4222004697
Short name T567
Test name
Test status
Simulation time 8350506320 ps
CPU time 955.43 seconds
Started Jul 20 06:42:28 PM PDT 24
Finished Jul 20 06:58:24 PM PDT 24
Peak memory 273352 kb
Host smart-45d699c1-b401-4a31-a94e-ba68c3a194a1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222004697 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_entropy.4222004697
Directory /workspace/36.alert_handler_entropy/latest

Test location /workspace/coverage/default/36.alert_handler_esc_alert_accum.3622401016
Short name T396
Test name
Test status
Simulation time 939384944 ps
CPU time 28.05 seconds
Started Jul 20 06:42:30 PM PDT 24
Finished Jul 20 06:42:59 PM PDT 24
Peak memory 256640 kb
Host smart-682aeb4b-bb31-4542-9a1c-82d7bf2275a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36224
01016 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_alert_accum.3622401016
Directory /workspace/36.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/36.alert_handler_esc_intr_timeout.47165310
Short name T617
Test name
Test status
Simulation time 435522296 ps
CPU time 25.2 seconds
Started Jul 20 06:42:29 PM PDT 24
Finished Jul 20 06:42:55 PM PDT 24
Peak memory 256276 kb
Host smart-00498e4b-c07e-4210-860b-015d6a79c72d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47165
310 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_intr_timeout.47165310
Directory /workspace/36.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_lpg.3813923011
Short name T301
Test name
Test status
Simulation time 34570355994 ps
CPU time 1501.95 seconds
Started Jul 20 06:42:30 PM PDT 24
Finished Jul 20 07:07:33 PM PDT 24
Peak memory 289412 kb
Host smart-24e46893-ec9e-4ff1-9858-9238aa43988e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813923011 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg.3813923011
Directory /workspace/36.alert_handler_lpg/latest

Test location /workspace/coverage/default/36.alert_handler_lpg_stub_clk.3986962031
Short name T624
Test name
Test status
Simulation time 25396677233 ps
CPU time 1133.68 seconds
Started Jul 20 06:42:32 PM PDT 24
Finished Jul 20 07:01:26 PM PDT 24
Peak memory 289844 kb
Host smart-68ca75dd-ff67-4607-bfc7-7735f29c8361
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986962031 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg_stub_clk.3986962031
Directory /workspace/36.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/36.alert_handler_ping_timeout.1820538802
Short name T628
Test name
Test status
Simulation time 11115922156 ps
CPU time 486.71 seconds
Started Jul 20 06:42:31 PM PDT 24
Finished Jul 20 06:50:38 PM PDT 24
Peak memory 249148 kb
Host smart-5047d7f5-1b1f-4058-b885-f6a463bdd7ad
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820538802 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_ping_timeout.1820538802
Directory /workspace/36.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_random_alerts.51189205
Short name T484
Test name
Test status
Simulation time 3487944423 ps
CPU time 57.83 seconds
Started Jul 20 06:42:29 PM PDT 24
Finished Jul 20 06:43:27 PM PDT 24
Peak memory 248920 kb
Host smart-e1200bf1-9d85-4241-aba1-16ca457b941b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51189
205 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_alerts.51189205
Directory /workspace/36.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/36.alert_handler_random_classes.3561230795
Short name T450
Test name
Test status
Simulation time 8304202014 ps
CPU time 45.35 seconds
Started Jul 20 06:42:29 PM PDT 24
Finished Jul 20 06:43:15 PM PDT 24
Peak memory 256724 kb
Host smart-48030000-3ed0-402b-8760-7e19f25ce726
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35612
30795 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_classes.3561230795
Directory /workspace/36.alert_handler_random_classes/latest

Test location /workspace/coverage/default/36.alert_handler_sig_int_fail.1774307726
Short name T39
Test name
Test status
Simulation time 128973410 ps
CPU time 21.98 seconds
Started Jul 20 06:42:28 PM PDT 24
Finished Jul 20 06:42:50 PM PDT 24
Peak memory 257096 kb
Host smart-0730fdb3-05c4-4857-aa2e-5505135e2ac8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17743
07726 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_sig_int_fail.1774307726
Directory /workspace/36.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/36.alert_handler_smoke.3283373198
Short name T211
Test name
Test status
Simulation time 607654424 ps
CPU time 38.71 seconds
Started Jul 20 06:42:31 PM PDT 24
Finished Jul 20 06:43:10 PM PDT 24
Peak memory 257144 kb
Host smart-9af0856f-7e93-4c6b-97bd-03cf20a1ca04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32833
73198 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_smoke.3283373198
Directory /workspace/36.alert_handler_smoke/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all.4056612259
Short name T228
Test name
Test status
Simulation time 878139212 ps
CPU time 36.05 seconds
Started Jul 20 06:42:28 PM PDT 24
Finished Jul 20 06:43:05 PM PDT 24
Peak memory 257176 kb
Host smart-fe64427e-a879-478b-bfd9-82ae4e39ede4
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056612259 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_ha
ndler_stress_all.4056612259
Directory /workspace/36.alert_handler_stress_all/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all_with_rand_reset.1420025326
Short name T703
Test name
Test status
Simulation time 103537210110 ps
CPU time 9198.78 seconds
Started Jul 20 06:42:29 PM PDT 24
Finished Jul 20 09:15:50 PM PDT 24
Peak memory 395508 kb
Host smart-73e15548-61ca-48a1-a5dc-87860e63ec9d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420025326 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 36.alert_handler_stress_all_with_rand_reset.1420025326
Directory /workspace/36.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.alert_handler_entropy.284284996
Short name T600
Test name
Test status
Simulation time 556365596633 ps
CPU time 1847.07 seconds
Started Jul 20 06:42:36 PM PDT 24
Finished Jul 20 07:13:24 PM PDT 24
Peak memory 273536 kb
Host smart-571a797c-2012-4063-9285-06d0f14c5e36
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284284996 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_entropy.284284996
Directory /workspace/37.alert_handler_entropy/latest

Test location /workspace/coverage/default/37.alert_handler_esc_alert_accum.2711517219
Short name T615
Test name
Test status
Simulation time 913863901 ps
CPU time 80.75 seconds
Started Jul 20 06:42:34 PM PDT 24
Finished Jul 20 06:43:55 PM PDT 24
Peak memory 256796 kb
Host smart-6d6e02e5-9b1a-4f2f-9759-872e8752921d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27115
17219 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_alert_accum.2711517219
Directory /workspace/37.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/37.alert_handler_esc_intr_timeout.1155564346
Short name T6
Test name
Test status
Simulation time 853943697 ps
CPU time 45.03 seconds
Started Jul 20 06:42:34 PM PDT 24
Finished Jul 20 06:43:19 PM PDT 24
Peak memory 256204 kb
Host smart-a03ce830-6833-451c-becf-3ae3df800f30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11555
64346 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_intr_timeout.1155564346
Directory /workspace/37.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_lpg_stub_clk.4291689686
Short name T542
Test name
Test status
Simulation time 9183804519 ps
CPU time 825.09 seconds
Started Jul 20 06:42:33 PM PDT 24
Finished Jul 20 06:56:18 PM PDT 24
Peak memory 273492 kb
Host smart-38433949-0296-4976-8090-fbc25ce043a9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291689686 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg_stub_clk.4291689686
Directory /workspace/37.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/37.alert_handler_ping_timeout.2139362100
Short name T553
Test name
Test status
Simulation time 9080556054 ps
CPU time 72.4 seconds
Started Jul 20 06:42:36 PM PDT 24
Finished Jul 20 06:43:49 PM PDT 24
Peak memory 256216 kb
Host smart-897492b9-cc0b-429b-989d-4429ca0f9abe
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2139362100 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_ping_timeout.2139362100
Directory /workspace/37.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_random_alerts.1089766684
Short name T62
Test name
Test status
Simulation time 11735265952 ps
CPU time 67.53 seconds
Started Jul 20 06:42:37 PM PDT 24
Finished Jul 20 06:43:45 PM PDT 24
Peak memory 256900 kb
Host smart-c290f1d4-47a8-4fac-b41a-95e9725ea603
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10897
66684 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_alerts.1089766684
Directory /workspace/37.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/37.alert_handler_random_classes.117884736
Short name T86
Test name
Test status
Simulation time 1463870806 ps
CPU time 23.07 seconds
Started Jul 20 06:42:34 PM PDT 24
Finished Jul 20 06:42:58 PM PDT 24
Peak memory 256264 kb
Host smart-285792df-bad6-4001-97c2-6d13afe6dc6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11788
4736 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_classes.117884736
Directory /workspace/37.alert_handler_random_classes/latest

Test location /workspace/coverage/default/37.alert_handler_sig_int_fail.3163034495
Short name T260
Test name
Test status
Simulation time 1419718026 ps
CPU time 16.89 seconds
Started Jul 20 06:42:37 PM PDT 24
Finished Jul 20 06:42:54 PM PDT 24
Peak memory 256536 kb
Host smart-f1842298-aaa8-445d-b77d-7ee4e78c644a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31630
34495 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_sig_int_fail.3163034495
Directory /workspace/37.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/37.alert_handler_smoke.1759318196
Short name T455
Test name
Test status
Simulation time 376714259 ps
CPU time 36.59 seconds
Started Jul 20 06:42:30 PM PDT 24
Finished Jul 20 06:43:08 PM PDT 24
Peak memory 257000 kb
Host smart-f2f92322-4a66-493c-8646-2c85c0438c1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17593
18196 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_smoke.1759318196
Directory /workspace/37.alert_handler_smoke/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all.2140692165
Short name T626
Test name
Test status
Simulation time 209328766630 ps
CPU time 3227.12 seconds
Started Jul 20 06:42:34 PM PDT 24
Finished Jul 20 07:36:23 PM PDT 24
Peak memory 290012 kb
Host smart-b89a2a3f-8d01-472a-98db-1a6e46d8f14b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140692165 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_ha
ndler_stress_all.2140692165
Directory /workspace/37.alert_handler_stress_all/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all_with_rand_reset.4077814975
Short name T99
Test name
Test status
Simulation time 123095857457 ps
CPU time 4013.12 seconds
Started Jul 20 06:42:34 PM PDT 24
Finished Jul 20 07:49:29 PM PDT 24
Peak memory 322312 kb
Host smart-92e9253a-ec56-4f78-9ec5-9d762c15925a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077814975 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 37.alert_handler_stress_all_with_rand_reset.4077814975
Directory /workspace/37.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.alert_handler_entropy.1882143723
Short name T561
Test name
Test status
Simulation time 47278144883 ps
CPU time 1894.67 seconds
Started Jul 20 06:42:34 PM PDT 24
Finished Jul 20 07:14:10 PM PDT 24
Peak memory 286756 kb
Host smart-087d95ae-c9fd-48d7-8af3-e86a28dbf303
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882143723 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_entropy.1882143723
Directory /workspace/38.alert_handler_entropy/latest

Test location /workspace/coverage/default/38.alert_handler_esc_alert_accum.1485294643
Short name T460
Test name
Test status
Simulation time 11757147726 ps
CPU time 343.85 seconds
Started Jul 20 06:42:37 PM PDT 24
Finished Jul 20 06:48:21 PM PDT 24
Peak memory 257300 kb
Host smart-52f5deb1-ebef-4f4c-9ab8-d3b4988b5caa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14852
94643 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_alert_accum.1485294643
Directory /workspace/38.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/38.alert_handler_esc_intr_timeout.707768206
Short name T489
Test name
Test status
Simulation time 4362025517 ps
CPU time 21.13 seconds
Started Jul 20 06:42:36 PM PDT 24
Finished Jul 20 06:42:58 PM PDT 24
Peak memory 256472 kb
Host smart-4f19e9b6-ceaf-4d29-b06d-c7ebe9a77aef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70776
8206 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_intr_timeout.707768206
Directory /workspace/38.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_lpg_stub_clk.4289820440
Short name T467
Test name
Test status
Simulation time 65649420986 ps
CPU time 1238.11 seconds
Started Jul 20 06:42:35 PM PDT 24
Finished Jul 20 07:03:14 PM PDT 24
Peak memory 286428 kb
Host smart-b2613db4-63d8-4ead-8084-a959a45bc669
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289820440 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg_stub_clk.4289820440
Directory /workspace/38.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/38.alert_handler_ping_timeout.3483630038
Short name T57
Test name
Test status
Simulation time 9528704702 ps
CPU time 399.48 seconds
Started Jul 20 06:42:35 PM PDT 24
Finished Jul 20 06:49:15 PM PDT 24
Peak memory 248880 kb
Host smart-219aa8b9-182a-49eb-adc2-f0f1091e6985
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483630038 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_ping_timeout.3483630038
Directory /workspace/38.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_random_alerts.1095070386
Short name T636
Test name
Test status
Simulation time 349505663 ps
CPU time 36.67 seconds
Started Jul 20 06:42:36 PM PDT 24
Finished Jul 20 06:43:13 PM PDT 24
Peak memory 248944 kb
Host smart-ed5d8c4b-e102-4d05-878f-a50aa2db21bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10950
70386 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_alerts.1095070386
Directory /workspace/38.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/38.alert_handler_random_classes.1531996719
Short name T646
Test name
Test status
Simulation time 324359187 ps
CPU time 23.56 seconds
Started Jul 20 06:42:34 PM PDT 24
Finished Jul 20 06:42:58 PM PDT 24
Peak memory 256144 kb
Host smart-10699545-a868-432c-8d10-3a3a4e66f371
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15319
96719 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_classes.1531996719
Directory /workspace/38.alert_handler_random_classes/latest

Test location /workspace/coverage/default/38.alert_handler_sig_int_fail.1101174172
Short name T526
Test name
Test status
Simulation time 934017233 ps
CPU time 55.11 seconds
Started Jul 20 06:42:37 PM PDT 24
Finished Jul 20 06:43:33 PM PDT 24
Peak memory 256540 kb
Host smart-7f81654e-fbcf-46bf-afa6-2652729dd9e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11011
74172 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_sig_int_fail.1101174172
Directory /workspace/38.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/38.alert_handler_smoke.2023515653
Short name T432
Test name
Test status
Simulation time 1422926619 ps
CPU time 42.85 seconds
Started Jul 20 06:42:35 PM PDT 24
Finished Jul 20 06:43:19 PM PDT 24
Peak memory 249172 kb
Host smart-9f73b3c8-d92f-4524-b66e-c5a270433bd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20235
15653 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_smoke.2023515653
Directory /workspace/38.alert_handler_smoke/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all.2939768294
Short name T475
Test name
Test status
Simulation time 93761538042 ps
CPU time 3161.88 seconds
Started Jul 20 06:42:42 PM PDT 24
Finished Jul 20 07:35:24 PM PDT 24
Peak memory 289544 kb
Host smart-4f3212d3-b61a-4b92-ae17-8b0f282d15c5
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939768294 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_ha
ndler_stress_all.2939768294
Directory /workspace/38.alert_handler_stress_all/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all_with_rand_reset.2994833039
Short name T238
Test name
Test status
Simulation time 10741143397 ps
CPU time 1068.71 seconds
Started Jul 20 06:42:42 PM PDT 24
Finished Jul 20 07:00:32 PM PDT 24
Peak memory 290140 kb
Host smart-9d1abe3c-fac1-42dd-8658-30f2c96d6f7b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994833039 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 38.alert_handler_stress_all_with_rand_reset.2994833039
Directory /workspace/38.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.alert_handler_entropy.371984625
Short name T17
Test name
Test status
Simulation time 49907240592 ps
CPU time 1151.33 seconds
Started Jul 20 06:42:43 PM PDT 24
Finished Jul 20 07:01:55 PM PDT 24
Peak memory 288980 kb
Host smart-fc8d12dd-a0cc-48d3-806f-14fae29d8ef1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371984625 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_entropy.371984625
Directory /workspace/39.alert_handler_entropy/latest

Test location /workspace/coverage/default/39.alert_handler_esc_alert_accum.1966643450
Short name T376
Test name
Test status
Simulation time 4338785253 ps
CPU time 88.19 seconds
Started Jul 20 06:42:42 PM PDT 24
Finished Jul 20 06:44:10 PM PDT 24
Peak memory 256568 kb
Host smart-0e6a611f-9834-4406-bebf-f134e6fcd474
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19666
43450 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_alert_accum.1966643450
Directory /workspace/39.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/39.alert_handler_esc_intr_timeout.1233354424
Short name T596
Test name
Test status
Simulation time 19860304 ps
CPU time 3.04 seconds
Started Jul 20 06:42:41 PM PDT 24
Finished Jul 20 06:42:44 PM PDT 24
Peak memory 240356 kb
Host smart-0ed5d4d7-b993-487e-8a5e-887d890062ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12333
54424 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_intr_timeout.1233354424
Directory /workspace/39.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_lpg.2470786970
Short name T320
Test name
Test status
Simulation time 24331808924 ps
CPU time 1240.26 seconds
Started Jul 20 06:42:41 PM PDT 24
Finished Jul 20 07:03:21 PM PDT 24
Peak memory 273660 kb
Host smart-ccd9ebf1-9724-4cb1-bd43-d6b590aa9e85
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2470786970 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg.2470786970
Directory /workspace/39.alert_handler_lpg/latest

Test location /workspace/coverage/default/39.alert_handler_lpg_stub_clk.1389156718
Short name T440
Test name
Test status
Simulation time 195746327217 ps
CPU time 3035.95 seconds
Started Jul 20 06:42:42 PM PDT 24
Finished Jul 20 07:33:20 PM PDT 24
Peak memory 287948 kb
Host smart-1970ee9f-5765-4c24-8faa-53abeecc22be
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389156718 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg_stub_clk.1389156718
Directory /workspace/39.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/39.alert_handler_ping_timeout.1983762770
Short name T317
Test name
Test status
Simulation time 3490949430 ps
CPU time 103.76 seconds
Started Jul 20 06:42:43 PM PDT 24
Finished Jul 20 06:44:28 PM PDT 24
Peak memory 247796 kb
Host smart-6c211108-2ce2-4205-8989-d407a38ddeb2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983762770 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_ping_timeout.1983762770
Directory /workspace/39.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_random_alerts.486865680
Short name T536
Test name
Test status
Simulation time 1381709614 ps
CPU time 35.91 seconds
Started Jul 20 06:42:44 PM PDT 24
Finished Jul 20 06:43:21 PM PDT 24
Peak memory 256532 kb
Host smart-39de364e-7bf8-413d-abb0-b7bbe769979d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48686
5680 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_alerts.486865680
Directory /workspace/39.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/39.alert_handler_random_classes.2520545050
Short name T295
Test name
Test status
Simulation time 611844651 ps
CPU time 21.56 seconds
Started Jul 20 06:42:43 PM PDT 24
Finished Jul 20 06:43:06 PM PDT 24
Peak memory 248360 kb
Host smart-9516b287-0258-40cf-85ba-64b3244b98c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25205
45050 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_classes.2520545050
Directory /workspace/39.alert_handler_random_classes/latest

Test location /workspace/coverage/default/39.alert_handler_sig_int_fail.2837775984
Short name T72
Test name
Test status
Simulation time 678155925 ps
CPU time 56.55 seconds
Started Jul 20 06:42:43 PM PDT 24
Finished Jul 20 06:43:41 PM PDT 24
Peak memory 256624 kb
Host smart-a11dbaa2-1209-405a-b607-0a26a3c9099f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28377
75984 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_sig_int_fail.2837775984
Directory /workspace/39.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/39.alert_handler_smoke.1890027257
Short name T449
Test name
Test status
Simulation time 330980709 ps
CPU time 7.88 seconds
Started Jul 20 06:42:43 PM PDT 24
Finished Jul 20 06:42:52 PM PDT 24
Peak memory 249444 kb
Host smart-7a084c99-bac5-4ece-a058-5025ce388627
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18900
27257 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_smoke.1890027257
Directory /workspace/39.alert_handler_smoke/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all.1742163216
Short name T247
Test name
Test status
Simulation time 182349678750 ps
CPU time 1507.62 seconds
Started Jul 20 06:42:41 PM PDT 24
Finished Jul 20 07:07:49 PM PDT 24
Peak memory 289708 kb
Host smart-b9109cac-40c5-4c44-8266-59b73bf43f95
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742163216 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_ha
ndler_stress_all.1742163216
Directory /workspace/39.alert_handler_stress_all/latest

Test location /workspace/coverage/default/4.alert_handler_alert_accum_saturation.4248125359
Short name T196
Test name
Test status
Simulation time 17542903 ps
CPU time 2.78 seconds
Started Jul 20 06:41:18 PM PDT 24
Finished Jul 20 06:41:21 PM PDT 24
Peak memory 249200 kb
Host smart-0f52cfe8-6a81-46a3-81c7-43c6dddbed44
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4248125359 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_alert_accum_saturation.4248125359
Directory /workspace/4.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/4.alert_handler_entropy.554554180
Short name T574
Test name
Test status
Simulation time 34183027391 ps
CPU time 1900.35 seconds
Started Jul 20 06:41:11 PM PDT 24
Finished Jul 20 07:12:53 PM PDT 24
Peak memory 273492 kb
Host smart-d6f3fe79-17d7-4a46-b011-ba66e3456fd8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554554180 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy.554554180
Directory /workspace/4.alert_handler_entropy/latest

Test location /workspace/coverage/default/4.alert_handler_entropy_stress.133629778
Short name T220
Test name
Test status
Simulation time 1195483130 ps
CPU time 35.81 seconds
Started Jul 20 06:41:09 PM PDT 24
Finished Jul 20 06:41:47 PM PDT 24
Peak memory 248904 kb
Host smart-b4624b11-b968-46d8-a346-b3fdf4fdb0d5
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=133629778 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy_stress.133629778
Directory /workspace/4.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/4.alert_handler_esc_alert_accum.12821141
Short name T654
Test name
Test status
Simulation time 5384175899 ps
CPU time 106.87 seconds
Started Jul 20 06:40:56 PM PDT 24
Finished Jul 20 06:42:45 PM PDT 24
Peak memory 251160 kb
Host smart-ed3e54c0-3df3-4a0c-ad20-0f21983c5aa7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12821
141 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_alert_accum.12821141
Directory /workspace/4.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/4.alert_handler_esc_intr_timeout.1093457014
Short name T644
Test name
Test status
Simulation time 2131425989 ps
CPU time 32.8 seconds
Started Jul 20 06:41:24 PM PDT 24
Finished Jul 20 06:41:58 PM PDT 24
Peak memory 248864 kb
Host smart-da89f5bd-eaf5-4088-ba7e-e1b2392a3ec7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10934
57014 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_intr_timeout.1093457014
Directory /workspace/4.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_lpg.2386458476
Short name T327
Test name
Test status
Simulation time 232097050171 ps
CPU time 2932.81 seconds
Started Jul 20 06:42:26 PM PDT 24
Finished Jul 20 07:31:20 PM PDT 24
Peak memory 289088 kb
Host smart-c4209144-3129-4ba2-880f-ed82254ad8ee
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386458476 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg.2386458476
Directory /workspace/4.alert_handler_lpg/latest

Test location /workspace/coverage/default/4.alert_handler_lpg_stub_clk.623836959
Short name T630
Test name
Test status
Simulation time 26254842807 ps
CPU time 1669.19 seconds
Started Jul 20 06:40:58 PM PDT 24
Finished Jul 20 07:08:49 PM PDT 24
Peak memory 273680 kb
Host smart-6fa31d7b-5846-4cb7-9f76-8afc0c8be15e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623836959 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg_stub_clk.623836959
Directory /workspace/4.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/4.alert_handler_ping_timeout.3889567637
Short name T329
Test name
Test status
Simulation time 2010972189 ps
CPU time 80.66 seconds
Started Jul 20 06:42:26 PM PDT 24
Finished Jul 20 06:43:48 PM PDT 24
Peak memory 248276 kb
Host smart-608784c5-62fb-40b7-bc5c-de99a28739f2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889567637 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_ping_timeout.3889567637
Directory /workspace/4.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_random_alerts.970369133
Short name T391
Test name
Test status
Simulation time 1122849473 ps
CPU time 73.03 seconds
Started Jul 20 06:41:06 PM PDT 24
Finished Jul 20 06:42:19 PM PDT 24
Peak memory 249008 kb
Host smart-acac3c1a-1ee8-441d-b8ee-1f9e5f89a9d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97036
9133 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_alerts.970369133
Directory /workspace/4.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/4.alert_handler_random_classes.792553183
Short name T517
Test name
Test status
Simulation time 697962137 ps
CPU time 51.23 seconds
Started Jul 20 06:41:24 PM PDT 24
Finished Jul 20 06:42:17 PM PDT 24
Peak memory 248876 kb
Host smart-920dbe4d-953b-4707-adf2-0f8297be77b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79255
3183 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_classes.792553183
Directory /workspace/4.alert_handler_random_classes/latest

Test location /workspace/coverage/default/4.alert_handler_sec_cm.2246171661
Short name T31
Test name
Test status
Simulation time 634666670 ps
CPU time 27.94 seconds
Started Jul 20 06:41:08 PM PDT 24
Finished Jul 20 06:41:38 PM PDT 24
Peak memory 267456 kb
Host smart-40cdac9d-28df-4a75-92c9-1e703d8f5c9c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2246171661 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sec_cm.2246171661
Directory /workspace/4.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/4.alert_handler_sig_int_fail.1237850041
Short name T704
Test name
Test status
Simulation time 279353994 ps
CPU time 30.49 seconds
Started Jul 20 06:41:15 PM PDT 24
Finished Jul 20 06:41:46 PM PDT 24
Peak memory 248956 kb
Host smart-0e9fadbc-def9-4f21-93e4-94d7493cb380
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12378
50041 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sig_int_fail.1237850041
Directory /workspace/4.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/4.alert_handler_smoke.3579210521
Short name T513
Test name
Test status
Simulation time 139163001 ps
CPU time 6.08 seconds
Started Jul 20 06:41:08 PM PDT 24
Finished Jul 20 06:41:17 PM PDT 24
Peak memory 255156 kb
Host smart-905cc29e-5405-4998-91f0-0f287b980acf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35792
10521 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_smoke.3579210521
Directory /workspace/4.alert_handler_smoke/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all.2831728403
Short name T283
Test name
Test status
Simulation time 6021364922 ps
CPU time 372.13 seconds
Started Jul 20 06:41:09 PM PDT 24
Finished Jul 20 06:47:23 PM PDT 24
Peak memory 257232 kb
Host smart-559ada5f-9130-4853-9f5d-fe930b8b2ff1
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831728403 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_han
dler_stress_all.2831728403
Directory /workspace/4.alert_handler_stress_all/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all_with_rand_reset.3347958618
Short name T46
Test name
Test status
Simulation time 129122013573 ps
CPU time 7194.53 seconds
Started Jul 20 06:41:07 PM PDT 24
Finished Jul 20 08:41:03 PM PDT 24
Peak memory 371356 kb
Host smart-584b48f8-f042-42b0-92ae-29cd6778f216
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347958618 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.alert_handler_stress_all_with_rand_reset.3347958618
Directory /workspace/4.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.alert_handler_entropy.4151547098
Short name T306
Test name
Test status
Simulation time 18412615696 ps
CPU time 1089.07 seconds
Started Jul 20 06:42:54 PM PDT 24
Finished Jul 20 07:01:03 PM PDT 24
Peak memory 273672 kb
Host smart-59d6cbe5-ea2c-4377-a3a7-b5b1c792c93e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151547098 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_entropy.4151547098
Directory /workspace/40.alert_handler_entropy/latest

Test location /workspace/coverage/default/40.alert_handler_esc_alert_accum.1666350118
Short name T296
Test name
Test status
Simulation time 2802631757 ps
CPU time 168.68 seconds
Started Jul 20 06:42:51 PM PDT 24
Finished Jul 20 06:45:41 PM PDT 24
Peak memory 251036 kb
Host smart-dbad33a2-2279-4efa-bfbc-a26ac88d967d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16663
50118 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_alert_accum.1666350118
Directory /workspace/40.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/40.alert_handler_esc_intr_timeout.230099191
Short name T597
Test name
Test status
Simulation time 921816293 ps
CPU time 29.77 seconds
Started Jul 20 06:42:49 PM PDT 24
Finished Jul 20 06:43:19 PM PDT 24
Peak memory 256688 kb
Host smart-0382ebd1-7902-438e-bc90-2d4cb88ce8c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23009
9191 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_intr_timeout.230099191
Directory /workspace/40.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_lpg_stub_clk.2765552109
Short name T104
Test name
Test status
Simulation time 83079134457 ps
CPU time 2432.01 seconds
Started Jul 20 06:42:52 PM PDT 24
Finished Jul 20 07:23:25 PM PDT 24
Peak memory 289928 kb
Host smart-b3146328-f391-4f4c-9526-0fc206c742c3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765552109 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg_stub_clk.2765552109
Directory /workspace/40.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/40.alert_handler_ping_timeout.2244794818
Short name T313
Test name
Test status
Simulation time 57671581160 ps
CPU time 515.2 seconds
Started Jul 20 06:42:50 PM PDT 24
Finished Jul 20 06:51:26 PM PDT 24
Peak memory 249068 kb
Host smart-9c980876-6408-44b2-b98d-798b3a5fa9f0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244794818 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_ping_timeout.2244794818
Directory /workspace/40.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_random_alerts.1810925355
Short name T498
Test name
Test status
Simulation time 653990473 ps
CPU time 40.3 seconds
Started Jul 20 06:42:43 PM PDT 24
Finished Jul 20 06:43:24 PM PDT 24
Peak memory 256176 kb
Host smart-15d6eb98-a3d0-40ea-ab52-ff56627a0478
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18109
25355 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_alerts.1810925355
Directory /workspace/40.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/40.alert_handler_random_classes.1516699286
Short name T659
Test name
Test status
Simulation time 2173662306 ps
CPU time 70.75 seconds
Started Jul 20 06:42:42 PM PDT 24
Finished Jul 20 06:43:54 PM PDT 24
Peak memory 256652 kb
Host smart-b3f61bd1-d2f4-4877-a47d-f5a7030e5ce4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15166
99286 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_classes.1516699286
Directory /workspace/40.alert_handler_random_classes/latest

Test location /workspace/coverage/default/40.alert_handler_sig_int_fail.890163647
Short name T91
Test name
Test status
Simulation time 1292199186 ps
CPU time 24.22 seconds
Started Jul 20 06:42:52 PM PDT 24
Finished Jul 20 06:43:17 PM PDT 24
Peak memory 256664 kb
Host smart-4a68fafe-d7c5-44e3-9b2a-fc3f79b4c7b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89016
3647 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_sig_int_fail.890163647
Directory /workspace/40.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/40.alert_handler_smoke.2954243947
Short name T21
Test name
Test status
Simulation time 209838507 ps
CPU time 7.64 seconds
Started Jul 20 06:42:43 PM PDT 24
Finished Jul 20 06:42:52 PM PDT 24
Peak memory 248984 kb
Host smart-ebdfbbee-75b1-46f5-9752-14ad1148f1bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29542
43947 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_smoke.2954243947
Directory /workspace/40.alert_handler_smoke/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all.2408988054
Short name T606
Test name
Test status
Simulation time 5855356289 ps
CPU time 377.93 seconds
Started Jul 20 06:42:51 PM PDT 24
Finished Jul 20 06:49:10 PM PDT 24
Peak memory 257288 kb
Host smart-38fd14af-ff76-4f2a-8ac0-297c0b92cbcd
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408988054 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_ha
ndler_stress_all.2408988054
Directory /workspace/40.alert_handler_stress_all/latest

Test location /workspace/coverage/default/41.alert_handler_entropy.1310446427
Short name T523
Test name
Test status
Simulation time 106170454474 ps
CPU time 1624.73 seconds
Started Jul 20 06:42:50 PM PDT 24
Finished Jul 20 07:09:55 PM PDT 24
Peak memory 273420 kb
Host smart-535b6879-d268-469f-97b7-ecd87eeb179f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310446427 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_entropy.1310446427
Directory /workspace/41.alert_handler_entropy/latest

Test location /workspace/coverage/default/41.alert_handler_esc_alert_accum.2851635832
Short name T280
Test name
Test status
Simulation time 8245057163 ps
CPU time 83.04 seconds
Started Jul 20 06:42:54 PM PDT 24
Finished Jul 20 06:44:18 PM PDT 24
Peak memory 256748 kb
Host smart-cb506d40-f97a-4243-81ea-904667ae6251
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28516
35832 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_alert_accum.2851635832
Directory /workspace/41.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/41.alert_handler_esc_intr_timeout.3522135178
Short name T274
Test name
Test status
Simulation time 857654754 ps
CPU time 28.33 seconds
Started Jul 20 06:42:53 PM PDT 24
Finished Jul 20 06:43:22 PM PDT 24
Peak memory 256020 kb
Host smart-15387c11-4a53-4b9a-b602-c13d0162b429
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35221
35178 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_intr_timeout.3522135178
Directory /workspace/41.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_lpg.3388918844
Short name T344
Test name
Test status
Simulation time 135280721252 ps
CPU time 2020.63 seconds
Started Jul 20 06:42:52 PM PDT 24
Finished Jul 20 07:16:34 PM PDT 24
Peak memory 290068 kb
Host smart-570b2f6c-7733-430a-a282-eea39a2eabb3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388918844 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg.3388918844
Directory /workspace/41.alert_handler_lpg/latest

Test location /workspace/coverage/default/41.alert_handler_lpg_stub_clk.3626151635
Short name T633
Test name
Test status
Simulation time 55163753754 ps
CPU time 1286.99 seconds
Started Jul 20 06:42:51 PM PDT 24
Finished Jul 20 07:04:19 PM PDT 24
Peak memory 287784 kb
Host smart-bc06b0fa-7c25-4dd8-96f1-a37004c33998
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626151635 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg_stub_clk.3626151635
Directory /workspace/41.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/41.alert_handler_random_alerts.733699394
Short name T406
Test name
Test status
Simulation time 764657401 ps
CPU time 46.63 seconds
Started Jul 20 06:42:49 PM PDT 24
Finished Jul 20 06:43:36 PM PDT 24
Peak memory 248924 kb
Host smart-2028c240-aab6-4afd-949e-30f5a2d51764
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73369
9394 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_alerts.733699394
Directory /workspace/41.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/41.alert_handler_random_classes.3559544679
Short name T582
Test name
Test status
Simulation time 2978306799 ps
CPU time 44.48 seconds
Started Jul 20 06:42:51 PM PDT 24
Finished Jul 20 06:43:36 PM PDT 24
Peak memory 248676 kb
Host smart-980a5875-4696-4b6c-9dea-e977b5db191d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35595
44679 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_classes.3559544679
Directory /workspace/41.alert_handler_random_classes/latest

Test location /workspace/coverage/default/41.alert_handler_sig_int_fail.503650559
Short name T85
Test name
Test status
Simulation time 2604761723 ps
CPU time 55.22 seconds
Started Jul 20 06:42:53 PM PDT 24
Finished Jul 20 06:43:49 PM PDT 24
Peak memory 249100 kb
Host smart-07369edf-bf17-482a-b0ea-aa5df4308bc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50365
0559 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_sig_int_fail.503650559
Directory /workspace/41.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/41.alert_handler_smoke.228912328
Short name T399
Test name
Test status
Simulation time 239321718 ps
CPU time 26.7 seconds
Started Jul 20 06:42:49 PM PDT 24
Finished Jul 20 06:43:16 PM PDT 24
Peak memory 257160 kb
Host smart-c0e09223-af72-43e9-bca3-a18426a4b4f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22891
2328 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_smoke.228912328
Directory /workspace/41.alert_handler_smoke/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all.834326294
Short name T239
Test name
Test status
Simulation time 591450831899 ps
CPU time 3908.99 seconds
Started Jul 20 06:42:49 PM PDT 24
Finished Jul 20 07:47:59 PM PDT 24
Peak memory 289568 kb
Host smart-cf7f6fca-5223-4435-babc-289c778bfaf9
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834326294 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_han
dler_stress_all.834326294
Directory /workspace/41.alert_handler_stress_all/latest

Test location /workspace/coverage/default/42.alert_handler_entropy.4194172334
Short name T79
Test name
Test status
Simulation time 44324944445 ps
CPU time 1393.02 seconds
Started Jul 20 06:42:58 PM PDT 24
Finished Jul 20 07:06:12 PM PDT 24
Peak memory 273516 kb
Host smart-1bcad5ee-4d64-4c22-bac7-ab9720dc4437
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4194172334 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_entropy.4194172334
Directory /workspace/42.alert_handler_entropy/latest

Test location /workspace/coverage/default/42.alert_handler_esc_alert_accum.960537704
Short name T272
Test name
Test status
Simulation time 1207272059 ps
CPU time 63.17 seconds
Started Jul 20 06:42:50 PM PDT 24
Finished Jul 20 06:43:54 PM PDT 24
Peak memory 256740 kb
Host smart-8238d4d9-f6bd-4f5d-a9c8-02dfd6e938d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96053
7704 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_alert_accum.960537704
Directory /workspace/42.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/42.alert_handler_esc_intr_timeout.1970556670
Short name T446
Test name
Test status
Simulation time 2661355793 ps
CPU time 47.06 seconds
Started Jul 20 06:42:50 PM PDT 24
Finished Jul 20 06:43:38 PM PDT 24
Peak memory 249472 kb
Host smart-45919fe7-16f6-4463-bb6c-e8c851c4a3cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19705
56670 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_intr_timeout.1970556670
Directory /workspace/42.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_lpg.4223716273
Short name T114
Test name
Test status
Simulation time 15039900420 ps
CPU time 1322.63 seconds
Started Jul 20 06:42:59 PM PDT 24
Finished Jul 20 07:05:02 PM PDT 24
Peak memory 281892 kb
Host smart-a065065a-8762-4052-87b3-5f3c1782ea63
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4223716273 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg.4223716273
Directory /workspace/42.alert_handler_lpg/latest

Test location /workspace/coverage/default/42.alert_handler_lpg_stub_clk.3412655842
Short name T458
Test name
Test status
Simulation time 45472356456 ps
CPU time 2627.34 seconds
Started Jul 20 06:42:58 PM PDT 24
Finished Jul 20 07:26:46 PM PDT 24
Peak memory 289864 kb
Host smart-52710f07-ef52-46ec-9b59-ae5f41c298fc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412655842 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg_stub_clk.3412655842
Directory /workspace/42.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/42.alert_handler_ping_timeout.3385610597
Short name T322
Test name
Test status
Simulation time 52799877009 ps
CPU time 526.63 seconds
Started Jul 20 06:42:58 PM PDT 24
Finished Jul 20 06:51:45 PM PDT 24
Peak memory 256200 kb
Host smart-d1e5fc8c-22bd-4755-a525-0bbbbaf05b50
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385610597 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_ping_timeout.3385610597
Directory /workspace/42.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_random_alerts.2659988420
Short name T44
Test name
Test status
Simulation time 1113736611 ps
CPU time 60.17 seconds
Started Jul 20 06:42:51 PM PDT 24
Finished Jul 20 06:43:51 PM PDT 24
Peak memory 256284 kb
Host smart-2af9c323-7cf6-49fd-9415-1a7fc33c796a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26599
88420 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_alerts.2659988420
Directory /workspace/42.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/42.alert_handler_random_classes.530974326
Short name T418
Test name
Test status
Simulation time 5042266367 ps
CPU time 50.46 seconds
Started Jul 20 06:42:50 PM PDT 24
Finished Jul 20 06:43:41 PM PDT 24
Peak memory 257288 kb
Host smart-b05054d1-6d85-4163-8ec6-5ac2220f0f5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53097
4326 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_classes.530974326
Directory /workspace/42.alert_handler_random_classes/latest

Test location /workspace/coverage/default/42.alert_handler_sig_int_fail.1342133839
Short name T241
Test name
Test status
Simulation time 90215562 ps
CPU time 15.88 seconds
Started Jul 20 06:42:56 PM PDT 24
Finished Jul 20 06:43:12 PM PDT 24
Peak memory 248524 kb
Host smart-ba4e0807-dd3d-4df4-b395-f28c72d728c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13421
33839 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_sig_int_fail.1342133839
Directory /workspace/42.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/42.alert_handler_smoke.1276600074
Short name T459
Test name
Test status
Simulation time 1161893781 ps
CPU time 74 seconds
Started Jul 20 06:42:50 PM PDT 24
Finished Jul 20 06:44:04 PM PDT 24
Peak memory 257100 kb
Host smart-724558b9-e38a-45e7-bd28-a1cbd2923b77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12766
00074 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_smoke.1276600074
Directory /workspace/42.alert_handler_smoke/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all.536216235
Short name T503
Test name
Test status
Simulation time 14706015179 ps
CPU time 347.18 seconds
Started Jul 20 06:42:57 PM PDT 24
Finished Jul 20 06:48:45 PM PDT 24
Peak memory 265508 kb
Host smart-8658d720-dbbb-4a46-82d7-9831ad821d10
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536216235 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_han
dler_stress_all.536216235
Directory /workspace/42.alert_handler_stress_all/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all_with_rand_reset.1654208680
Short name T113
Test name
Test status
Simulation time 141429752188 ps
CPU time 2755.33 seconds
Started Jul 20 06:42:57 PM PDT 24
Finished Jul 20 07:28:53 PM PDT 24
Peak memory 322284 kb
Host smart-b615708e-a1ec-4300-867a-21d68f2bf098
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654208680 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 42.alert_handler_stress_all_with_rand_reset.1654208680
Directory /workspace/42.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.alert_handler_entropy.2886568745
Short name T700
Test name
Test status
Simulation time 60833180793 ps
CPU time 846.24 seconds
Started Jul 20 06:42:57 PM PDT 24
Finished Jul 20 06:57:04 PM PDT 24
Peak memory 273588 kb
Host smart-3380dc37-1099-413f-aaa8-411419257199
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886568745 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_entropy.2886568745
Directory /workspace/43.alert_handler_entropy/latest

Test location /workspace/coverage/default/43.alert_handler_esc_alert_accum.1864752542
Short name T392
Test name
Test status
Simulation time 5913153727 ps
CPU time 95.35 seconds
Started Jul 20 06:42:58 PM PDT 24
Finished Jul 20 06:44:34 PM PDT 24
Peak memory 256868 kb
Host smart-ca2f8ee0-9188-4a37-a260-7ea8f7e9ba8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18647
52542 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_alert_accum.1864752542
Directory /workspace/43.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/43.alert_handler_esc_intr_timeout.856585114
Short name T416
Test name
Test status
Simulation time 503525167 ps
CPU time 6.35 seconds
Started Jul 20 06:42:57 PM PDT 24
Finished Jul 20 06:43:03 PM PDT 24
Peak memory 248500 kb
Host smart-b8feb183-775f-4c67-87a1-eb82b3ce0c08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85658
5114 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_intr_timeout.856585114
Directory /workspace/43.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_lpg.318337514
Short name T324
Test name
Test status
Simulation time 90868168977 ps
CPU time 1231.43 seconds
Started Jul 20 06:42:57 PM PDT 24
Finished Jul 20 07:03:29 PM PDT 24
Peak memory 272020 kb
Host smart-3e352fa7-c6af-470e-bb71-9b6052ccf43c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318337514 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg.318337514
Directory /workspace/43.alert_handler_lpg/latest

Test location /workspace/coverage/default/43.alert_handler_lpg_stub_clk.760402728
Short name T426
Test name
Test status
Simulation time 17891035564 ps
CPU time 1232.84 seconds
Started Jul 20 06:43:08 PM PDT 24
Finished Jul 20 07:03:41 PM PDT 24
Peak memory 272528 kb
Host smart-8b223bc5-2edf-4372-876f-879249bf959c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760402728 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg_stub_clk.760402728
Directory /workspace/43.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/43.alert_handler_random_alerts.565655979
Short name T525
Test name
Test status
Simulation time 4844472830 ps
CPU time 65.49 seconds
Started Jul 20 06:42:59 PM PDT 24
Finished Jul 20 06:44:05 PM PDT 24
Peak memory 249080 kb
Host smart-c7de54fa-edb9-4ff0-8f80-aa29a89bc799
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56565
5979 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_alerts.565655979
Directory /workspace/43.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/43.alert_handler_random_classes.3276941360
Short name T375
Test name
Test status
Simulation time 2397414060 ps
CPU time 39.37 seconds
Started Jul 20 06:42:57 PM PDT 24
Finished Jul 20 06:43:37 PM PDT 24
Peak memory 256312 kb
Host smart-858230e2-fdfe-4310-9f32-c679eb7fd30f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32769
41360 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_classes.3276941360
Directory /workspace/43.alert_handler_random_classes/latest

Test location /workspace/coverage/default/43.alert_handler_sig_int_fail.2218308305
Short name T509
Test name
Test status
Simulation time 436832071 ps
CPU time 30.84 seconds
Started Jul 20 06:42:57 PM PDT 24
Finished Jul 20 06:43:29 PM PDT 24
Peak memory 249604 kb
Host smart-82f8c22d-c7a2-45bd-9248-54a25fd9a1a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22183
08305 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_sig_int_fail.2218308305
Directory /workspace/43.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/43.alert_handler_smoke.1650723569
Short name T545
Test name
Test status
Simulation time 641384858 ps
CPU time 18.86 seconds
Started Jul 20 06:42:58 PM PDT 24
Finished Jul 20 06:43:18 PM PDT 24
Peak memory 256128 kb
Host smart-c7002000-2cb9-4248-92af-8c44e6f92d05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16507
23569 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_smoke.1650723569
Directory /workspace/43.alert_handler_smoke/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all_with_rand_reset.3296134258
Short name T225
Test name
Test status
Simulation time 21050575329 ps
CPU time 1251.43 seconds
Started Jul 20 06:43:05 PM PDT 24
Finished Jul 20 07:03:57 PM PDT 24
Peak memory 283272 kb
Host smart-b0d800eb-da27-4778-9d3d-a2d3c393f0f3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296134258 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 43.alert_handler_stress_all_with_rand_reset.3296134258
Directory /workspace/43.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.alert_handler_entropy.1198703315
Short name T93
Test name
Test status
Simulation time 57503006226 ps
CPU time 1464.27 seconds
Started Jul 20 06:43:07 PM PDT 24
Finished Jul 20 07:07:32 PM PDT 24
Peak memory 289820 kb
Host smart-4266eac3-8ded-4818-b818-78c41354b505
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198703315 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_entropy.1198703315
Directory /workspace/44.alert_handler_entropy/latest

Test location /workspace/coverage/default/44.alert_handler_esc_alert_accum.742268250
Short name T447
Test name
Test status
Simulation time 14911165178 ps
CPU time 115.36 seconds
Started Jul 20 06:43:07 PM PDT 24
Finished Jul 20 06:45:03 PM PDT 24
Peak memory 256452 kb
Host smart-5aa1a262-d625-4364-aa50-4abc729fdb3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74226
8250 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_alert_accum.742268250
Directory /workspace/44.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/44.alert_handler_esc_intr_timeout.497922755
Short name T454
Test name
Test status
Simulation time 574943646 ps
CPU time 46.31 seconds
Started Jul 20 06:43:05 PM PDT 24
Finished Jul 20 06:43:52 PM PDT 24
Peak memory 257212 kb
Host smart-4cf4c718-ee32-4f87-8238-dd4a6e314cb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49792
2755 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_intr_timeout.497922755
Directory /workspace/44.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_lpg.1065563812
Short name T222
Test name
Test status
Simulation time 42201686224 ps
CPU time 1309.93 seconds
Started Jul 20 06:43:02 PM PDT 24
Finished Jul 20 07:04:53 PM PDT 24
Peak memory 272996 kb
Host smart-a6be0629-56fd-49f1-b600-4783726193e6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065563812 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg.1065563812
Directory /workspace/44.alert_handler_lpg/latest

Test location /workspace/coverage/default/44.alert_handler_lpg_stub_clk.3358921810
Short name T419
Test name
Test status
Simulation time 597938815789 ps
CPU time 3538.03 seconds
Started Jul 20 06:43:08 PM PDT 24
Finished Jul 20 07:42:07 PM PDT 24
Peak memory 288948 kb
Host smart-889cca82-3d26-4918-9a45-bc25ff792c9f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3358921810 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg_stub_clk.3358921810
Directory /workspace/44.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/44.alert_handler_ping_timeout.2994286196
Short name T294
Test name
Test status
Simulation time 4379443150 ps
CPU time 175.87 seconds
Started Jul 20 06:43:04 PM PDT 24
Finished Jul 20 06:46:01 PM PDT 24
Peak memory 249080 kb
Host smart-a9b7c810-f844-488c-bc09-c4ecfb9f90b2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994286196 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_ping_timeout.2994286196
Directory /workspace/44.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_random_alerts.4025829542
Short name T386
Test name
Test status
Simulation time 1433162917 ps
CPU time 25.07 seconds
Started Jul 20 06:43:04 PM PDT 24
Finished Jul 20 06:43:30 PM PDT 24
Peak memory 257140 kb
Host smart-325b5ea9-b7db-46c3-9b1c-09d2a0f930bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40258
29542 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_alerts.4025829542
Directory /workspace/44.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/44.alert_handler_random_classes.190719538
Short name T487
Test name
Test status
Simulation time 778979780 ps
CPU time 43.86 seconds
Started Jul 20 06:43:03 PM PDT 24
Finished Jul 20 06:43:48 PM PDT 24
Peak memory 249504 kb
Host smart-1c7db706-fda0-4a46-9092-8696312639e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19071
9538 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_classes.190719538
Directory /workspace/44.alert_handler_random_classes/latest

Test location /workspace/coverage/default/44.alert_handler_sig_int_fail.2260717907
Short name T652
Test name
Test status
Simulation time 2233752209 ps
CPU time 24.29 seconds
Started Jul 20 06:43:04 PM PDT 24
Finished Jul 20 06:43:29 PM PDT 24
Peak memory 256592 kb
Host smart-04aeb642-ff71-48cd-b909-56624f2e5044
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22607
17907 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_sig_int_fail.2260717907
Directory /workspace/44.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/44.alert_handler_smoke.1192438924
Short name T364
Test name
Test status
Simulation time 1555248406 ps
CPU time 25.79 seconds
Started Jul 20 06:43:05 PM PDT 24
Finished Jul 20 06:43:32 PM PDT 24
Peak memory 257140 kb
Host smart-9e894de8-2548-4397-b438-aea36efd7c28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11924
38924 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_smoke.1192438924
Directory /workspace/44.alert_handler_smoke/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all.3758278035
Short name T591
Test name
Test status
Simulation time 6117365891 ps
CPU time 371.3 seconds
Started Jul 20 06:43:09 PM PDT 24
Finished Jul 20 06:49:20 PM PDT 24
Peak memory 257216 kb
Host smart-c29fe5b4-789f-4a30-b279-b51f5b3bdc82
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758278035 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_ha
ndler_stress_all.3758278035
Directory /workspace/44.alert_handler_stress_all/latest

Test location /workspace/coverage/default/45.alert_handler_entropy.897936560
Short name T505
Test name
Test status
Simulation time 26412751684 ps
CPU time 1699.38 seconds
Started Jul 20 06:43:06 PM PDT 24
Finished Jul 20 07:11:26 PM PDT 24
Peak memory 273392 kb
Host smart-b3622b9f-5cf7-460d-97aa-46abb8b1412a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897936560 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_entropy.897936560
Directory /workspace/45.alert_handler_entropy/latest

Test location /workspace/coverage/default/45.alert_handler_esc_alert_accum.2092495098
Short name T696
Test name
Test status
Simulation time 3017172889 ps
CPU time 72.5 seconds
Started Jul 20 06:43:06 PM PDT 24
Finished Jul 20 06:44:19 PM PDT 24
Peak memory 256612 kb
Host smart-a4600071-9d8f-4a8a-8d14-5ef646200f84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20924
95098 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_alert_accum.2092495098
Directory /workspace/45.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/45.alert_handler_esc_intr_timeout.1349018858
Short name T68
Test name
Test status
Simulation time 849135346 ps
CPU time 60.97 seconds
Started Jul 20 06:43:04 PM PDT 24
Finished Jul 20 06:44:05 PM PDT 24
Peak memory 256356 kb
Host smart-8e6e859f-832c-4a29-8afe-979cf7fc182a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13490
18858 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_intr_timeout.1349018858
Directory /workspace/45.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_lpg.3826933749
Short name T336
Test name
Test status
Simulation time 38622267351 ps
CPU time 2299.05 seconds
Started Jul 20 06:43:12 PM PDT 24
Finished Jul 20 07:21:31 PM PDT 24
Peak memory 273064 kb
Host smart-c46a71ee-1e3a-42c8-b8a9-aaf5d2e6c2c7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826933749 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg.3826933749
Directory /workspace/45.alert_handler_lpg/latest

Test location /workspace/coverage/default/45.alert_handler_lpg_stub_clk.411773084
Short name T669
Test name
Test status
Simulation time 41725025058 ps
CPU time 1404.48 seconds
Started Jul 20 06:43:12 PM PDT 24
Finished Jul 20 07:06:37 PM PDT 24
Peak memory 273776 kb
Host smart-d5e23403-d4ae-4146-86a4-05cceb487d7f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411773084 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg_stub_clk.411773084
Directory /workspace/45.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/45.alert_handler_ping_timeout.3437629570
Short name T285
Test name
Test status
Simulation time 13150178253 ps
CPU time 289.83 seconds
Started Jul 20 06:43:13 PM PDT 24
Finished Jul 20 06:48:03 PM PDT 24
Peak memory 247952 kb
Host smart-2170af1c-fb31-4e2f-b30d-dbbe4518e9ca
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437629570 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_ping_timeout.3437629570
Directory /workspace/45.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_random_alerts.2351822809
Short name T613
Test name
Test status
Simulation time 243753981 ps
CPU time 17.69 seconds
Started Jul 20 06:43:07 PM PDT 24
Finished Jul 20 06:43:25 PM PDT 24
Peak memory 249024 kb
Host smart-aa321586-0387-4c36-8e6a-5c6a7fbd2f03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23518
22809 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_alerts.2351822809
Directory /workspace/45.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/45.alert_handler_random_classes.3383951256
Short name T7
Test name
Test status
Simulation time 2097627758 ps
CPU time 11.89 seconds
Started Jul 20 06:43:05 PM PDT 24
Finished Jul 20 06:43:18 PM PDT 24
Peak memory 248980 kb
Host smart-36154e12-f245-4de4-a6c0-5f717c4b2317
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33839
51256 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_classes.3383951256
Directory /workspace/45.alert_handler_random_classes/latest

Test location /workspace/coverage/default/45.alert_handler_sig_int_fail.3675533628
Short name T666
Test name
Test status
Simulation time 155929211 ps
CPU time 21.26 seconds
Started Jul 20 06:43:08 PM PDT 24
Finished Jul 20 06:43:30 PM PDT 24
Peak memory 248412 kb
Host smart-712ff1f6-4e34-4c78-b549-42aff46d86f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36755
33628 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_sig_int_fail.3675533628
Directory /workspace/45.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/45.alert_handler_smoke.4113125798
Short name T632
Test name
Test status
Simulation time 163177291 ps
CPU time 13.8 seconds
Started Jul 20 06:43:04 PM PDT 24
Finished Jul 20 06:43:19 PM PDT 24
Peak memory 254984 kb
Host smart-1d677508-7eb7-4b92-a184-3aa014895d6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41131
25798 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_smoke.4113125798
Directory /workspace/45.alert_handler_smoke/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all.87477580
Short name T284
Test name
Test status
Simulation time 166366520591 ps
CPU time 2228.72 seconds
Started Jul 20 06:43:11 PM PDT 24
Finished Jul 20 07:20:20 PM PDT 24
Peak memory 302568 kb
Host smart-0151dc0a-317c-4714-bc76-4d32cd2a5504
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87477580 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_hand
ler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_hand
ler_stress_all.87477580
Directory /workspace/45.alert_handler_stress_all/latest

Test location /workspace/coverage/default/46.alert_handler_entropy.1120702089
Short name T209
Test name
Test status
Simulation time 97325171706 ps
CPU time 1800.97 seconds
Started Jul 20 06:43:12 PM PDT 24
Finished Jul 20 07:13:13 PM PDT 24
Peak memory 284008 kb
Host smart-a69cec19-b032-4f59-a75b-fdccdee864d2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120702089 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_entropy.1120702089
Directory /workspace/46.alert_handler_entropy/latest

Test location /workspace/coverage/default/46.alert_handler_esc_alert_accum.2301971844
Short name T581
Test name
Test status
Simulation time 1509322749 ps
CPU time 42.82 seconds
Started Jul 20 06:43:12 PM PDT 24
Finished Jul 20 06:43:56 PM PDT 24
Peak memory 256472 kb
Host smart-2eeb7334-d689-4f94-afa8-8f9f47702286
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23019
71844 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_alert_accum.2301971844
Directory /workspace/46.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/46.alert_handler_esc_intr_timeout.2689863724
Short name T687
Test name
Test status
Simulation time 974207528 ps
CPU time 7.21 seconds
Started Jul 20 06:43:11 PM PDT 24
Finished Jul 20 06:43:19 PM PDT 24
Peak memory 255036 kb
Host smart-04249cfd-7a74-4899-bee1-192ecc323a24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26898
63724 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_intr_timeout.2689863724
Directory /workspace/46.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_lpg.846196409
Short name T348
Test name
Test status
Simulation time 60771204266 ps
CPU time 3265.9 seconds
Started Jul 20 06:43:13 PM PDT 24
Finished Jul 20 07:37:40 PM PDT 24
Peak memory 289844 kb
Host smart-87c528fc-2394-45dd-88c3-df2ddf1fbc2b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=846196409 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg.846196409
Directory /workspace/46.alert_handler_lpg/latest

Test location /workspace/coverage/default/46.alert_handler_lpg_stub_clk.1854010547
Short name T94
Test name
Test status
Simulation time 79101040380 ps
CPU time 1278.38 seconds
Started Jul 20 06:43:13 PM PDT 24
Finished Jul 20 07:04:32 PM PDT 24
Peak memory 268600 kb
Host smart-0c0a7f93-a078-4170-9119-5b45b8777300
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1854010547 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg_stub_clk.1854010547
Directory /workspace/46.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/46.alert_handler_ping_timeout.3721691644
Short name T8
Test name
Test status
Simulation time 8117490518 ps
CPU time 352.36 seconds
Started Jul 20 06:43:13 PM PDT 24
Finished Jul 20 06:49:06 PM PDT 24
Peak memory 248092 kb
Host smart-04fbadee-c5d9-4093-9c79-90632c2c2c61
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721691644 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_ping_timeout.3721691644
Directory /workspace/46.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_random_alerts.2211397489
Short name T511
Test name
Test status
Simulation time 362292990 ps
CPU time 32.21 seconds
Started Jul 20 06:43:13 PM PDT 24
Finished Jul 20 06:43:46 PM PDT 24
Peak memory 256472 kb
Host smart-25a2f94f-b3a9-4dcd-bc98-fad3928a83fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22113
97489 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_alerts.2211397489
Directory /workspace/46.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/46.alert_handler_random_classes.3321466991
Short name T546
Test name
Test status
Simulation time 1372964261 ps
CPU time 51.28 seconds
Started Jul 20 06:43:12 PM PDT 24
Finished Jul 20 06:44:04 PM PDT 24
Peak memory 256500 kb
Host smart-4b64a3a9-9ba1-47c0-a70e-03939ff58127
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33214
66991 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_classes.3321466991
Directory /workspace/46.alert_handler_random_classes/latest

Test location /workspace/coverage/default/46.alert_handler_sig_int_fail.317865303
Short name T680
Test name
Test status
Simulation time 157690381 ps
CPU time 17.82 seconds
Started Jul 20 06:43:10 PM PDT 24
Finished Jul 20 06:43:28 PM PDT 24
Peak memory 256524 kb
Host smart-6f478d84-0a30-43c3-a9c1-2b17744fa869
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31786
5303 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_sig_int_fail.317865303
Directory /workspace/46.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/46.alert_handler_smoke.326525851
Short name T65
Test name
Test status
Simulation time 237206048 ps
CPU time 26.4 seconds
Started Jul 20 06:43:11 PM PDT 24
Finished Jul 20 06:43:38 PM PDT 24
Peak memory 257168 kb
Host smart-1b5030bd-9773-465f-983d-256e8f806675
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32652
5851 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_smoke.326525851
Directory /workspace/46.alert_handler_smoke/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all.40877889
Short name T244
Test name
Test status
Simulation time 34958151030 ps
CPU time 415.85 seconds
Started Jul 20 06:43:19 PM PDT 24
Finished Jul 20 06:50:16 PM PDT 24
Peak memory 257244 kb
Host smart-77743429-6d29-4329-9dbb-a621825667cc
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40877889 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_hand
ler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_hand
ler_stress_all.40877889
Directory /workspace/46.alert_handler_stress_all/latest

Test location /workspace/coverage/default/47.alert_handler_entropy.1524444
Short name T288
Test name
Test status
Simulation time 50414388372 ps
CPU time 1152.8 seconds
Started Jul 20 06:43:19 PM PDT 24
Finished Jul 20 07:02:32 PM PDT 24
Peak memory 286864 kb
Host smart-58a8c0cc-7f42-4170-9973-5ef6f67ae3f7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524444 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_entropy.1524444
Directory /workspace/47.alert_handler_entropy/latest

Test location /workspace/coverage/default/47.alert_handler_esc_alert_accum.1373481054
Short name T420
Test name
Test status
Simulation time 353903976 ps
CPU time 28.41 seconds
Started Jul 20 06:43:22 PM PDT 24
Finished Jul 20 06:43:51 PM PDT 24
Peak memory 256740 kb
Host smart-9b8a53b7-254a-4518-b326-2dbd8d7ba7b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13734
81054 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_alert_accum.1373481054
Directory /workspace/47.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/47.alert_handler_esc_intr_timeout.4160930134
Short name T706
Test name
Test status
Simulation time 152362944 ps
CPU time 16.62 seconds
Started Jul 20 06:43:18 PM PDT 24
Finished Jul 20 06:43:36 PM PDT 24
Peak memory 248504 kb
Host smart-6fbce447-dcdf-4072-90e0-1ca2fb8d7454
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41609
30134 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_intr_timeout.4160930134
Directory /workspace/47.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_lpg.2540506578
Short name T691
Test name
Test status
Simulation time 8198093951 ps
CPU time 858.71 seconds
Started Jul 20 06:43:21 PM PDT 24
Finished Jul 20 06:57:40 PM PDT 24
Peak memory 273720 kb
Host smart-56d82e5e-ee04-405e-88d7-5b39f0a418c0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540506578 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg.2540506578
Directory /workspace/47.alert_handler_lpg/latest

Test location /workspace/coverage/default/47.alert_handler_lpg_stub_clk.1882748801
Short name T518
Test name
Test status
Simulation time 32406860213 ps
CPU time 1002.69 seconds
Started Jul 20 06:43:19 PM PDT 24
Finished Jul 20 07:00:03 PM PDT 24
Peak memory 284708 kb
Host smart-7d9b638c-e4e4-453d-843a-1ae8ac5eec67
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882748801 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg_stub_clk.1882748801
Directory /workspace/47.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/47.alert_handler_ping_timeout.174298615
Short name T332
Test name
Test status
Simulation time 83966807289 ps
CPU time 279.62 seconds
Started Jul 20 06:43:18 PM PDT 24
Finished Jul 20 06:47:58 PM PDT 24
Peak memory 248664 kb
Host smart-17c3630f-ab41-495f-8883-4539b4da843d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174298615 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_ping_timeout.174298615
Directory /workspace/47.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_random_alerts.1917558950
Short name T642
Test name
Test status
Simulation time 268819650 ps
CPU time 37.01 seconds
Started Jul 20 06:43:16 PM PDT 24
Finished Jul 20 06:43:54 PM PDT 24
Peak memory 248896 kb
Host smart-6eb6321a-36f6-43f8-bc50-09ebb0eca072
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19175
58950 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_alerts.1917558950
Directory /workspace/47.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/47.alert_handler_random_classes.244761984
Short name T394
Test name
Test status
Simulation time 1515611126 ps
CPU time 26.41 seconds
Started Jul 20 06:43:18 PM PDT 24
Finished Jul 20 06:43:45 PM PDT 24
Peak memory 256548 kb
Host smart-8b489247-c16f-4711-b0c9-4ce1f9a15c34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24476
1984 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_classes.244761984
Directory /workspace/47.alert_handler_random_classes/latest

Test location /workspace/coverage/default/47.alert_handler_sig_int_fail.2555034595
Short name T35
Test name
Test status
Simulation time 510581477 ps
CPU time 16.41 seconds
Started Jul 20 06:43:17 PM PDT 24
Finished Jul 20 06:43:34 PM PDT 24
Peak memory 255320 kb
Host smart-a095e913-6f1e-4234-a8de-8d9bed3463ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25550
34595 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_sig_int_fail.2555034595
Directory /workspace/47.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/47.alert_handler_smoke.2853931429
Short name T404
Test name
Test status
Simulation time 515614383 ps
CPU time 18.14 seconds
Started Jul 20 06:43:18 PM PDT 24
Finished Jul 20 06:43:37 PM PDT 24
Peak memory 257168 kb
Host smart-164751b8-6f6b-4725-8b09-b7083bd618a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28539
31429 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_smoke.2853931429
Directory /workspace/47.alert_handler_smoke/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all.1646996289
Short name T264
Test name
Test status
Simulation time 45614495096 ps
CPU time 2524.99 seconds
Started Jul 20 06:43:21 PM PDT 24
Finished Jul 20 07:25:27 PM PDT 24
Peak memory 289912 kb
Host smart-b48afa72-9670-4dcf-9ba9-4c9328f88515
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646996289 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_ha
ndler_stress_all.1646996289
Directory /workspace/47.alert_handler_stress_all/latest

Test location /workspace/coverage/default/48.alert_handler_entropy.3305834929
Short name T524
Test name
Test status
Simulation time 142460027572 ps
CPU time 2107.84 seconds
Started Jul 20 06:43:31 PM PDT 24
Finished Jul 20 07:18:40 PM PDT 24
Peak memory 273400 kb
Host smart-961a1031-cee4-4202-9da5-b18c8722dd8a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305834929 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_entropy.3305834929
Directory /workspace/48.alert_handler_entropy/latest

Test location /workspace/coverage/default/48.alert_handler_esc_alert_accum.1011119418
Short name T660
Test name
Test status
Simulation time 2775484973 ps
CPU time 146.71 seconds
Started Jul 20 06:43:32 PM PDT 24
Finished Jul 20 06:45:59 PM PDT 24
Peak memory 257240 kb
Host smart-80992424-bfa1-4cf9-a0e5-d04ef9975c12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10111
19418 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_alert_accum.1011119418
Directory /workspace/48.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/48.alert_handler_esc_intr_timeout.443922788
Short name T105
Test name
Test status
Simulation time 5734791260 ps
CPU time 83.4 seconds
Started Jul 20 06:43:31 PM PDT 24
Finished Jul 20 06:44:55 PM PDT 24
Peak memory 257184 kb
Host smart-2ff795c7-c5e5-4a80-bb12-13348944ef90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44392
2788 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_intr_timeout.443922788
Directory /workspace/48.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_lpg.2593864096
Short name T312
Test name
Test status
Simulation time 127185927429 ps
CPU time 2153.17 seconds
Started Jul 20 06:43:28 PM PDT 24
Finished Jul 20 07:19:23 PM PDT 24
Peak memory 289456 kb
Host smart-e138c61d-4a1e-4f57-ae7f-83c58d92a69f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2593864096 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg.2593864096
Directory /workspace/48.alert_handler_lpg/latest

Test location /workspace/coverage/default/48.alert_handler_lpg_stub_clk.1005309553
Short name T54
Test name
Test status
Simulation time 46183876934 ps
CPU time 914.47 seconds
Started Jul 20 06:43:28 PM PDT 24
Finished Jul 20 06:58:44 PM PDT 24
Peak memory 265492 kb
Host smart-ddc8c223-4a89-459c-89a0-282f663a15b1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005309553 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg_stub_clk.1005309553
Directory /workspace/48.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/48.alert_handler_ping_timeout.580953802
Short name T681
Test name
Test status
Simulation time 85060767135 ps
CPU time 378.32 seconds
Started Jul 20 06:43:28 PM PDT 24
Finished Jul 20 06:49:48 PM PDT 24
Peak memory 249088 kb
Host smart-698aecfe-31bb-4cb0-ade3-9e4e419ae492
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580953802 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_ping_timeout.580953802
Directory /workspace/48.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_random_alerts.1825350283
Short name T452
Test name
Test status
Simulation time 509104637 ps
CPU time 37.66 seconds
Started Jul 20 06:43:20 PM PDT 24
Finished Jul 20 06:43:58 PM PDT 24
Peak memory 256460 kb
Host smart-7688d9c8-0b52-42a3-9c41-d9dfa671a5d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18253
50283 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_alerts.1825350283
Directory /workspace/48.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/48.alert_handler_random_classes.4264945415
Short name T643
Test name
Test status
Simulation time 176531321 ps
CPU time 12.18 seconds
Started Jul 20 06:43:19 PM PDT 24
Finished Jul 20 06:43:32 PM PDT 24
Peak memory 249444 kb
Host smart-8de89c82-dc90-4fd4-b457-a05dd42ba0c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42649
45415 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_classes.4264945415
Directory /workspace/48.alert_handler_random_classes/latest

Test location /workspace/coverage/default/48.alert_handler_sig_int_fail.4182742355
Short name T474
Test name
Test status
Simulation time 755518887 ps
CPU time 28.01 seconds
Started Jul 20 06:43:30 PM PDT 24
Finished Jul 20 06:43:59 PM PDT 24
Peak memory 248936 kb
Host smart-77522ba0-7cde-4ce1-9047-baec4d76c32e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41827
42355 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_sig_int_fail.4182742355
Directory /workspace/48.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/48.alert_handler_smoke.131701685
Short name T495
Test name
Test status
Simulation time 2059539317 ps
CPU time 37.65 seconds
Started Jul 20 06:43:19 PM PDT 24
Finished Jul 20 06:43:57 PM PDT 24
Peak memory 257240 kb
Host smart-7c2fed2d-6656-4059-ac2d-728175b2915b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13170
1685 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_smoke.131701685
Directory /workspace/48.alert_handler_smoke/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all.886047271
Short name T705
Test name
Test status
Simulation time 33079485682 ps
CPU time 811.95 seconds
Started Jul 20 06:43:29 PM PDT 24
Finished Jul 20 06:57:02 PM PDT 24
Peak memory 272552 kb
Host smart-14f073ba-8383-4d2a-9fd2-7c48b821e077
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886047271 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_han
dler_stress_all.886047271
Directory /workspace/48.alert_handler_stress_all/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all_with_rand_reset.3541230645
Short name T635
Test name
Test status
Simulation time 397875857757 ps
CPU time 10065.4 seconds
Started Jul 20 06:43:29 PM PDT 24
Finished Jul 20 09:31:17 PM PDT 24
Peak memory 404308 kb
Host smart-946690e2-dc02-411a-bbf1-6e2a120bcc0d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541230645 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 48.alert_handler_stress_all_with_rand_reset.3541230645
Directory /workspace/48.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.alert_handler_entropy.1107943768
Short name T631
Test name
Test status
Simulation time 117983495267 ps
CPU time 1892.67 seconds
Started Jul 20 06:43:31 PM PDT 24
Finished Jul 20 07:15:05 PM PDT 24
Peak memory 288844 kb
Host smart-47193d2f-a30d-4874-b98d-b76ca8c43066
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107943768 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_entropy.1107943768
Directory /workspace/49.alert_handler_entropy/latest

Test location /workspace/coverage/default/49.alert_handler_esc_alert_accum.3650432916
Short name T368
Test name
Test status
Simulation time 3816496999 ps
CPU time 216.95 seconds
Started Jul 20 06:43:27 PM PDT 24
Finished Jul 20 06:47:05 PM PDT 24
Peak memory 257328 kb
Host smart-b1ae9a95-e576-4923-b201-38af04a778e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36504
32916 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_alert_accum.3650432916
Directory /workspace/49.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/49.alert_handler_esc_intr_timeout.3768154306
Short name T491
Test name
Test status
Simulation time 4808571018 ps
CPU time 59.14 seconds
Started Jul 20 06:43:30 PM PDT 24
Finished Jul 20 06:44:30 PM PDT 24
Peak memory 249004 kb
Host smart-c152a4c4-d019-4479-aebb-d068b922b69f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37681
54306 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_intr_timeout.3768154306
Directory /workspace/49.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_lpg.2679647242
Short name T337
Test name
Test status
Simulation time 472787419461 ps
CPU time 2984.89 seconds
Started Jul 20 06:43:29 PM PDT 24
Finished Jul 20 07:33:15 PM PDT 24
Peak memory 289696 kb
Host smart-c1678c8d-c6c1-47e4-8898-283db12cfd09
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679647242 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg.2679647242
Directory /workspace/49.alert_handler_lpg/latest

Test location /workspace/coverage/default/49.alert_handler_lpg_stub_clk.3195709314
Short name T686
Test name
Test status
Simulation time 26962969450 ps
CPU time 1388.97 seconds
Started Jul 20 06:43:38 PM PDT 24
Finished Jul 20 07:06:49 PM PDT 24
Peak memory 273456 kb
Host smart-026efdee-d554-4f84-93be-1829aee5d2df
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195709314 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg_stub_clk.3195709314
Directory /workspace/49.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/49.alert_handler_ping_timeout.3193189087
Short name T175
Test name
Test status
Simulation time 5416012540 ps
CPU time 107.33 seconds
Started Jul 20 06:43:38 PM PDT 24
Finished Jul 20 06:45:27 PM PDT 24
Peak memory 247956 kb
Host smart-a7e7eafd-a39c-4a7c-8352-810f7079b540
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193189087 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_ping_timeout.3193189087
Directory /workspace/49.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_random_alerts.714606986
Short name T208
Test name
Test status
Simulation time 5908794130 ps
CPU time 32.81 seconds
Started Jul 20 06:43:39 PM PDT 24
Finished Jul 20 06:44:13 PM PDT 24
Peak memory 257240 kb
Host smart-7418c707-f6fa-4af3-81c0-78253a8a1748
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71460
6986 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_alerts.714606986
Directory /workspace/49.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/49.alert_handler_random_classes.1648544206
Short name T640
Test name
Test status
Simulation time 1378676182 ps
CPU time 24.66 seconds
Started Jul 20 06:43:39 PM PDT 24
Finished Jul 20 06:44:05 PM PDT 24
Peak memory 248756 kb
Host smart-7f8792a5-d168-424d-9741-b3a312a25686
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16485
44206 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_classes.1648544206
Directory /workspace/49.alert_handler_random_classes/latest

Test location /workspace/coverage/default/49.alert_handler_sig_int_fail.1968239600
Short name T648
Test name
Test status
Simulation time 581025470 ps
CPU time 35.03 seconds
Started Jul 20 06:43:30 PM PDT 24
Finished Jul 20 06:44:06 PM PDT 24
Peak memory 248252 kb
Host smart-fafd8fb5-c47e-4739-bdcf-84953c85eaca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19682
39600 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_sig_int_fail.1968239600
Directory /workspace/49.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/49.alert_handler_smoke.3042930039
Short name T620
Test name
Test status
Simulation time 1713273192 ps
CPU time 34.37 seconds
Started Jul 20 06:43:28 PM PDT 24
Finished Jul 20 06:44:04 PM PDT 24
Peak memory 256216 kb
Host smart-9695a24b-d57f-472b-aa35-7700d7388f8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30429
30039 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_smoke.3042930039
Directory /workspace/49.alert_handler_smoke/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all.4032576987
Short name T43
Test name
Test status
Simulation time 3908549995 ps
CPU time 101.75 seconds
Started Jul 20 06:43:28 PM PDT 24
Finished Jul 20 06:45:11 PM PDT 24
Peak memory 257236 kb
Host smart-8cd4a3bf-534f-4543-ad89-ab6830e47a2c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032576987 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_ha
ndler_stress_all.4032576987
Directory /workspace/49.alert_handler_stress_all/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all_with_rand_reset.3475380957
Short name T36
Test name
Test status
Simulation time 28562078227 ps
CPU time 3135.37 seconds
Started Jul 20 06:43:28 PM PDT 24
Finished Jul 20 07:35:45 PM PDT 24
Peak memory 322492 kb
Host smart-3e6ebc2f-5a5c-4c38-8d53-a3e91255bfdc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475380957 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 49.alert_handler_stress_all_with_rand_reset.3475380957
Directory /workspace/49.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.alert_handler_alert_accum_saturation.3273498521
Short name T198
Test name
Test status
Simulation time 60925470 ps
CPU time 2.83 seconds
Started Jul 20 06:41:01 PM PDT 24
Finished Jul 20 06:41:04 PM PDT 24
Peak memory 249320 kb
Host smart-19866f0c-cd76-4752-a9b5-83d388563b90
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3273498521 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_alert_accum_saturation.3273498521
Directory /workspace/5.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/5.alert_handler_entropy.512131961
Short name T519
Test name
Test status
Simulation time 41033512705 ps
CPU time 967.67 seconds
Started Jul 20 06:40:59 PM PDT 24
Finished Jul 20 06:57:08 PM PDT 24
Peak memory 273364 kb
Host smart-68560572-c4d5-4fd6-abf8-82bbbda20602
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=512131961 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy.512131961
Directory /workspace/5.alert_handler_entropy/latest

Test location /workspace/coverage/default/5.alert_handler_entropy_stress.3242957091
Short name T398
Test name
Test status
Simulation time 586857722 ps
CPU time 9.46 seconds
Started Jul 20 06:40:58 PM PDT 24
Finished Jul 20 06:41:09 PM PDT 24
Peak memory 248988 kb
Host smart-1791c49d-d0fc-4706-9703-a8ecd905bb06
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3242957091 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy_stress.3242957091
Directory /workspace/5.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/5.alert_handler_esc_alert_accum.3771395353
Short name T658
Test name
Test status
Simulation time 1340010386 ps
CPU time 134.62 seconds
Started Jul 20 06:40:57 PM PDT 24
Finished Jul 20 06:43:13 PM PDT 24
Peak memory 257188 kb
Host smart-4f29838a-635a-4952-8027-f7de1addf4f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37713
95353 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_alert_accum.3771395353
Directory /workspace/5.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/5.alert_handler_esc_intr_timeout.248963566
Short name T400
Test name
Test status
Simulation time 305980889 ps
CPU time 19.69 seconds
Started Jul 20 06:40:58 PM PDT 24
Finished Jul 20 06:41:19 PM PDT 24
Peak memory 248388 kb
Host smart-1a2eafb3-ecf8-4a45-8384-f53da6f46671
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24896
3566 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_intr_timeout.248963566
Directory /workspace/5.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_lpg.731294776
Short name T707
Test name
Test status
Simulation time 10454021558 ps
CPU time 943.37 seconds
Started Jul 20 06:40:57 PM PDT 24
Finished Jul 20 06:56:42 PM PDT 24
Peak memory 273672 kb
Host smart-8f106319-369b-44d9-a20b-222d75329adc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731294776 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg.731294776
Directory /workspace/5.alert_handler_lpg/latest

Test location /workspace/coverage/default/5.alert_handler_lpg_stub_clk.1721338434
Short name T346
Test name
Test status
Simulation time 50974284411 ps
CPU time 2915 seconds
Started Jul 20 06:40:57 PM PDT 24
Finished Jul 20 07:29:33 PM PDT 24
Peak memory 289540 kb
Host smart-18611fae-1270-47d5-a5de-698d6645afec
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721338434 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg_stub_clk.1721338434
Directory /workspace/5.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/5.alert_handler_ping_timeout.2809943284
Short name T330
Test name
Test status
Simulation time 16844883372 ps
CPU time 226.16 seconds
Started Jul 20 06:42:26 PM PDT 24
Finished Jul 20 06:46:13 PM PDT 24
Peak memory 248504 kb
Host smart-9f3b5017-4a49-40b8-81cc-4035cc32e114
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809943284 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_ping_timeout.2809943284
Directory /workspace/5.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_random_alerts.3203202127
Short name T520
Test name
Test status
Simulation time 601612899 ps
CPU time 39.68 seconds
Started Jul 20 06:40:57 PM PDT 24
Finished Jul 20 06:41:38 PM PDT 24
Peak memory 256280 kb
Host smart-0dbd7bd0-e17e-4db9-9f4c-1616201cd597
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32032
02127 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_alerts.3203202127
Directory /workspace/5.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/5.alert_handler_random_classes.266430883
Short name T507
Test name
Test status
Simulation time 617752447 ps
CPU time 41.03 seconds
Started Jul 20 06:41:23 PM PDT 24
Finished Jul 20 06:42:06 PM PDT 24
Peak memory 257076 kb
Host smart-f62e0e47-ded4-4f6f-a7f9-17e3c266a236
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26643
0883 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_classes.266430883
Directory /workspace/5.alert_handler_random_classes/latest

Test location /workspace/coverage/default/5.alert_handler_sig_int_fail.969444069
Short name T684
Test name
Test status
Simulation time 219525415 ps
CPU time 8.15 seconds
Started Jul 20 06:41:10 PM PDT 24
Finished Jul 20 06:41:20 PM PDT 24
Peak memory 248980 kb
Host smart-18a64e80-e4ab-49ac-9afb-e975f073a7aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96944
4069 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_sig_int_fail.969444069
Directory /workspace/5.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/5.alert_handler_smoke.816985525
Short name T268
Test name
Test status
Simulation time 1301170158 ps
CPU time 25.38 seconds
Started Jul 20 06:41:09 PM PDT 24
Finished Jul 20 06:41:37 PM PDT 24
Peak memory 256984 kb
Host smart-e5ef2997-2ade-46ff-bfa7-5d4239d8c505
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81698
5525 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_smoke.816985525
Directory /workspace/5.alert_handler_smoke/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all.1219156585
Short name T51
Test name
Test status
Simulation time 12061392588 ps
CPU time 1050.62 seconds
Started Jul 20 06:41:24 PM PDT 24
Finished Jul 20 06:58:56 PM PDT 24
Peak memory 273708 kb
Host smart-4601b755-35e3-440d-ba71-ef26ad804dc0
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219156585 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_han
dler_stress_all.1219156585
Directory /workspace/5.alert_handler_stress_all/latest

Test location /workspace/coverage/default/6.alert_handler_alert_accum_saturation.1864424036
Short name T193
Test name
Test status
Simulation time 34891670 ps
CPU time 3.65 seconds
Started Jul 20 06:41:08 PM PDT 24
Finished Jul 20 06:41:12 PM PDT 24
Peak memory 249216 kb
Host smart-c46d1663-b118-4f7a-a418-495e6b52b59b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1864424036 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_alert_accum_saturation.1864424036
Directory /workspace/6.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/6.alert_handler_entropy.3617903411
Short name T551
Test name
Test status
Simulation time 7398865688 ps
CPU time 730.13 seconds
Started Jul 20 06:42:26 PM PDT 24
Finished Jul 20 06:54:37 PM PDT 24
Peak memory 265180 kb
Host smart-72b9b2a0-a12e-4c75-aec4-04e135ee968f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617903411 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy.3617903411
Directory /workspace/6.alert_handler_entropy/latest

Test location /workspace/coverage/default/6.alert_handler_entropy_stress.1169280033
Short name T603
Test name
Test status
Simulation time 635955756 ps
CPU time 18.71 seconds
Started Jul 20 06:41:05 PM PDT 24
Finished Jul 20 06:41:25 PM PDT 24
Peak memory 248920 kb
Host smart-8208e304-4734-4ee9-8262-c4bf99abaaab
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1169280033 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy_stress.1169280033
Directory /workspace/6.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/6.alert_handler_esc_alert_accum.4210361098
Short name T679
Test name
Test status
Simulation time 1060388618 ps
CPU time 32.84 seconds
Started Jul 20 06:40:59 PM PDT 24
Finished Jul 20 06:41:33 PM PDT 24
Peak memory 256724 kb
Host smart-7d5e5930-0232-4d48-8845-190080d930fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42103
61098 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_alert_accum.4210361098
Directory /workspace/6.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/6.alert_handler_esc_intr_timeout.1995325327
Short name T74
Test name
Test status
Simulation time 350004227 ps
CPU time 33.34 seconds
Started Jul 20 06:40:57 PM PDT 24
Finished Jul 20 06:41:32 PM PDT 24
Peak memory 256716 kb
Host smart-726c4168-1268-45ac-ba12-2351a09dd321
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19953
25327 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_intr_timeout.1995325327
Directory /workspace/6.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_lpg.1435123371
Short name T641
Test name
Test status
Simulation time 63590463256 ps
CPU time 2181.48 seconds
Started Jul 20 06:41:20 PM PDT 24
Finished Jul 20 07:17:42 PM PDT 24
Peak memory 281872 kb
Host smart-5a914343-440a-40c2-8f25-a9d642d3a341
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435123371 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg.1435123371
Directory /workspace/6.alert_handler_lpg/latest

Test location /workspace/coverage/default/6.alert_handler_lpg_stub_clk.4079722400
Short name T111
Test name
Test status
Simulation time 13539496146 ps
CPU time 719.89 seconds
Started Jul 20 06:40:58 PM PDT 24
Finished Jul 20 06:52:59 PM PDT 24
Peak memory 273120 kb
Host smart-094b2962-f8b3-41a2-ac2e-43974949856d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079722400 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg_stub_clk.4079722400
Directory /workspace/6.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/6.alert_handler_ping_timeout.748128825
Short name T516
Test name
Test status
Simulation time 8404144000 ps
CPU time 171.98 seconds
Started Jul 20 06:41:01 PM PDT 24
Finished Jul 20 06:43:53 PM PDT 24
Peak memory 249120 kb
Host smart-e46112dc-e8da-49c2-8f71-5d8083e911d9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748128825 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_ping_timeout.748128825
Directory /workspace/6.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_random_alerts.3967769292
Short name T506
Test name
Test status
Simulation time 227024092 ps
CPU time 16.75 seconds
Started Jul 20 06:41:07 PM PDT 24
Finished Jul 20 06:41:25 PM PDT 24
Peak memory 248992 kb
Host smart-7e57494e-e422-4605-8a90-f638f9b499d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39677
69292 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_alerts.3967769292
Directory /workspace/6.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/6.alert_handler_random_classes.4252842321
Short name T282
Test name
Test status
Simulation time 779340820 ps
CPU time 47.21 seconds
Started Jul 20 06:40:58 PM PDT 24
Finished Jul 20 06:41:47 PM PDT 24
Peak memory 256252 kb
Host smart-adfb37ea-7a98-4455-87d7-cabc0e35d867
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42528
42321 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_classes.4252842321
Directory /workspace/6.alert_handler_random_classes/latest

Test location /workspace/coverage/default/6.alert_handler_sig_int_fail.1117371097
Short name T374
Test name
Test status
Simulation time 322459686 ps
CPU time 19.92 seconds
Started Jul 20 06:42:26 PM PDT 24
Finished Jul 20 06:42:47 PM PDT 24
Peak memory 255616 kb
Host smart-a3da1e52-f823-42ab-865e-03b8f1ab96af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11173
71097 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_sig_int_fail.1117371097
Directory /workspace/6.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/6.alert_handler_smoke.4031345683
Short name T362
Test name
Test status
Simulation time 2371320256 ps
CPU time 22.08 seconds
Started Jul 20 06:41:05 PM PDT 24
Finished Jul 20 06:41:28 PM PDT 24
Peak memory 257236 kb
Host smart-d8211324-074e-4c44-a78b-41bdfd261e88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40313
45683 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_smoke.4031345683
Directory /workspace/6.alert_handler_smoke/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all.2032499281
Short name T41
Test name
Test status
Simulation time 28681809020 ps
CPU time 2564.46 seconds
Started Jul 20 06:41:04 PM PDT 24
Finished Jul 20 07:23:49 PM PDT 24
Peak memory 306448 kb
Host smart-7a307ffc-29af-41e3-8a7a-aa248a7abda9
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032499281 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_han
dler_stress_all.2032499281
Directory /workspace/6.alert_handler_stress_all/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all_with_rand_reset.424347394
Short name T92
Test name
Test status
Simulation time 163979863922 ps
CPU time 3446.83 seconds
Started Jul 20 06:41:24 PM PDT 24
Finished Jul 20 07:38:52 PM PDT 24
Peak memory 322560 kb
Host smart-103c84aa-43ed-4545-a83c-e7b452c6f6df
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424347394 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 6.alert_handler_stress_all_with_rand_reset.424347394
Directory /workspace/6.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.alert_handler_alert_accum_saturation.997003462
Short name T192
Test name
Test status
Simulation time 51283139 ps
CPU time 2.93 seconds
Started Jul 20 06:41:19 PM PDT 24
Finished Jul 20 06:41:22 PM PDT 24
Peak memory 249256 kb
Host smart-150314f5-fb9e-4480-b7d1-197b70292097
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=997003462 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_alert_accum_saturation.997003462
Directory /workspace/7.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/7.alert_handler_esc_alert_accum.1553112568
Short name T58
Test name
Test status
Simulation time 6478643800 ps
CPU time 167.62 seconds
Started Jul 20 06:41:09 PM PDT 24
Finished Jul 20 06:43:59 PM PDT 24
Peak memory 257280 kb
Host smart-894ebd79-d430-458f-9d62-267b8ab7831e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15531
12568 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_alert_accum.1553112568
Directory /workspace/7.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/7.alert_handler_esc_intr_timeout.630928417
Short name T583
Test name
Test status
Simulation time 467795428 ps
CPU time 34.7 seconds
Started Jul 20 06:41:06 PM PDT 24
Finished Jul 20 06:41:42 PM PDT 24
Peak memory 248688 kb
Host smart-fdcf0f85-d223-4e9f-88d1-c4676b5b668d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63092
8417 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_intr_timeout.630928417
Directory /workspace/7.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_lpg.4191514195
Short name T303
Test name
Test status
Simulation time 46750765093 ps
CPU time 1429.02 seconds
Started Jul 20 06:41:09 PM PDT 24
Finished Jul 20 07:05:01 PM PDT 24
Peak memory 288436 kb
Host smart-c28513e4-23f3-433c-81a2-0e60a67840fd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191514195 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg.4191514195
Directory /workspace/7.alert_handler_lpg/latest

Test location /workspace/coverage/default/7.alert_handler_lpg_stub_clk.2456903008
Short name T573
Test name
Test status
Simulation time 19174505900 ps
CPU time 901.24 seconds
Started Jul 20 06:41:05 PM PDT 24
Finished Jul 20 06:56:07 PM PDT 24
Peak memory 273056 kb
Host smart-7c19b342-7d66-4367-bed4-9ef134ee7a09
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2456903008 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg_stub_clk.2456903008
Directory /workspace/7.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/7.alert_handler_ping_timeout.1497358071
Short name T311
Test name
Test status
Simulation time 22585861561 ps
CPU time 240.7 seconds
Started Jul 20 06:41:09 PM PDT 24
Finished Jul 20 06:45:12 PM PDT 24
Peak memory 255592 kb
Host smart-a238818f-730e-4459-9e98-b451a0be7547
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497358071 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_ping_timeout.1497358071
Directory /workspace/7.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_random_alerts.1385438381
Short name T604
Test name
Test status
Simulation time 10296259138 ps
CPU time 72.8 seconds
Started Jul 20 06:41:10 PM PDT 24
Finished Jul 20 06:42:25 PM PDT 24
Peak memory 249040 kb
Host smart-e53ef1ea-1880-4a48-9216-307112c91c1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13854
38381 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_alerts.1385438381
Directory /workspace/7.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/7.alert_handler_random_classes.3714927510
Short name T664
Test name
Test status
Simulation time 1147981402 ps
CPU time 19.24 seconds
Started Jul 20 06:41:04 PM PDT 24
Finished Jul 20 06:41:24 PM PDT 24
Peak memory 248160 kb
Host smart-14ab456a-ad90-489b-b2e7-e4e12426f895
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37149
27510 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_classes.3714927510
Directory /workspace/7.alert_handler_random_classes/latest

Test location /workspace/coverage/default/7.alert_handler_sig_int_fail.521139170
Short name T52
Test name
Test status
Simulation time 954748071 ps
CPU time 32.56 seconds
Started Jul 20 06:41:25 PM PDT 24
Finished Jul 20 06:42:00 PM PDT 24
Peak memory 248852 kb
Host smart-67388d48-6116-4c85-81ef-2132d1901937
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52113
9170 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_sig_int_fail.521139170
Directory /workspace/7.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/7.alert_handler_smoke.471274426
Short name T655
Test name
Test status
Simulation time 178584762 ps
CPU time 12.01 seconds
Started Jul 20 06:41:04 PM PDT 24
Finished Jul 20 06:41:16 PM PDT 24
Peak memory 254100 kb
Host smart-5d274db0-c333-40ec-9472-0f5d2190a354
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47127
4426 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_smoke.471274426
Directory /workspace/7.alert_handler_smoke/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all.3541261973
Short name T365
Test name
Test status
Simulation time 538456537 ps
CPU time 11.74 seconds
Started Jul 20 06:41:04 PM PDT 24
Finished Jul 20 06:41:17 PM PDT 24
Peak memory 254104 kb
Host smart-41320c96-d3a5-407b-b5d9-0c962d1df1c5
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541261973 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_han
dler_stress_all.3541261973
Directory /workspace/7.alert_handler_stress_all/latest

Test location /workspace/coverage/default/8.alert_handler_alert_accum_saturation.1661599681
Short name T197
Test name
Test status
Simulation time 36213063 ps
CPU time 3.76 seconds
Started Jul 20 06:41:09 PM PDT 24
Finished Jul 20 06:41:14 PM PDT 24
Peak memory 249236 kb
Host smart-3aa9b8fc-f5f4-4872-97b4-eb2b34a9ade5
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1661599681 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_alert_accum_saturation.1661599681
Directory /workspace/8.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/8.alert_handler_entropy.1751329708
Short name T673
Test name
Test status
Simulation time 236154543705 ps
CPU time 1723.94 seconds
Started Jul 20 06:41:09 PM PDT 24
Finished Jul 20 07:09:56 PM PDT 24
Peak memory 289428 kb
Host smart-c612822b-03ab-4d04-891e-cadc463fd006
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751329708 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy.1751329708
Directory /workspace/8.alert_handler_entropy/latest

Test location /workspace/coverage/default/8.alert_handler_entropy_stress.656233920
Short name T61
Test name
Test status
Simulation time 284524413 ps
CPU time 13.29 seconds
Started Jul 20 06:41:23 PM PDT 24
Finished Jul 20 06:41:38 PM PDT 24
Peak memory 248988 kb
Host smart-bc5672e9-2e5a-43be-893e-c09913c1b5d2
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=656233920 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy_stress.656233920
Directory /workspace/8.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/8.alert_handler_esc_alert_accum.2571082978
Short name T609
Test name
Test status
Simulation time 1731069631 ps
CPU time 103.15 seconds
Started Jul 20 06:41:23 PM PDT 24
Finished Jul 20 06:43:07 PM PDT 24
Peak memory 256744 kb
Host smart-13476449-e1c1-48d2-a894-37a75980078a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25710
82978 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_alert_accum.2571082978
Directory /workspace/8.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/8.alert_handler_esc_intr_timeout.453502469
Short name T627
Test name
Test status
Simulation time 694344279 ps
CPU time 16.28 seconds
Started Jul 20 06:41:20 PM PDT 24
Finished Jul 20 06:41:37 PM PDT 24
Peak memory 253476 kb
Host smart-85e72e6f-db73-4ddb-bb78-c5e74ba09cf4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45350
2469 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_intr_timeout.453502469
Directory /workspace/8.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_lpg.2515933767
Short name T349
Test name
Test status
Simulation time 54896297688 ps
CPU time 3271.65 seconds
Started Jul 20 06:41:21 PM PDT 24
Finished Jul 20 07:35:54 PM PDT 24
Peak memory 289488 kb
Host smart-20f8dbd8-7e45-4fe3-9b7f-839f37a9103c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515933767 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg.2515933767
Directory /workspace/8.alert_handler_lpg/latest

Test location /workspace/coverage/default/8.alert_handler_lpg_stub_clk.3261198888
Short name T584
Test name
Test status
Simulation time 16125835746 ps
CPU time 804.53 seconds
Started Jul 20 06:41:10 PM PDT 24
Finished Jul 20 06:54:36 PM PDT 24
Peak memory 272992 kb
Host smart-f8ffa6c6-a44a-4b3b-84f3-a9578e6ccbbd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3261198888 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg_stub_clk.3261198888
Directory /workspace/8.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/8.alert_handler_ping_timeout.2681108083
Short name T694
Test name
Test status
Simulation time 38396716686 ps
CPU time 385.84 seconds
Started Jul 20 06:41:10 PM PDT 24
Finished Jul 20 06:47:38 PM PDT 24
Peak memory 248912 kb
Host smart-d8f29b4e-9bf5-4f41-9f00-4109e0d6b91c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2681108083 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_ping_timeout.2681108083
Directory /workspace/8.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_random_alerts.3742930498
Short name T415
Test name
Test status
Simulation time 763472998 ps
CPU time 47.34 seconds
Started Jul 20 06:41:08 PM PDT 24
Finished Jul 20 06:41:56 PM PDT 24
Peak memory 249008 kb
Host smart-1f7fb470-e574-42dd-a26d-8ef47d24dfee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37429
30498 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_alerts.3742930498
Directory /workspace/8.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/8.alert_handler_random_classes.2301062596
Short name T97
Test name
Test status
Simulation time 120891898 ps
CPU time 8.8 seconds
Started Jul 20 06:41:10 PM PDT 24
Finished Jul 20 06:41:21 PM PDT 24
Peak memory 251796 kb
Host smart-e39aa473-7674-4b33-afb0-57271d8362ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23010
62596 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_classes.2301062596
Directory /workspace/8.alert_handler_random_classes/latest

Test location /workspace/coverage/default/8.alert_handler_sig_int_fail.774501559
Short name T442
Test name
Test status
Simulation time 214270644 ps
CPU time 24.81 seconds
Started Jul 20 06:41:22 PM PDT 24
Finished Jul 20 06:41:48 PM PDT 24
Peak memory 249040 kb
Host smart-bdd7b06f-80f3-4759-96ea-ae00a3ef6c3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77450
1559 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_sig_int_fail.774501559
Directory /workspace/8.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/8.alert_handler_smoke.3172230242
Short name T213
Test name
Test status
Simulation time 844891458 ps
CPU time 61.84 seconds
Started Jul 20 06:41:05 PM PDT 24
Finished Jul 20 06:42:07 PM PDT 24
Peak memory 257156 kb
Host smart-979c1599-9847-4f14-928e-b42c4f9ddeae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31722
30242 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_smoke.3172230242
Directory /workspace/8.alert_handler_smoke/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all.1550499669
Short name T252
Test name
Test status
Simulation time 803257028 ps
CPU time 84.75 seconds
Started Jul 20 06:41:18 PM PDT 24
Finished Jul 20 06:42:44 PM PDT 24
Peak memory 257184 kb
Host smart-8b5e2169-453f-4b73-8a3f-29ff15c81a7c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550499669 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_han
dler_stress_all.1550499669
Directory /workspace/8.alert_handler_stress_all/latest

Test location /workspace/coverage/default/9.alert_handler_alert_accum_saturation.2705755797
Short name T187
Test name
Test status
Simulation time 161049142 ps
CPU time 2.28 seconds
Started Jul 20 06:41:10 PM PDT 24
Finished Jul 20 06:41:14 PM PDT 24
Peak memory 249120 kb
Host smart-4bfc45ad-aa03-4516-9bd9-631433be6401
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2705755797 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_alert_accum_saturation.2705755797
Directory /workspace/9.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/9.alert_handler_entropy.451968802
Short name T478
Test name
Test status
Simulation time 45703241880 ps
CPU time 2219.2 seconds
Started Jul 20 06:41:23 PM PDT 24
Finished Jul 20 07:18:23 PM PDT 24
Peak memory 273588 kb
Host smart-6e4f71fc-be49-44b0-9324-2d6e09721155
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451968802 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy.451968802
Directory /workspace/9.alert_handler_entropy/latest

Test location /workspace/coverage/default/9.alert_handler_entropy_stress.4001422712
Short name T493
Test name
Test status
Simulation time 1209011264 ps
CPU time 10.87 seconds
Started Jul 20 06:41:19 PM PDT 24
Finished Jul 20 06:41:30 PM PDT 24
Peak memory 248948 kb
Host smart-51cfe67a-2cc5-4d81-884a-82fcd039d97e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4001422712 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy_stress.4001422712
Directory /workspace/9.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/9.alert_handler_esc_alert_accum.3836788457
Short name T428
Test name
Test status
Simulation time 1602154455 ps
CPU time 161.03 seconds
Started Jul 20 06:41:09 PM PDT 24
Finished Jul 20 06:43:52 PM PDT 24
Peak memory 256712 kb
Host smart-a49133be-36f5-4b33-8ef5-c0d46f4f53fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38367
88457 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_alert_accum.3836788457
Directory /workspace/9.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/9.alert_handler_esc_intr_timeout.2950769917
Short name T692
Test name
Test status
Simulation time 2541768649 ps
CPU time 34.58 seconds
Started Jul 20 06:41:09 PM PDT 24
Finished Jul 20 06:41:46 PM PDT 24
Peak memory 249060 kb
Host smart-6fe7956b-2b49-435f-9ee1-83e30164faab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29507
69917 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_intr_timeout.2950769917
Directory /workspace/9.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_lpg.3848957247
Short name T645
Test name
Test status
Simulation time 215532100319 ps
CPU time 3107.17 seconds
Started Jul 20 06:41:04 PM PDT 24
Finished Jul 20 07:32:52 PM PDT 24
Peak memory 281888 kb
Host smart-30db6924-eaca-45ca-8cac-da9c8c32e53c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848957247 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg.3848957247
Directory /workspace/9.alert_handler_lpg/latest

Test location /workspace/coverage/default/9.alert_handler_lpg_stub_clk.2255996636
Short name T465
Test name
Test status
Simulation time 164286287409 ps
CPU time 2476.55 seconds
Started Jul 20 06:41:11 PM PDT 24
Finished Jul 20 07:22:30 PM PDT 24
Peak memory 283916 kb
Host smart-5180636e-4aec-4238-8948-60fb3cfc0501
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255996636 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg_stub_clk.2255996636
Directory /workspace/9.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/9.alert_handler_ping_timeout.2273320566
Short name T530
Test name
Test status
Simulation time 19941364146 ps
CPU time 136.86 seconds
Started Jul 20 06:41:05 PM PDT 24
Finished Jul 20 06:43:23 PM PDT 24
Peak memory 249088 kb
Host smart-eaebc63d-6db3-499a-ab75-750956594a09
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273320566 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_ping_timeout.2273320566
Directory /workspace/9.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_random_alerts.2698526211
Short name T371
Test name
Test status
Simulation time 527632136 ps
CPU time 24.58 seconds
Started Jul 20 06:41:20 PM PDT 24
Finished Jul 20 06:41:45 PM PDT 24
Peak memory 248884 kb
Host smart-c801f6fb-f02d-49f4-a997-53ab7f9d0b34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26985
26211 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_alerts.2698526211
Directory /workspace/9.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/9.alert_handler_random_classes.3102383874
Short name T512
Test name
Test status
Simulation time 592832136 ps
CPU time 18.4 seconds
Started Jul 20 06:41:06 PM PDT 24
Finished Jul 20 06:41:25 PM PDT 24
Peak memory 248724 kb
Host smart-c0f77443-b706-4c75-ad1e-627b3ebbb652
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31023
83874 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_classes.3102383874
Directory /workspace/9.alert_handler_random_classes/latest

Test location /workspace/coverage/default/9.alert_handler_sig_int_fail.3229567397
Short name T538
Test name
Test status
Simulation time 713613881 ps
CPU time 50.29 seconds
Started Jul 20 06:41:08 PM PDT 24
Finished Jul 20 06:41:59 PM PDT 24
Peak memory 256616 kb
Host smart-397d086f-a2f5-461d-be1a-62c11c7db7e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32295
67397 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_sig_int_fail.3229567397
Directory /workspace/9.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/9.alert_handler_smoke.3857815556
Short name T569
Test name
Test status
Simulation time 3219955976 ps
CPU time 47.83 seconds
Started Jul 20 06:41:15 PM PDT 24
Finished Jul 20 06:42:04 PM PDT 24
Peak memory 257252 kb
Host smart-6c9e88bb-a0ce-4107-acd5-9010c6f5ab4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38578
15556 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_smoke.3857815556
Directory /workspace/9.alert_handler_smoke/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all.3951202920
Short name T73
Test name
Test status
Simulation time 58958306918 ps
CPU time 1665.01 seconds
Started Jul 20 06:41:09 PM PDT 24
Finished Jul 20 07:08:57 PM PDT 24
Peak memory 289324 kb
Host smart-5d313b90-2e08-41b1-a32b-464453190350
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951202920 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_han
dler_stress_all.3951202920
Directory /workspace/9.alert_handler_stress_all/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all_with_rand_reset.3757457199
Short name T184
Test name
Test status
Simulation time 94067492771 ps
CPU time 5492.61 seconds
Started Jul 20 06:41:07 PM PDT 24
Finished Jul 20 08:12:41 PM PDT 24
Peak memory 354680 kb
Host smart-c7a06b4f-818e-4899-96b2-58847006d6a2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757457199 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 9.alert_handler_stress_all_with_rand_reset.3757457199
Directory /workspace/9.alert_handler_stress_all_with_rand_reset/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%