Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
esc_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	8	0	8	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	81675	1			T3	6		T14	8		T49	11
class_i[0x1]	49345	1			T21	276		T17	4624		T26	2
class_i[0x2]	57262	1			T3	12		T13	5183		T14	15
class_i[0x3]	76172	1			T13	4		T6	4		T17	3879

---

Summary for Variable esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	63632	1			T3	1		T21	24		T13	1276
alert[0x1]	66861	1			T3	8		T21	10		T13	1267
alert[0x2]	66844	1			T3	4		T21	14		T13	1383
alert[0x3]	67117	1			T3	5		T21	228		T13	1261

---

Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

esc_integrity_fail

264179

1

T3

18

T21

276

T13

5187

esc_ping_fail

275

1

T6

4

T8

3

T9

11

---

Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	esc_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	alert[0x0]	63564	1			T3	1		T21	24		T13	1276
esc_integrity_fail	alert[0x1]	66775	1			T3	8		T21	10		T13	1267
esc_integrity_fail	alert[0x2]	66781	1			T3	4		T21	14		T13	1383
esc_integrity_fail	alert[0x3]	67059	1			T3	5		T21	228		T13	1261
esc_ping_fail	alert[0x0]	68	1			T8	1		T9	5		T324	1
esc_ping_fail	alert[0x1]	86	1			T6	1		T8	1		T9	2
esc_ping_fail	alert[0x2]	63	1			T6	2		T9	2		T79	2
esc_ping_fail	alert[0x3]	58	1			T6	1		T8	1		T9	2

---

Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	class_i[0x0]	81616	1			T3	6		T14	8		T49	11
esc_integrity_fail	class_i[0x1]	49272	1			T21	276		T17	4624		T26	2
esc_integrity_fail	class_i[0x2]	57187	1			T3	12		T13	5183		T14	15
esc_integrity_fail	class_i[0x3]	76104	1			T13	4		T17	3879		T26	59
esc_ping_fail	class_i[0x0]	59	1			T8	1		T79	4		T324	1
esc_ping_fail	class_i[0x1]	73	1			T327	8		T318	3		T315	1
esc_ping_fail	class_i[0x2]	75	1			T8	1		T9	1		T324	1
esc_ping_fail	class_i[0x3]	68	1			T6	4		T8	1		T9	10