Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.31	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	44	1	43	97.73

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_sig_index_cp	4	0	4	100.00	100	1	1	0
esc_sig_len_cp	11	0	11	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
len_per_esc_sig	44	1	43	97.73	100	1	1	0

Summary for Variable esc_sig_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_sig_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
index[0x0]	208	1			T13	1		T46	1		T49	1
index[0x1]	185	1			T25	6		T50	1		T23	4
index[0x2]	203	1			T13	1		T14	2		T16	1
index[0x3]	160	1			T3	1		T25	1		T51	1

---

Summary for Variable esc_sig_len_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for esc_sig_len_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
lens_less_than_1000[0]	213	1			T3	1		T25	1		T23	1
lens_less_than_1000[1]	151	1			T13	1		T23	3		T88	1
lens_less_than_1000[2]	91	1			T46	1		T25	5		T14	1
lens_less_than_1000[3]	97	1			T25	1		T14	1		T51	1
lens_less_than_1000[4]	64	1			T13	1		T17	7		T54	3
lens_less_than_1000[5]	39	1			T50	1		T23	1		T88	1
lens_less_than_1000[6]	44	1			T16	1		T49	1		T51	1
lens_less_than_1000[7]	21	1			T56	1		T117	1		T282	1
lens_less_than_1000[8]	21	1			T33	1		T59	1		T283	1
lens_less_than_1000[9]	8	1			T66	1		T119	1		T284	1
len_2	7	1			T270	1		T68	1		T285	1

---

Summary for Cross len_per_esc_sig

Samples crossed: esc_sig_index_cp esc_sig_len_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	44	1	43	97.73	1

Automatically Generated Cross Bins for len_per_esc_sig

Uncovered bins

esc_sig_index_cp	esc_sig_len_cp	COUNT	AT LEAST	NUMBER	STATUS
[index[0x0]]	[len_2]	0	1	1

Covered bins

esc_sig_index_cp	esc_sig_len_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
index[0x0]	lens_less_than_1000[0]	53	1			T54	1		T9	1		T33	1
index[0x0]	lens_less_than_1000[1]	46	1			T13	1		T17	1		T26	1
index[0x0]	lens_less_than_1000[2]	33	1			T46	1		T23	3		T286	1
index[0x0]	lens_less_than_1000[3]	23	1			T51	1		T287	1		T96	1
index[0x0]	lens_less_than_1000[4]	12	1			T33	1		T58	1		T288	1
index[0x0]	lens_less_than_1000[5]	16	1			T88	1		T96	1		T281	1
index[0x0]	lens_less_than_1000[6]	10	1			T49	1		T32	1		T289	1
index[0x0]	lens_less_than_1000[7]	5	1			T282	1		T290	1		T62	1
index[0x0]	lens_less_than_1000[8]	7	1			T197	1		T66	1		T291	1
index[0x0]	lens_less_than_1000[9]	3	1			T119	1		T206	1		T292	1
index[0x1]	lens_less_than_1000[0]	49	1			T25	1		T71	1		T28	1
index[0x1]	lens_less_than_1000[1]	33	1			T23	1		T26	1		T240	1
index[0x1]	lens_less_than_1000[2]	27	1			T25	5		T23	1		T32	2
index[0x1]	lens_less_than_1000[3]	29	1			T23	1		T59	1		T34	1
index[0x1]	lens_less_than_1000[4]	11	1			T32	1		T24	1		T197	1
index[0x1]	lens_less_than_1000[5]	8	1			T50	1		T41	1		T67	1
index[0x1]	lens_less_than_1000[6]	11	1			T23	1		T26	1		T97	1
index[0x1]	lens_less_than_1000[7]	7	1			T56	1		T201	1		T293	1
index[0x1]	lens_less_than_1000[8]	6	1			T67	1		T294	1		T273	1
index[0x1]	lens_less_than_1000[9]	2	1			T66	1		T295	1		-	-
index[0x1]	len_2	2	1			T68	1		T276	1		-	-
index[0x2]	lens_less_than_1000[0]	63	1			T32	1		T117	1		T239	1
index[0x2]	lens_less_than_1000[1]	34	1			T86	1		T7	1		T33	1
index[0x2]	lens_less_than_1000[2]	19	1			T14	1		T50	1		T96	1
index[0x2]	lens_less_than_1000[3]	18	1			T14	1		T26	1		T33	2
index[0x2]	lens_less_than_1000[4]	31	1			T13	1		T17	7		T54	1
index[0x2]	lens_less_than_1000[5]	6	1			T23	1		T253	1		T256	1
index[0x2]	lens_less_than_1000[6]	15	1			T16	1		T17	1		T33	1
index[0x2]	lens_less_than_1000[7]	8	1			T117	1		T290	1		T296	1
index[0x2]	lens_less_than_1000[8]	6	1			T59	1		T283	1		T286	1
index[0x2]	lens_less_than_1000[9]	1	1			T297	1		-	-		-	-
index[0x2]	len_2	2	1			T270	1		T285	1		-	-
index[0x3]	lens_less_than_1000[0]	48	1			T3	1		T23	1		T17	4
index[0x3]	lens_less_than_1000[1]	38	1			T23	2		T88	1		T298	1
index[0x3]	lens_less_than_1000[2]	12	1			T299	1		T59	1		T300	1
index[0x3]	lens_less_than_1000[3]	27	1			T25	1		T23	1		T33	1
index[0x3]	lens_less_than_1000[4]	10	1			T54	2		T197	1		T301	1
index[0x3]	lens_less_than_1000[5]	9	1			T82	1		T302	1		T303	1
index[0x3]	lens_less_than_1000[6]	8	1			T51	1		T304	1		T305	1
index[0x3]	lens_less_than_1000[7]	1	1			T306	1		-	-		-	-
index[0x3]	lens_less_than_1000[8]	2	1			T33	1		T307	1		-	-
index[0x3]	lens_less_than_1000[9]	2	1			T284	1		T297	1		-	-
index[0x3]	len_2	3	1			T245	1		T308	1		T309	1