Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.15	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	40	1	39	97.50

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
intr_timeout_cnt_cp	10	0	10	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	40	1	39	97.50	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	75	1			T25	1		T14	1		T49	1
class_index[0x1]	62	1			T25	1		T17	1		T26	1
class_index[0x2]	62	1			T3	2		T25	1		T49	1
class_index[0x3]	69	1			T25	1		T49	1		T87	1

---

Summary for Variable intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for intr_timeout_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
intr_timeout_cnt[0]	93	1			T3	2		T87	1		T23	4
intr_timeout_cnt[1]	70	1			T14	1		T17	2		T90	1
intr_timeout_cnt[2]	24	1			T25	1		T49	1		T84	1
intr_timeout_cnt[3]	14	1			T25	1		T58	1		T63	1
intr_timeout_cnt[4]	17	1			T25	1		T49	1		T17	1
intr_timeout_cnt[5]	14	1			T49	1		T101	1		T102	1
intr_timeout_cnt[6]	9	1			T113	1		T255	1		T66	1
intr_timeout_cnt[7]	9	1			T28	1		T85	1		T256	1
intr_timeout_cnt[8]	12	1			T56	1		T91	1		T256	1
intr_timeout_cnt[9]	6	1			T25	1		T28	1		T197	1

---

Summary for Cross class_cnt_cross

Samples crossed: class_index_cp intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	1	39	97.50	1

Automatically Generated Cross Bins for class_cnt_cross

Uncovered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	NUMBER	STATUS
[class_index[0x3]]	[intr_timeout_cnt[9]]	0	1	1

Covered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	intr_timeout_cnt[0]	30	1			T23	1		T26	2		T58	1
class_index[0x0]	intr_timeout_cnt[1]	20	1			T14	1		T17	2		T90	1
class_index[0x0]	intr_timeout_cnt[2]	8	1			T49	1		T257	1		T256	1
class_index[0x0]	intr_timeout_cnt[3]	5	1			T25	1		T58	1		T110	1
class_index[0x0]	intr_timeout_cnt[4]	2	1			T56	1		T258	1		-	-
class_index[0x0]	intr_timeout_cnt[5]	2	1			T259	1		T260	1		-	-
class_index[0x0]	intr_timeout_cnt[6]	1	1			T113	1		-	-		-	-
class_index[0x0]	intr_timeout_cnt[7]	1	1			T256	1		-	-		-	-
class_index[0x0]	intr_timeout_cnt[8]	4	1			T261	2		T262	1		T263	1
class_index[0x0]	intr_timeout_cnt[9]	2	1			T28	1		T206	1		-	-
class_index[0x1]	intr_timeout_cnt[0]	16	1			T26	1		T58	1		T93	1
class_index[0x1]	intr_timeout_cnt[1]	24	1			T89	1		T29	5		T264	1
class_index[0x1]	intr_timeout_cnt[2]	2	1			T92	1		T265	1		-	-
class_index[0x1]	intr_timeout_cnt[3]	4	1			T63	1		T123	1		T66	1
class_index[0x1]	intr_timeout_cnt[4]	3	1			T17	1		T266	1		T267	1
class_index[0x1]	intr_timeout_cnt[5]	3	1			T101	1		T102	1		T268	1
class_index[0x1]	intr_timeout_cnt[6]	1	1			T66	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[7]	2	1			T269	2		-	-		-	-
class_index[0x1]	intr_timeout_cnt[8]	4	1			T91	1		T270	1		T261	1
class_index[0x1]	intr_timeout_cnt[9]	3	1			T25	1		T68	1		T271	1
class_index[0x2]	intr_timeout_cnt[0]	28	1			T3	2		T23	2		T26	1
class_index[0x2]	intr_timeout_cnt[1]	14	1			T32	1		T197	1		T37	1
class_index[0x2]	intr_timeout_cnt[2]	5	1			T25	1		T272	1		T245	1
class_index[0x2]	intr_timeout_cnt[3]	1	1			T256	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[4]	3	1			T49	1		T273	1		T274	1
class_index[0x2]	intr_timeout_cnt[5]	2	1			T275	1		T276	1		-	-
class_index[0x2]	intr_timeout_cnt[6]	3	1			T103	1		T108	1		T206	1
class_index[0x2]	intr_timeout_cnt[7]	4	1			T85	1		T269	2		T277	1
class_index[0x2]	intr_timeout_cnt[8]	1	1			T56	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[9]	1	1			T197	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[0]	19	1			T87	1		T23	1		T58	1
class_index[0x3]	intr_timeout_cnt[1]	12	1			T89	1		T58	1		T92	1
class_index[0x3]	intr_timeout_cnt[2]	9	1			T84	1		T85	1		T67	1
class_index[0x3]	intr_timeout_cnt[3]	4	1			T278	1		T276	1		T279	1
class_index[0x3]	intr_timeout_cnt[4]	9	1			T25	1		T58	2		T198	2
class_index[0x3]	intr_timeout_cnt[5]	7	1			T49	1		T108	2		T280	1
class_index[0x3]	intr_timeout_cnt[6]	4	1			T255	1		T281	3		-	-
class_index[0x3]	intr_timeout_cnt[7]	2	1			T28	1		T270	1		-	-
class_index[0x3]	intr_timeout_cnt[8]	3	1			T256	1		T245	1		T277	1