Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	361694	1			T2	137		T3	3646		T19	5
all_values[1]	361694	1			T2	137		T3	3646		T19	5
all_values[2]	361694	1			T2	137		T3	3646		T19	5
all_values[3]	361694	1			T2	137		T3	3646		T19	5

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

719178

1

T2

266

T3

7284

T19

10

auto[1]

727598

1

T2

282

T3

7300

T19

10

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

858609

1

T2

277

T3

10273

T19

18

auto[1]

588167

1

T2

271

T3

4311

T19

2

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	101779	1			T2	34		T3	1195		T19	1
all_values[0]	auto[0]	auto[1]	77685	1			T2	33		T3	646		T19	1
all_values[0]	auto[1]	auto[0]	103745	1			T2	35		T3	1161		T19	2
all_values[0]	auto[1]	auto[1]	78485	1			T2	35		T3	644		T19	1
all_values[1]	auto[0]	auto[0]	107301	1			T2	30		T3	1357		T19	3
all_values[1]	auto[0]	auto[1]	72273	1			T2	29		T3	495		T4	360
all_values[1]	auto[1]	auto[0]	109494	1			T2	40		T3	1326		T19	2
all_values[1]	auto[1]	auto[1]	72626	1			T2	38		T3	468		T4	393
all_values[2]	auto[0]	auto[0]	109275	1			T2	30		T3	1310		T19	3
all_values[2]	auto[0]	auto[1]	71014	1			T2	30		T3	465		T4	374
all_values[2]	auto[1]	auto[0]	110551	1			T2	39		T3	1375		T19	2
all_values[2]	auto[1]	auto[1]	70854	1			T2	38		T3	496		T4	378
all_values[3]	auto[0]	auto[0]	107403	1			T2	40		T3	1276		T19	2
all_values[3]	auto[0]	auto[1]	72448	1			T2	40		T3	540		T4	364
all_values[3]	auto[1]	auto[0]	109061	1			T2	29		T3	1273		T19	3
all_values[3]	auto[1]	auto[1]	72782	1			T2	28		T3	557		T4	374