Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	4	0	4	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	361694	1			T2	137		T3	3646		T19	5
all_pins[1]	361694	1			T2	137		T3	3646		T19	5
all_pins[2]	361694	1			T2	137		T3	3646		T19	5
all_pins[3]	361694	1			T2	137		T3	3646		T19	5

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1152029	1			T2	409		T3	12419		T19	19
values[0x1]	294747	1			T2	139		T3	2165		T19	1
transitions[0x0=>0x1]	195985	1			T2	84		T3	1484		T19	1
transitions[0x1=>0x0]	196229	1			T2	84		T3	1485		T19	1

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	283209	1			T2	102		T3	3002		T19	4
all_pins[0]	values[0x1]	78485	1			T2	35		T3	644		T19	1
all_pins[0]	transitions[0x0=>0x1]	77785	1			T2	35		T3	642		T19	1
all_pins[0]	transitions[0x1=>0x0]	72326	1			T2	28		T3	556		T4	374
all_pins[1]	values[0x0]	289068	1			T2	99		T3	3178		T19	5
all_pins[1]	values[0x1]	72626	1			T2	38		T3	468		T4	393
all_pins[1]	transitions[0x0=>0x1]	39187	1			T2	17		T3	241		T4	179
all_pins[1]	transitions[0x1=>0x0]	45046	1			T2	14		T3	417		T19	1
all_pins[2]	values[0x0]	290840	1			T2	99		T3	3150		T19	5
all_pins[2]	values[0x1]	70854	1			T2	38		T3	496		T4	378
all_pins[2]	transitions[0x0=>0x1]	38498	1			T2	18		T3	288		T4	199
all_pins[2]	transitions[0x1=>0x0]	40270	1			T2	18		T3	260		T4	214
all_pins[3]	values[0x0]	288912	1			T2	109		T3	3089		T19	5
all_pins[3]	values[0x1]	72782	1			T2	28		T3	557		T4	374
all_pins[3]	transitions[0x0=>0x1]	40515	1			T2	14		T3	313		T4	183
all_pins[3]	transitions[0x1=>0x0]	38587	1			T2	24		T3	252		T4	187