Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
accum_cnt_cp	6	0	6	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	24	0	24	100.00	100	1	1	0

Summary for Variable accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for accum_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
accum_cnt_2000	87773	1			T3	482		T4	545		T13	268
accum_cnt_1000	230787	1			T2	37		T3	3257		T4	529
accum_cnt_100	27882	1			T2	15		T3	516		T4	28
accum_cnt_50	61387	1			T2	13		T3	440		T4	23
accum_cnt_10	204075	1			T2	62		T3	80		T4	7
accum_cnt_0	410170	1			T2	145		T3	6261		T19	16

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	266616	1			T2	68		T3	2759		T19	4
class_index[0x1]	266616	1			T2	68		T3	2759		T19	4
class_index[0x2]	266616	1			T2	68		T3	2759		T19	4
class_index[0x3]	266616	1			T2	68		T3	2759		T19	4

---

Summary for Cross class_cnt_cross

Samples crossed: class_index_cp accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for class_cnt_cross

Bins

class_index_cp	accum_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	accum_cnt_2000	23704	1			T3	482		T16	113		T23	114
class_index[0x0]	accum_cnt_1000	59496	1			T2	37		T3	1287		T16	73
class_index[0x0]	accum_cnt_100	7716	1			T2	15		T3	325		T16	5
class_index[0x0]	accum_cnt_50	16039	1			T2	13		T3	304		T21	12
class_index[0x0]	accum_cnt_10	47340	1			T2	3		T3	53		T20	25
class_index[0x0]	accum_cnt_0	96325	1			T3	308		T19	4		T4	1132
class_index[0x1]	accum_cnt_2000	26115	1			T4	545		T16	493		T17	493
class_index[0x1]	accum_cnt_1000	61347	1			T3	954		T4	529		T16	426
class_index[0x1]	accum_cnt_100	7103	1			T3	111		T4	28		T16	23
class_index[0x1]	accum_cnt_50	12755	1			T3	80		T4	23		T21	6
class_index[0x1]	accum_cnt_10	53540	1			T2	59		T3	17		T4	7
class_index[0x1]	accum_cnt_0	95958	1			T2	9		T3	1597		T19	4
class_index[0x2]	accum_cnt_2000	20224	1			T13	268		T14	670		T15	232
class_index[0x2]	accum_cnt_1000	55166	1			T3	777		T13	224		T14	563
class_index[0x2]	accum_cnt_100	6231	1			T3	48		T13	12		T14	36
class_index[0x2]	accum_cnt_50	15978	1			T3	37		T13	10		T52	8
class_index[0x2]	accum_cnt_10	52145	1			T3	7		T21	25		T5	1019
class_index[0x2]	accum_cnt_0	105160	1			T2	68		T3	1890		T19	4
class_index[0x3]	accum_cnt_2000	17730	1			T86	407		T54	17		T80	229
class_index[0x3]	accum_cnt_1000	54778	1			T3	239		T5	741		T23	28
class_index[0x3]	accum_cnt_100	6832	1			T3	32		T5	144		T23	39
class_index[0x3]	accum_cnt_50	16615	1			T3	19		T21	2		T5	98
class_index[0x3]	accum_cnt_10	51050	1			T3	3		T21	19		T5	41
class_index[0x3]	accum_cnt_0	112727	1			T2	68		T3	2466		T19	4