Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	71	0	71	100.00
Crosses	138	0	138	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
alert_index_cp	65	0	65	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	130	0	130	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for alert_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	5231	1			T3	112		T6	1		T49	3
alert[0x1]	1681	1			T3	21		T14	67		T16	72
alert[0x2]	11479	1			T3	35		T16	1521		T27	2
alert[0x3]	4803	1			T13	93		T16	5		T17	35
alert[0x4]	7293	1			T25	1		T17	3		T27	460
alert[0x5]	12554	1			T3	50		T13	349		T14	82
alert[0x6]	4114	1			T13	34		T14	56		T16	18
alert[0x7]	9196	1			T3	47		T6	1		T23	549
alert[0x8]	8640	1			T13	301		T6	1		T17	18
alert[0x9]	5053	1			T3	698		T17	904		T26	92
alert[0xa]	7918	1			T16	26		T23	324		T17	37
alert[0xb]	6360	1			T16	511		T6	1		T23	19
alert[0xc]	9230	1			T13	180		T14	750		T17	5
alert[0xd]	12587	1			T14	96		T17	199		T27	53
alert[0xe]	1222	1			T17	55		T237	70		T128	226
alert[0xf]	7052	1			T3	175		T13	296		T27	19
alert[0x10]	5564	1			T25	36		T14	79		T23	1906
alert[0x11]	3377	1			T16	28		T27	233		T9	1
alert[0x12]	9605	1			T3	378		T13	518		T14	58
alert[0x13]	8784	1			T3	34		T13	193		T25	7
alert[0x14]	3695	1			T3	560		T14	1027		T16	496
alert[0x15]	4386	1			T3	7		T49	2		T17	34
alert[0x16]	6926	1			T16	76		T23	1260		T17	5
alert[0x17]	1413	1			T13	55		T14	218		T23	3
alert[0x18]	4796	1			T25	3		T23	102		T17	24
alert[0x19]	3369	1			T3	31		T25	3		T14	35
alert[0x1a]	3723	1			T13	327		T16	847		T17	246
alert[0x1b]	11548	1			T3	50		T14	28		T16	512
alert[0x1c]	6832	1			T13	31		T14	20		T23	328
alert[0x1d]	8287	1			T14	25		T16	68		T26	19
alert[0x1e]	6168	1			T16	1538		T23	4		T17	182
alert[0x1f]	3548	1			T13	51		T25	1		T17	71
alert[0x20]	9684	1			T3	68		T13	120		T14	163
alert[0x21]	11035	1			T13	36		T16	773		T6	1
alert[0x22]	6038	1			T5	1		T14	250		T49	27
alert[0x23]	7536	1			T3	123		T13	1037		T49	4
alert[0x24]	4914	1			T3	60		T13	120		T16	18
alert[0x25]	5156	1			T3	195		T17	9		T27	72
alert[0x26]	2137	1			T23	114		T27	112		T8	1
alert[0x27]	4049	1			T13	101		T16	87		T6	1
alert[0x28]	3668	1			T25	1		T17	90		T90	2
alert[0x29]	7229	1			T3	187		T13	2298		T14	202
alert[0x2a]	6550	1			T16	69		T17	10		T80	1
alert[0x2b]	4391	1			T16	63		T17	3		T9	2
alert[0x2c]	3778	1			T13	92		T14	42		T6	1
alert[0x2d]	5549	1			T25	9		T23	9		T27	10
alert[0x2e]	7621	1			T13	394		T14	209		T6	1
alert[0x2f]	3685	1			T5	1		T14	459		T7	1
alert[0x30]	11160	1			T25	10		T14	103		T16	219
alert[0x31]	7160	1			T13	11		T23	61		T26	13
alert[0x32]	6560	1			T3	479		T14	368		T17	1
alert[0x33]	6934	1			T13	17		T14	4		T27	14
alert[0x34]	6940	1			T3	41		T13	28		T14	741
alert[0x35]	5089	1			T14	34		T16	64		T27	38
alert[0x36]	11876	1			T3	36		T13	94		T14	17
alert[0x37]	2391	1			T13	136		T14	33		T23	19
alert[0x38]	6660	1			T3	39		T25	1		T16	317
alert[0x39]	5188	1			T3	295		T25	10		T14	14
alert[0x3a]	9373	1			T3	2053		T14	849		T16	441
alert[0x3b]	2934	1			T5	1		T13	64		T6	1
alert[0x3c]	10399	1			T13	170		T16	173		T23	3552
alert[0x3d]	6505	1			T3	16		T85	3		T243	1
alert[0x3e]	6014	1			T13	20		T14	311		T16	57
alert[0x3f]	5774	1			T13	2		T16	493		T27	7
alert[0x40]	6464	1			T16	666		T6	1		T90	5

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	155582	1			T3	1685		T14	6333		T16	17354
class_i[0x1]	53983	1			T5	3		T13	7161		T14	4
class_i[0x2]	115852	1			T13	7		T14	2		T6	1
class_i[0x3]	91458	1			T3	4105		T25	82		T14	1

---

Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

alert_integrity_fail

416227

1

T3

5790

T13

7168

T25

82

alert_ping_fail

648

1

T5

3

T6

10

T7

4

---

Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	0	130	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	alert_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	alert[0x0]	5217	1			T3	112		T49	3		T54	4
alert_integrity_fail	alert[0x1]	1677	1			T3	21		T14	67		T16	72
alert_integrity_fail	alert[0x2]	11470	1			T3	35		T16	1521		T27	2
alert_integrity_fail	alert[0x3]	4793	1			T13	93		T16	5		T17	35
alert_integrity_fail	alert[0x4]	7279	1			T25	1		T17	3		T27	460
alert_integrity_fail	alert[0x5]	12544	1			T3	50		T13	349		T14	82
alert_integrity_fail	alert[0x6]	4106	1			T13	34		T14	56		T16	18
alert_integrity_fail	alert[0x7]	9185	1			T3	47		T23	549		T26	10
alert_integrity_fail	alert[0x8]	8633	1			T13	301		T17	18		T90	2
alert_integrity_fail	alert[0x9]	5040	1			T3	698		T17	904		T26	92
alert_integrity_fail	alert[0xa]	7899	1			T16	26		T23	324		T17	37
alert_integrity_fail	alert[0xb]	6354	1			T16	511		T23	19		T17	12
alert_integrity_fail	alert[0xc]	9228	1			T13	180		T14	750		T17	5
alert_integrity_fail	alert[0xd]	12574	1			T14	96		T17	199		T27	53
alert_integrity_fail	alert[0xe]	1209	1			T17	55		T237	70		T128	226
alert_integrity_fail	alert[0xf]	7038	1			T3	175		T13	296		T27	19
alert_integrity_fail	alert[0x10]	5558	1			T25	36		T14	79		T23	1906
alert_integrity_fail	alert[0x11]	3367	1			T16	28		T27	233		T84	1
alert_integrity_fail	alert[0x12]	9594	1			T3	378		T13	518		T14	58
alert_integrity_fail	alert[0x13]	8779	1			T3	34		T13	193		T25	7
alert_integrity_fail	alert[0x14]	3678	1			T3	560		T14	1027		T16	496
alert_integrity_fail	alert[0x15]	4370	1			T3	7		T49	2		T17	34
alert_integrity_fail	alert[0x16]	6913	1			T16	76		T23	1260		T17	5
alert_integrity_fail	alert[0x17]	1401	1			T13	55		T14	218		T23	3
alert_integrity_fail	alert[0x18]	4786	1			T25	3		T23	102		T17	24
alert_integrity_fail	alert[0x19]	3358	1			T3	31		T25	3		T14	35
alert_integrity_fail	alert[0x1a]	3719	1			T13	327		T16	847		T17	246
alert_integrity_fail	alert[0x1b]	11545	1			T3	50		T14	28		T16	512
alert_integrity_fail	alert[0x1c]	6818	1			T13	31		T14	20		T23	328
alert_integrity_fail	alert[0x1d]	8278	1			T14	25		T16	68		T26	19
alert_integrity_fail	alert[0x1e]	6156	1			T16	1538		T23	4		T17	182
alert_integrity_fail	alert[0x1f]	3537	1			T13	51		T25	1		T17	71
alert_integrity_fail	alert[0x20]	9675	1			T3	68		T13	120		T14	163
alert_integrity_fail	alert[0x21]	11028	1			T13	36		T16	773		T17	603
alert_integrity_fail	alert[0x22]	6025	1			T14	250		T49	27		T17	5
alert_integrity_fail	alert[0x23]	7527	1			T3	123		T13	1037		T49	4
alert_integrity_fail	alert[0x24]	4903	1			T3	60		T13	120		T16	18
alert_integrity_fail	alert[0x25]	5150	1			T3	195		T17	9		T27	72
alert_integrity_fail	alert[0x26]	2124	1			T23	114		T27	112		T84	2
alert_integrity_fail	alert[0x27]	4042	1			T13	101		T16	87		T26	1
alert_integrity_fail	alert[0x28]	3658	1			T25	1		T17	90		T90	2
alert_integrity_fail	alert[0x29]	7216	1			T3	187		T13	2298		T14	202
alert_integrity_fail	alert[0x2a]	6542	1			T16	69		T17	10		T80	1
alert_integrity_fail	alert[0x2b]	4378	1			T16	63		T17	3		T85	1
alert_integrity_fail	alert[0x2c]	3765	1			T13	92		T14	42		T23	1073
alert_integrity_fail	alert[0x2d]	5538	1			T25	9		T23	9		T27	10
alert_integrity_fail	alert[0x2e]	7606	1			T13	394		T14	209		T23	122
alert_integrity_fail	alert[0x2f]	3677	1			T14	459		T32	303		T128	8
alert_integrity_fail	alert[0x30]	11146	1			T25	10		T14	103		T16	219
alert_integrity_fail	alert[0x31]	7147	1			T13	11		T23	61		T26	13
alert_integrity_fail	alert[0x32]	6553	1			T3	479		T14	368		T17	1
alert_integrity_fail	alert[0x33]	6924	1			T13	17		T14	4		T27	14
alert_integrity_fail	alert[0x34]	6934	1			T3	41		T13	28		T14	741
alert_integrity_fail	alert[0x35]	5084	1			T14	34		T16	64		T27	38
alert_integrity_fail	alert[0x36]	11862	1			T3	36		T13	94		T14	17
alert_integrity_fail	alert[0x37]	2382	1			T13	136		T14	33		T23	19
alert_integrity_fail	alert[0x38]	6653	1			T3	39		T25	1		T16	317
alert_integrity_fail	alert[0x39]	5176	1			T3	295		T25	10		T14	14
alert_integrity_fail	alert[0x3a]	9366	1			T3	2053		T14	849		T16	441
alert_integrity_fail	alert[0x3b]	2921	1			T13	64		T27	283		T117	4
alert_integrity_fail	alert[0x3c]	10393	1			T13	170		T16	173		T23	3552
alert_integrity_fail	alert[0x3d]	6492	1			T3	16		T85	3		T128	19
alert_integrity_fail	alert[0x3e]	6009	1			T13	20		T14	311		T16	57
alert_integrity_fail	alert[0x3f]	5770	1			T13	2		T16	493		T27	7
alert_integrity_fail	alert[0x40]	6458	1			T16	666		T90	5		T27	801
alert_ping_fail	alert[0x0]	14	1			T6	1		T9	3		T310	1
alert_ping_fail	alert[0x1]	4	1			T311	1		T312	1		T297	1
alert_ping_fail	alert[0x2]	9	1			T310	1		T313	1		T314	1
alert_ping_fail	alert[0x3]	10	1			T315	1		T316	1		T317	1
alert_ping_fail	alert[0x4]	14	1			T79	1		T318	1		T319	1
alert_ping_fail	alert[0x5]	10	1			T243	2		T125	1		T320	1
alert_ping_fail	alert[0x6]	8	1			T318	1		T321	1		T322	1
alert_ping_fail	alert[0x7]	11	1			T6	1		T242	1		T323	2
alert_ping_fail	alert[0x8]	7	1			T6	1		T8	1		T324	1
alert_ping_fail	alert[0x9]	13	1			T243	2		T310	1		T318	3
alert_ping_fail	alert[0xa]	19	1			T8	1		T9	1		T243	1
alert_ping_fail	alert[0xb]	6	1			T6	1		T310	1		T311	1
alert_ping_fail	alert[0xc]	2	1			T314	1		T325	1		-	-
alert_ping_fail	alert[0xd]	13	1			T324	1		T315	1		T316	1
alert_ping_fail	alert[0xe]	13	1			T310	1		T326	2		T313	1
alert_ping_fail	alert[0xf]	14	1			T324	1		T323	1		T327	1
alert_ping_fail	alert[0x10]	6	1			T79	1		T315	1		T251	1
alert_ping_fail	alert[0x11]	10	1			T9	1		T251	1		T316	1
alert_ping_fail	alert[0x12]	11	1			T9	1		T318	1		T326	1
alert_ping_fail	alert[0x13]	5	1			T328	1		T325	1		T329	1
alert_ping_fail	alert[0x14]	17	1			T7	1		T9	1		T298	1
alert_ping_fail	alert[0x15]	16	1			T298	1		T315	2		T330	1
alert_ping_fail	alert[0x16]	13	1			T9	2		T331	1		T308	1
alert_ping_fail	alert[0x17]	12	1			T243	1		T318	1		T315	1
alert_ping_fail	alert[0x18]	10	1			T9	2		T315	1		T313	1
alert_ping_fail	alert[0x19]	11	1			T310	1		T322	1		T296	1
alert_ping_fail	alert[0x1a]	4	1			T327	1		T317	1		T332	1
alert_ping_fail	alert[0x1b]	3	1			T333	1		T328	1		T334	1
alert_ping_fail	alert[0x1c]	14	1			T7	1		T9	3		T315	1
alert_ping_fail	alert[0x1d]	9	1			T243	1		T335	1		T336	1
alert_ping_fail	alert[0x1e]	12	1			T9	1		T323	1		T315	2
alert_ping_fail	alert[0x1f]	11	1			T240	1		T242	1		T337	1
alert_ping_fail	alert[0x20]	9	1			T9	1		T327	1		T296	1
alert_ping_fail	alert[0x21]	7	1			T6	1		T318	2		T319	1
alert_ping_fail	alert[0x22]	13	1			T5	1		T310	1		T327	1
alert_ping_fail	alert[0x23]	9	1			T310	1		T315	1		T311	1
alert_ping_fail	alert[0x24]	11	1			T9	2		T321	1		T296	1
alert_ping_fail	alert[0x25]	6	1			T308	1		T338	1		T334	1
alert_ping_fail	alert[0x26]	13	1			T8	1		T79	1		T323	2
alert_ping_fail	alert[0x27]	7	1			T6	1		T327	1		T319	1
alert_ping_fail	alert[0x28]	10	1			T324	1		T321	1		T200	1
alert_ping_fail	alert[0x29]	13	1			T9	1		T79	3		T321	1
alert_ping_fail	alert[0x2a]	8	1			T243	1		T333	1		T322	1
alert_ping_fail	alert[0x2b]	13	1			T9	2		T310	1		T251	1
alert_ping_fail	alert[0x2c]	13	1			T6	1		T79	1		T339	1
alert_ping_fail	alert[0x2d]	11	1			T310	1		T322	1		T251	1
alert_ping_fail	alert[0x2e]	15	1			T6	1		T125	2		T327	1
alert_ping_fail	alert[0x2f]	8	1			T5	1		T7	1		T240	1
alert_ping_fail	alert[0x30]	14	1			T7	1		T327	1		T315	1
alert_ping_fail	alert[0x31]	13	1			T243	2		T319	1		T313	1
alert_ping_fail	alert[0x32]	7	1			T8	1		T310	1		T327	1
alert_ping_fail	alert[0x33]	10	1			T9	1		T310	1		T327	1
alert_ping_fail	alert[0x34]	6	1			T310	1		T319	1		T312	1
alert_ping_fail	alert[0x35]	5	1			T335	1		T326	1		T317	1
alert_ping_fail	alert[0x36]	14	1			T310	1		T327	1		T311	1
alert_ping_fail	alert[0x37]	9	1			T79	1		T313	2		T328	1
alert_ping_fail	alert[0x38]	7	1			T335	1		T316	1		T296	1
alert_ping_fail	alert[0x39]	12	1			T243	1		T323	1		T327	1
alert_ping_fail	alert[0x3a]	7	1			T322	1		T311	1		T340	2
alert_ping_fail	alert[0x3b]	13	1			T5	1		T6	1		T310	1
alert_ping_fail	alert[0x3c]	6	1			T243	1		T310	1		T321	1
alert_ping_fail	alert[0x3d]	13	1			T243	1		T310	1		T315	1
alert_ping_fail	alert[0x3e]	5	1			T321	1		T314	1		T332	1
alert_ping_fail	alert[0x3f]	4	1			T251	1		T340	1		T341	1
alert_ping_fail	alert[0x40]	6	1			T6	1		T315	1		T251	1

---

Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	class_i[0x0]	155422	1			T3	1685		T14	6333		T16	17354
alert_integrity_fail	class_i[0x1]	53834	1			T13	7161		T14	4		T23	37
alert_integrity_fail	class_i[0x2]	115667	1			T13	7		T14	2		T23	43
alert_integrity_fail	class_i[0x3]	91304	1			T3	4105		T25	82		T14	1
alert_ping_fail	class_i[0x0]	160	1			T9	21		T324	3		T243	1
alert_ping_fail	class_i[0x1]	149	1			T5	3		T8	1		T79	1
alert_ping_fail	class_i[0x2]	185	1			T6	1		T7	4		T8	2
alert_ping_fail	class_i[0x3]	154	1			T6	9		T8	1		T9	1