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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.68 99.99 98.70 100.00 100.00 100.00 99.38 99.72


Total test records in report: 840
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html
T776 /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.3657108716 Jul 22 05:24:48 PM PDT 24 Jul 22 05:24:49 PM PDT 24 9885870 ps
T777 /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.2473732927 Jul 22 05:24:54 PM PDT 24 Jul 22 05:24:58 PM PDT 24 20349418 ps
T778 /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.4123966643 Jul 22 05:23:40 PM PDT 24 Jul 22 05:27:02 PM PDT 24 5107840824 ps
T140 /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.2668094106 Jul 22 05:23:43 PM PDT 24 Jul 22 05:26:42 PM PDT 24 2544116395 ps
T779 /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.1715173197 Jul 22 05:23:53 PM PDT 24 Jul 22 05:32:24 PM PDT 24 8555086073 ps
T780 /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.3780895771 Jul 22 05:24:11 PM PDT 24 Jul 22 05:24:18 PM PDT 24 522859028 ps
T781 /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.154602700 Jul 22 05:24:42 PM PDT 24 Jul 22 05:24:45 PM PDT 24 12092240 ps
T182 /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.1147141343 Jul 22 05:26:07 PM PDT 24 Jul 22 05:26:10 PM PDT 24 72789897 ps
T782 /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.3276204799 Jul 22 05:24:49 PM PDT 24 Jul 22 05:24:51 PM PDT 24 50650430 ps
T141 /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.251976458 Jul 22 05:24:19 PM PDT 24 Jul 22 05:26:58 PM PDT 24 9722047334 ps
T160 /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.217135824 Jul 22 05:23:53 PM PDT 24 Jul 22 05:25:39 PM PDT 24 3556239803 ps
T783 /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.4198374353 Jul 22 05:23:53 PM PDT 24 Jul 22 05:24:16 PM PDT 24 178741661 ps
T187 /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.2665946164 Jul 22 05:24:20 PM PDT 24 Jul 22 05:24:23 PM PDT 24 92354812 ps
T784 /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.1184249717 Jul 22 05:24:17 PM PDT 24 Jul 22 05:24:26 PM PDT 24 284997983 ps
T196 /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.1816770243 Jul 22 05:24:22 PM PDT 24 Jul 22 05:24:26 PM PDT 24 51212583 ps
T785 /workspace/coverage/cover_reg_top/33.alert_handler_intr_test.4075851332 Jul 22 05:24:50 PM PDT 24 Jul 22 05:24:52 PM PDT 24 10539022 ps
T167 /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.4205386925 Jul 22 05:25:03 PM PDT 24 Jul 22 05:43:14 PM PDT 24 31636139954 ps
T180 /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.2817166671 Jul 22 05:24:34 PM PDT 24 Jul 22 05:24:39 PM PDT 24 256161157 ps
T163 /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.3791438755 Jul 22 05:23:55 PM PDT 24 Jul 22 05:34:29 PM PDT 24 4618852263 ps
T786 /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.3946052385 Jul 22 05:23:40 PM PDT 24 Jul 22 05:25:33 PM PDT 24 3407645619 ps
T787 /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.4200301687 Jul 22 05:24:40 PM PDT 24 Jul 22 05:24:44 PM PDT 24 75612074 ps
T788 /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.875663742 Jul 22 05:24:11 PM PDT 24 Jul 22 05:24:21 PM PDT 24 162130084 ps
T789 /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.1090547756 Jul 22 05:23:56 PM PDT 24 Jul 22 05:28:23 PM PDT 24 15576691183 ps
T790 /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.3855722796 Jul 22 05:24:18 PM PDT 24 Jul 22 05:24:28 PM PDT 24 101725255 ps
T185 /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.1142737054 Jul 22 05:24:33 PM PDT 24 Jul 22 05:25:41 PM PDT 24 3524004239 ps
T164 /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.2022997811 Jul 22 05:24:03 PM PDT 24 Jul 22 05:41:54 PM PDT 24 14836442236 ps
T791 /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.1902526617 Jul 22 05:24:50 PM PDT 24 Jul 22 05:24:52 PM PDT 24 95231417 ps
T792 /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.2835210696 Jul 22 05:23:48 PM PDT 24 Jul 22 05:24:03 PM PDT 24 2874618406 ps
T793 /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.4173682446 Jul 22 05:26:01 PM PDT 24 Jul 22 05:26:10 PM PDT 24 244383861 ps
T794 /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.1444345901 Jul 22 05:24:19 PM PDT 24 Jul 22 05:24:27 PM PDT 24 96254657 ps
T795 /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.2766659077 Jul 22 05:23:53 PM PDT 24 Jul 22 05:24:34 PM PDT 24 1794972523 ps
T183 /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.3055495344 Jul 22 05:23:52 PM PDT 24 Jul 22 05:25:17 PM PDT 24 4401030942 ps
T796 /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.3010948865 Jul 22 05:23:37 PM PDT 24 Jul 22 05:24:01 PM PDT 24 339095602 ps
T797 /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.1338382399 Jul 22 05:24:42 PM PDT 24 Jul 22 05:24:50 PM PDT 24 190409904 ps
T798 /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.82615733 Jul 22 05:24:02 PM PDT 24 Jul 22 05:24:12 PM PDT 24 116829665 ps
T799 /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.2169671316 Jul 22 05:24:40 PM PDT 24 Jul 22 05:24:42 PM PDT 24 20654874 ps
T800 /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.2449651895 Jul 22 05:24:02 PM PDT 24 Jul 22 05:24:09 PM PDT 24 38099495 ps
T195 /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.602567857 Jul 22 05:24:43 PM PDT 24 Jul 22 05:25:29 PM PDT 24 1248740368 ps
T801 /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.352620127 Jul 22 05:23:44 PM PDT 24 Jul 22 05:24:07 PM PDT 24 957735685 ps
T802 /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.1588890601 Jul 22 05:23:35 PM PDT 24 Jul 22 05:23:40 PM PDT 24 291091218 ps
T803 /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.3872678426 Jul 22 05:24:32 PM PDT 24 Jul 22 05:24:56 PM PDT 24 2525986992 ps
T804 /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.3950016005 Jul 22 05:24:21 PM PDT 24 Jul 22 05:24:27 PM PDT 24 50654169 ps
T805 /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.356904186 Jul 22 05:24:31 PM PDT 24 Jul 22 05:24:40 PM PDT 24 108387204 ps
T806 /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.2485643547 Jul 22 05:24:12 PM PDT 24 Jul 22 05:32:38 PM PDT 24 17080243678 ps
T807 /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.3678281478 Jul 22 05:23:48 PM PDT 24 Jul 22 05:23:59 PM PDT 24 313095757 ps
T168 /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.1237782436 Jul 22 05:24:04 PM PDT 24 Jul 22 05:27:17 PM PDT 24 3214145576 ps
T808 /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.53767373 Jul 22 05:24:34 PM PDT 24 Jul 22 05:24:57 PM PDT 24 543086020 ps
T809 /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.498962902 Jul 22 05:24:21 PM PDT 24 Jul 22 05:24:23 PM PDT 24 12555268 ps
T810 /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.4065458421 Jul 22 05:24:33 PM PDT 24 Jul 22 05:24:42 PM PDT 24 414133402 ps
T158 /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.2240432398 Jul 22 05:23:46 PM PDT 24 Jul 22 05:40:09 PM PDT 24 12495272564 ps
T811 /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.721711922 Jul 22 05:24:58 PM PDT 24 Jul 22 05:25:00 PM PDT 24 13652751 ps
T812 /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.3765865039 Jul 22 05:24:33 PM PDT 24 Jul 22 05:24:56 PM PDT 24 324980521 ps
T813 /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.2432863856 Jul 22 05:26:01 PM PDT 24 Jul 22 05:26:14 PM PDT 24 156888786 ps
T814 /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.2785193219 Jul 22 05:25:03 PM PDT 24 Jul 22 05:25:31 PM PDT 24 353893650 ps
T815 /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.2787473327 Jul 22 05:23:53 PM PDT 24 Jul 22 05:23:55 PM PDT 24 6695096 ps
T816 /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.3637468867 Jul 22 05:23:30 PM PDT 24 Jul 22 05:23:57 PM PDT 24 1413362765 ps
T817 /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.2946417745 Jul 22 05:23:40 PM PDT 24 Jul 22 05:23:44 PM PDT 24 20611920 ps
T818 /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.3328520947 Jul 22 05:24:53 PM PDT 24 Jul 22 05:24:54 PM PDT 24 11834309 ps
T194 /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.1766949204 Jul 22 05:23:57 PM PDT 24 Jul 22 05:24:00 PM PDT 24 153132705 ps
T819 /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.2820800382 Jul 22 05:24:53 PM PDT 24 Jul 22 05:25:04 PM PDT 24 480463899 ps
T820 /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.3524575030 Jul 22 05:24:00 PM PDT 24 Jul 22 05:31:20 PM PDT 24 28474682110 ps
T821 /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.161241403 Jul 22 05:24:03 PM PDT 24 Jul 22 05:24:10 PM PDT 24 136141490 ps
T822 /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.871304182 Jul 22 05:24:49 PM PDT 24 Jul 22 05:24:51 PM PDT 24 17525636 ps
T823 /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.2665697686 Jul 22 05:23:35 PM PDT 24 Jul 22 05:23:49 PM PDT 24 749536230 ps
T184 /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.2691713377 Jul 22 05:24:04 PM PDT 24 Jul 22 05:24:09 PM PDT 24 164514264 ps
T824 /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.3025177791 Jul 22 05:23:49 PM PDT 24 Jul 22 05:29:03 PM PDT 24 20230428443 ps
T169 /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.399007274 Jul 22 05:24:18 PM PDT 24 Jul 22 05:35:31 PM PDT 24 8599009628 ps
T825 /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.2153713867 Jul 22 05:24:51 PM PDT 24 Jul 22 05:24:53 PM PDT 24 6829804 ps
T826 /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.2120175895 Jul 22 05:23:53 PM PDT 24 Jul 22 05:24:03 PM PDT 24 73185626 ps
T827 /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.2572122116 Jul 22 05:24:04 PM PDT 24 Jul 22 05:24:17 PM PDT 24 601820042 ps
T166 /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.3128067272 Jul 22 05:23:30 PM PDT 24 Jul 22 05:28:06 PM PDT 24 27568641641 ps
T828 /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.2036773396 Jul 22 05:24:38 PM PDT 24 Jul 22 05:24:55 PM PDT 24 258756656 ps
T829 /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.1985012593 Jul 22 05:24:48 PM PDT 24 Jul 22 05:24:50 PM PDT 24 15148050 ps
T171 /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.2726957151 Jul 22 05:24:18 PM PDT 24 Jul 22 05:27:14 PM PDT 24 30806987819 ps
T830 /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.3115419720 Jul 22 05:23:49 PM PDT 24 Jul 22 05:23:56 PM PDT 24 45622086 ps
T831 /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.1068381111 Jul 22 05:24:32 PM PDT 24 Jul 22 05:24:39 PM PDT 24 75092967 ps
T159 /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.2877075218 Jul 22 05:23:27 PM PDT 24 Jul 22 05:28:27 PM PDT 24 3118840846 ps
T832 /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.2180554425 Jul 22 05:24:30 PM PDT 24 Jul 22 05:24:32 PM PDT 24 9331761 ps
T833 /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.2302731580 Jul 22 05:26:07 PM PDT 24 Jul 22 05:26:19 PM PDT 24 1644630333 ps
T834 /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.336188613 Jul 22 05:24:49 PM PDT 24 Jul 22 05:24:51 PM PDT 24 12847875 ps
T162 /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.2824684542 Jul 22 05:24:33 PM PDT 24 Jul 22 05:38:45 PM PDT 24 20326408898 ps
T186 /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.1219086896 Jul 22 05:25:09 PM PDT 24 Jul 22 05:25:15 PM PDT 24 101070793 ps
T165 /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.1250809005 Jul 22 05:24:33 PM PDT 24 Jul 22 05:29:44 PM PDT 24 4820627046 ps
T835 /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.2240201028 Jul 22 05:24:23 PM PDT 24 Jul 22 05:26:10 PM PDT 24 859618392 ps
T836 /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.217174343 Jul 22 05:24:51 PM PDT 24 Jul 22 05:24:52 PM PDT 24 18468712 ps
T837 /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.1374819297 Jul 22 05:24:38 PM PDT 24 Jul 22 05:25:20 PM PDT 24 2239443397 ps
T170 /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.1147126645 Jul 22 05:24:10 PM PDT 24 Jul 22 05:28:07 PM PDT 24 1632864408 ps
T838 /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.1748841256 Jul 22 05:23:27 PM PDT 24 Jul 22 05:29:10 PM PDT 24 30085224195 ps
T839 /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.4003095263 Jul 22 05:24:30 PM PDT 24 Jul 22 05:24:34 PM PDT 24 62344467 ps
T840 /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.1542767416 Jul 22 05:24:20 PM PDT 24 Jul 22 05:24:46 PM PDT 24 326032264 ps

Test location /workspace/coverage/default/24.alert_handler_stress_all_with_rand_reset.2124701977
Short name T3
Test name
Test status
Simulation time 51624797894 ps
CPU time 5221.78 seconds
Started Jul 22 07:18:18 PM PDT 24
Finished Jul 22 08:46:13 PM PDT 24
Peak memory 338120 kb
Host smart-216f6d0d-ef27-4984-9daa-be633e5f9ca2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124701977 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 24.alert_handler_stress_all_with_rand_reset.2124701977
Directory /workspace/24.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all.2048108581
Short name T14
Test name
Test status
Simulation time 39098462462 ps
CPU time 2631.56 seconds
Started Jul 22 07:17:10 PM PDT 24
Finished Jul 22 08:02:02 PM PDT 24
Peak memory 289640 kb
Host smart-e7215a72-dfdf-475e-aaa7-29c187468510
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048108581 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_han
dler_stress_all.2048108581
Directory /workspace/7.alert_handler_stress_all/latest

Test location /workspace/coverage/default/0.alert_handler_sec_cm.3311869915
Short name T11
Test name
Test status
Simulation time 830894511 ps
CPU time 24.56 seconds
Started Jul 22 07:16:28 PM PDT 24
Finished Jul 22 07:17:57 PM PDT 24
Peak memory 271032 kb
Host smart-4864509c-ad83-4f1d-b151-1c7dface3959
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3311869915 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sec_cm.3311869915
Directory /workspace/0.alert_handler_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.3066356312
Short name T134
Test name
Test status
Simulation time 16000598355 ps
CPU time 1159.76 seconds
Started Jul 22 05:24:20 PM PDT 24
Finished Jul 22 05:43:40 PM PDT 24
Peak memory 266000 kb
Host smart-2497c00f-c509-4ea1-b932-51c7253ff851
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066356312 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 13.alert_handler_shadow_reg_errors_with_csr_rw.3066356312
Directory /workspace/13.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all_with_rand_reset.1322897246
Short name T58
Test name
Test status
Simulation time 34439469487 ps
CPU time 3660.19 seconds
Started Jul 22 07:23:33 PM PDT 24
Finished Jul 22 08:24:53 PM PDT 24
Peak memory 321004 kb
Host smart-125f798f-7b04-4ec5-a986-a0af2a91cb61
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322897246 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 49.alert_handler_stress_all_with_rand_reset.1322897246
Directory /workspace/49.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all.220318696
Short name T23
Test name
Test status
Simulation time 59168359778 ps
CPU time 3434.75 seconds
Started Jul 22 07:17:33 PM PDT 24
Finished Jul 22 08:15:43 PM PDT 24
Peak memory 289260 kb
Host smart-b44fa5d9-1ed0-424c-a77a-0f9bce1350fa
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220318696 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_han
dler_stress_all.220318696
Directory /workspace/15.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.40944349
Short name T172
Test name
Test status
Simulation time 317830086 ps
CPU time 39.28 seconds
Started Jul 22 05:24:21 PM PDT 24
Finished Jul 22 05:25:01 PM PDT 24
Peak memory 240888 kb
Host smart-11e8863f-00db-42f4-884f-a1c9daf8b636
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=40944349 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_intg_err.40944349
Directory /workspace/11.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all_with_rand_reset.3100790368
Short name T34
Test name
Test status
Simulation time 63371277680 ps
CPU time 3645.68 seconds
Started Jul 22 07:19:00 PM PDT 24
Finished Jul 22 08:20:28 PM PDT 24
Peak memory 305484 kb
Host smart-fd64f8aa-ebe2-4ebf-8a1b-2471b88d3f8c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100790368 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.alert_handler_stress_all_with_rand_reset.3100790368
Directory /workspace/34.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all_with_rand_reset.1564906422
Short name T258
Test name
Test status
Simulation time 45733345134 ps
CPU time 5060.15 seconds
Started Jul 22 07:20:29 PM PDT 24
Finished Jul 22 08:44:53 PM PDT 24
Peak memory 337804 kb
Host smart-21606903-bd80-4c0c-bf2e-5c70234cba0f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564906422 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 43.alert_handler_stress_all_with_rand_reset.1564906422
Directory /workspace/43.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.alert_handler_lpg.2841013824
Short name T127
Test name
Test status
Simulation time 187184912400 ps
CPU time 1891 seconds
Started Jul 22 07:20:16 PM PDT 24
Finished Jul 22 07:51:57 PM PDT 24
Peak memory 273180 kb
Host smart-0dc36bac-4e12-4cab-8b24-9809bb87a126
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2841013824 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg.2841013824
Directory /workspace/44.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.1125324724
Short name T155
Test name
Test status
Simulation time 5400716811 ps
CPU time 397.63 seconds
Started Jul 22 05:24:42 PM PDT 24
Finished Jul 22 05:31:20 PM PDT 24
Peak memory 266112 kb
Host smart-0f107864-a930-44ff-bf53-ba0dad4a646f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1125324724 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shadow_reg_err
ors.1125324724
Directory /workspace/19.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/35.alert_handler_entropy.126251901
Short name T117
Test name
Test status
Simulation time 206657122187 ps
CPU time 1801.66 seconds
Started Jul 22 07:18:59 PM PDT 24
Finished Jul 22 07:49:43 PM PDT 24
Peak memory 285412 kb
Host smart-e34c3024-f1a2-4d34-9b97-c624dfcf05ad
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126251901 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_entropy.126251901
Directory /workspace/35.alert_handler_entropy/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all.286829318
Short name T277
Test name
Test status
Simulation time 167876405101 ps
CPU time 2425.18 seconds
Started Jul 22 07:16:56 PM PDT 24
Finished Jul 22 07:58:24 PM PDT 24
Peak memory 289300 kb
Host smart-abf3a630-e8db-4186-b2bd-d2270224b894
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286829318 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_hand
ler_stress_all.286829318
Directory /workspace/3.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.2575353626
Short name T149
Test name
Test status
Simulation time 45016743978 ps
CPU time 302.83 seconds
Started Jul 22 05:24:22 PM PDT 24
Finished Jul 22 05:29:25 PM PDT 24
Peak memory 266044 kb
Host smart-20199a49-7543-443b-8940-acccb3ade660
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2575353626 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shadow_reg_err
ors.2575353626
Directory /workspace/12.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/32.alert_handler_entropy.305393087
Short name T13
Test name
Test status
Simulation time 57757048251 ps
CPU time 3339.58 seconds
Started Jul 22 07:18:50 PM PDT 24
Finished Jul 22 08:15:16 PM PDT 24
Peak memory 289588 kb
Host smart-7ddacc87-55a7-484c-9532-8cb2560a7bd6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305393087 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_entropy.305393087
Directory /workspace/32.alert_handler_entropy/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all.3062103314
Short name T67
Test name
Test status
Simulation time 344911483159 ps
CPU time 3269.97 seconds
Started Jul 22 07:17:38 PM PDT 24
Finished Jul 22 08:13:02 PM PDT 24
Peak memory 288936 kb
Host smart-d1429b0b-0400-4f2d-8df6-04168f07047d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062103314 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_ha
ndler_stress_all.3062103314
Directory /workspace/16.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.3637713136
Short name T150
Test name
Test status
Simulation time 5775997921 ps
CPU time 734.2 seconds
Started Jul 22 05:24:03 PM PDT 24
Finished Jul 22 05:36:18 PM PDT 24
Peak memory 266056 kb
Host smart-3fa1252e-1d64-4ccd-aae1-214e51202540
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637713136 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.alert_handler_shadow_reg_errors_with_csr_rw.3637713136
Directory /workspace/7.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/4.alert_handler_ping_timeout.2284696499
Short name T243
Test name
Test status
Simulation time 141978648178 ps
CPU time 422.23 seconds
Started Jul 22 07:16:52 PM PDT 24
Finished Jul 22 07:25:00 PM PDT 24
Peak memory 248548 kb
Host smart-a04898fc-068c-429d-98fe-618696d15d06
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284696499 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_ping_timeout.2284696499
Directory /workspace/4.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.472172862
Short name T362
Test name
Test status
Simulation time 11244350 ps
CPU time 1.33 seconds
Started Jul 22 05:23:38 PM PDT 24
Finished Jul 22 05:23:39 PM PDT 24
Peak memory 237100 kb
Host smart-4f3cd611-b350-4b64-b952-3e0de7d66cd9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=472172862 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_intr_test.472172862
Directory /workspace/1.alert_handler_intr_test/latest

Test location /workspace/coverage/default/13.alert_handler_lpg.4198459108
Short name T302
Test name
Test status
Simulation time 371949729123 ps
CPU time 2029.31 seconds
Started Jul 22 07:17:36 PM PDT 24
Finished Jul 22 07:52:19 PM PDT 24
Peak memory 284824 kb
Host smart-66b527a2-8cad-4e52-b8b9-1910cfce0e09
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198459108 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg.4198459108
Directory /workspace/13.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.2240432398
Short name T158
Test name
Test status
Simulation time 12495272564 ps
CPU time 982.42 seconds
Started Jul 22 05:23:46 PM PDT 24
Finished Jul 22 05:40:09 PM PDT 24
Peak memory 265976 kb
Host smart-63d85c94-85db-4a74-b8d0-e48a67eb24c6
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240432398 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.alert_handler_shadow_reg_errors_with_csr_rw.2240432398
Directory /workspace/4.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/22.alert_handler_lpg.93883719
Short name T5
Test name
Test status
Simulation time 28573008561 ps
CPU time 2010.23 seconds
Started Jul 22 07:18:04 PM PDT 24
Finished Jul 22 07:52:25 PM PDT 24
Peak memory 281344 kb
Host smart-cb189839-984e-4bb0-91de-d5b71da1aa3a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93883719 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg.93883719
Directory /workspace/22.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.396076206
Short name T138
Test name
Test status
Simulation time 18246308776 ps
CPU time 940.47 seconds
Started Jul 22 05:24:59 PM PDT 24
Finished Jul 22 05:40:40 PM PDT 24
Peak memory 274216 kb
Host smart-1e7a362f-5426-4979-a1a5-af61c445f77d
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396076206 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.alert_handler_shadow_reg_errors_with_csr_rw.396076206
Directory /workspace/2.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/33.alert_handler_ping_timeout.4066997606
Short name T9
Test name
Test status
Simulation time 13556374385 ps
CPU time 526.18 seconds
Started Jul 22 07:18:44 PM PDT 24
Finished Jul 22 07:28:16 PM PDT 24
Peak memory 247532 kb
Host smart-53c4d72e-0726-49bc-a123-bd60d513a830
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4066997606 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_ping_timeout.4066997606
Directory /workspace/33.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.1147126645
Short name T170
Test name
Test status
Simulation time 1632864408 ps
CPU time 236.61 seconds
Started Jul 22 05:24:10 PM PDT 24
Finished Jul 22 05:28:07 PM PDT 24
Peak memory 265692 kb
Host smart-d5591eaa-80b8-415e-b422-81973025a71d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1147126645 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shadow_reg_erro
rs.1147126645
Directory /workspace/9.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/28.alert_handler_ping_timeout.1005648161
Short name T327
Test name
Test status
Simulation time 89688056155 ps
CPU time 622.64 seconds
Started Jul 22 07:18:32 PM PDT 24
Finished Jul 22 07:29:44 PM PDT 24
Peak memory 248688 kb
Host smart-1fc4d431-e1be-41d7-b1f5-6a4fb9d1a401
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005648161 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_ping_timeout.1005648161
Directory /workspace/28.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_ping_timeout.3118163533
Short name T334
Test name
Test status
Simulation time 175550454060 ps
CPU time 614.73 seconds
Started Jul 22 07:17:27 PM PDT 24
Finished Jul 22 07:28:41 PM PDT 24
Peak memory 248332 kb
Host smart-1f17edc7-b19a-421e-bc6f-a4ee8ea0f27b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118163533 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_ping_timeout.3118163533
Directory /workspace/13.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_lpg.386886242
Short name T71
Test name
Test status
Simulation time 73414565569 ps
CPU time 1989.13 seconds
Started Jul 22 07:16:41 PM PDT 24
Finished Jul 22 07:50:57 PM PDT 24
Peak memory 272656 kb
Host smart-1f449223-1765-4ab3-8ed0-e5267f78ec1f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386886242 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg.386886242
Directory /workspace/2.alert_handler_lpg/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all_with_rand_reset.1696961147
Short name T17
Test name
Test status
Simulation time 36647916307 ps
CPU time 3847.11 seconds
Started Jul 22 07:18:46 PM PDT 24
Finished Jul 22 08:23:41 PM PDT 24
Peak memory 322044 kb
Host smart-518187fd-8c1b-4c88-8f1f-73e0b9c1f751
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696961147 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 32.alert_handler_stress_all_with_rand_reset.1696961147
Directory /workspace/32.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all_with_rand_reset.3018896625
Short name T206
Test name
Test status
Simulation time 340110602844 ps
CPU time 7648.07 seconds
Started Jul 22 07:19:39 PM PDT 24
Finished Jul 22 09:27:26 PM PDT 24
Peak memory 392572 kb
Host smart-40adf0f2-a21d-4795-87b4-a5f01c3aa6f4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018896625 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 25.alert_handler_stress_all_with_rand_reset.3018896625
Directory /workspace/25.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.1237782436
Short name T168
Test name
Test status
Simulation time 3214145576 ps
CPU time 193.14 seconds
Started Jul 22 05:24:04 PM PDT 24
Finished Jul 22 05:27:17 PM PDT 24
Peak memory 266076 kb
Host smart-f0445784-febd-4ef2-b75e-44d8edd11ff1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1237782436 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shadow_reg_erro
rs.1237782436
Directory /workspace/7.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.37691547
Short name T143
Test name
Test status
Simulation time 65782900886 ps
CPU time 984.98 seconds
Started Jul 22 05:23:35 PM PDT 24
Finished Jul 22 05:40:01 PM PDT 24
Peak memory 266096 kb
Host smart-a4d7a910-5466-4ec3-85c3-6267844e29c5
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37691547 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_
TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -
cm_name 1.alert_handler_shadow_reg_errors_with_csr_rw.37691547
Directory /workspace/1.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/27.alert_handler_lpg.2726400520
Short name T357
Test name
Test status
Simulation time 16320148891 ps
CPU time 1435.7 seconds
Started Jul 22 07:18:20 PM PDT 24
Finished Jul 22 07:43:08 PM PDT 24
Peak memory 289512 kb
Host smart-1ad4f727-9a07-4e10-9f10-c496e44142f6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726400520 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg.2726400520
Directory /workspace/27.alert_handler_lpg/latest

Test location /workspace/coverage/default/27.alert_handler_ping_timeout.95960353
Short name T325
Test name
Test status
Simulation time 6683779960 ps
CPU time 293.31 seconds
Started Jul 22 07:18:22 PM PDT 24
Finished Jul 22 07:24:07 PM PDT 24
Peak memory 248660 kb
Host smart-65d7171f-f6b8-4163-ada6-7332498e8b92
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95960353 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_ping_timeout.95960353
Directory /workspace/27.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all.4210391750
Short name T256
Test name
Test status
Simulation time 130831107438 ps
CPU time 3716.45 seconds
Started Jul 22 07:17:26 PM PDT 24
Finished Jul 22 08:20:23 PM PDT 24
Peak memory 297736 kb
Host smart-b5122419-a271-483e-a0a3-8495508c5de8
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210391750 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_han
dler_stress_all.4210391750
Directory /workspace/8.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.2667068329
Short name T368
Test name
Test status
Simulation time 15429081 ps
CPU time 1.85 seconds
Started Jul 22 05:24:49 PM PDT 24
Finished Jul 22 05:24:52 PM PDT 24
Peak memory 237048 kb
Host smart-a6753aee-7bd7-4948-9808-68b005bbe1a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2667068329 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.alert_handler_intr_test.2667068329
Directory /workspace/36.alert_handler_intr_test/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all_with_rand_reset.2946700492
Short name T197
Test name
Test status
Simulation time 130262310304 ps
CPU time 8062.24 seconds
Started Jul 22 07:16:39 PM PDT 24
Finished Jul 22 09:32:08 PM PDT 24
Peak memory 338132 kb
Host smart-93d3a8ec-3861-471d-84d7-26c4da172fae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946700492 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.alert_handler_stress_all_with_rand_reset.2946700492
Directory /workspace/1.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.alert_handler_lpg.559706944
Short name T285
Test name
Test status
Simulation time 61268339242 ps
CPU time 2070.79 seconds
Started Jul 22 07:19:56 PM PDT 24
Finished Jul 22 07:54:34 PM PDT 24
Peak memory 272844 kb
Host smart-60ecbcac-8237-4ffd-b187-fa53f95dcfd4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559706944 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg.559706944
Directory /workspace/37.alert_handler_lpg/latest

Test location /workspace/coverage/default/16.alert_handler_ping_timeout.1033547769
Short name T315
Test name
Test status
Simulation time 9977697174 ps
CPU time 410.75 seconds
Started Jul 22 07:17:38 PM PDT 24
Finished Jul 22 07:25:22 PM PDT 24
Peak memory 248500 kb
Host smart-e67b0f03-9b58-41fe-9703-c328be1511b2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033547769 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_ping_timeout.1033547769
Directory /workspace/16.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all.2422033147
Short name T68
Test name
Test status
Simulation time 130651630821 ps
CPU time 3830.32 seconds
Started Jul 22 07:18:27 PM PDT 24
Finished Jul 22 08:23:08 PM PDT 24
Peak memory 289540 kb
Host smart-441990f0-90f5-44c4-a1d0-e92e1c6b578b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422033147 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_ha
ndler_stress_all.2422033147
Directory /workspace/27.alert_handler_stress_all/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all_with_rand_reset.4080453236
Short name T66
Test name
Test status
Simulation time 65185634708 ps
CPU time 6473.15 seconds
Started Jul 22 07:16:54 PM PDT 24
Finished Jul 22 09:05:52 PM PDT 24
Peak memory 346848 kb
Host smart-aa6de6de-d71b-4008-a6e3-25e96a767a10
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080453236 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 5.alert_handler_stress_all_with_rand_reset.4080453236
Directory /workspace/5.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.2260185093
Short name T207
Test name
Test status
Simulation time 186285863 ps
CPU time 4.61 seconds
Started Jul 22 05:23:36 PM PDT 24
Finished Jul 22 05:23:41 PM PDT 24
Peak memory 240980 kb
Host smart-406f7a6e-3e36-485b-98ce-e2f56c602d86
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2260185093 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_rw.2260185093
Directory /workspace/1.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.2853800333
Short name T147
Test name
Test status
Simulation time 2679085117 ps
CPU time 236.59 seconds
Started Jul 22 05:23:39 PM PDT 24
Finished Jul 22 05:27:36 PM PDT 24
Peak memory 266020 kb
Host smart-18036740-0420-472d-ab82-5f8456014266
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2853800333 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shadow_reg_erro
rs.2853800333
Directory /workspace/2.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/31.alert_handler_ping_timeout.3095554565
Short name T340
Test name
Test status
Simulation time 66892965205 ps
CPU time 676.92 seconds
Started Jul 22 07:18:42 PM PDT 24
Finished Jul 22 07:30:46 PM PDT 24
Peak memory 248684 kb
Host smart-4de0b44f-c725-42af-9cf8-4c9cdc1896cd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3095554565 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_ping_timeout.3095554565
Directory /workspace/31.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_ping_timeout.108051772
Short name T308
Test name
Test status
Simulation time 18180708495 ps
CPU time 336.4 seconds
Started Jul 22 07:19:17 PM PDT 24
Finished Jul 22 07:25:27 PM PDT 24
Peak memory 255728 kb
Host smart-da8ee9d5-7aa8-480e-8513-89df2e71487e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108051772 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_ping_timeout.108051772
Directory /workspace/35.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.2691713377
Short name T184
Test name
Test status
Simulation time 164514264 ps
CPU time 4 seconds
Started Jul 22 05:24:04 PM PDT 24
Finished Jul 22 05:24:09 PM PDT 24
Peak memory 239024 kb
Host smart-b52b21d3-85c9-4e02-a593-ff750f5bbb7f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2691713377 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_intg_err.2691713377
Directory /workspace/6.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/0.alert_handler_alert_accum_saturation.2836666547
Short name T235
Test name
Test status
Simulation time 20063275 ps
CPU time 2.67 seconds
Started Jul 22 07:16:28 PM PDT 24
Finished Jul 22 07:17:35 PM PDT 24
Peak memory 248892 kb
Host smart-27d2b10f-2136-4035-aafc-d2e9f617dbbf
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2836666547 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_alert_accum_saturation.2836666547
Directory /workspace/0.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/1.alert_handler_alert_accum_saturation.1353510465
Short name T227
Test name
Test status
Simulation time 64211730 ps
CPU time 4.12 seconds
Started Jul 22 07:16:55 PM PDT 24
Finished Jul 22 07:18:03 PM PDT 24
Peak memory 248860 kb
Host smart-3b0ff43a-32f7-49a0-a42f-1c04ea7ddf8c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1353510465 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_alert_accum_saturation.1353510465
Directory /workspace/1.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/10.alert_handler_alert_accum_saturation.97487354
Short name T48
Test name
Test status
Simulation time 101715272 ps
CPU time 2.84 seconds
Started Jul 22 07:17:23 PM PDT 24
Finished Jul 22 07:18:26 PM PDT 24
Peak memory 248892 kb
Host smart-c9c36c83-f5a3-4291-90c8-4dd107d3fd4a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=97487354 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_alert_accum_saturation.97487354
Directory /workspace/10.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/16.alert_handler_alert_accum_saturation.2060278190
Short name T231
Test name
Test status
Simulation time 261122028 ps
CPU time 3.34 seconds
Started Jul 22 07:17:47 PM PDT 24
Finished Jul 22 07:18:45 PM PDT 24
Peak memory 248976 kb
Host smart-df21bcb4-5bba-457d-bc15-35534fa8a060
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2060278190 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_alert_accum_saturation.2060278190
Directory /workspace/16.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all.1189034047
Short name T275
Test name
Test status
Simulation time 77643377319 ps
CPU time 2545.47 seconds
Started Jul 22 07:17:20 PM PDT 24
Finished Jul 22 08:00:47 PM PDT 24
Peak memory 289356 kb
Host smart-f2700beb-e955-4213-8740-e9b73134866c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189034047 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_ha
ndler_stress_all.1189034047
Directory /workspace/11.alert_handler_stress_all/latest

Test location /workspace/coverage/default/15.alert_handler_lpg.2178580719
Short name T361
Test name
Test status
Simulation time 19067739748 ps
CPU time 692.82 seconds
Started Jul 22 07:17:34 PM PDT 24
Finished Jul 22 07:30:02 PM PDT 24
Peak memory 273124 kb
Host smart-89c1d5c8-236f-4c10-b87a-a33d2457881d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178580719 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg.2178580719
Directory /workspace/15.alert_handler_lpg/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all_with_rand_reset.3398693382
Short name T261
Test name
Test status
Simulation time 92302843755 ps
CPU time 3284.6 seconds
Started Jul 22 07:17:46 PM PDT 24
Finished Jul 22 08:13:25 PM PDT 24
Peak memory 306216 kb
Host smart-f361b300-8d4d-4fa9-9c40-134cf280de98
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398693382 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.alert_handler_stress_all_with_rand_reset.3398693382
Directory /workspace/18.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.alert_handler_lpg.292040423
Short name T354
Test name
Test status
Simulation time 16440015637 ps
CPU time 1529.43 seconds
Started Jul 22 07:18:20 PM PDT 24
Finished Jul 22 07:44:41 PM PDT 24
Peak memory 288944 kb
Host smart-6928de90-a69b-4fd5-88a8-5a572ac90986
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292040423 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg.292040423
Directory /workspace/24.alert_handler_lpg/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all.2688138605
Short name T255
Test name
Test status
Simulation time 34107758436 ps
CPU time 1869.62 seconds
Started Jul 22 07:19:07 PM PDT 24
Finished Jul 22 07:50:56 PM PDT 24
Peak memory 282972 kb
Host smart-a1ee8c1e-41a4-421a-b54b-6adf6cbd1dfa
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688138605 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_ha
ndler_stress_all.2688138605
Directory /workspace/25.alert_handler_stress_all/latest

Test location /workspace/coverage/default/33.alert_handler_lpg.3676744213
Short name T360
Test name
Test status
Simulation time 171152660014 ps
CPU time 3364.68 seconds
Started Jul 22 07:18:56 PM PDT 24
Finished Jul 22 08:15:45 PM PDT 24
Peak memory 281440 kb
Host smart-65b69993-bb49-4391-b539-f8588394ecb7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3676744213 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg.3676744213
Directory /workspace/33.alert_handler_lpg/latest

Test location /workspace/coverage/default/38.alert_handler_ping_timeout.4196775724
Short name T297
Test name
Test status
Simulation time 3266514495 ps
CPU time 123.77 seconds
Started Jul 22 07:19:32 PM PDT 24
Finished Jul 22 07:21:59 PM PDT 24
Peak memory 248536 kb
Host smart-2635cf81-582a-404d-98ed-ee71b21a6c3e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196775724 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_ping_timeout.4196775724
Directory /workspace/38.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_ping_timeout.2993938573
Short name T332
Test name
Test status
Simulation time 6580859855 ps
CPU time 286.58 seconds
Started Jul 22 07:19:32 PM PDT 24
Finished Jul 22 07:24:42 PM PDT 24
Peak memory 248600 kb
Host smart-8cc8dc13-2d01-42fa-978a-6881be15bb43
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993938573 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_ping_timeout.2993938573
Directory /workspace/39.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_sig_int_fail.1213660313
Short name T101
Test name
Test status
Simulation time 367746146 ps
CPU time 12.32 seconds
Started Jul 22 07:17:23 PM PDT 24
Finished Jul 22 07:18:36 PM PDT 24
Peak memory 248656 kb
Host smart-5c709612-9937-407a-a01a-e59326344212
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12136
60313 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_sig_int_fail.1213660313
Directory /workspace/11.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.3634886249
Short name T145
Test name
Test status
Simulation time 1564840397 ps
CPU time 186.52 seconds
Started Jul 22 05:24:29 PM PDT 24
Finished Jul 22 05:27:36 PM PDT 24
Peak memory 266008 kb
Host smart-15e8be82-77ef-4dbd-a825-655876eb085a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3634886249 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shadow_reg_err
ors.3634886249
Directory /workspace/17.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.3457297256
Short name T161
Test name
Test status
Simulation time 7889866504 ps
CPU time 129.8 seconds
Started Jul 22 05:24:04 PM PDT 24
Finished Jul 22 05:26:14 PM PDT 24
Peak memory 265124 kb
Host smart-f12f3c7e-85f3-4f6f-b245-a26fdc79d586
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3457297256 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shadow_reg_erro
rs.3457297256
Directory /workspace/8.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.3791438755
Short name T163
Test name
Test status
Simulation time 4618852263 ps
CPU time 633.2 seconds
Started Jul 22 05:23:55 PM PDT 24
Finished Jul 22 05:34:29 PM PDT 24
Peak memory 266004 kb
Host smart-c926bdfe-5c10-43e8-b2fa-9e9310e09f56
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791438755 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.alert_handler_shadow_reg_errors_with_csr_rw.3791438755
Directory /workspace/5.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.3484047130
Short name T363
Test name
Test status
Simulation time 16256476 ps
CPU time 1.28 seconds
Started Jul 22 05:23:28 PM PDT 24
Finished Jul 22 05:23:30 PM PDT 24
Peak memory 238080 kb
Host smart-5463d3d4-708f-4522-b6bb-1be94397bc5f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3484047130 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_intr_test.3484047130
Directory /workspace/0.alert_handler_intr_test/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all.3174485523
Short name T265
Test name
Test status
Simulation time 207064896806 ps
CPU time 2444.54 seconds
Started Jul 22 07:16:39 PM PDT 24
Finished Jul 22 07:58:30 PM PDT 24
Peak memory 281388 kb
Host smart-1e983aae-ea4a-4dc5-82df-d51ae8d1cd84
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174485523 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_han
dler_stress_all.3174485523
Directory /workspace/1.alert_handler_stress_all/latest

Test location /workspace/coverage/default/12.alert_handler_sig_int_fail.918491797
Short name T696
Test name
Test status
Simulation time 657283872 ps
CPU time 11.89 seconds
Started Jul 22 07:17:21 PM PDT 24
Finished Jul 22 07:18:33 PM PDT 24
Peak memory 248464 kb
Host smart-bf045604-ab75-4daf-ba9d-5eeea8b26f0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91849
1797 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_sig_int_fail.918491797
Directory /workspace/12.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/14.alert_handler_lpg.2542588543
Short name T351
Test name
Test status
Simulation time 7309332454 ps
CPU time 544.99 seconds
Started Jul 22 07:18:24 PM PDT 24
Finished Jul 22 07:28:20 PM PDT 24
Peak memory 272596 kb
Host smart-a1ed2340-614c-45dd-a31d-4bab72b8e4b2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542588543 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg.2542588543
Directory /workspace/14.alert_handler_lpg/latest

Test location /workspace/coverage/default/15.alert_handler_sig_int_fail.749567619
Short name T28
Test name
Test status
Simulation time 149326441 ps
CPU time 18.53 seconds
Started Jul 22 07:17:34 PM PDT 24
Finished Jul 22 07:18:47 PM PDT 24
Peak memory 248556 kb
Host smart-a71865f3-70c3-4a86-85f9-2a1257ab8fcf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74956
7619 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_sig_int_fail.749567619
Directory /workspace/15.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/17.alert_handler_sig_int_fail.1010531918
Short name T56
Test name
Test status
Simulation time 4049123109 ps
CPU time 54.19 seconds
Started Jul 22 07:17:45 PM PDT 24
Finished Jul 22 07:19:34 PM PDT 24
Peak memory 256032 kb
Host smart-e778311d-0f98-4ae2-8f13-09d13ec5d41b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10105
31918 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_sig_int_fail.1010531918
Directory /workspace/17.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all.2443886206
Short name T269
Test name
Test status
Simulation time 201738636591 ps
CPU time 2534.59 seconds
Started Jul 22 07:17:48 PM PDT 24
Finished Jul 22 08:00:57 PM PDT 24
Peak memory 285140 kb
Host smart-019ed544-e175-4ee3-9f57-f20481cb00b4
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443886206 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_ha
ndler_stress_all.2443886206
Directory /workspace/17.alert_handler_stress_all/latest

Test location /workspace/coverage/default/18.alert_handler_lpg.871355094
Short name T359
Test name
Test status
Simulation time 60025591673 ps
CPU time 975.38 seconds
Started Jul 22 07:17:46 PM PDT 24
Finished Jul 22 07:34:56 PM PDT 24
Peak memory 272652 kb
Host smart-64892abf-9335-42fb-900e-aba9bfa629f6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871355094 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg.871355094
Directory /workspace/18.alert_handler_lpg/latest

Test location /workspace/coverage/default/18.alert_handler_ping_timeout.1687283763
Short name T711
Test name
Test status
Simulation time 6964264329 ps
CPU time 288.97 seconds
Started Jul 22 07:17:47 PM PDT 24
Finished Jul 22 07:23:30 PM PDT 24
Peak memory 256328 kb
Host smart-855fc8de-f0a7-4576-a621-33a22fa626a8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687283763 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_ping_timeout.1687283763
Directory /workspace/18.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all.1863107004
Short name T274
Test name
Test status
Simulation time 8277149455 ps
CPU time 168.46 seconds
Started Jul 22 07:18:06 PM PDT 24
Finished Jul 22 07:21:46 PM PDT 24
Peak memory 254640 kb
Host smart-3164c814-4824-462a-ad24-bddb371c996e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863107004 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_ha
ndler_stress_all.1863107004
Directory /workspace/20.alert_handler_stress_all/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all_with_rand_reset.3978381355
Short name T260
Test name
Test status
Simulation time 161225250638 ps
CPU time 2179.1 seconds
Started Jul 22 07:19:26 PM PDT 24
Finished Jul 22 07:56:13 PM PDT 24
Peak memory 289084 kb
Host smart-3bd1addc-0b30-419d-886a-a21e3c301da2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978381355 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 20.alert_handler_stress_all_with_rand_reset.3978381355
Directory /workspace/20.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.alert_handler_ping_timeout.1911397650
Short name T307
Test name
Test status
Simulation time 9713463540 ps
CPU time 400.34 seconds
Started Jul 22 07:18:36 PM PDT 24
Finished Jul 22 07:26:05 PM PDT 24
Peak memory 248676 kb
Host smart-2da277ad-73aa-470c-8622-c6abc95eca16
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911397650 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_ping_timeout.1911397650
Directory /workspace/24.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_sig_int_fail.514730496
Short name T113
Test name
Test status
Simulation time 3657347134 ps
CPU time 55.19 seconds
Started Jul 22 07:18:45 PM PDT 24
Finished Jul 22 07:20:26 PM PDT 24
Peak memory 256232 kb
Host smart-40736afa-44cc-409c-8c40-847783c82b7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51473
0496 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_sig_int_fail.514730496
Directory /workspace/29.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/6.alert_handler_random_classes.599187001
Short name T306
Test name
Test status
Simulation time 1471617114 ps
CPU time 27.38 seconds
Started Jul 22 07:16:54 PM PDT 24
Finished Jul 22 07:18:26 PM PDT 24
Peak memory 255804 kb
Host smart-44e8bb32-1288-4184-b40f-b8d9abad2e86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59918
7001 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_classes.599187001
Directory /workspace/6.alert_handler_random_classes/latest

Test location /workspace/coverage/default/10.alert_handler_lpg.1922981919
Short name T7
Test name
Test status
Simulation time 35339745047 ps
CPU time 1685.87 seconds
Started Jul 22 07:17:23 PM PDT 24
Finished Jul 22 07:46:28 PM PDT 24
Peak memory 272644 kb
Host smart-8e56287e-0386-4bea-8f64-aac929fb4889
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922981919 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg.1922981919
Directory /workspace/10.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.2817166671
Short name T180
Test name
Test status
Simulation time 256161157 ps
CPU time 4.54 seconds
Started Jul 22 05:24:34 PM PDT 24
Finished Jul 22 05:24:39 PM PDT 24
Peak memory 238368 kb
Host smart-a2369499-04e0-4ffd-8912-77c6b0a272d8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2817166671 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_intg_err.2817166671
Directory /workspace/17.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.735107845
Short name T179
Test name
Test status
Simulation time 3118022588 ps
CPU time 63.82 seconds
Started Jul 22 05:23:39 PM PDT 24
Finished Jul 22 05:24:44 PM PDT 24
Peak memory 241048 kb
Host smart-0e896468-ca04-46fc-a3fb-03e074147a11
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=735107845 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_intg_err.735107845
Directory /workspace/2.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.1142737054
Short name T185
Test name
Test status
Simulation time 3524004239 ps
CPU time 67.73 seconds
Started Jul 22 05:24:33 PM PDT 24
Finished Jul 22 05:25:41 PM PDT 24
Peak memory 241080 kb
Host smart-afa3400d-c7d8-4eca-9d18-2bce4cd218bc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1142737054 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_intg_err.1142737054
Directory /workspace/14.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.2877075218
Short name T159
Test name
Test status
Simulation time 3118840846 ps
CPU time 300.4 seconds
Started Jul 22 05:23:27 PM PDT 24
Finished Jul 22 05:28:27 PM PDT 24
Peak memory 273184 kb
Host smart-cac3d99a-918d-4ec5-900c-32ee5a2f294e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2877075218 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shadow_reg_erro
rs.2877075218
Directory /workspace/0.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.2824684542
Short name T162
Test name
Test status
Simulation time 20326408898 ps
CPU time 851.23 seconds
Started Jul 22 05:24:33 PM PDT 24
Finished Jul 22 05:38:45 PM PDT 24
Peak memory 273872 kb
Host smart-468bcf04-c842-4d75-b785-a458f45dd32e
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824684542 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 16.alert_handler_shadow_reg_errors_with_csr_rw.2824684542
Directory /workspace/16.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.1219086896
Short name T186
Test name
Test status
Simulation time 101070793 ps
CPU time 6.05 seconds
Started Jul 22 05:25:09 PM PDT 24
Finished Jul 22 05:25:15 PM PDT 24
Peak memory 238988 kb
Host smart-549b7214-0a58-4119-8b20-21379839df50
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1219086896 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_intg_err.1219086896
Directory /workspace/18.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.1068247379
Short name T181
Test name
Test status
Simulation time 175911578 ps
CPU time 25.54 seconds
Started Jul 22 05:23:50 PM PDT 24
Finished Jul 22 05:24:16 PM PDT 24
Peak memory 240952 kb
Host smart-c8c272b9-d462-4cfd-a5d5-b92fc7a27eaa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1068247379 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_intg_err.1068247379
Directory /workspace/3.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.177004684
Short name T178
Test name
Test status
Simulation time 756167081 ps
CPU time 55.1 seconds
Started Jul 22 05:23:44 PM PDT 24
Finished Jul 22 05:24:39 PM PDT 24
Peak memory 240912 kb
Host smart-7ed02f7f-afc4-427c-bb58-890a6e47f1f8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=177004684 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_intg_err.177004684
Directory /workspace/4.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.3055495344
Short name T183
Test name
Test status
Simulation time 4401030942 ps
CPU time 84.11 seconds
Started Jul 22 05:23:52 PM PDT 24
Finished Jul 22 05:25:17 PM PDT 24
Peak memory 241000 kb
Host smart-4b83ed90-fa86-415a-93ec-454f73f2dfed
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3055495344 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_intg_err.3055495344
Directory /workspace/5.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.2113976973
Short name T174
Test name
Test status
Simulation time 1122327682 ps
CPU time 49.62 seconds
Started Jul 22 05:24:03 PM PDT 24
Finished Jul 22 05:24:53 PM PDT 24
Peak memory 240828 kb
Host smart-a814d4e1-9353-466b-a672-91845e3718dc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2113976973 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_intg_err.2113976973
Directory /workspace/7.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.253210609
Short name T173
Test name
Test status
Simulation time 63261203 ps
CPU time 2.33 seconds
Started Jul 22 05:24:07 PM PDT 24
Finished Jul 22 05:24:09 PM PDT 24
Peak memory 239004 kb
Host smart-1f05acb8-9825-40ad-90d8-ded006819dd3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=253210609 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_intg_err.253210609
Directory /workspace/1.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_intg_err.2464180257
Short name T193
Test name
Test status
Simulation time 902695412 ps
CPU time 31.43 seconds
Started Jul 22 05:24:20 PM PDT 24
Finished Jul 22 05:24:52 PM PDT 24
Peak memory 240976 kb
Host smart-0e7e3e79-62d4-4c9b-bfee-942c8975cb9c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2464180257 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_intg_err.2464180257
Directory /workspace/12.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.1816770243
Short name T196
Test name
Test status
Simulation time 51212583 ps
CPU time 3.62 seconds
Started Jul 22 05:24:22 PM PDT 24
Finished Jul 22 05:24:26 PM PDT 24
Peak memory 238040 kb
Host smart-137d17a0-8bb5-4fd3-a4ec-7cec39734b83
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1816770243 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_intg_err.1816770243
Directory /workspace/13.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.3323037687
Short name T192
Test name
Test status
Simulation time 40996650 ps
CPU time 3.37 seconds
Started Jul 22 05:24:33 PM PDT 24
Finished Jul 22 05:24:37 PM PDT 24
Peak memory 239088 kb
Host smart-3b6bf659-9432-42b8-9da0-4e9730a1b28b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3323037687 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_intg_err.3323037687
Directory /workspace/15.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.602567857
Short name T195
Test name
Test status
Simulation time 1248740368 ps
CPU time 45.83 seconds
Started Jul 22 05:24:43 PM PDT 24
Finished Jul 22 05:25:29 PM PDT 24
Peak memory 240264 kb
Host smart-7d9f8a97-33ef-4dfc-8351-e26b864983e6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=602567857 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_intg_err.602567857
Directory /workspace/19.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.3700844115
Short name T191
Test name
Test status
Simulation time 52309945 ps
CPU time 2.85 seconds
Started Jul 22 05:24:15 PM PDT 24
Finished Jul 22 05:24:18 PM PDT 24
Peak memory 238264 kb
Host smart-1fcda147-6b83-4c1f-a3d2-9571ac49b7fb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3700844115 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_intg_err.3700844115
Directory /workspace/8.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.1147141343
Short name T182
Test name
Test status
Simulation time 72789897 ps
CPU time 2.9 seconds
Started Jul 22 05:26:07 PM PDT 24
Finished Jul 22 05:26:10 PM PDT 24
Peak memory 237104 kb
Host smart-2056e769-64c7-4d19-b426-d916209693ad
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1147141343 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_intg_err.1147141343
Directory /workspace/9.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/0.alert_handler_random_classes.4241297938
Short name T24
Test name
Test status
Simulation time 1781759915 ps
CPU time 18.73 seconds
Started Jul 22 07:16:29 PM PDT 24
Finished Jul 22 07:17:55 PM PDT 24
Peak memory 248068 kb
Host smart-65c88fb3-9b50-4e5c-968a-ed945fffbe80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42412
97938 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_classes.4241297938
Directory /workspace/0.alert_handler_random_classes/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.1748841256
Short name T838
Test name
Test status
Simulation time 30085224195 ps
CPU time 342.98 seconds
Started Jul 22 05:23:27 PM PDT 24
Finished Jul 22 05:29:10 PM PDT 24
Peak memory 241820 kb
Host smart-2f1513d7-a410-46f2-a777-6073663da915
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1748841256 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_aliasing.1748841256
Directory /workspace/0.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.723491575
Short name T758
Test name
Test status
Simulation time 7716058560 ps
CPU time 212.73 seconds
Started Jul 22 05:23:29 PM PDT 24
Finished Jul 22 05:27:02 PM PDT 24
Peak memory 237204 kb
Host smart-717c26ab-7843-45d4-a6d9-4a9153b3f9f0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=723491575 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_bit_bash.723491575
Directory /workspace/0.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.2106385951
Short name T763
Test name
Test status
Simulation time 60206747 ps
CPU time 5.27 seconds
Started Jul 22 05:23:27 PM PDT 24
Finished Jul 22 05:23:33 PM PDT 24
Peak memory 249104 kb
Host smart-c249b207-2090-48aa-92a2-75e6508b2e41
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2106385951 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_hw_reset.2106385951
Directory /workspace/0.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.1424791467
Short name T190
Test name
Test status
Simulation time 108770033 ps
CPU time 4.89 seconds
Started Jul 22 05:23:27 PM PDT 24
Finished Jul 22 05:23:33 PM PDT 24
Peak memory 240128 kb
Host smart-6138f3ab-2fb2-4bf2-8091-b566f5150195
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424791467 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 0.alert_handler_csr_mem_rw_with_rand_reset.1424791467
Directory /workspace/0.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.2449651895
Short name T800
Test name
Test status
Simulation time 38099495 ps
CPU time 5.72 seconds
Started Jul 22 05:24:02 PM PDT 24
Finished Jul 22 05:24:09 PM PDT 24
Peak memory 238064 kb
Host smart-ae40ad31-7555-4c40-913d-2d947e107f1f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2449651895 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_rw.2449651895
Directory /workspace/0.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.3303667842
Short name T728
Test name
Test status
Simulation time 85560076 ps
CPU time 11.4 seconds
Started Jul 22 05:23:28 PM PDT 24
Finished Jul 22 05:23:40 PM PDT 24
Peak memory 245264 kb
Host smart-b5f02c00-a39d-4597-8d49-fe51c7f35674
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3303667842 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_same_csr_out
standing.3303667842
Directory /workspace/0.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.3128067272
Short name T166
Test name
Test status
Simulation time 27568641641 ps
CPU time 274.91 seconds
Started Jul 22 05:23:30 PM PDT 24
Finished Jul 22 05:28:06 PM PDT 24
Peak memory 269676 kb
Host smart-63fcb328-d852-434d-bf78-4c13bc4a0a1f
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128067272 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.alert_handler_shadow_reg_errors_with_csr_rw.3128067272
Directory /workspace/0.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.3637468867
Short name T816
Test name
Test status
Simulation time 1413362765 ps
CPU time 26.15 seconds
Started Jul 22 05:23:30 PM PDT 24
Finished Jul 22 05:23:57 PM PDT 24
Peak memory 255100 kb
Host smart-bbaedcc6-34e2-4601-835b-ddef4582707b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3637468867 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_errors.3637468867
Directory /workspace/0.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.1766949204
Short name T194
Test name
Test status
Simulation time 153132705 ps
CPU time 2.59 seconds
Started Jul 22 05:23:57 PM PDT 24
Finished Jul 22 05:24:00 PM PDT 24
Peak memory 238372 kb
Host smart-c266d0a4-6321-4bd3-9a56-9a79a0dda42e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1766949204 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_intg_err.1766949204
Directory /workspace/0.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.2257020455
Short name T212
Test name
Test status
Simulation time 4886660697 ps
CPU time 309.24 seconds
Started Jul 22 05:24:59 PM PDT 24
Finished Jul 22 05:30:09 PM PDT 24
Peak memory 242444 kb
Host smart-5593432c-87b2-42eb-add6-91e3a6be52c8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2257020455 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_aliasing.2257020455
Directory /workspace/1.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.3946052385
Short name T786
Test name
Test status
Simulation time 3407645619 ps
CPU time 112.36 seconds
Started Jul 22 05:23:40 PM PDT 24
Finished Jul 22 05:25:33 PM PDT 24
Peak memory 238144 kb
Host smart-a8050a57-27d6-470e-8f72-d4e2d96770ef
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3946052385 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_bit_bash.3946052385
Directory /workspace/1.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.3579676390
Short name T725
Test name
Test status
Simulation time 147190914 ps
CPU time 6.96 seconds
Started Jul 22 05:24:59 PM PDT 24
Finished Jul 22 05:25:06 PM PDT 24
Peak memory 249160 kb
Host smart-62366e47-df32-480d-9c6f-df392927f990
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3579676390 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_hw_reset.3579676390
Directory /workspace/1.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.1588890601
Short name T802
Test name
Test status
Simulation time 291091218 ps
CPU time 4.97 seconds
Started Jul 22 05:23:35 PM PDT 24
Finished Jul 22 05:23:40 PM PDT 24
Peak memory 240240 kb
Host smart-6aa16c00-7888-4648-94d6-ffc89a468ffe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588890601 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 1.alert_handler_csr_mem_rw_with_rand_reset.1588890601
Directory /workspace/1.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.2665697686
Short name T823
Test name
Test status
Simulation time 749536230 ps
CPU time 13.99 seconds
Started Jul 22 05:23:35 PM PDT 24
Finished Jul 22 05:23:49 PM PDT 24
Peak memory 246252 kb
Host smart-80a002e2-a22d-45dd-99be-95f8de5278e9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2665697686 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_same_csr_out
standing.2665697686
Directory /workspace/1.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.511110403
Short name T154
Test name
Test status
Simulation time 1913792629 ps
CPU time 189.76 seconds
Started Jul 22 05:23:35 PM PDT 24
Finished Jul 22 05:26:46 PM PDT 24
Peak memory 265912 kb
Host smart-f1e655ca-b280-477b-839d-70a0549aa59c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=511110403 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shadow_reg_error
s.511110403
Directory /workspace/1.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.4268659681
Short name T737
Test name
Test status
Simulation time 312672904 ps
CPU time 22.27 seconds
Started Jul 22 05:23:40 PM PDT 24
Finished Jul 22 05:24:03 PM PDT 24
Peak memory 249176 kb
Host smart-a1e71b52-9d5c-4351-8a4b-1c8db660cf54
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4268659681 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_errors.4268659681
Directory /workspace/1.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.2432863856
Short name T813
Test name
Test status
Simulation time 156888786 ps
CPU time 12.23 seconds
Started Jul 22 05:26:01 PM PDT 24
Finished Jul 22 05:26:14 PM PDT 24
Peak memory 250336 kb
Host smart-29fad9b4-caf2-4a14-9891-80fac1070b57
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432863856 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 10.alert_handler_csr_mem_rw_with_rand_reset.2432863856
Directory /workspace/10.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.1444345901
Short name T794
Test name
Test status
Simulation time 96254657 ps
CPU time 7.62 seconds
Started Jul 22 05:24:19 PM PDT 24
Finished Jul 22 05:24:27 PM PDT 24
Peak memory 237056 kb
Host smart-5a391219-5f70-41f6-871d-486989411c5d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1444345901 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_csr_rw.1444345901
Directory /workspace/10.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.1725234157
Short name T769
Test name
Test status
Simulation time 16484779 ps
CPU time 1.77 seconds
Started Jul 22 05:24:21 PM PDT 24
Finished Jul 22 05:24:23 PM PDT 24
Peak memory 237120 kb
Host smart-8d7496ac-3c2b-46f5-b903-132565caeb7b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1725234157 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_intr_test.1725234157
Directory /workspace/10.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.474398040
Short name T730
Test name
Test status
Simulation time 334023297 ps
CPU time 24.11 seconds
Started Jul 22 05:24:19 PM PDT 24
Finished Jul 22 05:24:43 PM PDT 24
Peak memory 246224 kb
Host smart-d216b437-e623-4816-a850-8c4229a18c94
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=474398040 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_same_csr_out
standing.474398040
Directory /workspace/10.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.1434152562
Short name T157
Test name
Test status
Simulation time 2056225459 ps
CPU time 125.19 seconds
Started Jul 22 05:24:12 PM PDT 24
Finished Jul 22 05:26:17 PM PDT 24
Peak memory 266164 kb
Host smart-86990199-b9fe-46d7-a5b1-078757d42815
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1434152562 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shadow_reg_err
ors.1434152562
Directory /workspace/10.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.2485643547
Short name T806
Test name
Test status
Simulation time 17080243678 ps
CPU time 504.82 seconds
Started Jul 22 05:24:12 PM PDT 24
Finished Jul 22 05:32:38 PM PDT 24
Peak memory 268880 kb
Host smart-1089244e-2edb-4fb9-bb8d-daa3bee7aef4
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485643547 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 10.alert_handler_shadow_reg_errors_with_csr_rw.2485643547
Directory /workspace/10.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.2631504528
Short name T768
Test name
Test status
Simulation time 71767852 ps
CPU time 8.7 seconds
Started Jul 22 05:24:10 PM PDT 24
Finished Jul 22 05:24:19 PM PDT 24
Peak memory 253788 kb
Host smart-670c8343-d38d-4eff-b821-d224a07ebed5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2631504528 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_errors.2631504528
Directory /workspace/10.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.2665946164
Short name T187
Test name
Test status
Simulation time 92354812 ps
CPU time 2.86 seconds
Started Jul 22 05:24:20 PM PDT 24
Finished Jul 22 05:24:23 PM PDT 24
Peak memory 238060 kb
Host smart-a285ec52-d1e9-469d-8d45-86876322bb9e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2665946164 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_intg_err.2665946164
Directory /workspace/10.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.3460484779
Short name T731
Test name
Test status
Simulation time 99665931 ps
CPU time 9.18 seconds
Started Jul 22 05:24:20 PM PDT 24
Finished Jul 22 05:24:29 PM PDT 24
Peak memory 240988 kb
Host smart-f8c37c04-4a22-45b5-adde-3232251185b0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460484779 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 11.alert_handler_csr_mem_rw_with_rand_reset.3460484779
Directory /workspace/11.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.3950016005
Short name T804
Test name
Test status
Simulation time 50654169 ps
CPU time 5.35 seconds
Started Jul 22 05:24:21 PM PDT 24
Finished Jul 22 05:24:27 PM PDT 24
Peak memory 238004 kb
Host smart-cc95cbc0-8920-4a15-8829-af57a5139c64
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3950016005 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_csr_rw.3950016005
Directory /workspace/11.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.2601451157
Short name T751
Test name
Test status
Simulation time 17664435 ps
CPU time 1.42 seconds
Started Jul 22 05:24:21 PM PDT 24
Finished Jul 22 05:24:23 PM PDT 24
Peak memory 238060 kb
Host smart-ca55c484-845b-4d99-9636-13603a2037ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2601451157 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_intr_test.2601451157
Directory /workspace/11.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.3123474225
Short name T208
Test name
Test status
Simulation time 266637690 ps
CPU time 23.15 seconds
Started Jul 22 05:24:18 PM PDT 24
Finished Jul 22 05:24:42 PM PDT 24
Peak memory 247284 kb
Host smart-59f1b416-99d2-4798-9bcc-d1c41f47b1ac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3123474225 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_same_csr_ou
tstanding.3123474225
Directory /workspace/11.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.251976458
Short name T141
Test name
Test status
Simulation time 9722047334 ps
CPU time 158.71 seconds
Started Jul 22 05:24:19 PM PDT 24
Finished Jul 22 05:26:58 PM PDT 24
Peak memory 257760 kb
Host smart-696ac01a-dc91-439b-b08a-cdf6b0a043a1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=251976458 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shadow_reg_erro
rs.251976458
Directory /workspace/11.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.399007274
Short name T169
Test name
Test status
Simulation time 8599009628 ps
CPU time 671.61 seconds
Started Jul 22 05:24:18 PM PDT 24
Finished Jul 22 05:35:31 PM PDT 24
Peak memory 266028 kb
Host smart-34fe16ab-38bb-4427-a375-790fd8dcbddc
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399007274 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 11.alert_handler_shadow_reg_errors_with_csr_rw.399007274
Directory /workspace/11.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.3063635886
Short name T753
Test name
Test status
Simulation time 757945661 ps
CPU time 14.14 seconds
Started Jul 22 05:24:18 PM PDT 24
Finished Jul 22 05:24:32 PM PDT 24
Peak memory 249112 kb
Host smart-f744409c-15ad-4040-aa58-fed36159123c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3063635886 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_errors.3063635886
Directory /workspace/11.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.1707399373
Short name T217
Test name
Test status
Simulation time 506092746 ps
CPU time 5.73 seconds
Started Jul 22 05:24:18 PM PDT 24
Finished Jul 22 05:24:24 PM PDT 24
Peak memory 257468 kb
Host smart-b4b1046e-1628-4b1e-b9fc-f61893a5f4bf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707399373 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 12.alert_handler_csr_mem_rw_with_rand_reset.1707399373
Directory /workspace/12.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.2820800382
Short name T819
Test name
Test status
Simulation time 480463899 ps
CPU time 9.84 seconds
Started Jul 22 05:24:53 PM PDT 24
Finished Jul 22 05:25:04 PM PDT 24
Peak memory 238036 kb
Host smart-84f777be-74c4-4038-a119-916a412b4b10
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2820800382 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_csr_rw.2820800382
Directory /workspace/12.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.498962902
Short name T809
Test name
Test status
Simulation time 12555268 ps
CPU time 1.59 seconds
Started Jul 22 05:24:21 PM PDT 24
Finished Jul 22 05:24:23 PM PDT 24
Peak memory 237188 kb
Host smart-20404cb6-a2c5-4096-a45d-8fcee4192e3a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=498962902 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_intr_test.498962902
Directory /workspace/12.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.1542767416
Short name T840
Test name
Test status
Simulation time 326032264 ps
CPU time 25.07 seconds
Started Jul 22 05:24:20 PM PDT 24
Finished Jul 22 05:24:46 PM PDT 24
Peak memory 246248 kb
Host smart-3b9ed550-f648-4d04-830b-2137c8c44a22
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1542767416 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_same_csr_ou
tstanding.1542767416
Directory /workspace/12.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.827507129
Short name T135
Test name
Test status
Simulation time 2196549794 ps
CPU time 327.95 seconds
Started Jul 22 05:24:22 PM PDT 24
Finished Jul 22 05:29:50 PM PDT 24
Peak memory 269480 kb
Host smart-5a95e459-5797-4952-95cd-a3375f47715f
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827507129 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 12.alert_handler_shadow_reg_errors_with_csr_rw.827507129
Directory /workspace/12.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.3919209919
Short name T764
Test name
Test status
Simulation time 1049611700 ps
CPU time 19.44 seconds
Started Jul 22 05:24:21 PM PDT 24
Finished Jul 22 05:24:41 PM PDT 24
Peak memory 249016 kb
Host smart-9ed0640e-6a4c-4d43-b38e-11b1866a74c9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3919209919 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_errors.3919209919
Directory /workspace/12.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.1068381111
Short name T831
Test name
Test status
Simulation time 75092967 ps
CPU time 6.74 seconds
Started Jul 22 05:24:32 PM PDT 24
Finished Jul 22 05:24:39 PM PDT 24
Peak memory 241080 kb
Host smart-3feb6fa1-65b8-4574-a890-d802c8b86201
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068381111 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 13.alert_handler_csr_mem_rw_with_rand_reset.1068381111
Directory /workspace/13.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.2473732927
Short name T777
Test name
Test status
Simulation time 20349418 ps
CPU time 3.66 seconds
Started Jul 22 05:24:54 PM PDT 24
Finished Jul 22 05:24:58 PM PDT 24
Peak memory 240904 kb
Host smart-7e55be81-c1bb-40f4-9f82-9535a530f07e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2473732927 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_csr_rw.2473732927
Directory /workspace/13.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.4167295730
Short name T734
Test name
Test status
Simulation time 19667573 ps
CPU time 1.3 seconds
Started Jul 22 05:24:48 PM PDT 24
Finished Jul 22 05:24:50 PM PDT 24
Peak memory 238036 kb
Host smart-d5745d67-adf3-446b-9424-cfce416a9a50
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4167295730 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_intr_test.4167295730
Directory /workspace/13.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.3872678426
Short name T803
Test name
Test status
Simulation time 2525986992 ps
CPU time 23.53 seconds
Started Jul 22 05:24:32 PM PDT 24
Finished Jul 22 05:24:56 PM PDT 24
Peak memory 249304 kb
Host smart-7c0d76c5-0384-4009-a000-a8ccb622b33c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3872678426 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_same_csr_ou
tstanding.3872678426
Directory /workspace/13.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.2240201028
Short name T835
Test name
Test status
Simulation time 859618392 ps
CPU time 107.08 seconds
Started Jul 22 05:24:23 PM PDT 24
Finished Jul 22 05:26:10 PM PDT 24
Peak memory 265948 kb
Host smart-0d3357cf-0c4b-440d-97ca-3bdbf5365b0b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2240201028 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shadow_reg_err
ors.2240201028
Directory /workspace/13.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.2350864176
Short name T722
Test name
Test status
Simulation time 272662004 ps
CPU time 21.14 seconds
Started Jul 22 05:26:01 PM PDT 24
Finished Jul 22 05:26:22 PM PDT 24
Peak memory 249236 kb
Host smart-ed5e7985-b009-4c1e-b3ee-7aa17d6b3c24
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2350864176 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_errors.2350864176
Directory /workspace/13.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.4065458421
Short name T810
Test name
Test status
Simulation time 414133402 ps
CPU time 8.39 seconds
Started Jul 22 05:24:33 PM PDT 24
Finished Jul 22 05:24:42 PM PDT 24
Peak memory 241484 kb
Host smart-beb86460-d790-4262-a34a-05f43724e4e4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065458421 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 14.alert_handler_csr_mem_rw_with_rand_reset.4065458421
Directory /workspace/14.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.1840832222
Short name T724
Test name
Test status
Simulation time 1304306168 ps
CPU time 8.93 seconds
Started Jul 22 05:24:31 PM PDT 24
Finished Jul 22 05:24:40 PM PDT 24
Peak memory 238064 kb
Host smart-9db55e7b-f285-4122-ae02-c30e0571cfdf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1840832222 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_csr_rw.1840832222
Directory /workspace/14.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.108587879
Short name T366
Test name
Test status
Simulation time 8458873 ps
CPU time 1.55 seconds
Started Jul 22 05:24:31 PM PDT 24
Finished Jul 22 05:24:33 PM PDT 24
Peak memory 236120 kb
Host smart-786d27a9-86d3-455b-b71b-e2b6c00aee33
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=108587879 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_intr_test.108587879
Directory /workspace/14.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.3765865039
Short name T812
Test name
Test status
Simulation time 324980521 ps
CPU time 22.37 seconds
Started Jul 22 05:24:33 PM PDT 24
Finished Jul 22 05:24:56 PM PDT 24
Peak memory 249072 kb
Host smart-180e31d2-6d1a-4d80-8d17-c5676b390b1b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3765865039 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_same_csr_ou
tstanding.3765865039
Directory /workspace/14.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.1490432890
Short name T156
Test name
Test status
Simulation time 17455540819 ps
CPU time 314.47 seconds
Started Jul 22 05:24:29 PM PDT 24
Finished Jul 22 05:29:45 PM PDT 24
Peak memory 266028 kb
Host smart-9b94717b-68e7-48b8-9c11-14414307bff8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1490432890 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shadow_reg_err
ors.1490432890
Directory /workspace/14.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.2588600691
Short name T148
Test name
Test status
Simulation time 2327181377 ps
CPU time 330.24 seconds
Started Jul 22 05:24:29 PM PDT 24
Finished Jul 22 05:30:00 PM PDT 24
Peak memory 269664 kb
Host smart-aa03b39f-d412-435d-aae2-2b44bbd3bd75
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588600691 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 14.alert_handler_shadow_reg_errors_with_csr_rw.2588600691
Directory /workspace/14.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.1859676574
Short name T746
Test name
Test status
Simulation time 697124830 ps
CPU time 24.09 seconds
Started Jul 22 05:24:37 PM PDT 24
Finished Jul 22 05:25:02 PM PDT 24
Peak memory 249240 kb
Host smart-e242467c-463f-4e73-888b-0eddb652ba75
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1859676574 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_errors.1859676574
Directory /workspace/14.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.1248703107
Short name T372
Test name
Test status
Simulation time 100343337 ps
CPU time 5.72 seconds
Started Jul 22 05:24:33 PM PDT 24
Finished Jul 22 05:24:39 PM PDT 24
Peak memory 239900 kb
Host smart-64ecb04f-7cd0-4419-96da-86d3bd4631ea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248703107 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 15.alert_handler_csr_mem_rw_with_rand_reset.1248703107
Directory /workspace/15.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.4177682497
Short name T189
Test name
Test status
Simulation time 174922446 ps
CPU time 5.05 seconds
Started Jul 22 05:24:32 PM PDT 24
Finished Jul 22 05:24:38 PM PDT 24
Peak memory 238024 kb
Host smart-e434496d-078c-44fe-b6b6-115b1b322279
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4177682497 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_csr_rw.4177682497
Directory /workspace/15.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.1823305183
Short name T177
Test name
Test status
Simulation time 8313841 ps
CPU time 1.56 seconds
Started Jul 22 05:24:30 PM PDT 24
Finished Jul 22 05:24:32 PM PDT 24
Peak memory 236108 kb
Host smart-000b083e-2bc7-47ad-9364-b5ce5cd69d88
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1823305183 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_intr_test.1823305183
Directory /workspace/15.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.3978476010
Short name T766
Test name
Test status
Simulation time 4552296489 ps
CPU time 39.31 seconds
Started Jul 22 05:24:31 PM PDT 24
Finished Jul 22 05:25:11 PM PDT 24
Peak memory 249272 kb
Host smart-a0e000cb-2e2d-40e3-935f-50f23da1882c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3978476010 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_same_csr_ou
tstanding.3978476010
Directory /workspace/15.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.1150964084
Short name T136
Test name
Test status
Simulation time 2471658235 ps
CPU time 184.37 seconds
Started Jul 22 05:24:33 PM PDT 24
Finished Jul 22 05:27:38 PM PDT 24
Peak memory 266108 kb
Host smart-0c32558d-1940-4679-8e10-f1481398600d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1150964084 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shadow_reg_err
ors.1150964084
Directory /workspace/15.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.4205386925
Short name T167
Test name
Test status
Simulation time 31636139954 ps
CPU time 1090.16 seconds
Started Jul 22 05:25:03 PM PDT 24
Finished Jul 22 05:43:14 PM PDT 24
Peak memory 273644 kb
Host smart-21d1c58d-61df-410f-978b-93db374b1c87
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205386925 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 15.alert_handler_shadow_reg_errors_with_csr_rw.4205386925
Directory /workspace/15.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.1699485529
Short name T750
Test name
Test status
Simulation time 71010659 ps
CPU time 5.08 seconds
Started Jul 22 05:24:33 PM PDT 24
Finished Jul 22 05:24:39 PM PDT 24
Peak memory 254848 kb
Host smart-3e5c617d-f1d9-4642-b803-efdce0c44f44
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1699485529 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_errors.1699485529
Directory /workspace/15.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.3312810099
Short name T759
Test name
Test status
Simulation time 87392406 ps
CPU time 6.79 seconds
Started Jul 22 05:24:34 PM PDT 24
Finished Jul 22 05:24:41 PM PDT 24
Peak memory 240212 kb
Host smart-72c34818-2032-4968-947b-b0e9909c8147
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312810099 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 16.alert_handler_csr_mem_rw_with_rand_reset.3312810099
Directory /workspace/16.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.741110638
Short name T771
Test name
Test status
Simulation time 132271448 ps
CPU time 9.45 seconds
Started Jul 22 05:24:32 PM PDT 24
Finished Jul 22 05:24:42 PM PDT 24
Peak memory 237104 kb
Host smart-5561d48f-975d-4ad2-ad30-19b47549e169
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=741110638 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_csr_rw.741110638
Directory /workspace/16.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.2180554425
Short name T832
Test name
Test status
Simulation time 9331761 ps
CPU time 1.72 seconds
Started Jul 22 05:24:30 PM PDT 24
Finished Jul 22 05:24:32 PM PDT 24
Peak memory 237160 kb
Host smart-4a681e54-a7c5-42b8-89e0-269dd278a7ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2180554425 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_intr_test.2180554425
Directory /workspace/16.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.2785193219
Short name T814
Test name
Test status
Simulation time 353893650 ps
CPU time 27.41 seconds
Started Jul 22 05:25:03 PM PDT 24
Finished Jul 22 05:25:31 PM PDT 24
Peak memory 249072 kb
Host smart-345aa494-0ef1-4340-8039-ca3d875afefc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2785193219 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_same_csr_ou
tstanding.2785193219
Directory /workspace/16.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.1250809005
Short name T165
Test name
Test status
Simulation time 4820627046 ps
CPU time 310.79 seconds
Started Jul 22 05:24:33 PM PDT 24
Finished Jul 22 05:29:44 PM PDT 24
Peak memory 265828 kb
Host smart-f701e90f-03c1-44a2-945f-6660f336ea29
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1250809005 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shadow_reg_err
ors.1250809005
Directory /workspace/16.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.2112989808
Short name T767
Test name
Test status
Simulation time 170715618 ps
CPU time 13.65 seconds
Started Jul 22 05:24:37 PM PDT 24
Finished Jul 22 05:24:51 PM PDT 24
Peak memory 248964 kb
Host smart-fe368a24-b060-4f58-b02c-588d803cc4ff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2112989808 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_errors.2112989808
Directory /workspace/16.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.53767373
Short name T808
Test name
Test status
Simulation time 543086020 ps
CPU time 22.64 seconds
Started Jul 22 05:24:34 PM PDT 24
Finished Jul 22 05:24:57 PM PDT 24
Peak memory 248052 kb
Host smart-a86eb49b-c04a-4490-b1f9-24736ac6d813
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=53767373 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_intg_err.53767373
Directory /workspace/16.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.1362438429
Short name T373
Test name
Test status
Simulation time 260420913 ps
CPU time 10.48 seconds
Started Jul 22 05:24:42 PM PDT 24
Finished Jul 22 05:24:53 PM PDT 24
Peak memory 257180 kb
Host smart-42c00cc9-2e54-4f44-879f-7cf469c4de18
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362438429 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 17.alert_handler_csr_mem_rw_with_rand_reset.1362438429
Directory /workspace/17.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.4003095263
Short name T839
Test name
Test status
Simulation time 62344467 ps
CPU time 3.29 seconds
Started Jul 22 05:24:30 PM PDT 24
Finished Jul 22 05:24:34 PM PDT 24
Peak memory 240940 kb
Host smart-7a538611-2df4-4d17-b62d-00fb0980f9ce
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4003095263 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_csr_rw.4003095263
Directory /workspace/17.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.842596050
Short name T775
Test name
Test status
Simulation time 66616412 ps
CPU time 1.41 seconds
Started Jul 22 05:24:38 PM PDT 24
Finished Jul 22 05:24:39 PM PDT 24
Peak memory 237216 kb
Host smart-63809ce4-5f5e-416b-88f0-fb34ba50cd9b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=842596050 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_intr_test.842596050
Directory /workspace/17.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.2036773396
Short name T828
Test name
Test status
Simulation time 258756656 ps
CPU time 17.24 seconds
Started Jul 22 05:24:38 PM PDT 24
Finished Jul 22 05:24:55 PM PDT 24
Peak memory 249044 kb
Host smart-18cb766f-4210-43a9-b4ec-1cb62f6e2eb0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2036773396 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_same_csr_ou
tstanding.2036773396
Directory /workspace/17.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.2683616710
Short name T139
Test name
Test status
Simulation time 28862874826 ps
CPU time 499.34 seconds
Started Jul 22 05:24:32 PM PDT 24
Finished Jul 22 05:32:52 PM PDT 24
Peak memory 266048 kb
Host smart-a7330684-9325-437d-870c-6df4fae6a791
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683616710 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 17.alert_handler_shadow_reg_errors_with_csr_rw.2683616710
Directory /workspace/17.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.356904186
Short name T805
Test name
Test status
Simulation time 108387204 ps
CPU time 8.39 seconds
Started Jul 22 05:24:31 PM PDT 24
Finished Jul 22 05:24:40 PM PDT 24
Peak memory 249360 kb
Host smart-5ec4aa93-4c44-4c86-99ee-9a2a66752a13
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=356904186 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_errors.356904186
Directory /workspace/17.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.1338382399
Short name T797
Test name
Test status
Simulation time 190409904 ps
CPU time 6.97 seconds
Started Jul 22 05:24:42 PM PDT 24
Finished Jul 22 05:24:50 PM PDT 24
Peak memory 241632 kb
Host smart-db8d2def-658e-4ba0-bb8a-e7efc6a8bb7c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338382399 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 18.alert_handler_csr_mem_rw_with_rand_reset.1338382399
Directory /workspace/18.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.630127828
Short name T773
Test name
Test status
Simulation time 570523212 ps
CPU time 7.94 seconds
Started Jul 22 05:24:46 PM PDT 24
Finished Jul 22 05:24:55 PM PDT 24
Peak memory 238036 kb
Host smart-fdb85e78-6e0f-4ca1-95d0-27fcb431ac73
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=630127828 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_csr_rw.630127828
Directory /workspace/18.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.3277461808
Short name T176
Test name
Test status
Simulation time 9487703 ps
CPU time 1.54 seconds
Started Jul 22 05:24:42 PM PDT 24
Finished Jul 22 05:24:45 PM PDT 24
Peak memory 238072 kb
Host smart-b3f7ecf8-01a1-4835-98fa-15479ae92d3d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3277461808 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_intr_test.3277461808
Directory /workspace/18.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.2591972763
Short name T743
Test name
Test status
Simulation time 12946990204 ps
CPU time 44.08 seconds
Started Jul 22 05:25:28 PM PDT 24
Finished Jul 22 05:26:13 PM PDT 24
Peak memory 249296 kb
Host smart-850fc66c-17ec-42f6-ab17-3337f68887ac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2591972763 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_same_csr_ou
tstanding.2591972763
Directory /workspace/18.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.3293102315
Short name T144
Test name
Test status
Simulation time 5060092851 ps
CPU time 184.02 seconds
Started Jul 22 05:24:42 PM PDT 24
Finished Jul 22 05:27:47 PM PDT 24
Peak memory 257792 kb
Host smart-5f542e99-ab58-4231-b270-2af8d0f83ad4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3293102315 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shadow_reg_err
ors.3293102315
Directory /workspace/18.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.2410693701
Short name T146
Test name
Test status
Simulation time 31169814305 ps
CPU time 1201.23 seconds
Started Jul 22 05:24:42 PM PDT 24
Finished Jul 22 05:44:44 PM PDT 24
Peak memory 273236 kb
Host smart-11a51b73-d59f-4ed1-baaf-6099b1101da4
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410693701 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 18.alert_handler_shadow_reg_errors_with_csr_rw.2410693701
Directory /workspace/18.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.4083918337
Short name T772
Test name
Test status
Simulation time 236549508 ps
CPU time 5.2 seconds
Started Jul 22 05:24:41 PM PDT 24
Finished Jul 22 05:24:46 PM PDT 24
Peak memory 248876 kb
Host smart-4dc5de89-1bb4-4c68-8c22-fff302432c18
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4083918337 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_errors.4083918337
Directory /workspace/18.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.2742401283
Short name T371
Test name
Test status
Simulation time 224913300 ps
CPU time 11.08 seconds
Started Jul 22 05:24:39 PM PDT 24
Finished Jul 22 05:24:50 PM PDT 24
Peak memory 253372 kb
Host smart-c8ab39fb-4199-4ac4-8d69-e8d6380f09ec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742401283 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 19.alert_handler_csr_mem_rw_with_rand_reset.2742401283
Directory /workspace/19.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.1285562488
Short name T209
Test name
Test status
Simulation time 127761872 ps
CPU time 5.86 seconds
Started Jul 22 05:25:25 PM PDT 24
Finished Jul 22 05:25:31 PM PDT 24
Peak memory 238032 kb
Host smart-94f8f842-4ed8-4554-8648-ba0f74daf504
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1285562488 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_csr_rw.1285562488
Directory /workspace/19.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.2753884271
Short name T765
Test name
Test status
Simulation time 12265320 ps
CPU time 1.46 seconds
Started Jul 22 05:24:40 PM PDT 24
Finished Jul 22 05:24:42 PM PDT 24
Peak memory 236244 kb
Host smart-ea4022f3-5700-437a-aed0-60cd94c54a0c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2753884271 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_intr_test.2753884271
Directory /workspace/19.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.1374819297
Short name T837
Test name
Test status
Simulation time 2239443397 ps
CPU time 40.99 seconds
Started Jul 22 05:24:38 PM PDT 24
Finished Jul 22 05:25:20 PM PDT 24
Peak memory 245376 kb
Host smart-6ede90b7-4b20-4f75-9490-4a2766cd226e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1374819297 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_same_csr_ou
tstanding.1374819297
Directory /workspace/19.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.2114568496
Short name T137
Test name
Test status
Simulation time 7733504131 ps
CPU time 558.33 seconds
Started Jul 22 05:24:38 PM PDT 24
Finished Jul 22 05:33:57 PM PDT 24
Peak memory 266100 kb
Host smart-03a3c158-6b18-448c-a3f9-d84996a0f2d7
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114568496 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 19.alert_handler_shadow_reg_errors_with_csr_rw.2114568496
Directory /workspace/19.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.4200301687
Short name T787
Test name
Test status
Simulation time 75612074 ps
CPU time 3.51 seconds
Started Jul 22 05:24:40 PM PDT 24
Finished Jul 22 05:24:44 PM PDT 24
Peak memory 249300 kb
Host smart-7f6067ad-28af-4007-a3f4-8dff5bb4cc58
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4200301687 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_errors.4200301687
Directory /workspace/19.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.3441164811
Short name T747
Test name
Test status
Simulation time 4225706687 ps
CPU time 126.7 seconds
Started Jul 22 05:23:39 PM PDT 24
Finished Jul 22 05:25:46 PM PDT 24
Peak memory 241092 kb
Host smart-e1b1be74-d3bd-41eb-9d31-7137b1562c12
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3441164811 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_aliasing.3441164811
Directory /workspace/2.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.4123966643
Short name T778
Test name
Test status
Simulation time 5107840824 ps
CPU time 201.28 seconds
Started Jul 22 05:23:40 PM PDT 24
Finished Jul 22 05:27:02 PM PDT 24
Peak memory 241092 kb
Host smart-57ff2e46-90be-4478-85af-aff31fb035dc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4123966643 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_bit_bash.4123966643
Directory /workspace/2.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.3268321157
Short name T744
Test name
Test status
Simulation time 604575240 ps
CPU time 8.81 seconds
Started Jul 22 05:23:38 PM PDT 24
Finished Jul 22 05:23:47 PM PDT 24
Peak memory 249132 kb
Host smart-3fac90e2-63e5-4b5d-8f11-b893077ba444
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3268321157 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_hw_reset.3268321157
Directory /workspace/2.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.1254278739
Short name T374
Test name
Test status
Simulation time 51797939 ps
CPU time 4.68 seconds
Started Jul 22 05:23:40 PM PDT 24
Finished Jul 22 05:23:46 PM PDT 24
Peak memory 240908 kb
Host smart-00a0cffe-1340-4055-b20c-61ecf27330bc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254278739 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 2.alert_handler_csr_mem_rw_with_rand_reset.1254278739
Directory /workspace/2.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.2946417745
Short name T817
Test name
Test status
Simulation time 20611920 ps
CPU time 3.34 seconds
Started Jul 22 05:23:40 PM PDT 24
Finished Jul 22 05:23:44 PM PDT 24
Peak memory 237980 kb
Host smart-65941f4c-e378-43fd-afc5-1aafa99dbc20
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2946417745 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_rw.2946417745
Directory /workspace/2.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.3651874701
Short name T726
Test name
Test status
Simulation time 10586822 ps
CPU time 1.3 seconds
Started Jul 22 05:23:40 PM PDT 24
Finished Jul 22 05:23:42 PM PDT 24
Peak memory 237172 kb
Host smart-ee90535e-4a3a-45ac-ae2b-51545e65bb2d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3651874701 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_intr_test.3651874701
Directory /workspace/2.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.3010948865
Short name T796
Test name
Test status
Simulation time 339095602 ps
CPU time 24.17 seconds
Started Jul 22 05:23:37 PM PDT 24
Finished Jul 22 05:24:01 PM PDT 24
Peak memory 246192 kb
Host smart-d705d217-61e8-4260-92fd-211191e72672
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3010948865 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_same_csr_out
standing.3010948865
Directory /workspace/2.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.1372803285
Short name T720
Test name
Test status
Simulation time 71823184 ps
CPU time 9.06 seconds
Started Jul 22 05:24:07 PM PDT 24
Finished Jul 22 05:24:16 PM PDT 24
Peak memory 254296 kb
Host smart-3f22be5e-9e7e-44a8-9f22-ee5f6dcaf086
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1372803285 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_errors.1372803285
Directory /workspace/2.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.2169671316
Short name T799
Test name
Test status
Simulation time 20654874 ps
CPU time 1.4 seconds
Started Jul 22 05:24:40 PM PDT 24
Finished Jul 22 05:24:42 PM PDT 24
Peak memory 237060 kb
Host smart-c128dbc7-5588-4ad1-b567-f72ff4aad792
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2169671316 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.alert_handler_intr_test.2169671316
Directory /workspace/20.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.3547515139
Short name T748
Test name
Test status
Simulation time 8000192 ps
CPU time 1.53 seconds
Started Jul 22 05:24:45 PM PDT 24
Finished Jul 22 05:24:47 PM PDT 24
Peak memory 238120 kb
Host smart-0b19e0a8-a116-41a0-9733-eb5c545a2f40
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3547515139 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.alert_handler_intr_test.3547515139
Directory /workspace/21.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.1167590173
Short name T367
Test name
Test status
Simulation time 6811424 ps
CPU time 1.33 seconds
Started Jul 22 05:25:10 PM PDT 24
Finished Jul 22 05:25:12 PM PDT 24
Peak memory 236156 kb
Host smart-0fa6b47d-0c29-4e3a-bca3-f18dbfccf177
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1167590173 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.alert_handler_intr_test.1167590173
Directory /workspace/22.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.2238823810
Short name T733
Test name
Test status
Simulation time 7621342 ps
CPU time 1.44 seconds
Started Jul 22 05:24:40 PM PDT 24
Finished Jul 22 05:24:42 PM PDT 24
Peak memory 238132 kb
Host smart-35190647-e029-4570-902e-9403c5cbfa50
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2238823810 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.alert_handler_intr_test.2238823810
Directory /workspace/23.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.2189385239
Short name T738
Test name
Test status
Simulation time 7401208 ps
CPU time 1.48 seconds
Started Jul 22 05:24:43 PM PDT 24
Finished Jul 22 05:24:45 PM PDT 24
Peak memory 238036 kb
Host smart-4070fb95-7964-4ef0-8200-0c13f92ad928
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2189385239 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.alert_handler_intr_test.2189385239
Directory /workspace/24.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.1398673732
Short name T727
Test name
Test status
Simulation time 11148577 ps
CPU time 1.28 seconds
Started Jul 22 05:24:42 PM PDT 24
Finished Jul 22 05:24:45 PM PDT 24
Peak memory 237092 kb
Host smart-3df155c7-ffee-4fd3-808c-6df1780cab82
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1398673732 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.alert_handler_intr_test.1398673732
Directory /workspace/25.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.154602700
Short name T781
Test name
Test status
Simulation time 12092240 ps
CPU time 1.6 seconds
Started Jul 22 05:24:42 PM PDT 24
Finished Jul 22 05:24:45 PM PDT 24
Peak memory 238072 kb
Host smart-e1948759-1523-4bb8-b9dc-959988b0522a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=154602700 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.alert_handler_intr_test.154602700
Directory /workspace/26.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.3632656841
Short name T755
Test name
Test status
Simulation time 29134994 ps
CPU time 1.45 seconds
Started Jul 22 05:24:41 PM PDT 24
Finished Jul 22 05:24:43 PM PDT 24
Peak memory 238084 kb
Host smart-901dd39b-c216-4650-90b2-860f69aacaec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3632656841 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.alert_handler_intr_test.3632656841
Directory /workspace/27.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.2618358280
Short name T365
Test name
Test status
Simulation time 9543550 ps
CPU time 1.53 seconds
Started Jul 22 05:24:43 PM PDT 24
Finished Jul 22 05:24:45 PM PDT 24
Peak memory 237208 kb
Host smart-4ef89d13-6e11-471a-9b43-5a71de3919a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2618358280 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.alert_handler_intr_test.2618358280
Directory /workspace/28.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.2137182619
Short name T756
Test name
Test status
Simulation time 12508475 ps
CPU time 1.57 seconds
Started Jul 22 05:24:48 PM PDT 24
Finished Jul 22 05:24:50 PM PDT 24
Peak memory 237192 kb
Host smart-bd534aae-41b0-4a43-a15b-035e231f046d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2137182619 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.alert_handler_intr_test.2137182619
Directory /workspace/29.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.3025177791
Short name T824
Test name
Test status
Simulation time 20230428443 ps
CPU time 312.71 seconds
Started Jul 22 05:23:49 PM PDT 24
Finished Jul 22 05:29:03 PM PDT 24
Peak memory 240668 kb
Host smart-c5d7a9cb-5b39-4937-9069-75cc154e4ad4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3025177791 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_aliasing.3025177791
Directory /workspace/3.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.3524575030
Short name T820
Test name
Test status
Simulation time 28474682110 ps
CPU time 438.77 seconds
Started Jul 22 05:24:00 PM PDT 24
Finished Jul 22 05:31:20 PM PDT 24
Peak memory 238168 kb
Host smart-96f10b62-aa41-499c-8669-aaf132459a79
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3524575030 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_bit_bash.3524575030
Directory /workspace/3.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.3115419720
Short name T830
Test name
Test status
Simulation time 45622086 ps
CPU time 6.17 seconds
Started Jul 22 05:23:49 PM PDT 24
Finished Jul 22 05:23:56 PM PDT 24
Peak memory 249520 kb
Host smart-5a2f6c80-4385-4025-8dd9-a10d802b787b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3115419720 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_hw_reset.3115419720
Directory /workspace/3.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.1184249717
Short name T784
Test name
Test status
Simulation time 284997983 ps
CPU time 7.73 seconds
Started Jul 22 05:24:17 PM PDT 24
Finished Jul 22 05:24:26 PM PDT 24
Peak memory 241292 kb
Host smart-8f188dc4-357a-4940-9cb1-be663ac3e967
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184249717 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 3.alert_handler_csr_mem_rw_with_rand_reset.1184249717
Directory /workspace/3.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.3855722796
Short name T790
Test name
Test status
Simulation time 101725255 ps
CPU time 9.56 seconds
Started Jul 22 05:24:18 PM PDT 24
Finished Jul 22 05:24:28 PM PDT 24
Peak memory 238008 kb
Host smart-9c5ab590-2b44-46b1-aeb3-f25fe030d969
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3855722796 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_rw.3855722796
Directory /workspace/3.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.1845818197
Short name T757
Test name
Test status
Simulation time 11268891 ps
CPU time 1.31 seconds
Started Jul 22 05:24:13 PM PDT 24
Finished Jul 22 05:24:15 PM PDT 24
Peak memory 237176 kb
Host smart-cb544faf-fd31-4254-8c87-99e7d14b2375
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1845818197 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_intr_test.1845818197
Directory /workspace/3.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.352620127
Short name T801
Test name
Test status
Simulation time 957735685 ps
CPU time 22.03 seconds
Started Jul 22 05:23:44 PM PDT 24
Finished Jul 22 05:24:07 PM PDT 24
Peak memory 240924 kb
Host smart-fdd97c34-0f8c-427f-9043-755fa9edcbbe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=352620127 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_same_csr_outs
tanding.352620127
Directory /workspace/3.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.2668094106
Short name T140
Test name
Test status
Simulation time 2544116395 ps
CPU time 179.24 seconds
Started Jul 22 05:23:43 PM PDT 24
Finished Jul 22 05:26:42 PM PDT 24
Peak memory 266044 kb
Host smart-4634c410-9729-47d8-b922-d2aafcf11db6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2668094106 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shadow_reg_erro
rs.2668094106
Directory /workspace/3.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.287860341
Short name T151
Test name
Test status
Simulation time 23620536157 ps
CPU time 512.96 seconds
Started Jul 22 05:23:38 PM PDT 24
Finished Jul 22 05:32:11 PM PDT 24
Peak memory 265900 kb
Host smart-daf4b4ac-382c-4e55-8857-26e815e127f5
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287860341 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.alert_handler_shadow_reg_errors_with_csr_rw.287860341
Directory /workspace/3.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.3678281478
Short name T807
Test name
Test status
Simulation time 313095757 ps
CPU time 10.12 seconds
Started Jul 22 05:23:48 PM PDT 24
Finished Jul 22 05:23:59 PM PDT 24
Peak memory 247884 kb
Host smart-87eff4a4-9227-4140-ba30-0ae74d531504
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3678281478 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_errors.3678281478
Directory /workspace/3.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.336188613
Short name T834
Test name
Test status
Simulation time 12847875 ps
CPU time 1.33 seconds
Started Jul 22 05:24:49 PM PDT 24
Finished Jul 22 05:24:51 PM PDT 24
Peak memory 238112 kb
Host smart-6de71b03-303d-4dca-9c7b-f4474834f5fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=336188613 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.alert_handler_intr_test.336188613
Directory /workspace/30.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.3913778979
Short name T745
Test name
Test status
Simulation time 7347502 ps
CPU time 1.47 seconds
Started Jul 22 05:24:48 PM PDT 24
Finished Jul 22 05:24:50 PM PDT 24
Peak memory 238132 kb
Host smart-7a463447-d9fb-44b1-82d3-9c772b63f1d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3913778979 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.alert_handler_intr_test.3913778979
Directory /workspace/31.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.1902526617
Short name T791
Test name
Test status
Simulation time 95231417 ps
CPU time 1.48 seconds
Started Jul 22 05:24:50 PM PDT 24
Finished Jul 22 05:24:52 PM PDT 24
Peak memory 237852 kb
Host smart-c0220bd5-7f5a-4fb7-a72c-b2b668452170
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1902526617 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.alert_handler_intr_test.1902526617
Directory /workspace/32.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.alert_handler_intr_test.4075851332
Short name T785
Test name
Test status
Simulation time 10539022 ps
CPU time 1.37 seconds
Started Jul 22 05:24:50 PM PDT 24
Finished Jul 22 05:24:52 PM PDT 24
Peak memory 237168 kb
Host smart-bfe4a62d-f898-456d-b9b6-2340aecd5847
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4075851332 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.alert_handler_intr_test.4075851332
Directory /workspace/33.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.1606365007
Short name T774
Test name
Test status
Simulation time 24931136 ps
CPU time 1.54 seconds
Started Jul 22 05:24:50 PM PDT 24
Finished Jul 22 05:24:52 PM PDT 24
Peak memory 237988 kb
Host smart-826a238a-d258-4a12-8d83-aa9c514865e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1606365007 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.alert_handler_intr_test.1606365007
Directory /workspace/34.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.3657108716
Short name T776
Test name
Test status
Simulation time 9885870 ps
CPU time 1.29 seconds
Started Jul 22 05:24:48 PM PDT 24
Finished Jul 22 05:24:49 PM PDT 24
Peak memory 236104 kb
Host smart-07e1adc1-0f72-4cdc-8ecf-796bce7291ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3657108716 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.alert_handler_intr_test.3657108716
Directory /workspace/35.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.217174343
Short name T836
Test name
Test status
Simulation time 18468712 ps
CPU time 1.43 seconds
Started Jul 22 05:24:51 PM PDT 24
Finished Jul 22 05:24:52 PM PDT 24
Peak memory 238012 kb
Host smart-f47801a6-e8da-4bfe-9780-48ca82785c46
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=217174343 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.alert_handler_intr_test.217174343
Directory /workspace/37.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.1363712453
Short name T741
Test name
Test status
Simulation time 11127076 ps
CPU time 1.36 seconds
Started Jul 22 05:24:50 PM PDT 24
Finished Jul 22 05:24:52 PM PDT 24
Peak memory 238112 kb
Host smart-f2b1ce8d-fceb-4c7b-ae48-0f6b71bd0896
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1363712453 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.alert_handler_intr_test.1363712453
Directory /workspace/38.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.871304182
Short name T822
Test name
Test status
Simulation time 17525636 ps
CPU time 1.36 seconds
Started Jul 22 05:24:49 PM PDT 24
Finished Jul 22 05:24:51 PM PDT 24
Peak memory 238124 kb
Host smart-59db32e2-eef6-4a52-b01a-28d51c87fd96
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=871304182 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.alert_handler_intr_test.871304182
Directory /workspace/39.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.1090547756
Short name T789
Test name
Test status
Simulation time 15576691183 ps
CPU time 266.65 seconds
Started Jul 22 05:23:56 PM PDT 24
Finished Jul 22 05:28:23 PM PDT 24
Peak memory 241020 kb
Host smart-dab20398-e40e-45d8-aaf7-2e7df644d78f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1090547756 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_aliasing.1090547756
Directory /workspace/4.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.1715173197
Short name T779
Test name
Test status
Simulation time 8555086073 ps
CPU time 510.08 seconds
Started Jul 22 05:23:53 PM PDT 24
Finished Jul 22 05:32:24 PM PDT 24
Peak memory 238108 kb
Host smart-aa32da57-55ac-44b4-82e3-4cc010b5e90d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1715173197 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_bit_bash.1715173197
Directory /workspace/4.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.865369651
Short name T211
Test name
Test status
Simulation time 458850702 ps
CPU time 9.07 seconds
Started Jul 22 05:23:55 PM PDT 24
Finished Jul 22 05:24:04 PM PDT 24
Peak memory 241044 kb
Host smart-d66fd625-e782-455d-86da-2016b2ec6bd9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=865369651 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_hw_reset.865369651
Directory /workspace/4.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.2110660017
Short name T752
Test name
Test status
Simulation time 104961187 ps
CPU time 8.15 seconds
Started Jul 22 05:23:54 PM PDT 24
Finished Jul 22 05:24:02 PM PDT 24
Peak memory 253000 kb
Host smart-4e3b3c0f-2acd-464c-a81b-50940349398c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110660017 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 4.alert_handler_csr_mem_rw_with_rand_reset.2110660017
Directory /workspace/4.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.2547228945
Short name T761
Test name
Test status
Simulation time 179273270 ps
CPU time 8.35 seconds
Started Jul 22 05:23:51 PM PDT 24
Finished Jul 22 05:24:00 PM PDT 24
Peak memory 238036 kb
Host smart-0c1cb562-dadc-4fc9-a283-fd2e2ab7b42e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2547228945 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_rw.2547228945
Directory /workspace/4.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.1784119480
Short name T760
Test name
Test status
Simulation time 11581302 ps
CPU time 1.5 seconds
Started Jul 22 05:24:00 PM PDT 24
Finished Jul 22 05:24:02 PM PDT 24
Peak memory 236156 kb
Host smart-90568202-b53c-4fa3-861f-ce1c30ab0b91
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1784119480 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_intr_test.1784119480
Directory /workspace/4.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.4198374353
Short name T783
Test name
Test status
Simulation time 178741661 ps
CPU time 23.25 seconds
Started Jul 22 05:23:53 PM PDT 24
Finished Jul 22 05:24:16 PM PDT 24
Peak memory 246208 kb
Host smart-ab5809d2-a54b-441d-88b4-af97ae53376b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4198374353 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_same_csr_out
standing.4198374353
Directory /workspace/4.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.3945334230
Short name T152
Test name
Test status
Simulation time 10459203097 ps
CPU time 144.32 seconds
Started Jul 22 05:23:44 PM PDT 24
Finished Jul 22 05:26:09 PM PDT 24
Peak memory 265964 kb
Host smart-35b2939b-f56a-49b4-b434-a250fe0094ff
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3945334230 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shadow_reg_erro
rs.3945334230
Directory /workspace/4.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.2835210696
Short name T792
Test name
Test status
Simulation time 2874618406 ps
CPU time 14.98 seconds
Started Jul 22 05:23:48 PM PDT 24
Finished Jul 22 05:24:03 PM PDT 24
Peak memory 248912 kb
Host smart-8ee49ef3-bfc2-4ac9-9566-94967597e051
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2835210696 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_errors.2835210696
Directory /workspace/4.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.3320523903
Short name T723
Test name
Test status
Simulation time 14956694 ps
CPU time 1.58 seconds
Started Jul 22 05:24:48 PM PDT 24
Finished Jul 22 05:24:50 PM PDT 24
Peak memory 238072 kb
Host smart-651fd4fa-bbdd-411b-a1e5-185fa76877e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3320523903 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.alert_handler_intr_test.3320523903
Directory /workspace/40.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.3276204799
Short name T782
Test name
Test status
Simulation time 50650430 ps
CPU time 1.37 seconds
Started Jul 22 05:24:49 PM PDT 24
Finished Jul 22 05:24:51 PM PDT 24
Peak memory 236924 kb
Host smart-7f3381d9-e4e2-4d92-a5f2-3b188f1f7b23
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3276204799 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.alert_handler_intr_test.3276204799
Directory /workspace/41.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.1985012593
Short name T829
Test name
Test status
Simulation time 15148050 ps
CPU time 1.36 seconds
Started Jul 22 05:24:48 PM PDT 24
Finished Jul 22 05:24:50 PM PDT 24
Peak memory 237108 kb
Host smart-c1aee9a8-1d55-42ef-9b97-8228093922e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1985012593 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.alert_handler_intr_test.1985012593
Directory /workspace/42.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.2682894666
Short name T736
Test name
Test status
Simulation time 8378126 ps
CPU time 1.62 seconds
Started Jul 22 05:24:48 PM PDT 24
Finished Jul 22 05:24:51 PM PDT 24
Peak memory 237168 kb
Host smart-b6139ad4-bb7d-4222-9b05-78a55072c7e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2682894666 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.alert_handler_intr_test.2682894666
Directory /workspace/43.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.3315459840
Short name T740
Test name
Test status
Simulation time 6452714 ps
CPU time 1.46 seconds
Started Jul 22 05:24:49 PM PDT 24
Finished Jul 22 05:24:51 PM PDT 24
Peak memory 238008 kb
Host smart-9eea366b-5fa0-4fcb-891b-23e5d69d478e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3315459840 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.alert_handler_intr_test.3315459840
Directory /workspace/44.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.721711922
Short name T811
Test name
Test status
Simulation time 13652751 ps
CPU time 1.47 seconds
Started Jul 22 05:24:58 PM PDT 24
Finished Jul 22 05:25:00 PM PDT 24
Peak memory 237164 kb
Host smart-07167786-d4a9-41c8-882c-92260d0495e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=721711922 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.alert_handler_intr_test.721711922
Directory /workspace/45.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.545541944
Short name T729
Test name
Test status
Simulation time 24530537 ps
CPU time 1.53 seconds
Started Jul 22 05:24:47 PM PDT 24
Finished Jul 22 05:24:49 PM PDT 24
Peak memory 238080 kb
Host smart-87699572-0677-4ffa-bc46-a4137f0f0aae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=545541944 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.alert_handler_intr_test.545541944
Directory /workspace/46.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.3095443635
Short name T762
Test name
Test status
Simulation time 18263478 ps
CPU time 1.46 seconds
Started Jul 22 05:24:47 PM PDT 24
Finished Jul 22 05:24:49 PM PDT 24
Peak memory 237156 kb
Host smart-a39af103-6524-42ae-b38e-d6e3d0e17770
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3095443635 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.alert_handler_intr_test.3095443635
Directory /workspace/47.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.3148324600
Short name T175
Test name
Test status
Simulation time 15280964 ps
CPU time 1.38 seconds
Started Jul 22 05:24:49 PM PDT 24
Finished Jul 22 05:24:51 PM PDT 24
Peak memory 238132 kb
Host smart-bd442e54-d87b-4599-aef2-8af776384aaa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3148324600 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.alert_handler_intr_test.3148324600
Directory /workspace/48.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.2153713867
Short name T825
Test name
Test status
Simulation time 6829804 ps
CPU time 1.54 seconds
Started Jul 22 05:24:51 PM PDT 24
Finished Jul 22 05:24:53 PM PDT 24
Peak memory 237060 kb
Host smart-bd6478c1-9ccd-4a2b-86f5-3ac39af2dcf9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2153713867 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.alert_handler_intr_test.2153713867
Directory /workspace/49.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.325151446
Short name T770
Test name
Test status
Simulation time 116769667 ps
CPU time 9.67 seconds
Started Jul 22 05:23:56 PM PDT 24
Finished Jul 22 05:24:07 PM PDT 24
Peak memory 249308 kb
Host smart-c3ef3374-9171-42de-ac33-62e284167482
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325151446 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 5.alert_handler_csr_mem_rw_with_rand_reset.325151446
Directory /workspace/5.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.388219664
Short name T210
Test name
Test status
Simulation time 365567696 ps
CPU time 8.3 seconds
Started Jul 22 05:23:54 PM PDT 24
Finished Jul 22 05:24:02 PM PDT 24
Peak memory 237932 kb
Host smart-d5840ffb-b0b5-4d4f-9312-b6f55b41314e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=388219664 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_csr_rw.388219664
Directory /workspace/5.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.2787473327
Short name T815
Test name
Test status
Simulation time 6695096 ps
CPU time 1.62 seconds
Started Jul 22 05:23:53 PM PDT 24
Finished Jul 22 05:23:55 PM PDT 24
Peak memory 238132 kb
Host smart-c1ab0fe1-7b7c-46a8-8292-e847540d0734
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2787473327 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_intr_test.2787473327
Directory /workspace/5.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.2766659077
Short name T795
Test name
Test status
Simulation time 1794972523 ps
CPU time 40.62 seconds
Started Jul 22 05:23:53 PM PDT 24
Finished Jul 22 05:24:34 PM PDT 24
Peak memory 245376 kb
Host smart-695ba58c-852e-4987-ac72-326ff8154153
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2766659077 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_same_csr_out
standing.2766659077
Directory /workspace/5.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.2726957151
Short name T171
Test name
Test status
Simulation time 30806987819 ps
CPU time 174.89 seconds
Started Jul 22 05:24:18 PM PDT 24
Finished Jul 22 05:27:14 PM PDT 24
Peak memory 266016 kb
Host smart-9d3207c2-981d-4c40-a126-d2704264928c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2726957151 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shadow_reg_erro
rs.2726957151
Directory /workspace/5.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.2120175895
Short name T826
Test name
Test status
Simulation time 73185626 ps
CPU time 9.29 seconds
Started Jul 22 05:23:53 PM PDT 24
Finished Jul 22 05:24:03 PM PDT 24
Peak memory 256028 kb
Host smart-7ce11452-8170-4d7a-a22c-ad6870b94471
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2120175895 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_errors.2120175895
Directory /workspace/5.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.392593223
Short name T754
Test name
Test status
Simulation time 141816603 ps
CPU time 11.53 seconds
Started Jul 22 05:24:04 PM PDT 24
Finished Jul 22 05:24:17 PM PDT 24
Peak memory 257320 kb
Host smart-c7770649-bb36-4fb8-9753-cd7c4f45e934
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392593223 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 6.alert_handler_csr_mem_rw_with_rand_reset.392593223
Directory /workspace/6.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.161241403
Short name T821
Test name
Test status
Simulation time 136141490 ps
CPU time 5.84 seconds
Started Jul 22 05:24:03 PM PDT 24
Finished Jul 22 05:24:10 PM PDT 24
Peak memory 237996 kb
Host smart-ef34d349-1c78-4f1e-a861-48e7d7e5daa3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=161241403 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_csr_rw.161241403
Directory /workspace/6.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.2475657236
Short name T732
Test name
Test status
Simulation time 20679284 ps
CPU time 1.42 seconds
Started Jul 22 05:24:02 PM PDT 24
Finished Jul 22 05:24:03 PM PDT 24
Peak memory 237084 kb
Host smart-08a2b14a-129d-4c04-8b81-9edf5d7ad493
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2475657236 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_intr_test.2475657236
Directory /workspace/6.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.388633489
Short name T188
Test name
Test status
Simulation time 382639753 ps
CPU time 25.21 seconds
Started Jul 22 05:24:03 PM PDT 24
Finished Jul 22 05:24:28 PM PDT 24
Peak memory 246208 kb
Host smart-e9f2259d-d021-4d77-9991-087eb9f31170
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=388633489 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_same_csr_outs
tanding.388633489
Directory /workspace/6.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.217135824
Short name T160
Test name
Test status
Simulation time 3556239803 ps
CPU time 106.11 seconds
Started Jul 22 05:23:53 PM PDT 24
Finished Jul 22 05:25:39 PM PDT 24
Peak memory 266092 kb
Host smart-ae4ad91a-a659-4bed-b35c-08d1c975e03e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=217135824 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shadow_reg_error
s.217135824
Directory /workspace/6.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.4151159494
Short name T153
Test name
Test status
Simulation time 9572370853 ps
CPU time 651.76 seconds
Started Jul 22 05:23:53 PM PDT 24
Finished Jul 22 05:34:45 PM PDT 24
Peak memory 265976 kb
Host smart-7354334c-c6bc-42c5-a693-de40ed519c46
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151159494 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.alert_handler_shadow_reg_errors_with_csr_rw.4151159494
Directory /workspace/6.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.82615733
Short name T798
Test name
Test status
Simulation time 116829665 ps
CPU time 9.91 seconds
Started Jul 22 05:24:02 PM PDT 24
Finished Jul 22 05:24:12 PM PDT 24
Peak memory 249412 kb
Host smart-40a6fd40-1290-435e-bb94-77f12da9b298
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=82615733 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_errors.82615733
Directory /workspace/6.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.2572122116
Short name T827
Test name
Test status
Simulation time 601820042 ps
CPU time 11.73 seconds
Started Jul 22 05:24:04 PM PDT 24
Finished Jul 22 05:24:17 PM PDT 24
Peak memory 255944 kb
Host smart-d7516048-2f04-47f8-88bd-cf66363d848a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572122116 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 7.alert_handler_csr_mem_rw_with_rand_reset.2572122116
Directory /workspace/7.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.403970051
Short name T735
Test name
Test status
Simulation time 185975426 ps
CPU time 9.91 seconds
Started Jul 22 05:24:03 PM PDT 24
Finished Jul 22 05:24:13 PM PDT 24
Peak memory 241000 kb
Host smart-0ece314d-af99-4466-a2af-1446915f4bed
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=403970051 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_csr_rw.403970051
Directory /workspace/7.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.4039363382
Short name T369
Test name
Test status
Simulation time 14402905 ps
CPU time 1.39 seconds
Started Jul 22 05:24:03 PM PDT 24
Finished Jul 22 05:24:05 PM PDT 24
Peak memory 238132 kb
Host smart-b4f5efa5-5bf3-481e-9c0f-05389e9b8b9d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4039363382 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_intr_test.4039363382
Directory /workspace/7.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.4173121271
Short name T739
Test name
Test status
Simulation time 346482364 ps
CPU time 21.04 seconds
Started Jul 22 05:24:31 PM PDT 24
Finished Jul 22 05:24:53 PM PDT 24
Peak memory 246272 kb
Host smart-87cc3593-5b3c-43de-8092-747323a33572
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4173121271 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_same_csr_out
standing.4173121271
Directory /workspace/7.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.3780895771
Short name T780
Test name
Test status
Simulation time 522859028 ps
CPU time 6.32 seconds
Started Jul 22 05:24:11 PM PDT 24
Finished Jul 22 05:24:18 PM PDT 24
Peak memory 249224 kb
Host smart-17c9e572-617a-41b7-9d31-e02f710c5809
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3780895771 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_errors.3780895771
Directory /workspace/7.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.1814298087
Short name T375
Test name
Test status
Simulation time 71232115 ps
CPU time 5.86 seconds
Started Jul 22 05:24:38 PM PDT 24
Finished Jul 22 05:24:45 PM PDT 24
Peak memory 254476 kb
Host smart-7af02b7e-f6a4-4186-9c36-b1f52405703a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814298087 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 8.alert_handler_csr_mem_rw_with_rand_reset.1814298087
Directory /workspace/8.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.875663742
Short name T788
Test name
Test status
Simulation time 162130084 ps
CPU time 9.1 seconds
Started Jul 22 05:24:11 PM PDT 24
Finished Jul 22 05:24:21 PM PDT 24
Peak memory 238024 kb
Host smart-69d40e06-bbe1-4c31-8e61-3f25b59a7b2d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=875663742 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_csr_rw.875663742
Directory /workspace/8.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.2606519614
Short name T364
Test name
Test status
Simulation time 7861499 ps
CPU time 1.47 seconds
Started Jul 22 05:24:16 PM PDT 24
Finished Jul 22 05:24:18 PM PDT 24
Peak memory 237180 kb
Host smart-75393488-b58c-49cc-8613-01f6d60e3114
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2606519614 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_intr_test.2606519614
Directory /workspace/8.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.2373420518
Short name T742
Test name
Test status
Simulation time 320554872 ps
CPU time 22.28 seconds
Started Jul 22 05:26:01 PM PDT 24
Finished Jul 22 05:26:23 PM PDT 24
Peak memory 240976 kb
Host smart-40673004-1fd9-47c3-82de-76b4b7d47c97
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2373420518 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_same_csr_out
standing.2373420518
Directory /workspace/8.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.2022997811
Short name T164
Test name
Test status
Simulation time 14836442236 ps
CPU time 1070.07 seconds
Started Jul 22 05:24:03 PM PDT 24
Finished Jul 22 05:41:54 PM PDT 24
Peak memory 266076 kb
Host smart-31d93c02-cc91-44d5-a97e-6edbf5a77be3
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022997811 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.alert_handler_shadow_reg_errors_with_csr_rw.2022997811
Directory /workspace/8.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.4173682446
Short name T793
Test name
Test status
Simulation time 244383861 ps
CPU time 8.27 seconds
Started Jul 22 05:26:01 PM PDT 24
Finished Jul 22 05:26:10 PM PDT 24
Peak memory 249232 kb
Host smart-ca72a399-8371-428b-a437-0a170eaaa1e8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4173682446 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_errors.4173682446
Directory /workspace/8.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.3767331759
Short name T370
Test name
Test status
Simulation time 254274743 ps
CPU time 6.42 seconds
Started Jul 22 05:24:13 PM PDT 24
Finished Jul 22 05:24:20 PM PDT 24
Peak memory 240248 kb
Host smart-ce798971-85b5-4d07-90ed-dca865e72873
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767331759 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 9.alert_handler_csr_mem_rw_with_rand_reset.3767331759
Directory /workspace/9.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.884519617
Short name T749
Test name
Test status
Simulation time 49098413 ps
CPU time 4.85 seconds
Started Jul 22 05:26:07 PM PDT 24
Finished Jul 22 05:26:12 PM PDT 24
Peak memory 238056 kb
Host smart-db35d662-2a79-4e0b-b125-ebf725c219a4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=884519617 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_csr_rw.884519617
Directory /workspace/9.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.3328520947
Short name T818
Test name
Test status
Simulation time 11834309 ps
CPU time 1.29 seconds
Started Jul 22 05:24:53 PM PDT 24
Finished Jul 22 05:24:54 PM PDT 24
Peak memory 237968 kb
Host smart-bfaff48e-546e-48ca-a996-0dc86ad2b005
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3328520947 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_intr_test.3328520947
Directory /workspace/9.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.2302731580
Short name T833
Test name
Test status
Simulation time 1644630333 ps
CPU time 12.1 seconds
Started Jul 22 05:26:07 PM PDT 24
Finished Jul 22 05:26:19 PM PDT 24
Peak memory 249208 kb
Host smart-815c4442-b040-4bed-b91d-44acddf872f4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2302731580 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_same_csr_out
standing.2302731580
Directory /workspace/9.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.437783031
Short name T142
Test name
Test status
Simulation time 13029492258 ps
CPU time 1052.59 seconds
Started Jul 22 05:24:11 PM PDT 24
Finished Jul 22 05:41:44 PM PDT 24
Peak memory 267040 kb
Host smart-5099a138-3098-4486-a974-6e2193c78c5a
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437783031 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.alert_handler_shadow_reg_errors_with_csr_rw.437783031
Directory /workspace/9.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.671896586
Short name T721
Test name
Test status
Simulation time 456656346 ps
CPU time 16.36 seconds
Started Jul 22 05:24:12 PM PDT 24
Finished Jul 22 05:24:28 PM PDT 24
Peak memory 249064 kb
Host smart-8d662944-7804-4157-9e0a-4cfba36ebefd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=671896586 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_errors.671896586
Directory /workspace/9.alert_handler_tl_errors/latest

Test location /workspace/coverage/default/0.alert_handler_entropy.2477461379
Short name T519
Test name
Test status
Simulation time 72513388604 ps
CPU time 2163.04 seconds
Started Jul 22 07:16:27 PM PDT 24
Finished Jul 22 07:53:34 PM PDT 24
Peak memory 282384 kb
Host smart-98680f89-50a4-441d-ba59-d2c5817caf8e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477461379 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy.2477461379
Directory /workspace/0.alert_handler_entropy/latest

Test location /workspace/coverage/default/0.alert_handler_entropy_stress.2649157087
Short name T477
Test name
Test status
Simulation time 169714073 ps
CPU time 8.74 seconds
Started Jul 22 07:16:26 PM PDT 24
Finished Jul 22 07:17:39 PM PDT 24
Peak memory 248688 kb
Host smart-b7ba8a00-d8e6-4ba6-8e51-8b72dee673d8
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2649157087 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy_stress.2649157087
Directory /workspace/0.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/0.alert_handler_esc_alert_accum.284620653
Short name T236
Test name
Test status
Simulation time 874332519 ps
CPU time 15.04 seconds
Started Jul 22 07:16:27 PM PDT 24
Finished Jul 22 07:17:47 PM PDT 24
Peak memory 248064 kb
Host smart-1fa2f71b-d55e-4e35-96e8-ec5e12c08b89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28462
0653 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_alert_accum.284620653
Directory /workspace/0.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/0.alert_handler_esc_intr_timeout.2204610123
Short name T681
Test name
Test status
Simulation time 189309522 ps
CPU time 12.47 seconds
Started Jul 22 07:16:26 PM PDT 24
Finished Jul 22 07:17:42 PM PDT 24
Peak memory 248544 kb
Host smart-86af57d6-ac06-4d34-ac35-25e7ea45ebf1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22046
10123 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_intr_timeout.2204610123
Directory /workspace/0.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_lpg.1361421535
Short name T353
Test name
Test status
Simulation time 25442321212 ps
CPU time 1110.9 seconds
Started Jul 22 07:16:26 PM PDT 24
Finished Jul 22 07:36:01 PM PDT 24
Peak memory 289628 kb
Host smart-29561aea-6344-4ad6-bfee-b6fdfe870239
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1361421535 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg.1361421535
Directory /workspace/0.alert_handler_lpg/latest

Test location /workspace/coverage/default/0.alert_handler_lpg_stub_clk.3097162942
Short name T15
Test name
Test status
Simulation time 17403740825 ps
CPU time 798.14 seconds
Started Jul 22 07:16:26 PM PDT 24
Finished Jul 22 07:30:48 PM PDT 24
Peak memory 272580 kb
Host smart-55564b2f-6f36-4cff-85ac-5c9060865c39
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3097162942 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg_stub_clk.3097162942
Directory /workspace/0.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/0.alert_handler_ping_timeout.1969177660
Short name T323
Test name
Test status
Simulation time 6721602314 ps
CPU time 262.42 seconds
Started Jul 22 07:16:27 PM PDT 24
Finished Jul 22 07:21:54 PM PDT 24
Peak memory 248512 kb
Host smart-ada57c30-2640-4993-b041-a69dfb945c9d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1969177660 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_ping_timeout.1969177660
Directory /workspace/0.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_random_alerts.1710108536
Short name T238
Test name
Test status
Simulation time 512843651 ps
CPU time 24.5 seconds
Started Jul 22 07:16:30 PM PDT 24
Finished Jul 22 07:17:59 PM PDT 24
Peak memory 248556 kb
Host smart-c11a44f5-9c12-459a-80ca-bb9af52c2e01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17101
08536 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_alerts.1710108536
Directory /workspace/0.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/0.alert_handler_sig_int_fail.1448454750
Short name T267
Test name
Test status
Simulation time 785905062 ps
CPU time 20.79 seconds
Started Jul 22 07:16:29 PM PDT 24
Finished Jul 22 07:17:55 PM PDT 24
Peak memory 249028 kb
Host smart-cd2f30be-c27a-4ba2-aabe-77a979765ab9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14484
54750 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sig_int_fail.1448454750
Directory /workspace/0.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/0.alert_handler_smoke.1966949503
Short name T22
Test name
Test status
Simulation time 1852057835 ps
CPU time 19.51 seconds
Started Jul 22 07:18:25 PM PDT 24
Finished Jul 22 07:19:35 PM PDT 24
Peak memory 248992 kb
Host smart-ab94b3ad-5aba-4822-a7b0-c0bb05fe49fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19669
49503 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_smoke.1966949503
Directory /workspace/0.alert_handler_smoke/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all.1005041396
Short name T619
Test name
Test status
Simulation time 68519942038 ps
CPU time 1898.8 seconds
Started Jul 22 07:16:28 PM PDT 24
Finished Jul 22 07:49:13 PM PDT 24
Peak memory 273272 kb
Host smart-6a833adc-10e1-403c-b3dd-bc4ba8881b52
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005041396 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_han
dler_stress_all.1005041396
Directory /workspace/0.alert_handler_stress_all/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all_with_rand_reset.91674150
Short name T593
Test name
Test status
Simulation time 206393396377 ps
CPU time 2692.7 seconds
Started Jul 22 07:16:26 PM PDT 24
Finished Jul 22 08:02:23 PM PDT 24
Peak memory 298184 kb
Host smart-0bdac38f-270c-4863-86a7-6d640a82e078
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91674150 -assert nopostproc +UVM_TESTNAME=alert_
handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 0.alert_handler_stress_all_with_rand_reset.91674150
Directory /workspace/0.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.alert_handler_entropy.3347098658
Short name T510
Test name
Test status
Simulation time 38505797586 ps
CPU time 639.78 seconds
Started Jul 22 07:16:38 PM PDT 24
Finished Jul 22 07:28:22 PM PDT 24
Peak memory 268064 kb
Host smart-fb943aca-0736-40ca-9149-544fe2f37189
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347098658 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy.3347098658
Directory /workspace/1.alert_handler_entropy/latest

Test location /workspace/coverage/default/1.alert_handler_entropy_stress.3243805771
Short name T677
Test name
Test status
Simulation time 352820315 ps
CPU time 6.91 seconds
Started Jul 22 07:16:55 PM PDT 24
Finished Jul 22 07:18:06 PM PDT 24
Peak memory 248592 kb
Host smart-fcacc89d-020b-4cef-ab1b-fe3b5501086f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3243805771 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy_stress.3243805771
Directory /workspace/1.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/1.alert_handler_esc_alert_accum.161192663
Short name T393
Test name
Test status
Simulation time 2453180066 ps
CPU time 81.25 seconds
Started Jul 22 07:16:54 PM PDT 24
Finished Jul 22 07:19:20 PM PDT 24
Peak memory 256528 kb
Host smart-73d399cf-7c9e-4dac-b749-93715533a5b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16119
2663 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_alert_accum.161192663
Directory /workspace/1.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/1.alert_handler_esc_intr_timeout.1277179905
Short name T423
Test name
Test status
Simulation time 54712983 ps
CPU time 4.61 seconds
Started Jul 22 07:16:54 PM PDT 24
Finished Jul 22 07:18:03 PM PDT 24
Peak memory 239820 kb
Host smart-fe6545c3-5a0d-45d5-bf0f-8fcc50fef855
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12771
79905 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_intr_timeout.1277179905
Directory /workspace/1.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_lpg.3922193674
Short name T336
Test name
Test status
Simulation time 21046466112 ps
CPU time 1392.64 seconds
Started Jul 22 07:16:38 PM PDT 24
Finished Jul 22 07:40:55 PM PDT 24
Peak memory 273180 kb
Host smart-a0684cf0-4d01-438b-a60c-d21785fca338
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3922193674 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg.3922193674
Directory /workspace/1.alert_handler_lpg/latest

Test location /workspace/coverage/default/1.alert_handler_lpg_stub_clk.3332683958
Short name T588
Test name
Test status
Simulation time 33067594986 ps
CPU time 2024.87 seconds
Started Jul 22 07:18:25 PM PDT 24
Finished Jul 22 07:53:00 PM PDT 24
Peak memory 281332 kb
Host smart-ff09bab2-0969-4397-b180-b2ccb01a5236
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332683958 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg_stub_clk.3332683958
Directory /workspace/1.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/1.alert_handler_ping_timeout.3459764762
Short name T321
Test name
Test status
Simulation time 40291354565 ps
CPU time 407.27 seconds
Started Jul 22 07:18:04 PM PDT 24
Finished Jul 22 07:25:43 PM PDT 24
Peak memory 255364 kb
Host smart-c5833ec8-5d26-4fc9-a57b-2ae7acf4bef9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459764762 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_ping_timeout.3459764762
Directory /workspace/1.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_random_alerts.2532384379
Short name T550
Test name
Test status
Simulation time 805821945 ps
CPU time 33.79 seconds
Started Jul 22 07:16:54 PM PDT 24
Finished Jul 22 07:18:32 PM PDT 24
Peak memory 248588 kb
Host smart-9e27e29f-83d8-4a9f-8ad1-a4aecbb6076e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25323
84379 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_alerts.2532384379
Directory /workspace/1.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/1.alert_handler_random_classes.3578231347
Short name T430
Test name
Test status
Simulation time 615674180 ps
CPU time 16.57 seconds
Started Jul 22 07:16:48 PM PDT 24
Finished Jul 22 07:18:11 PM PDT 24
Peak memory 248484 kb
Host smart-c664dfda-989e-4d7d-b4ea-c4f7d7ffc4b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35782
31347 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_classes.3578231347
Directory /workspace/1.alert_handler_random_classes/latest

Test location /workspace/coverage/default/1.alert_handler_sec_cm.1262970911
Short name T36
Test name
Test status
Simulation time 601490916 ps
CPU time 15.77 seconds
Started Jul 22 07:16:39 PM PDT 24
Finished Jul 22 07:18:01 PM PDT 24
Peak memory 270068 kb
Host smart-cf6aa78a-49de-4ca7-b31e-0ac95a84ee72
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1262970911 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sec_cm.1262970911
Directory /workspace/1.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/1.alert_handler_sig_int_fail.2723320137
Short name T284
Test name
Test status
Simulation time 1215904629 ps
CPU time 44.07 seconds
Started Jul 22 07:16:54 PM PDT 24
Finished Jul 22 07:18:42 PM PDT 24
Peak memory 248632 kb
Host smart-836a86a5-7798-4a30-ac49-86bd0e00769a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27233
20137 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sig_int_fail.2723320137
Directory /workspace/1.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/1.alert_handler_smoke.1474110417
Short name T78
Test name
Test status
Simulation time 1099954830 ps
CPU time 19.69 seconds
Started Jul 22 07:16:40 PM PDT 24
Finished Jul 22 07:18:05 PM PDT 24
Peak memory 256704 kb
Host smart-c39a2da5-dae7-4238-86d9-c47f203db7cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14741
10417 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_smoke.1474110417
Directory /workspace/1.alert_handler_smoke/latest

Test location /workspace/coverage/default/10.alert_handler_entropy.873293391
Short name T31
Test name
Test status
Simulation time 13718050205 ps
CPU time 817.71 seconds
Started Jul 22 07:17:20 PM PDT 24
Finished Jul 22 07:31:57 PM PDT 24
Peak memory 272924 kb
Host smart-c547bbcd-4362-4f4f-86e2-b6038d74c80b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873293391 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy.873293391
Directory /workspace/10.alert_handler_entropy/latest

Test location /workspace/coverage/default/10.alert_handler_entropy_stress.1899860267
Short name T413
Test name
Test status
Simulation time 585869452 ps
CPU time 9.45 seconds
Started Jul 22 07:17:22 PM PDT 24
Finished Jul 22 07:18:31 PM PDT 24
Peak memory 248612 kb
Host smart-d28655d8-2267-4300-b5d3-f1bf9c8cb569
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1899860267 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy_stress.1899860267
Directory /workspace/10.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/10.alert_handler_esc_alert_accum.1047903170
Short name T41
Test name
Test status
Simulation time 5554957726 ps
CPU time 79.68 seconds
Started Jul 22 07:17:20 PM PDT 24
Finished Jul 22 07:19:39 PM PDT 24
Peak memory 256664 kb
Host smart-f1ccf7e3-7363-4f06-b578-942075209231
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10479
03170 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_alert_accum.1047903170
Directory /workspace/10.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/10.alert_handler_esc_intr_timeout.3537574215
Short name T205
Test name
Test status
Simulation time 230204650 ps
CPU time 3.42 seconds
Started Jul 22 07:17:21 PM PDT 24
Finished Jul 22 07:18:24 PM PDT 24
Peak memory 240444 kb
Host smart-9f92cf11-0925-4b7f-bd53-e9751abedfd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35375
74215 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_intr_timeout.3537574215
Directory /workspace/10.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_lpg_stub_clk.537865265
Short name T645
Test name
Test status
Simulation time 50797487165 ps
CPU time 1187.98 seconds
Started Jul 22 07:17:20 PM PDT 24
Finished Jul 22 07:38:08 PM PDT 24
Peak memory 284168 kb
Host smart-63e698a2-709f-4db8-b3da-68cab341ffc9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537865265 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg_stub_clk.537865265
Directory /workspace/10.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/10.alert_handler_ping_timeout.509573511
Short name T8
Test name
Test status
Simulation time 2976337846 ps
CPU time 124.28 seconds
Started Jul 22 07:17:20 PM PDT 24
Finished Jul 22 07:20:25 PM PDT 24
Peak memory 248644 kb
Host smart-aa630a17-da68-48d7-9c55-4a68a867f402
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=509573511 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_ping_timeout.509573511
Directory /workspace/10.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_random_alerts.2376106917
Short name T394
Test name
Test status
Simulation time 249471986 ps
CPU time 26.92 seconds
Started Jul 22 07:17:24 PM PDT 24
Finished Jul 22 07:18:50 PM PDT 24
Peak memory 248664 kb
Host smart-2cc35115-c1a0-49a5-b19e-24484fd03693
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23761
06917 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_alerts.2376106917
Directory /workspace/10.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/10.alert_handler_random_classes.3904257225
Short name T531
Test name
Test status
Simulation time 585340049 ps
CPU time 14.51 seconds
Started Jul 22 07:17:07 PM PDT 24
Finished Jul 22 07:18:24 PM PDT 24
Peak memory 256748 kb
Host smart-c3761240-fbd0-4c5d-bc34-1dc7f1a07aa5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39042
57225 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_classes.3904257225
Directory /workspace/10.alert_handler_random_classes/latest

Test location /workspace/coverage/default/10.alert_handler_sig_int_fail.4092757934
Short name T91
Test name
Test status
Simulation time 1931695967 ps
CPU time 58.53 seconds
Started Jul 22 07:17:31 PM PDT 24
Finished Jul 22 07:19:26 PM PDT 24
Peak memory 256164 kb
Host smart-56612b56-1920-4988-882e-fa866f3ca5be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40927
57934 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_sig_int_fail.4092757934
Directory /workspace/10.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/10.alert_handler_smoke.987922891
Short name T460
Test name
Test status
Simulation time 349066362 ps
CPU time 12.84 seconds
Started Jul 22 07:17:25 PM PDT 24
Finished Jul 22 07:18:37 PM PDT 24
Peak memory 248644 kb
Host smart-39c5da2d-5102-4e38-a655-b652114c2c9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98792
2891 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_smoke.987922891
Directory /workspace/10.alert_handler_smoke/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all.3735836620
Short name T32
Test name
Test status
Simulation time 52498526639 ps
CPU time 3341.68 seconds
Started Jul 22 07:17:31 PM PDT 24
Finished Jul 22 08:14:09 PM PDT 24
Peak memory 304568 kb
Host smart-03420bc6-4c36-4066-b67b-1391c47828df
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735836620 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_ha
ndler_stress_all.3735836620
Directory /workspace/10.alert_handler_stress_all/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all_with_rand_reset.4037612113
Short name T544
Test name
Test status
Simulation time 68772907346 ps
CPU time 1853.46 seconds
Started Jul 22 07:17:24 PM PDT 24
Finished Jul 22 07:49:17 PM PDT 24
Peak memory 305984 kb
Host smart-107b0ad3-e704-470d-a14f-80f8319ae24e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037612113 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 10.alert_handler_stress_all_with_rand_reset.4037612113
Directory /workspace/10.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.alert_handler_alert_accum_saturation.3610169209
Short name T224
Test name
Test status
Simulation time 43736768 ps
CPU time 3.55 seconds
Started Jul 22 07:17:53 PM PDT 24
Finished Jul 22 07:18:49 PM PDT 24
Peak memory 253780 kb
Host smart-fdda433d-57a7-466c-a85a-91e6c74b2853
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3610169209 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_alert_accum_saturation.3610169209
Directory /workspace/11.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/11.alert_handler_entropy.4001683109
Short name T600
Test name
Test status
Simulation time 77831756688 ps
CPU time 2241.45 seconds
Started Jul 22 07:17:23 PM PDT 24
Finished Jul 22 07:55:44 PM PDT 24
Peak memory 289008 kb
Host smart-e803bd83-257c-4e61-b22d-20286b5105e5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001683109 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy.4001683109
Directory /workspace/11.alert_handler_entropy/latest

Test location /workspace/coverage/default/11.alert_handler_entropy_stress.3046279342
Short name T637
Test name
Test status
Simulation time 501842962 ps
CPU time 23.54 seconds
Started Jul 22 07:17:27 PM PDT 24
Finished Jul 22 07:18:49 PM PDT 24
Peak memory 248348 kb
Host smart-d1da2819-3ee1-4bab-9deb-85fd68ad55e1
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3046279342 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy_stress.3046279342
Directory /workspace/11.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/11.alert_handler_esc_alert_accum.4131571569
Short name T383
Test name
Test status
Simulation time 6959130456 ps
CPU time 193.58 seconds
Started Jul 22 07:17:36 PM PDT 24
Finished Jul 22 07:21:44 PM PDT 24
Peak memory 256320 kb
Host smart-bed7832e-8e89-4b10-b857-a647eabf0324
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41315
71569 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_alert_accum.4131571569
Directory /workspace/11.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/11.alert_handler_esc_intr_timeout.647405689
Short name T418
Test name
Test status
Simulation time 577760774 ps
CPU time 32.32 seconds
Started Jul 22 07:17:24 PM PDT 24
Finished Jul 22 07:18:56 PM PDT 24
Peak memory 248688 kb
Host smart-1fa8108a-98b2-4005-86aa-e0b04d08549e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64740
5689 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_intr_timeout.647405689
Directory /workspace/11.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_lpg.3053865815
Short name T242
Test name
Test status
Simulation time 32573310936 ps
CPU time 1856.72 seconds
Started Jul 22 07:17:22 PM PDT 24
Finished Jul 22 07:49:19 PM PDT 24
Peak memory 273016 kb
Host smart-b8a2fef7-4d84-4275-9585-11b3cff79952
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3053865815 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg.3053865815
Directory /workspace/11.alert_handler_lpg/latest

Test location /workspace/coverage/default/11.alert_handler_lpg_stub_clk.224821328
Short name T553
Test name
Test status
Simulation time 21413223377 ps
CPU time 966.97 seconds
Started Jul 22 07:17:24 PM PDT 24
Finished Jul 22 07:34:31 PM PDT 24
Peak memory 272404 kb
Host smart-498689b3-1f77-422d-a937-8c5d36e175f9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224821328 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg_stub_clk.224821328
Directory /workspace/11.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/11.alert_handler_ping_timeout.1598942286
Short name T311
Test name
Test status
Simulation time 6813244598 ps
CPU time 152.06 seconds
Started Jul 22 07:17:30 PM PDT 24
Finished Jul 22 07:20:59 PM PDT 24
Peak memory 248736 kb
Host smart-aa430b1e-1723-427f-8b4f-27688845f9b8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598942286 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_ping_timeout.1598942286
Directory /workspace/11.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_random_alerts.2853137762
Short name T501
Test name
Test status
Simulation time 211654338 ps
CPU time 14.55 seconds
Started Jul 22 07:17:20 PM PDT 24
Finished Jul 22 07:18:35 PM PDT 24
Peak memory 248584 kb
Host smart-e6abe593-23e4-469a-bfca-5c2f7e2254e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28531
37762 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_alerts.2853137762
Directory /workspace/11.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/11.alert_handler_random_classes.1314929624
Short name T465
Test name
Test status
Simulation time 2938578794 ps
CPU time 47.24 seconds
Started Jul 22 07:17:24 PM PDT 24
Finished Jul 22 07:19:11 PM PDT 24
Peak memory 248488 kb
Host smart-8f264ead-fdf0-4ef7-b185-50eea94b2e0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13149
29624 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_classes.1314929624
Directory /workspace/11.alert_handler_random_classes/latest

Test location /workspace/coverage/default/11.alert_handler_smoke.370093705
Short name T621
Test name
Test status
Simulation time 184427540 ps
CPU time 16.21 seconds
Started Jul 22 07:17:20 PM PDT 24
Finished Jul 22 07:18:37 PM PDT 24
Peak memory 256696 kb
Host smart-4cde277f-878e-46f7-834d-209303278b88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37009
3705 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_smoke.370093705
Directory /workspace/11.alert_handler_smoke/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all_with_rand_reset.2487881413
Short name T111
Test name
Test status
Simulation time 101883941537 ps
CPU time 5963.16 seconds
Started Jul 22 07:17:24 PM PDT 24
Finished Jul 22 08:57:48 PM PDT 24
Peak memory 332504 kb
Host smart-6df42633-a604-433c-9140-152b262e340d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487881413 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 11.alert_handler_stress_all_with_rand_reset.2487881413
Directory /workspace/11.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.alert_handler_alert_accum_saturation.2171170481
Short name T226
Test name
Test status
Simulation time 459964046 ps
CPU time 3.53 seconds
Started Jul 22 07:17:22 PM PDT 24
Finished Jul 22 07:18:25 PM PDT 24
Peak memory 257008 kb
Host smart-cce89609-a926-4886-b248-9595e4eb89a6
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2171170481 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_alert_accum_saturation.2171170481
Directory /workspace/12.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/12.alert_handler_entropy.3157653290
Short name T106
Test name
Test status
Simulation time 44128451642 ps
CPU time 2676.66 seconds
Started Jul 22 07:17:24 PM PDT 24
Finished Jul 22 08:03:00 PM PDT 24
Peak memory 281452 kb
Host smart-9ee50c00-0800-4fa4-816f-5576820967cc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157653290 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy.3157653290
Directory /workspace/12.alert_handler_entropy/latest

Test location /workspace/coverage/default/12.alert_handler_entropy_stress.2689326916
Short name T529
Test name
Test status
Simulation time 5039919384 ps
CPU time 52.31 seconds
Started Jul 22 07:17:27 PM PDT 24
Finished Jul 22 07:19:18 PM PDT 24
Peak memory 248384 kb
Host smart-710c0f41-f121-4041-9c03-f5e6ed5e6a67
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2689326916 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy_stress.2689326916
Directory /workspace/12.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/12.alert_handler_esc_alert_accum.416080922
Short name T462
Test name
Test status
Simulation time 2194386607 ps
CPU time 91.6 seconds
Started Jul 22 07:17:30 PM PDT 24
Finished Jul 22 07:19:59 PM PDT 24
Peak memory 256404 kb
Host smart-d25325ca-46fc-4dee-976f-6a44be3f786c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41608
0922 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_alert_accum.416080922
Directory /workspace/12.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/12.alert_handler_esc_intr_timeout.569166834
Short name T648
Test name
Test status
Simulation time 1044916867 ps
CPU time 17.26 seconds
Started Jul 22 07:17:23 PM PDT 24
Finished Jul 22 07:18:40 PM PDT 24
Peak memory 248628 kb
Host smart-c61c7383-1182-4e1f-9279-fb27d8817d9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56916
6834 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_intr_timeout.569166834
Directory /workspace/12.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_lpg.2333178396
Short name T504
Test name
Test status
Simulation time 48349325941 ps
CPU time 1533.06 seconds
Started Jul 22 07:17:25 PM PDT 24
Finished Jul 22 07:43:58 PM PDT 24
Peak memory 273180 kb
Host smart-1713b0f5-16cf-47f8-9037-b37f3f3ec540
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2333178396 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg.2333178396
Directory /workspace/12.alert_handler_lpg/latest

Test location /workspace/coverage/default/12.alert_handler_lpg_stub_clk.2082279351
Short name T45
Test name
Test status
Simulation time 6797927948 ps
CPU time 709.49 seconds
Started Jul 22 07:17:28 PM PDT 24
Finished Jul 22 07:30:15 PM PDT 24
Peak memory 272396 kb
Host smart-347cce79-5cb4-4faf-98be-e45e7e336864
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2082279351 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg_stub_clk.2082279351
Directory /workspace/12.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/12.alert_handler_ping_timeout.402574932
Short name T296
Test name
Test status
Simulation time 33449062433 ps
CPU time 614.31 seconds
Started Jul 22 07:17:36 PM PDT 24
Finished Jul 22 07:28:44 PM PDT 24
Peak memory 248600 kb
Host smart-49df1ed1-784a-413e-adaf-9d5eba6440ef
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=402574932 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_ping_timeout.402574932
Directory /workspace/12.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_random_alerts.3842333625
Short name T404
Test name
Test status
Simulation time 212479445 ps
CPU time 13.72 seconds
Started Jul 22 07:17:25 PM PDT 24
Finished Jul 22 07:18:38 PM PDT 24
Peak memory 248596 kb
Host smart-9b5c30d5-9c34-431b-a3b0-b7f4f63e94fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38423
33625 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_alerts.3842333625
Directory /workspace/12.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/12.alert_handler_random_classes.788290870
Short name T292
Test name
Test status
Simulation time 1877854750 ps
CPU time 53.9 seconds
Started Jul 22 07:17:27 PM PDT 24
Finished Jul 22 07:19:20 PM PDT 24
Peak memory 247800 kb
Host smart-dfda0e79-377b-44a2-9e15-debb114918fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78829
0870 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_classes.788290870
Directory /workspace/12.alert_handler_random_classes/latest

Test location /workspace/coverage/default/12.alert_handler_smoke.1490468368
Short name T376
Test name
Test status
Simulation time 647058282 ps
CPU time 8.73 seconds
Started Jul 22 07:17:36 PM PDT 24
Finished Jul 22 07:18:39 PM PDT 24
Peak memory 255236 kb
Host smart-f113c7c6-1cac-4f1a-9a8e-8c834afef2fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14904
68368 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_smoke.1490468368
Directory /workspace/12.alert_handler_smoke/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all.582267453
Short name T291
Test name
Test status
Simulation time 153431721792 ps
CPU time 2328.34 seconds
Started Jul 22 07:17:24 PM PDT 24
Finished Jul 22 07:57:12 PM PDT 24
Peak memory 288992 kb
Host smart-982b50b2-58f1-47da-b257-2e38948fcb49
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582267453 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_han
dler_stress_all.582267453
Directory /workspace/12.alert_handler_stress_all/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all_with_rand_reset.1322012758
Short name T104
Test name
Test status
Simulation time 59396873744 ps
CPU time 5913.44 seconds
Started Jul 22 07:17:20 PM PDT 24
Finished Jul 22 08:56:55 PM PDT 24
Peak memory 354532 kb
Host smart-f8f95c8d-f27d-477e-9043-b9148da584c1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322012758 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.alert_handler_stress_all_with_rand_reset.1322012758
Directory /workspace/12.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.alert_handler_alert_accum_saturation.1225379448
Short name T223
Test name
Test status
Simulation time 63534663 ps
CPU time 3.24 seconds
Started Jul 22 07:17:23 PM PDT 24
Finished Jul 22 07:18:26 PM PDT 24
Peak memory 248860 kb
Host smart-2230114b-0301-44e5-9409-e24a197d82b3
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1225379448 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_alert_accum_saturation.1225379448
Directory /workspace/13.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/13.alert_handler_entropy.3859885434
Short name T602
Test name
Test status
Simulation time 39207031917 ps
CPU time 2025.48 seconds
Started Jul 22 07:17:36 PM PDT 24
Finished Jul 22 07:52:15 PM PDT 24
Peak memory 281396 kb
Host smart-27403e71-0e1f-4aee-a98c-5e45a2a91943
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859885434 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy.3859885434
Directory /workspace/13.alert_handler_entropy/latest

Test location /workspace/coverage/default/13.alert_handler_entropy_stress.1724876530
Short name T244
Test name
Test status
Simulation time 491957995 ps
CPU time 14 seconds
Started Jul 22 07:17:30 PM PDT 24
Finished Jul 22 07:18:41 PM PDT 24
Peak memory 248672 kb
Host smart-4b56f938-4f2b-4f08-a5e4-74ed2a8fd916
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1724876530 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy_stress.1724876530
Directory /workspace/13.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/13.alert_handler_esc_alert_accum.111919623
Short name T439
Test name
Test status
Simulation time 2378913560 ps
CPU time 129.55 seconds
Started Jul 22 07:17:31 PM PDT 24
Finished Jul 22 07:20:37 PM PDT 24
Peak memory 256312 kb
Host smart-c93e9caa-a2e6-4b81-9f32-e0ef681b3fd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11191
9623 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_alert_accum.111919623
Directory /workspace/13.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/13.alert_handler_esc_intr_timeout.2889736256
Short name T509
Test name
Test status
Simulation time 1487215263 ps
CPU time 25.47 seconds
Started Jul 22 07:17:21 PM PDT 24
Finished Jul 22 07:18:46 PM PDT 24
Peak memory 256352 kb
Host smart-5e818b0b-3f36-42ad-a9a1-29799e4cf07f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28897
36256 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_intr_timeout.2889736256
Directory /workspace/13.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_lpg_stub_clk.1265239628
Short name T100
Test name
Test status
Simulation time 249771150043 ps
CPU time 2110.98 seconds
Started Jul 22 07:17:22 PM PDT 24
Finished Jul 22 07:53:33 PM PDT 24
Peak memory 273256 kb
Host smart-a0965a8a-39f6-4b3e-90cd-5fde54f9dac5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1265239628 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg_stub_clk.1265239628
Directory /workspace/13.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/13.alert_handler_random_alerts.298948966
Short name T616
Test name
Test status
Simulation time 244264266 ps
CPU time 14.53 seconds
Started Jul 22 07:17:23 PM PDT 24
Finished Jul 22 07:18:37 PM PDT 24
Peak memory 256492 kb
Host smart-0c4a6ed8-a61b-4549-8f46-b451a22f23f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29894
8966 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_alerts.298948966
Directory /workspace/13.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/13.alert_handler_random_classes.3036799112
Short name T424
Test name
Test status
Simulation time 1503993702 ps
CPU time 34.13 seconds
Started Jul 22 07:17:21 PM PDT 24
Finished Jul 22 07:18:55 PM PDT 24
Peak memory 248300 kb
Host smart-e14a638f-b2c0-4f55-9dae-b14e13c00250
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30367
99112 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_classes.3036799112
Directory /workspace/13.alert_handler_random_classes/latest

Test location /workspace/coverage/default/13.alert_handler_sig_int_fail.1187230175
Short name T201
Test name
Test status
Simulation time 213616664 ps
CPU time 6.52 seconds
Started Jul 22 07:17:24 PM PDT 24
Finished Jul 22 07:18:30 PM PDT 24
Peak memory 253028 kb
Host smart-e9804800-99b4-4293-b8c6-850bfbae117a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11872
30175 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_sig_int_fail.1187230175
Directory /workspace/13.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/13.alert_handler_smoke.3912101047
Short name T554
Test name
Test status
Simulation time 217809603 ps
CPU time 11.92 seconds
Started Jul 22 07:17:35 PM PDT 24
Finished Jul 22 07:18:42 PM PDT 24
Peak memory 254828 kb
Host smart-f51e2f61-4430-453c-9f8c-d7d5d5d919e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39121
01047 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_smoke.3912101047
Directory /workspace/13.alert_handler_smoke/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all.254689672
Short name T673
Test name
Test status
Simulation time 90590430882 ps
CPU time 1939.88 seconds
Started Jul 22 07:17:21 PM PDT 24
Finished Jul 22 07:50:41 PM PDT 24
Peak memory 273100 kb
Host smart-4bbeb063-e476-4749-b95d-6cc5c737eed4
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254689672 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_han
dler_stress_all.254689672
Directory /workspace/13.alert_handler_stress_all/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all_with_rand_reset.3612893561
Short name T309
Test name
Test status
Simulation time 19557573165 ps
CPU time 1793.55 seconds
Started Jul 22 07:17:35 PM PDT 24
Finished Jul 22 07:48:23 PM PDT 24
Peak memory 306024 kb
Host smart-75d89fb8-56ae-4afb-a915-7a7c7cbebe25
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612893561 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.alert_handler_stress_all_with_rand_reset.3612893561
Directory /workspace/13.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.alert_handler_alert_accum_saturation.806128
Short name T233
Test name
Test status
Simulation time 36877042 ps
CPU time 3.07 seconds
Started Jul 22 07:17:40 PM PDT 24
Finished Jul 22 07:18:37 PM PDT 24
Peak memory 248820 kb
Host smart-8e64170b-c79a-44d9-beb9-4f88ee656ab8
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=806128 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_alert_accum_saturation.806128
Directory /workspace/14.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/14.alert_handler_entropy.3156801452
Short name T130
Test name
Test status
Simulation time 137232709696 ps
CPU time 675.92 seconds
Started Jul 22 07:17:37 PM PDT 24
Finished Jul 22 07:29:47 PM PDT 24
Peak memory 273116 kb
Host smart-bea8b073-0830-4493-bfcc-1ba49f86cc3c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156801452 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy.3156801452
Directory /workspace/14.alert_handler_entropy/latest

Test location /workspace/coverage/default/14.alert_handler_entropy_stress.1823644820
Short name T435
Test name
Test status
Simulation time 1099251861 ps
CPU time 44.13 seconds
Started Jul 22 07:17:31 PM PDT 24
Finished Jul 22 07:19:12 PM PDT 24
Peak memory 248660 kb
Host smart-ab6acd9d-51fb-4cfc-a273-c98d571850fe
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1823644820 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy_stress.1823644820
Directory /workspace/14.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/14.alert_handler_esc_alert_accum.272159489
Short name T40
Test name
Test status
Simulation time 2106326128 ps
CPU time 27.16 seconds
Started Jul 22 07:17:44 PM PDT 24
Finished Jul 22 07:19:06 PM PDT 24
Peak memory 256300 kb
Host smart-c1ddfa51-4231-450d-a3e5-16619bfba95c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27215
9489 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_alert_accum.272159489
Directory /workspace/14.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/14.alert_handler_esc_intr_timeout.2953241252
Short name T76
Test name
Test status
Simulation time 85874042 ps
CPU time 8.68 seconds
Started Jul 22 07:17:32 PM PDT 24
Finished Jul 22 07:18:37 PM PDT 24
Peak memory 254700 kb
Host smart-3d28a944-7393-46a3-a94d-782508171b32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29532
41252 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_intr_timeout.2953241252
Directory /workspace/14.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_lpg_stub_clk.2885330598
Short name T304
Test name
Test status
Simulation time 255435494557 ps
CPU time 2216.43 seconds
Started Jul 22 07:17:38 PM PDT 24
Finished Jul 22 07:55:28 PM PDT 24
Peak memory 273100 kb
Host smart-816c3451-66cc-4945-83c1-3deb1f91707e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885330598 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg_stub_clk.2885330598
Directory /workspace/14.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/14.alert_handler_ping_timeout.4003423802
Short name T322
Test name
Test status
Simulation time 51557421962 ps
CPU time 387.49 seconds
Started Jul 22 07:17:33 PM PDT 24
Finished Jul 22 07:24:56 PM PDT 24
Peak memory 248664 kb
Host smart-0f3ba177-54ad-4e29-95fe-1acef771fec1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4003423802 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_ping_timeout.4003423802
Directory /workspace/14.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_random_alerts.1725434142
Short name T463
Test name
Test status
Simulation time 1138950833 ps
CPU time 59.95 seconds
Started Jul 22 07:17:24 PM PDT 24
Finished Jul 22 07:19:23 PM PDT 24
Peak memory 248720 kb
Host smart-7e33e01f-4435-4128-b054-e428115eb4f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17254
34142 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_alerts.1725434142
Directory /workspace/14.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/14.alert_handler_random_classes.1842788220
Short name T643
Test name
Test status
Simulation time 314533896 ps
CPU time 22.48 seconds
Started Jul 22 07:17:35 PM PDT 24
Finished Jul 22 07:18:52 PM PDT 24
Peak memory 248928 kb
Host smart-02ee0200-e77d-4766-b37e-e0de291595fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18427
88220 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_classes.1842788220
Directory /workspace/14.alert_handler_random_classes/latest

Test location /workspace/coverage/default/14.alert_handler_sig_int_fail.3458282503
Short name T682
Test name
Test status
Simulation time 120692396 ps
CPU time 11.68 seconds
Started Jul 22 07:17:49 PM PDT 24
Finished Jul 22 07:18:54 PM PDT 24
Peak memory 249160 kb
Host smart-2d2c4322-a834-422e-b364-61583304ee9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34582
82503 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_sig_int_fail.3458282503
Directory /workspace/14.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/14.alert_handler_smoke.2383495622
Short name T717
Test name
Test status
Simulation time 1026148504 ps
CPU time 16.88 seconds
Started Jul 22 07:17:24 PM PDT 24
Finished Jul 22 07:18:40 PM PDT 24
Peak memory 255956 kb
Host smart-aff30515-8278-4d26-8656-c3c8f814991e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23834
95622 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_smoke.2383495622
Directory /workspace/14.alert_handler_smoke/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all.115881204
Short name T278
Test name
Test status
Simulation time 30504013738 ps
CPU time 810.03 seconds
Started Jul 22 07:17:38 PM PDT 24
Finished Jul 22 07:32:01 PM PDT 24
Peak memory 281440 kb
Host smart-54b9e048-5dce-40a5-a78e-83efde498370
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115881204 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_han
dler_stress_all.115881204
Directory /workspace/14.alert_handler_stress_all/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all_with_rand_reset.1884452644
Short name T480
Test name
Test status
Simulation time 123480051898 ps
CPU time 5393.76 seconds
Started Jul 22 07:17:38 PM PDT 24
Finished Jul 22 08:48:25 PM PDT 24
Peak memory 332200 kb
Host smart-c9c32acf-4fa6-421c-90c3-4e55fedf39aa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884452644 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 14.alert_handler_stress_all_with_rand_reset.1884452644
Directory /workspace/14.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.alert_handler_alert_accum_saturation.1371390033
Short name T230
Test name
Test status
Simulation time 45259894 ps
CPU time 2.32 seconds
Started Jul 22 07:17:36 PM PDT 24
Finished Jul 22 07:18:32 PM PDT 24
Peak memory 248820 kb
Host smart-9c81f8cf-655c-4193-b73b-5a5d2507e6fb
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1371390033 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_alert_accum_saturation.1371390033
Directory /workspace/15.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/15.alert_handler_entropy.1414209273
Short name T121
Test name
Test status
Simulation time 551903428019 ps
CPU time 2781.97 seconds
Started Jul 22 07:17:33 PM PDT 24
Finished Jul 22 08:04:50 PM PDT 24
Peak memory 288644 kb
Host smart-7e7ec9bf-eb47-401f-9a0f-ad77fed377c6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414209273 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy.1414209273
Directory /workspace/15.alert_handler_entropy/latest

Test location /workspace/coverage/default/15.alert_handler_entropy_stress.4050189091
Short name T1
Test name
Test status
Simulation time 2564610123 ps
CPU time 19.22 seconds
Started Jul 22 07:17:40 PM PDT 24
Finished Jul 22 07:18:54 PM PDT 24
Peak memory 248568 kb
Host smart-eae691ee-e26e-4511-b6f6-2d5fd8596081
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4050189091 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy_stress.4050189091
Directory /workspace/15.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/15.alert_handler_esc_alert_accum.539107646
Short name T629
Test name
Test status
Simulation time 2978569357 ps
CPU time 44.98 seconds
Started Jul 22 07:17:38 PM PDT 24
Finished Jul 22 07:19:16 PM PDT 24
Peak memory 256300 kb
Host smart-93284469-44f7-4108-a961-7c5841995c40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53910
7646 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_alert_accum.539107646
Directory /workspace/15.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/15.alert_handler_esc_intr_timeout.2138550950
Short name T692
Test name
Test status
Simulation time 158966567 ps
CPU time 6.18 seconds
Started Jul 22 07:17:37 PM PDT 24
Finished Jul 22 07:18:36 PM PDT 24
Peak memory 248720 kb
Host smart-6145904a-8e22-46f7-99e2-cd5713299da6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21385
50950 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_intr_timeout.2138550950
Directory /workspace/15.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_lpg_stub_clk.2926678044
Short name T671
Test name
Test status
Simulation time 17212961006 ps
CPU time 1085.86 seconds
Started Jul 22 07:17:38 PM PDT 24
Finished Jul 22 07:36:37 PM PDT 24
Peak memory 272564 kb
Host smart-a60e601a-59b3-4629-81d2-a2ad3661ec03
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926678044 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg_stub_clk.2926678044
Directory /workspace/15.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/15.alert_handler_ping_timeout.1161187923
Short name T316
Test name
Test status
Simulation time 9049887689 ps
CPU time 315.36 seconds
Started Jul 22 07:18:17 PM PDT 24
Finished Jul 22 07:24:26 PM PDT 24
Peak memory 248644 kb
Host smart-85133892-4571-4d08-8093-33750e633689
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161187923 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_ping_timeout.1161187923
Directory /workspace/15.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_random_alerts.1821175387
Short name T215
Test name
Test status
Simulation time 613574041 ps
CPU time 28.53 seconds
Started Jul 22 07:17:40 PM PDT 24
Finished Jul 22 07:19:02 PM PDT 24
Peak memory 256696 kb
Host smart-c0aece03-8a48-4679-8a43-48ab0d4dc2a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18211
75387 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_alerts.1821175387
Directory /workspace/15.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/15.alert_handler_random_classes.1586445100
Short name T389
Test name
Test status
Simulation time 779743025 ps
CPU time 7.6 seconds
Started Jul 22 07:17:32 PM PDT 24
Finished Jul 22 07:18:36 PM PDT 24
Peak memory 248952 kb
Host smart-27d4dcb1-9bb2-4103-90cd-2ebae58ad177
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15864
45100 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_classes.1586445100
Directory /workspace/15.alert_handler_random_classes/latest

Test location /workspace/coverage/default/15.alert_handler_smoke.2293409433
Short name T659
Test name
Test status
Simulation time 1167351024 ps
CPU time 32.78 seconds
Started Jul 22 07:18:07 PM PDT 24
Finished Jul 22 07:19:30 PM PDT 24
Peak memory 256028 kb
Host smart-467388fa-1020-4fe9-a6e4-04c9db813abf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22934
09433 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_smoke.2293409433
Directory /workspace/15.alert_handler_smoke/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all_with_rand_reset.1694086471
Short name T605
Test name
Test status
Simulation time 40039004714 ps
CPU time 1533.04 seconds
Started Jul 22 07:17:44 PM PDT 24
Finished Jul 22 07:44:10 PM PDT 24
Peak memory 271860 kb
Host smart-9e113106-f8be-4d14-9d1a-2c94fa56b7ce
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694086471 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 15.alert_handler_stress_all_with_rand_reset.1694086471
Directory /workspace/15.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.alert_handler_entropy.3759004510
Short name T448
Test name
Test status
Simulation time 104753684784 ps
CPU time 2901.14 seconds
Started Jul 22 07:17:40 PM PDT 24
Finished Jul 22 08:06:56 PM PDT 24
Peak memory 289388 kb
Host smart-ba54bdac-d53d-4d4f-b5e9-aaade307d6f4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759004510 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy.3759004510
Directory /workspace/16.alert_handler_entropy/latest

Test location /workspace/coverage/default/16.alert_handler_entropy_stress.3827656387
Short name T522
Test name
Test status
Simulation time 1519451419 ps
CPU time 61.26 seconds
Started Jul 22 07:17:32 PM PDT 24
Finished Jul 22 07:19:29 PM PDT 24
Peak memory 248612 kb
Host smart-3d9f214c-a1cf-4d28-8d30-fe2b862b2e94
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3827656387 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy_stress.3827656387
Directory /workspace/16.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/16.alert_handler_esc_alert_accum.630737814
Short name T608
Test name
Test status
Simulation time 8590459977 ps
CPU time 124.79 seconds
Started Jul 22 07:17:35 PM PDT 24
Finished Jul 22 07:20:34 PM PDT 24
Peak memory 256724 kb
Host smart-82b1566e-61aa-4b90-8565-7e1250f86385
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63073
7814 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_alert_accum.630737814
Directory /workspace/16.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/16.alert_handler_esc_intr_timeout.288725984
Short name T598
Test name
Test status
Simulation time 2498231947 ps
CPU time 50.18 seconds
Started Jul 22 07:17:36 PM PDT 24
Finished Jul 22 07:19:20 PM PDT 24
Peak memory 249804 kb
Host smart-e49600f1-778a-463d-a540-158226f4e6f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28872
5984 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_intr_timeout.288725984
Directory /workspace/16.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_lpg.618956440
Short name T680
Test name
Test status
Simulation time 66197302484 ps
CPU time 1456.7 seconds
Started Jul 22 07:17:35 PM PDT 24
Finished Jul 22 07:42:46 PM PDT 24
Peak memory 289296 kb
Host smart-f1c26c79-6281-424b-b29a-6ee3b4c02846
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=618956440 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg.618956440
Directory /workspace/16.alert_handler_lpg/latest

Test location /workspace/coverage/default/16.alert_handler_lpg_stub_clk.3493061231
Short name T422
Test name
Test status
Simulation time 57043589993 ps
CPU time 1581.6 seconds
Started Jul 22 07:17:36 PM PDT 24
Finished Jul 22 07:44:52 PM PDT 24
Peak memory 272784 kb
Host smart-22d5c4ca-5442-4813-bc3c-110a81b09433
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3493061231 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg_stub_clk.3493061231
Directory /workspace/16.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/16.alert_handler_random_alerts.4203532109
Short name T565
Test name
Test status
Simulation time 581033908 ps
CPU time 21.71 seconds
Started Jul 22 07:17:36 PM PDT 24
Finished Jul 22 07:18:52 PM PDT 24
Peak memory 248652 kb
Host smart-8be1e071-3b8d-450d-a034-c7139d8b53d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42035
32109 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_alerts.4203532109
Directory /workspace/16.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/16.alert_handler_random_classes.268882936
Short name T640
Test name
Test status
Simulation time 222774252 ps
CPU time 13.92 seconds
Started Jul 22 07:17:44 PM PDT 24
Finished Jul 22 07:18:52 PM PDT 24
Peak memory 248956 kb
Host smart-e638d217-6cf6-492e-8b44-c3f86e550825
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26888
2936 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_classes.268882936
Directory /workspace/16.alert_handler_random_classes/latest

Test location /workspace/coverage/default/16.alert_handler_sig_int_fail.1572150171
Short name T518
Test name
Test status
Simulation time 128062899 ps
CPU time 14.12 seconds
Started Jul 22 07:17:39 PM PDT 24
Finished Jul 22 07:18:46 PM PDT 24
Peak memory 256320 kb
Host smart-6a4c45de-ed0c-4133-92d0-54d112b76954
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15721
50171 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_sig_int_fail.1572150171
Directory /workspace/16.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/16.alert_handler_smoke.3137207803
Short name T397
Test name
Test status
Simulation time 234854324 ps
CPU time 19.98 seconds
Started Jul 22 07:17:40 PM PDT 24
Finished Jul 22 07:18:54 PM PDT 24
Peak memory 256648 kb
Host smart-3727da1c-8d60-48ea-aee0-bb2e8bfffba0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31372
07803 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_smoke.3137207803
Directory /workspace/16.alert_handler_smoke/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all_with_rand_reset.1154669674
Short name T489
Test name
Test status
Simulation time 17993202000 ps
CPU time 1986.96 seconds
Started Jul 22 07:17:47 PM PDT 24
Finished Jul 22 07:51:49 PM PDT 24
Peak memory 305400 kb
Host smart-c13e7398-5536-40c5-8f11-4c7111dd4086
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154669674 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 16.alert_handler_stress_all_with_rand_reset.1154669674
Directory /workspace/16.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.alert_handler_alert_accum_saturation.2930207121
Short name T225
Test name
Test status
Simulation time 14893239 ps
CPU time 2.87 seconds
Started Jul 22 07:17:45 PM PDT 24
Finished Jul 22 07:18:43 PM PDT 24
Peak memory 248932 kb
Host smart-6a382a1d-9792-47d8-bd75-4fdbfdcc8803
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2930207121 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_alert_accum_saturation.2930207121
Directory /workspace/17.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/17.alert_handler_entropy.2579846096
Short name T547
Test name
Test status
Simulation time 10384389928 ps
CPU time 963 seconds
Started Jul 22 07:17:44 PM PDT 24
Finished Jul 22 07:34:42 PM PDT 24
Peak memory 272232 kb
Host smart-5d39732d-b2fc-4449-8412-a90b44f70430
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579846096 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy.2579846096
Directory /workspace/17.alert_handler_entropy/latest

Test location /workspace/coverage/default/17.alert_handler_entropy_stress.2057178967
Short name T549
Test name
Test status
Simulation time 1783131879 ps
CPU time 25.17 seconds
Started Jul 22 07:17:47 PM PDT 24
Finished Jul 22 07:19:07 PM PDT 24
Peak memory 248552 kb
Host smart-44e579b2-6af5-42f2-b570-3c43546ad402
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2057178967 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy_stress.2057178967
Directory /workspace/17.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/17.alert_handler_esc_alert_accum.4153552028
Short name T612
Test name
Test status
Simulation time 2154174280 ps
CPU time 47.22 seconds
Started Jul 22 07:18:17 PM PDT 24
Finished Jul 22 07:19:58 PM PDT 24
Peak memory 256860 kb
Host smart-5dc3f019-e74b-497b-8f09-2fbe504ff913
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41535
52028 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_alert_accum.4153552028
Directory /workspace/17.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/17.alert_handler_esc_intr_timeout.1942433594
Short name T402
Test name
Test status
Simulation time 134480141 ps
CPU time 9.02 seconds
Started Jul 22 07:17:46 PM PDT 24
Finished Jul 22 07:18:49 PM PDT 24
Peak memory 248540 kb
Host smart-60f7df98-711b-4f2c-93cf-c963f9620692
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19424
33594 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_intr_timeout.1942433594
Directory /workspace/17.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_lpg.2158368589
Short name T356
Test name
Test status
Simulation time 127101218351 ps
CPU time 1693.88 seconds
Started Jul 22 07:17:47 PM PDT 24
Finished Jul 22 07:46:55 PM PDT 24
Peak memory 289612 kb
Host smart-43322969-bccf-4655-8118-ec4f503dcdd7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2158368589 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg.2158368589
Directory /workspace/17.alert_handler_lpg/latest

Test location /workspace/coverage/default/17.alert_handler_lpg_stub_clk.2145396663
Short name T468
Test name
Test status
Simulation time 48458833940 ps
CPU time 1560.51 seconds
Started Jul 22 07:17:46 PM PDT 24
Finished Jul 22 07:44:42 PM PDT 24
Peak memory 273176 kb
Host smart-4d578208-ab2e-4770-8aad-c763ae0d86e2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2145396663 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg_stub_clk.2145396663
Directory /workspace/17.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/17.alert_handler_ping_timeout.1624788800
Short name T604
Test name
Test status
Simulation time 3226450412 ps
CPU time 128.9 seconds
Started Jul 22 07:17:46 PM PDT 24
Finished Jul 22 07:20:49 PM PDT 24
Peak memory 248672 kb
Host smart-9202688e-f882-487f-acca-bf70a7139314
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1624788800 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_ping_timeout.1624788800
Directory /workspace/17.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_random_alerts.461957077
Short name T440
Test name
Test status
Simulation time 296691176 ps
CPU time 16.04 seconds
Started Jul 22 07:17:47 PM PDT 24
Finished Jul 22 07:18:58 PM PDT 24
Peak memory 248632 kb
Host smart-dc45dc48-954b-41c1-b8a9-d07ccd8ccf57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46195
7077 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_alerts.461957077
Directory /workspace/17.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/17.alert_handler_random_classes.1222140599
Short name T55
Test name
Test status
Simulation time 949208742 ps
CPU time 65.48 seconds
Started Jul 22 07:17:47 PM PDT 24
Finished Jul 22 07:19:47 PM PDT 24
Peak memory 249616 kb
Host smart-9f018d9f-79d8-4f75-b97a-4b605518da6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12221
40599 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_classes.1222140599
Directory /workspace/17.alert_handler_random_classes/latest

Test location /workspace/coverage/default/17.alert_handler_smoke.3322365642
Short name T20
Test name
Test status
Simulation time 716142802 ps
CPU time 47.46 seconds
Started Jul 22 07:17:47 PM PDT 24
Finished Jul 22 07:19:29 PM PDT 24
Peak memory 255796 kb
Host smart-b2a466cb-e059-4514-9f05-3846fb099808
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33223
65642 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_smoke.3322365642
Directory /workspace/17.alert_handler_smoke/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all_with_rand_reset.3457143920
Short name T110
Test name
Test status
Simulation time 10982583424 ps
CPU time 1281.53 seconds
Started Jul 22 07:17:48 PM PDT 24
Finished Jul 22 07:40:04 PM PDT 24
Peak memory 288928 kb
Host smart-6574584b-8195-40d0-a5af-c9e9ec2d28b2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457143920 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 17.alert_handler_stress_all_with_rand_reset.3457143920
Directory /workspace/17.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.alert_handler_alert_accum_saturation.4057867276
Short name T218
Test name
Test status
Simulation time 29482492 ps
CPU time 2.88 seconds
Started Jul 22 07:18:25 PM PDT 24
Finished Jul 22 07:19:18 PM PDT 24
Peak memory 248800 kb
Host smart-2f2457f9-c585-49d6-966d-38d489a3f463
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4057867276 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_alert_accum_saturation.4057867276
Directory /workspace/18.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/18.alert_handler_entropy.1783987848
Short name T60
Test name
Test status
Simulation time 47480330812 ps
CPU time 2919.91 seconds
Started Jul 22 07:17:48 PM PDT 24
Finished Jul 22 08:07:22 PM PDT 24
Peak memory 288476 kb
Host smart-a350a9fb-aeab-402d-bf23-300224bb291c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1783987848 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy.1783987848
Directory /workspace/18.alert_handler_entropy/latest

Test location /workspace/coverage/default/18.alert_handler_entropy_stress.2412143279
Short name T587
Test name
Test status
Simulation time 5496203060 ps
CPU time 61.58 seconds
Started Jul 22 07:17:46 PM PDT 24
Finished Jul 22 07:19:43 PM PDT 24
Peak memory 248620 kb
Host smart-0fd28c8c-4678-4a8d-9de8-5e77dc29d306
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2412143279 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy_stress.2412143279
Directory /workspace/18.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/18.alert_handler_esc_alert_accum.3787939349
Short name T457
Test name
Test status
Simulation time 273300654 ps
CPU time 14.66 seconds
Started Jul 22 07:17:44 PM PDT 24
Finished Jul 22 07:18:54 PM PDT 24
Peak memory 256092 kb
Host smart-f52f2459-0fb6-4994-95ee-3cfadbb59990
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37879
39349 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_alert_accum.3787939349
Directory /workspace/18.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/18.alert_handler_esc_intr_timeout.210484055
Short name T488
Test name
Test status
Simulation time 1409363957 ps
CPU time 37.98 seconds
Started Jul 22 07:17:48 PM PDT 24
Finished Jul 22 07:19:20 PM PDT 24
Peak memory 248540 kb
Host smart-b50e3bac-c10e-485b-8be8-0f484c3da1e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21048
4055 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_intr_timeout.210484055
Directory /workspace/18.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_lpg_stub_clk.3951417529
Short name T213
Test name
Test status
Simulation time 119077595519 ps
CPU time 3454.71 seconds
Started Jul 22 07:17:47 PM PDT 24
Finished Jul 22 08:16:16 PM PDT 24
Peak memory 288692 kb
Host smart-7b18c82e-fe7a-4d75-abf8-4d522b85973d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951417529 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg_stub_clk.3951417529
Directory /workspace/18.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/18.alert_handler_random_alerts.1514598977
Short name T126
Test name
Test status
Simulation time 152787077 ps
CPU time 5.94 seconds
Started Jul 22 07:17:47 PM PDT 24
Finished Jul 22 07:18:47 PM PDT 24
Peak memory 248632 kb
Host smart-c510a065-d8b0-4363-9ee6-268ae52ca5be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15145
98977 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_alerts.1514598977
Directory /workspace/18.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/18.alert_handler_random_classes.1035874910
Short name T705
Test name
Test status
Simulation time 2424865476 ps
CPU time 38.03 seconds
Started Jul 22 07:17:46 PM PDT 24
Finished Jul 22 07:19:18 PM PDT 24
Peak memory 256308 kb
Host smart-a992170d-ab2c-4463-bbf0-072af9b3b30f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10358
74910 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_classes.1035874910
Directory /workspace/18.alert_handler_random_classes/latest

Test location /workspace/coverage/default/18.alert_handler_sig_int_fail.1238939963
Short name T279
Test name
Test status
Simulation time 2947859540 ps
CPU time 10.36 seconds
Started Jul 22 07:17:45 PM PDT 24
Finished Jul 22 07:18:50 PM PDT 24
Peak memory 248728 kb
Host smart-f3fec93c-34a5-4bef-83e5-5680cd8f55dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12389
39963 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_sig_int_fail.1238939963
Directory /workspace/18.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/18.alert_handler_smoke.1544470130
Short name T487
Test name
Test status
Simulation time 113580623 ps
CPU time 8.73 seconds
Started Jul 22 07:17:45 PM PDT 24
Finished Jul 22 07:18:49 PM PDT 24
Peak memory 252972 kb
Host smart-55f1e248-9ee9-46da-bcfe-7c9017b6785a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15444
70130 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_smoke.1544470130
Directory /workspace/18.alert_handler_smoke/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all.599161997
Short name T276
Test name
Test status
Simulation time 45823692289 ps
CPU time 1343.53 seconds
Started Jul 22 07:17:50 PM PDT 24
Finished Jul 22 07:41:07 PM PDT 24
Peak memory 265052 kb
Host smart-75f94ec2-22e0-42d7-a066-280f449ca200
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599161997 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_han
dler_stress_all.599161997
Directory /workspace/18.alert_handler_stress_all/latest

Test location /workspace/coverage/default/19.alert_handler_alert_accum_saturation.1414431357
Short name T220
Test name
Test status
Simulation time 551100981 ps
CPU time 3.78 seconds
Started Jul 22 07:18:07 PM PDT 24
Finished Jul 22 07:19:02 PM PDT 24
Peak memory 248944 kb
Host smart-64583b02-d32f-490f-9173-ed1f717ec4d9
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1414431357 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_alert_accum_saturation.1414431357
Directory /workspace/19.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/19.alert_handler_entropy.4134001390
Short name T479
Test name
Test status
Simulation time 19304341205 ps
CPU time 939.64 seconds
Started Jul 22 07:17:47 PM PDT 24
Finished Jul 22 07:34:21 PM PDT 24
Peak memory 272956 kb
Host smart-e2262956-55e5-4faf-a487-02b1299a3285
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134001390 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy.4134001390
Directory /workspace/19.alert_handler_entropy/latest

Test location /workspace/coverage/default/19.alert_handler_entropy_stress.417819800
Short name T203
Test name
Test status
Simulation time 689448913 ps
CPU time 9.55 seconds
Started Jul 22 07:18:05 PM PDT 24
Finished Jul 22 07:19:06 PM PDT 24
Peak memory 248676 kb
Host smart-72b23bd6-17dd-4dba-84f4-5901c1d81df9
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=417819800 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy_stress.417819800
Directory /workspace/19.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/19.alert_handler_esc_alert_accum.1157023126
Short name T395
Test name
Test status
Simulation time 8932565424 ps
CPU time 66.01 seconds
Started Jul 22 07:17:47 PM PDT 24
Finished Jul 22 07:19:47 PM PDT 24
Peak memory 256864 kb
Host smart-c5f5f03c-752c-4ea6-923c-ac5e99fb4128
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11570
23126 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_alert_accum.1157023126
Directory /workspace/19.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/19.alert_handler_esc_intr_timeout.2438249563
Short name T678
Test name
Test status
Simulation time 317530916 ps
CPU time 5.66 seconds
Started Jul 22 07:17:48 PM PDT 24
Finished Jul 22 07:18:48 PM PDT 24
Peak memory 252152 kb
Host smart-13ffdcf9-ae72-4d16-8316-5bcb94dc45a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24382
49563 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_intr_timeout.2438249563
Directory /workspace/19.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_lpg.998811052
Short name T350
Test name
Test status
Simulation time 10480553759 ps
CPU time 856.55 seconds
Started Jul 22 07:18:03 PM PDT 24
Finished Jul 22 07:33:11 PM PDT 24
Peak memory 273300 kb
Host smart-60cb78d2-6d25-4d67-a501-0503d87bb15c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998811052 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg.998811052
Directory /workspace/19.alert_handler_lpg/latest

Test location /workspace/coverage/default/19.alert_handler_lpg_stub_clk.2692916397
Short name T456
Test name
Test status
Simulation time 10637095096 ps
CPU time 550.52 seconds
Started Jul 22 07:18:06 PM PDT 24
Finished Jul 22 07:28:08 PM PDT 24
Peak memory 272496 kb
Host smart-6f053f33-aa21-44fd-962d-eede85756550
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692916397 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg_stub_clk.2692916397
Directory /workspace/19.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/19.alert_handler_ping_timeout.3565552195
Short name T317
Test name
Test status
Simulation time 15241608245 ps
CPU time 312.9 seconds
Started Jul 22 07:18:07 PM PDT 24
Finished Jul 22 07:24:11 PM PDT 24
Peak memory 248688 kb
Host smart-962b495a-4647-4dbd-a774-d60950844816
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565552195 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_ping_timeout.3565552195
Directory /workspace/19.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_random_alerts.3816654955
Short name T44
Test name
Test status
Simulation time 3520327242 ps
CPU time 44.22 seconds
Started Jul 22 07:17:47 PM PDT 24
Finished Jul 22 07:19:26 PM PDT 24
Peak memory 256872 kb
Host smart-ab895193-7ef4-4838-861d-2cbcd575332e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38166
54955 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_alerts.3816654955
Directory /workspace/19.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/19.alert_handler_random_classes.551749680
Short name T475
Test name
Test status
Simulation time 1869543670 ps
CPU time 49.62 seconds
Started Jul 22 07:17:47 PM PDT 24
Finished Jul 22 07:19:31 PM PDT 24
Peak memory 248980 kb
Host smart-9125c6db-d6de-4d53-96d7-4ad706184bf7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55174
9680 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_classes.551749680
Directory /workspace/19.alert_handler_random_classes/latest

Test location /workspace/coverage/default/19.alert_handler_sig_int_fail.2872164331
Short name T294
Test name
Test status
Simulation time 178132054 ps
CPU time 17.06 seconds
Started Jul 22 07:17:47 PM PDT 24
Finished Jul 22 07:18:59 PM PDT 24
Peak memory 248008 kb
Host smart-c523fc6f-f496-4656-a76a-a5622163b88b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28721
64331 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_sig_int_fail.2872164331
Directory /workspace/19.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/19.alert_handler_smoke.2848071617
Short name T455
Test name
Test status
Simulation time 2915448184 ps
CPU time 48.82 seconds
Started Jul 22 07:17:44 PM PDT 24
Finished Jul 22 07:19:28 PM PDT 24
Peak memory 248644 kb
Host smart-875f43ad-97bd-4b24-a31d-d2af07c3ab8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28480
71617 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_smoke.2848071617
Directory /workspace/19.alert_handler_smoke/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all.2905302533
Short name T634
Test name
Test status
Simulation time 6657897829 ps
CPU time 422.48 seconds
Started Jul 22 07:18:03 PM PDT 24
Finished Jul 22 07:25:57 PM PDT 24
Peak memory 256872 kb
Host smart-bb33a195-7500-4c88-8f09-98e4e2fcf910
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905302533 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_ha
ndler_stress_all.2905302533
Directory /workspace/19.alert_handler_stress_all/latest

Test location /workspace/coverage/default/2.alert_handler_alert_accum_saturation.1083811948
Short name T221
Test name
Test status
Simulation time 63606365 ps
CPU time 3.34 seconds
Started Jul 22 07:16:40 PM PDT 24
Finished Jul 22 07:17:49 PM PDT 24
Peak memory 248972 kb
Host smart-e3335b39-53a1-411e-b971-8b4ead585ce9
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1083811948 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_alert_accum_saturation.1083811948
Directory /workspace/2.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/2.alert_handler_entropy.2854554229
Short name T116
Test name
Test status
Simulation time 41802794695 ps
CPU time 869.58 seconds
Started Jul 22 07:16:38 PM PDT 24
Finished Jul 22 07:32:12 PM PDT 24
Peak memory 273040 kb
Host smart-48caab4b-b4c7-419a-a97a-de2d887542af
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854554229 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy.2854554229
Directory /workspace/2.alert_handler_entropy/latest

Test location /workspace/coverage/default/2.alert_handler_entropy_stress.3208756656
Short name T493
Test name
Test status
Simulation time 1601225541 ps
CPU time 31.89 seconds
Started Jul 22 07:16:41 PM PDT 24
Finished Jul 22 07:18:18 PM PDT 24
Peak memory 248524 kb
Host smart-fdd85e3f-3ada-4a7d-9024-d31faa857b9d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3208756656 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy_stress.3208756656
Directory /workspace/2.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/2.alert_handler_esc_alert_accum.2502523744
Short name T657
Test name
Test status
Simulation time 662248644 ps
CPU time 54.73 seconds
Started Jul 22 07:16:54 PM PDT 24
Finished Jul 22 07:18:53 PM PDT 24
Peak memory 256340 kb
Host smart-22370d8c-4d88-4cbd-a00a-eab1892e6ee3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25025
23744 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_alert_accum.2502523744
Directory /workspace/2.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/2.alert_handler_esc_intr_timeout.67228188
Short name T667
Test name
Test status
Simulation time 612921456 ps
CPU time 37.45 seconds
Started Jul 22 07:16:55 PM PDT 24
Finished Jul 22 07:18:36 PM PDT 24
Peak memory 249012 kb
Host smart-08b82b1b-f0d5-4a79-9030-9fc2a7f7db69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67228
188 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_intr_timeout.67228188
Directory /workspace/2.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_lpg_stub_clk.2572159042
Short name T289
Test name
Test status
Simulation time 58310223748 ps
CPU time 651.47 seconds
Started Jul 22 07:16:39 PM PDT 24
Finished Jul 22 07:28:36 PM PDT 24
Peak memory 272084 kb
Host smart-8b32038d-df4f-4b52-bc02-7a07a8492e29
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572159042 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg_stub_clk.2572159042
Directory /workspace/2.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/2.alert_handler_ping_timeout.3826293929
Short name T615
Test name
Test status
Simulation time 28260888161 ps
CPU time 280.33 seconds
Started Jul 22 07:16:55 PM PDT 24
Finished Jul 22 07:22:39 PM PDT 24
Peak memory 248492 kb
Host smart-8b236556-9bb0-4c83-aa01-9d2b482bc711
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826293929 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_ping_timeout.3826293929
Directory /workspace/2.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_random_alerts.845355490
Short name T638
Test name
Test status
Simulation time 146911989 ps
CPU time 16.04 seconds
Started Jul 22 07:16:38 PM PDT 24
Finished Jul 22 07:17:57 PM PDT 24
Peak memory 248544 kb
Host smart-a4aeeb2f-777c-4aab-8ffc-05b17231448a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84535
5490 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_alerts.845355490
Directory /workspace/2.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/2.alert_handler_random_classes.669102675
Short name T396
Test name
Test status
Simulation time 153571767 ps
CPU time 7.67 seconds
Started Jul 22 07:16:48 PM PDT 24
Finished Jul 22 07:18:02 PM PDT 24
Peak memory 247876 kb
Host smart-99b64a97-8594-4f6c-a7d0-179fb0820579
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66910
2675 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_classes.669102675
Directory /workspace/2.alert_handler_random_classes/latest

Test location /workspace/coverage/default/2.alert_handler_sec_cm.3930753374
Short name T35
Test name
Test status
Simulation time 1770184677 ps
CPU time 23.36 seconds
Started Jul 22 07:16:40 PM PDT 24
Finished Jul 22 07:18:09 PM PDT 24
Peak memory 273888 kb
Host smart-ec45b284-5c49-4c2b-82f6-95a551371f03
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3930753374 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sec_cm.3930753374
Directory /workspace/2.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/2.alert_handler_sig_int_fail.462379501
Short name T471
Test name
Test status
Simulation time 111951101 ps
CPU time 5.11 seconds
Started Jul 22 07:16:37 PM PDT 24
Finished Jul 22 07:17:47 PM PDT 24
Peak memory 251408 kb
Host smart-9706abda-dacb-4592-99ed-aedf11a07a3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46237
9501 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sig_int_fail.462379501
Directory /workspace/2.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/2.alert_handler_smoke.3165813790
Short name T557
Test name
Test status
Simulation time 3104597592 ps
CPU time 39.77 seconds
Started Jul 22 07:16:54 PM PDT 24
Finished Jul 22 07:18:38 PM PDT 24
Peak memory 256096 kb
Host smart-41bf84d1-f1fe-4d8d-b89c-3196a7584832
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31658
13790 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_smoke.3165813790
Directory /workspace/2.alert_handler_smoke/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all.2553346484
Short name T102
Test name
Test status
Simulation time 5512932501 ps
CPU time 123.26 seconds
Started Jul 22 07:16:37 PM PDT 24
Finished Jul 22 07:19:45 PM PDT 24
Peak memory 256956 kb
Host smart-bfe47284-4a90-4433-b2e2-0525f7ea3807
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553346484 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_han
dler_stress_all.2553346484
Directory /workspace/2.alert_handler_stress_all/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all_with_rand_reset.2835092165
Short name T683
Test name
Test status
Simulation time 349398602391 ps
CPU time 4018.12 seconds
Started Jul 22 07:16:38 PM PDT 24
Finished Jul 22 08:24:41 PM PDT 24
Peak memory 322196 kb
Host smart-87caaf02-1934-418d-81b0-b7c65ee16b81
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835092165 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.alert_handler_stress_all_with_rand_reset.2835092165
Directory /workspace/2.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.alert_handler_entropy.1116297591
Short name T16
Test name
Test status
Simulation time 101550998232 ps
CPU time 2853.53 seconds
Started Jul 22 07:18:06 PM PDT 24
Finished Jul 22 08:06:31 PM PDT 24
Peak memory 288848 kb
Host smart-60bd6863-0735-4086-afc0-330a4acc673b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116297591 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_entropy.1116297591
Directory /workspace/20.alert_handler_entropy/latest

Test location /workspace/coverage/default/20.alert_handler_esc_alert_accum.2548489038
Short name T431
Test name
Test status
Simulation time 11757875774 ps
CPU time 124.47 seconds
Started Jul 22 07:18:07 PM PDT 24
Finished Jul 22 07:21:02 PM PDT 24
Peak memory 256836 kb
Host smart-a288dfd0-605b-4d26-9789-04448e7b8ad8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25484
89038 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_alert_accum.2548489038
Directory /workspace/20.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/20.alert_handler_esc_intr_timeout.186069109
Short name T494
Test name
Test status
Simulation time 1519424393 ps
CPU time 23.46 seconds
Started Jul 22 07:19:26 PM PDT 24
Finished Jul 22 07:20:17 PM PDT 24
Peak memory 255432 kb
Host smart-4de459aa-c10c-4749-b3dd-31fb9a9acc75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18606
9109 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_intr_timeout.186069109
Directory /workspace/20.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_lpg.3913471280
Short name T200
Test name
Test status
Simulation time 97163587930 ps
CPU time 1284.56 seconds
Started Jul 22 07:18:04 PM PDT 24
Finished Jul 22 07:40:20 PM PDT 24
Peak memory 272372 kb
Host smart-86b0c044-126a-4af3-b4d1-0661d56bcd40
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913471280 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg.3913471280
Directory /workspace/20.alert_handler_lpg/latest

Test location /workspace/coverage/default/20.alert_handler_lpg_stub_clk.3715504665
Short name T564
Test name
Test status
Simulation time 33627940595 ps
CPU time 1202.98 seconds
Started Jul 22 07:18:03 PM PDT 24
Finished Jul 22 07:38:58 PM PDT 24
Peak memory 285888 kb
Host smart-1c6b2b08-9001-43da-9133-1bb658e22a7a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715504665 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg_stub_clk.3715504665
Directory /workspace/20.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/20.alert_handler_ping_timeout.1955081764
Short name T333
Test name
Test status
Simulation time 9637388099 ps
CPU time 105.44 seconds
Started Jul 22 07:18:57 PM PDT 24
Finished Jul 22 07:21:26 PM PDT 24
Peak memory 248656 kb
Host smart-1f0579da-bc38-49ac-8e4c-a12d88940105
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955081764 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_ping_timeout.1955081764
Directory /workspace/20.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_random_alerts.941627202
Short name T534
Test name
Test status
Simulation time 292511451 ps
CPU time 18.12 seconds
Started Jul 22 07:18:07 PM PDT 24
Finished Jul 22 07:19:16 PM PDT 24
Peak memory 248588 kb
Host smart-ff80b319-856f-40e1-9416-5604094ca94d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94162
7202 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_alerts.941627202
Directory /workspace/20.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/20.alert_handler_random_classes.2499934693
Short name T449
Test name
Test status
Simulation time 373576575 ps
CPU time 8.36 seconds
Started Jul 22 07:18:05 PM PDT 24
Finished Jul 22 07:19:05 PM PDT 24
Peak memory 248964 kb
Host smart-afc5b1c5-f32e-4ddc-b49f-4fe29b385203
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24999
34693 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_classes.2499934693
Directory /workspace/20.alert_handler_random_classes/latest

Test location /workspace/coverage/default/20.alert_handler_sig_int_fail.4023201979
Short name T555
Test name
Test status
Simulation time 62407536 ps
CPU time 4.49 seconds
Started Jul 22 07:18:03 PM PDT 24
Finished Jul 22 07:18:59 PM PDT 24
Peak memory 240360 kb
Host smart-d108a25a-9897-4ecb-a0db-f3b6d95ca45f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40232
01979 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_sig_int_fail.4023201979
Directory /workspace/20.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/20.alert_handler_smoke.190382775
Short name T655
Test name
Test status
Simulation time 2918860975 ps
CPU time 38.78 seconds
Started Jul 22 07:18:02 PM PDT 24
Finished Jul 22 07:19:33 PM PDT 24
Peak memory 256832 kb
Host smart-9f417c95-2bb3-4c85-bc34-62126796083e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19038
2775 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_smoke.190382775
Directory /workspace/20.alert_handler_smoke/latest

Test location /workspace/coverage/default/21.alert_handler_entropy.1153623572
Short name T607
Test name
Test status
Simulation time 20914267491 ps
CPU time 1419.61 seconds
Started Jul 22 07:18:05 PM PDT 24
Finished Jul 22 07:42:36 PM PDT 24
Peak memory 267188 kb
Host smart-bd67f392-0ada-4d6b-b4d2-fcd4f10bf7db
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1153623572 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_entropy.1153623572
Directory /workspace/21.alert_handler_entropy/latest

Test location /workspace/coverage/default/21.alert_handler_esc_alert_accum.818433438
Short name T2
Test name
Test status
Simulation time 7445977483 ps
CPU time 200.09 seconds
Started Jul 22 07:18:06 PM PDT 24
Finished Jul 22 07:22:17 PM PDT 24
Peak memory 256120 kb
Host smart-0d9dd030-81e7-4319-851c-9b39f88b3209
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81843
3438 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_alert_accum.818433438
Directory /workspace/21.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/21.alert_handler_esc_intr_timeout.515231920
Short name T92
Test name
Test status
Simulation time 2231079660 ps
CPU time 34.63 seconds
Started Jul 22 07:18:06 PM PDT 24
Finished Jul 22 07:19:32 PM PDT 24
Peak memory 248632 kb
Host smart-20de766f-afe7-41d4-a5cd-570d7db2c702
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51523
1920 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_intr_timeout.515231920
Directory /workspace/21.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_lpg.77510972
Short name T298
Test name
Test status
Simulation time 386957965202 ps
CPU time 2729.37 seconds
Started Jul 22 07:18:07 PM PDT 24
Finished Jul 22 08:04:27 PM PDT 24
Peak memory 289572 kb
Host smart-e7270ac4-7772-48d5-8dc9-4faf90fbfb35
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77510972 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg.77510972
Directory /workspace/21.alert_handler_lpg/latest

Test location /workspace/coverage/default/21.alert_handler_lpg_stub_clk.4002411279
Short name T380
Test name
Test status
Simulation time 35956188550 ps
CPU time 614.15 seconds
Started Jul 22 07:18:05 PM PDT 24
Finished Jul 22 07:29:11 PM PDT 24
Peak memory 272572 kb
Host smart-8fcc5519-5aec-4b74-82aa-df7e5753ab48
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4002411279 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg_stub_clk.4002411279
Directory /workspace/21.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/21.alert_handler_ping_timeout.1131236044
Short name T338
Test name
Test status
Simulation time 27319771738 ps
CPU time 262.19 seconds
Started Jul 22 07:18:10 PM PDT 24
Finished Jul 22 07:23:23 PM PDT 24
Peak memory 248656 kb
Host smart-8358b389-55b3-459d-a3a4-566ab4741f2b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1131236044 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_ping_timeout.1131236044
Directory /workspace/21.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_random_alerts.600455787
Short name T249
Test name
Test status
Simulation time 1367998993 ps
CPU time 70.81 seconds
Started Jul 22 07:18:05 PM PDT 24
Finished Jul 22 07:20:07 PM PDT 24
Peak memory 256000 kb
Host smart-244ef89e-3069-4f35-8689-d8b9cb306399
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60045
5787 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_alerts.600455787
Directory /workspace/21.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/21.alert_handler_random_classes.3555487213
Short name T515
Test name
Test status
Simulation time 1164953373 ps
CPU time 61.02 seconds
Started Jul 22 07:18:10 PM PDT 24
Finished Jul 22 07:20:02 PM PDT 24
Peak memory 256164 kb
Host smart-3110d656-4456-4fb7-8ea6-c982efa5f99c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35554
87213 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_classes.3555487213
Directory /workspace/21.alert_handler_random_classes/latest

Test location /workspace/coverage/default/21.alert_handler_sig_int_fail.285876804
Short name T199
Test name
Test status
Simulation time 792553904 ps
CPU time 26.53 seconds
Started Jul 22 07:18:08 PM PDT 24
Finished Jul 22 07:19:25 PM PDT 24
Peak memory 256280 kb
Host smart-ffecc16b-e4ff-4083-a437-24149c264b1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28587
6804 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_sig_int_fail.285876804
Directory /workspace/21.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/21.alert_handler_smoke.655220965
Short name T451
Test name
Test status
Simulation time 283026060 ps
CPU time 8.1 seconds
Started Jul 22 07:18:57 PM PDT 24
Finished Jul 22 07:19:48 PM PDT 24
Peak memory 253460 kb
Host smart-a3192cc6-6059-4249-b44f-7ae54227fd87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65522
0965 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_smoke.655220965
Directory /workspace/21.alert_handler_smoke/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all.208764844
Short name T684
Test name
Test status
Simulation time 49204033463 ps
CPU time 2632.16 seconds
Started Jul 22 07:19:25 PM PDT 24
Finished Jul 22 08:03:46 PM PDT 24
Peak memory 289220 kb
Host smart-4868e3ce-c7b5-4851-8990-6b8913bcb913
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208764844 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_han
dler_stress_all.208764844
Directory /workspace/21.alert_handler_stress_all/latest

Test location /workspace/coverage/default/22.alert_handler_entropy.3160511595
Short name T506
Test name
Test status
Simulation time 93274352195 ps
CPU time 2776.83 seconds
Started Jul 22 07:19:03 PM PDT 24
Finished Jul 22 08:06:02 PM PDT 24
Peak memory 281388 kb
Host smart-9a694783-9cb9-4145-ab16-b860e778ece3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160511595 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_entropy.3160511595
Directory /workspace/22.alert_handler_entropy/latest

Test location /workspace/coverage/default/22.alert_handler_esc_alert_accum.1423620490
Short name T254
Test name
Test status
Simulation time 1580046269 ps
CPU time 81.06 seconds
Started Jul 22 07:18:05 PM PDT 24
Finished Jul 22 07:20:18 PM PDT 24
Peak memory 256372 kb
Host smart-71636480-eb17-498b-9709-8703b88a79b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14236
20490 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_alert_accum.1423620490
Directory /workspace/22.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/22.alert_handler_esc_intr_timeout.4179874671
Short name T482
Test name
Test status
Simulation time 227984423 ps
CPU time 13.57 seconds
Started Jul 22 07:18:07 PM PDT 24
Finished Jul 22 07:19:11 PM PDT 24
Peak memory 255332 kb
Host smart-ff1dd70e-6e6e-4371-ac12-a91de8ee921f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41798
74671 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_intr_timeout.4179874671
Directory /workspace/22.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_lpg_stub_clk.1540375580
Short name T4
Test name
Test status
Simulation time 78946037929 ps
CPU time 2370.26 seconds
Started Jul 22 07:18:09 PM PDT 24
Finished Jul 22 07:58:30 PM PDT 24
Peak memory 284816 kb
Host smart-3ddde672-6e7d-46e1-9de7-5fa178d7cd2c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540375580 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg_stub_clk.1540375580
Directory /workspace/22.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/22.alert_handler_ping_timeout.2403466894
Short name T312
Test name
Test status
Simulation time 19868261505 ps
CPU time 201.22 seconds
Started Jul 22 07:18:05 PM PDT 24
Finished Jul 22 07:22:18 PM PDT 24
Peak memory 254784 kb
Host smart-67de14e9-73d2-4970-9e1c-5915943e92b3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403466894 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_ping_timeout.2403466894
Directory /workspace/22.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_random_alerts.1704548430
Short name T417
Test name
Test status
Simulation time 886962213 ps
CPU time 50.65 seconds
Started Jul 22 07:18:07 PM PDT 24
Finished Jul 22 07:19:48 PM PDT 24
Peak memory 255700 kb
Host smart-914233b0-cf74-4d64-9672-ba72746087b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17045
48430 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_alerts.1704548430
Directory /workspace/22.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/22.alert_handler_random_classes.2462699270
Short name T377
Test name
Test status
Simulation time 514875662 ps
CPU time 32.57 seconds
Started Jul 22 07:18:06 PM PDT 24
Finished Jul 22 07:19:30 PM PDT 24
Peak memory 255112 kb
Host smart-2f0abf9d-3b45-4ed5-9594-77c98741d778
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24626
99270 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_classes.2462699270
Directory /workspace/22.alert_handler_random_classes/latest

Test location /workspace/coverage/default/22.alert_handler_sig_int_fail.4147965412
Short name T719
Test name
Test status
Simulation time 58782841 ps
CPU time 7.25 seconds
Started Jul 22 07:18:04 PM PDT 24
Finished Jul 22 07:19:03 PM PDT 24
Peak memory 253824 kb
Host smart-235edab3-17e5-40ed-93b3-d77b293e7fa1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41479
65412 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_sig_int_fail.4147965412
Directory /workspace/22.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/22.alert_handler_smoke.971149455
Short name T601
Test name
Test status
Simulation time 2686843344 ps
CPU time 40.67 seconds
Started Jul 22 07:18:31 PM PDT 24
Finished Jul 22 07:20:01 PM PDT 24
Peak memory 256756 kb
Host smart-0f68d6ab-fe3d-4785-a7c1-d7e5746f4680
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97114
9455 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_smoke.971149455
Directory /workspace/22.alert_handler_smoke/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all.2691467780
Short name T305
Test name
Test status
Simulation time 172871115537 ps
CPU time 2849.19 seconds
Started Jul 22 07:18:04 PM PDT 24
Finished Jul 22 08:06:25 PM PDT 24
Peak memory 299292 kb
Host smart-0996d1dd-ed5b-4ab9-91d6-61470757caed
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691467780 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_ha
ndler_stress_all.2691467780
Directory /workspace/22.alert_handler_stress_all/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all_with_rand_reset.4162574527
Short name T295
Test name
Test status
Simulation time 213863358438 ps
CPU time 4810.6 seconds
Started Jul 22 07:18:10 PM PDT 24
Finished Jul 22 08:39:12 PM PDT 24
Peak memory 305992 kb
Host smart-cbde81f6-f6ee-4fcf-9a7b-244c1fbc46ec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162574527 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 22.alert_handler_stress_all_with_rand_reset.4162574527
Directory /workspace/22.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.alert_handler_entropy.2315452637
Short name T676
Test name
Test status
Simulation time 9672833124 ps
CPU time 765.08 seconds
Started Jul 22 07:18:23 PM PDT 24
Finished Jul 22 07:31:59 PM PDT 24
Peak memory 272720 kb
Host smart-0b225c66-2d6b-4ff0-98c6-1279d4e070a9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315452637 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_entropy.2315452637
Directory /workspace/23.alert_handler_entropy/latest

Test location /workspace/coverage/default/23.alert_handler_esc_alert_accum.3125341535
Short name T620
Test name
Test status
Simulation time 5208558417 ps
CPU time 270.89 seconds
Started Jul 22 07:18:06 PM PDT 24
Finished Jul 22 07:23:28 PM PDT 24
Peak memory 256952 kb
Host smart-fda417eb-9ce1-4412-b3ed-294ea056fe88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31253
41535 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_alert_accum.3125341535
Directory /workspace/23.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/23.alert_handler_esc_intr_timeout.3040966366
Short name T264
Test name
Test status
Simulation time 737776579 ps
CPU time 38.6 seconds
Started Jul 22 07:18:05 PM PDT 24
Finished Jul 22 07:19:35 PM PDT 24
Peak memory 256776 kb
Host smart-8f9b412f-96f1-4f61-b099-6c3490be7941
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30409
66366 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_intr_timeout.3040966366
Directory /workspace/23.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_lpg.4046934700
Short name T344
Test name
Test status
Simulation time 52498273854 ps
CPU time 988.88 seconds
Started Jul 22 07:19:03 PM PDT 24
Finished Jul 22 07:36:13 PM PDT 24
Peak memory 281740 kb
Host smart-66a606ff-6bcc-43c9-b42a-6fe1ee60e152
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046934700 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg.4046934700
Directory /workspace/23.alert_handler_lpg/latest

Test location /workspace/coverage/default/23.alert_handler_lpg_stub_clk.3398799474
Short name T496
Test name
Test status
Simulation time 132960281043 ps
CPU time 1786.65 seconds
Started Jul 22 07:18:09 PM PDT 24
Finished Jul 22 07:48:46 PM PDT 24
Peak memory 272876 kb
Host smart-519b8044-da35-4a2f-8fee-2b1b1060af41
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3398799474 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg_stub_clk.3398799474
Directory /workspace/23.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/23.alert_handler_ping_timeout.831913386
Short name T668
Test name
Test status
Simulation time 28825525908 ps
CPU time 558.39 seconds
Started Jul 22 07:18:06 PM PDT 24
Finished Jul 22 07:28:16 PM PDT 24
Peak memory 248616 kb
Host smart-1cbacc75-3773-41e1-a56e-bbf8cc17902b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=831913386 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_ping_timeout.831913386
Directory /workspace/23.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_random_alerts.1083806163
Short name T586
Test name
Test status
Simulation time 76356281 ps
CPU time 3.88 seconds
Started Jul 22 07:18:09 PM PDT 24
Finished Jul 22 07:19:04 PM PDT 24
Peak memory 248584 kb
Host smart-30f82c69-b193-4dac-ae71-374b59e22387
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10838
06163 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_alerts.1083806163
Directory /workspace/23.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/23.alert_handler_random_classes.4138381706
Short name T570
Test name
Test status
Simulation time 1446632021 ps
CPU time 40.37 seconds
Started Jul 22 07:18:10 PM PDT 24
Finished Jul 22 07:19:41 PM PDT 24
Peak memory 249660 kb
Host smart-6c376e4e-9ce5-483d-ad2c-c8afd1072ca7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41383
81706 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_classes.4138381706
Directory /workspace/23.alert_handler_random_classes/latest

Test location /workspace/coverage/default/23.alert_handler_sig_int_fail.1816623612
Short name T77
Test name
Test status
Simulation time 252287316 ps
CPU time 27.51 seconds
Started Jul 22 07:18:05 PM PDT 24
Finished Jul 22 07:19:24 PM PDT 24
Peak memory 248540 kb
Host smart-1f986ae8-18eb-462d-af0b-90c9294369a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18166
23612 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_sig_int_fail.1816623612
Directory /workspace/23.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/23.alert_handler_smoke.1950329259
Short name T581
Test name
Test status
Simulation time 80983545 ps
CPU time 4.8 seconds
Started Jul 22 07:18:31 PM PDT 24
Finished Jul 22 07:19:26 PM PDT 24
Peak memory 250528 kb
Host smart-97bb086a-4970-43cf-b3a0-b0b58910da72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19503
29259 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_smoke.1950329259
Directory /workspace/23.alert_handler_smoke/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all.1890430360
Short name T86
Test name
Test status
Simulation time 73738204653 ps
CPU time 1415.7 seconds
Started Jul 22 07:18:05 PM PDT 24
Finished Jul 22 07:42:33 PM PDT 24
Peak memory 289360 kb
Host smart-b88e6270-1b28-4600-a40c-27fa1577ea59
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890430360 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_ha
ndler_stress_all.1890430360
Directory /workspace/23.alert_handler_stress_all/latest

Test location /workspace/coverage/default/24.alert_handler_entropy.1933421003
Short name T690
Test name
Test status
Simulation time 6627486570 ps
CPU time 665.16 seconds
Started Jul 22 07:18:26 PM PDT 24
Finished Jul 22 07:30:21 PM PDT 24
Peak memory 272736 kb
Host smart-3f6de42f-accf-40e6-af5a-a6b706be0f2e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933421003 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_entropy.1933421003
Directory /workspace/24.alert_handler_entropy/latest

Test location /workspace/coverage/default/24.alert_handler_esc_alert_accum.3205138395
Short name T675
Test name
Test status
Simulation time 15195375537 ps
CPU time 201.59 seconds
Started Jul 22 07:18:40 PM PDT 24
Finished Jul 22 07:22:49 PM PDT 24
Peak memory 250804 kb
Host smart-c9acb5de-4881-4fb5-b388-39554bd5d264
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32051
38395 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_alert_accum.3205138395
Directory /workspace/24.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/24.alert_handler_esc_intr_timeout.1891829087
Short name T420
Test name
Test status
Simulation time 1378240234 ps
CPU time 25.6 seconds
Started Jul 22 07:19:39 PM PDT 24
Finished Jul 22 07:20:23 PM PDT 24
Peak memory 256808 kb
Host smart-2bd42f06-e38c-4417-b879-29e09bfe1d7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18918
29087 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_intr_timeout.1891829087
Directory /workspace/24.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_lpg_stub_clk.2434792541
Short name T693
Test name
Test status
Simulation time 181608274766 ps
CPU time 1878.61 seconds
Started Jul 22 07:18:20 PM PDT 24
Finished Jul 22 07:50:30 PM PDT 24
Peak memory 272600 kb
Host smart-72f1bade-4bdb-4bb8-81ff-7ddc5ac312b4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434792541 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg_stub_clk.2434792541
Directory /workspace/24.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/24.alert_handler_random_alerts.533592399
Short name T483
Test name
Test status
Simulation time 381081212 ps
CPU time 29.88 seconds
Started Jul 22 07:18:26 PM PDT 24
Finished Jul 22 07:19:47 PM PDT 24
Peak memory 248548 kb
Host smart-6e72f5e1-dfa8-4f02-9414-9dffe6f13740
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53359
2399 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_alerts.533592399
Directory /workspace/24.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/24.alert_handler_random_classes.270777704
Short name T303
Test name
Test status
Simulation time 711290785 ps
CPU time 15.38 seconds
Started Jul 22 07:18:23 PM PDT 24
Finished Jul 22 07:19:29 PM PDT 24
Peak memory 248060 kb
Host smart-7aa60299-464a-4bfe-834a-24a86340076d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27077
7704 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_classes.270777704
Directory /workspace/24.alert_handler_random_classes/latest

Test location /workspace/coverage/default/24.alert_handler_sig_int_fail.2867679515
Short name T466
Test name
Test status
Simulation time 2565510955 ps
CPU time 29.9 seconds
Started Jul 22 07:18:19 PM PDT 24
Finished Jul 22 07:19:40 PM PDT 24
Peak memory 248360 kb
Host smart-c5b23957-bb65-42b5-8bdb-314118fff656
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28676
79515 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_sig_int_fail.2867679515
Directory /workspace/24.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/24.alert_handler_smoke.2880024962
Short name T476
Test name
Test status
Simulation time 38757132 ps
CPU time 4.92 seconds
Started Jul 22 07:18:24 PM PDT 24
Finished Jul 22 07:19:20 PM PDT 24
Peak memory 251732 kb
Host smart-3271d2ea-1b7d-4f9d-911c-9ded6b19b419
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28800
24962 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_smoke.2880024962
Directory /workspace/24.alert_handler_smoke/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all.2296854579
Short name T63
Test name
Test status
Simulation time 377741164999 ps
CPU time 3143.55 seconds
Started Jul 22 07:18:21 PM PDT 24
Finished Jul 22 08:11:37 PM PDT 24
Peak memory 288952 kb
Host smart-0127547e-17c0-4b42-9306-238e9147a011
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296854579 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_ha
ndler_stress_all.2296854579
Directory /workspace/24.alert_handler_stress_all/latest

Test location /workspace/coverage/default/25.alert_handler_entropy.1090220105
Short name T635
Test name
Test status
Simulation time 46653409514 ps
CPU time 2700.79 seconds
Started Jul 22 07:19:39 PM PDT 24
Finished Jul 22 08:04:58 PM PDT 24
Peak memory 288640 kb
Host smart-f6c3eec1-0c5a-4d64-aa63-e2e64a59ba49
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090220105 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_entropy.1090220105
Directory /workspace/25.alert_handler_entropy/latest

Test location /workspace/coverage/default/25.alert_handler_esc_alert_accum.33165333
Short name T599
Test name
Test status
Simulation time 5557203350 ps
CPU time 78.67 seconds
Started Jul 22 07:18:28 PM PDT 24
Finished Jul 22 07:20:36 PM PDT 24
Peak memory 256868 kb
Host smart-c42c53fc-6654-429b-b1cc-b8d237da6d92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33165
333 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_alert_accum.33165333
Directory /workspace/25.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/25.alert_handler_esc_intr_timeout.2048363183
Short name T37
Test name
Test status
Simulation time 1703635807 ps
CPU time 54.87 seconds
Started Jul 22 07:18:26 PM PDT 24
Finished Jul 22 07:20:11 PM PDT 24
Peak memory 256352 kb
Host smart-c0f5b0fc-8a1f-4f9c-b2c1-4880d2aa9cc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20483
63183 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_intr_timeout.2048363183
Directory /workspace/25.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_lpg.3531193144
Short name T343
Test name
Test status
Simulation time 34987588787 ps
CPU time 1908.53 seconds
Started Jul 22 07:18:24 PM PDT 24
Finished Jul 22 07:51:03 PM PDT 24
Peak memory 272532 kb
Host smart-962e452d-2daa-4f73-83cb-0908f51d1a25
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531193144 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg.3531193144
Directory /workspace/25.alert_handler_lpg/latest

Test location /workspace/coverage/default/25.alert_handler_lpg_stub_clk.728802571
Short name T283
Test name
Test status
Simulation time 36781225217 ps
CPU time 1654.68 seconds
Started Jul 22 07:18:20 PM PDT 24
Finished Jul 22 07:46:47 PM PDT 24
Peak memory 289632 kb
Host smart-a709c30f-4bde-434a-8384-d91d317d4dc9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728802571 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg_stub_clk.728802571
Directory /workspace/25.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/25.alert_handler_ping_timeout.3897592455
Short name T335
Test name
Test status
Simulation time 5834038553 ps
CPU time 226.4 seconds
Started Jul 22 07:18:18 PM PDT 24
Finished Jul 22 07:22:57 PM PDT 24
Peak memory 247456 kb
Host smart-d32dba25-2765-4345-b2b7-70aa380a77e4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3897592455 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_ping_timeout.3897592455
Directory /workspace/25.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_random_alerts.3221437238
Short name T405
Test name
Test status
Simulation time 467684672 ps
CPU time 23.29 seconds
Started Jul 22 07:18:28 PM PDT 24
Finished Jul 22 07:19:41 PM PDT 24
Peak memory 248552 kb
Host smart-58571b4f-c039-407f-8471-45e8fc998cbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32214
37238 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_alerts.3221437238
Directory /workspace/25.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/25.alert_handler_random_classes.2308636661
Short name T704
Test name
Test status
Simulation time 2687181320 ps
CPU time 40.08 seconds
Started Jul 22 07:19:39 PM PDT 24
Finished Jul 22 07:20:37 PM PDT 24
Peak memory 248284 kb
Host smart-17760988-5c0a-467a-8bfe-2644af0e137a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23086
36661 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_classes.2308636661
Directory /workspace/25.alert_handler_random_classes/latest

Test location /workspace/coverage/default/25.alert_handler_sig_int_fail.3948843856
Short name T109
Test name
Test status
Simulation time 1966564529 ps
CPU time 32.87 seconds
Started Jul 22 07:19:07 PM PDT 24
Finished Jul 22 07:20:19 PM PDT 24
Peak memory 248604 kb
Host smart-5bfe5b21-7077-4ccb-b0d4-b44e086b36da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39488
43856 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_sig_int_fail.3948843856
Directory /workspace/25.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/25.alert_handler_smoke.1528104263
Short name T384
Test name
Test status
Simulation time 671474494 ps
CPU time 41.33 seconds
Started Jul 22 07:18:27 PM PDT 24
Finished Jul 22 07:19:59 PM PDT 24
Peak memory 256100 kb
Host smart-a6ea2620-2033-476e-a590-f5daea818458
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15281
04263 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_smoke.1528104263
Directory /workspace/25.alert_handler_smoke/latest

Test location /workspace/coverage/default/26.alert_handler_entropy.1852122243
Short name T27
Test name
Test status
Simulation time 195354547435 ps
CPU time 2904.57 seconds
Started Jul 22 07:18:21 PM PDT 24
Finished Jul 22 08:07:38 PM PDT 24
Peak memory 288832 kb
Host smart-aa9531d4-e239-428c-a3f6-8296a4de95a3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852122243 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_entropy.1852122243
Directory /workspace/26.alert_handler_entropy/latest

Test location /workspace/coverage/default/26.alert_handler_esc_alert_accum.2291689963
Short name T662
Test name
Test status
Simulation time 31527796106 ps
CPU time 184.08 seconds
Started Jul 22 07:18:19 PM PDT 24
Finished Jul 22 07:22:15 PM PDT 24
Peak memory 256860 kb
Host smart-710c7534-1ec7-4579-addb-4798fe509b86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22916
89963 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_alert_accum.2291689963
Directory /workspace/26.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/26.alert_handler_esc_intr_timeout.3485417019
Short name T495
Test name
Test status
Simulation time 684602526 ps
CPU time 44.87 seconds
Started Jul 22 07:18:24 PM PDT 24
Finished Jul 22 07:20:00 PM PDT 24
Peak memory 249024 kb
Host smart-6e5bd727-5c51-4ba6-8562-fc3e6a3fc0e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34854
17019 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_intr_timeout.3485417019
Directory /workspace/26.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_lpg.3283916262
Short name T330
Test name
Test status
Simulation time 189431210431 ps
CPU time 2550.26 seconds
Started Jul 22 07:18:28 PM PDT 24
Finished Jul 22 08:01:48 PM PDT 24
Peak memory 284908 kb
Host smart-adafad12-ecc6-464c-af5c-8dc39365dd99
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283916262 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg.3283916262
Directory /workspace/26.alert_handler_lpg/latest

Test location /workspace/coverage/default/26.alert_handler_lpg_stub_clk.70597606
Short name T611
Test name
Test status
Simulation time 10166473569 ps
CPU time 1026.69 seconds
Started Jul 22 07:18:18 PM PDT 24
Finished Jul 22 07:36:17 PM PDT 24
Peak memory 289524 kb
Host smart-5b759153-22af-4124-9f4c-e72757baf05d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70597606 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg_stub_clk.70597606
Directory /workspace/26.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/26.alert_handler_ping_timeout.2786208640
Short name T313
Test name
Test status
Simulation time 23015812748 ps
CPU time 468.28 seconds
Started Jul 22 07:19:39 PM PDT 24
Finished Jul 22 07:27:46 PM PDT 24
Peak memory 248604 kb
Host smart-b06995ff-1220-458c-b09a-6d387dbb2eaf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786208640 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_ping_timeout.2786208640
Directory /workspace/26.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_random_alerts.3544934343
Short name T282
Test name
Test status
Simulation time 114440854 ps
CPU time 13.04 seconds
Started Jul 22 07:19:07 PM PDT 24
Finished Jul 22 07:19:59 PM PDT 24
Peak memory 248576 kb
Host smart-abf4cc3a-4ef3-4d73-b77a-9f455f004ad6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35449
34343 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_alerts.3544934343
Directory /workspace/26.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/26.alert_handler_random_classes.2402235669
Short name T530
Test name
Test status
Simulation time 1116106128 ps
CPU time 59.26 seconds
Started Jul 22 07:18:20 PM PDT 24
Finished Jul 22 07:20:11 PM PDT 24
Peak memory 255784 kb
Host smart-b2cac915-2494-4a71-8d36-0e650fbd3a8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24022
35669 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_classes.2402235669
Directory /workspace/26.alert_handler_random_classes/latest

Test location /workspace/coverage/default/26.alert_handler_sig_int_fail.4082972116
Short name T290
Test name
Test status
Simulation time 1124277203 ps
CPU time 17.67 seconds
Started Jul 22 07:18:19 PM PDT 24
Finished Jul 22 07:19:28 PM PDT 24
Peak memory 248764 kb
Host smart-69e6ce33-1dcc-4931-b756-8107302f2e22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40829
72116 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_sig_int_fail.4082972116
Directory /workspace/26.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/26.alert_handler_smoke.1117827422
Short name T484
Test name
Test status
Simulation time 7753844667 ps
CPU time 25.5 seconds
Started Jul 22 07:18:23 PM PDT 24
Finished Jul 22 07:19:39 PM PDT 24
Peak memory 255908 kb
Host smart-c36828f2-6c55-4805-a8ac-25196c9e17c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11178
27422 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_smoke.1117827422
Directory /workspace/26.alert_handler_smoke/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all.2793727088
Short name T613
Test name
Test status
Simulation time 402390614 ps
CPU time 38.76 seconds
Started Jul 22 07:18:28 PM PDT 24
Finished Jul 22 07:19:56 PM PDT 24
Peak memory 256264 kb
Host smart-9e4f45ba-453c-4bae-891d-d28ebe478cd0
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793727088 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_ha
ndler_stress_all.2793727088
Directory /workspace/26.alert_handler_stress_all/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all_with_rand_reset.3844397099
Short name T512
Test name
Test status
Simulation time 21876066414 ps
CPU time 2226.77 seconds
Started Jul 22 07:18:21 PM PDT 24
Finished Jul 22 07:56:20 PM PDT 24
Peak memory 305144 kb
Host smart-20d1898d-8959-43f5-8495-dfe859f52a88
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844397099 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 26.alert_handler_stress_all_with_rand_reset.3844397099
Directory /workspace/26.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.alert_handler_entropy.320457203
Short name T660
Test name
Test status
Simulation time 51041001666 ps
CPU time 1960.7 seconds
Started Jul 22 07:19:07 PM PDT 24
Finished Jul 22 07:52:27 PM PDT 24
Peak memory 273016 kb
Host smart-e27745d3-5a6d-48f1-94b3-47e261090bfb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320457203 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_entropy.320457203
Directory /workspace/27.alert_handler_entropy/latest

Test location /workspace/coverage/default/27.alert_handler_esc_alert_accum.3370489112
Short name T253
Test name
Test status
Simulation time 759673755 ps
CPU time 35.46 seconds
Started Jul 22 07:18:27 PM PDT 24
Finished Jul 22 07:19:53 PM PDT 24
Peak memory 256100 kb
Host smart-7042fa2e-b096-43ec-abd1-6129ce71e4ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33704
89112 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_alert_accum.3370489112
Directory /workspace/27.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/27.alert_handler_esc_intr_timeout.298783395
Short name T699
Test name
Test status
Simulation time 19229713 ps
CPU time 2.85 seconds
Started Jul 22 07:18:26 PM PDT 24
Finished Jul 22 07:19:18 PM PDT 24
Peak memory 249172 kb
Host smart-73731cb0-eb5d-4f90-8365-6849c52dcc60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29878
3395 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_intr_timeout.298783395
Directory /workspace/27.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_lpg_stub_clk.3119191620
Short name T39
Test name
Test status
Simulation time 40670875737 ps
CPU time 2425.55 seconds
Started Jul 22 07:18:27 PM PDT 24
Finished Jul 22 07:59:43 PM PDT 24
Peak memory 288312 kb
Host smart-72ef94d3-1e64-49f9-be8a-e4ef1f7d86cb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119191620 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg_stub_clk.3119191620
Directory /workspace/27.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/27.alert_handler_random_alerts.1211780651
Short name T650
Test name
Test status
Simulation time 775933606 ps
CPU time 46.23 seconds
Started Jul 22 07:18:26 PM PDT 24
Finished Jul 22 07:20:03 PM PDT 24
Peak memory 255920 kb
Host smart-0fefbe7a-bdc4-4270-b758-dd2202d54d60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12117
80651 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_alerts.1211780651
Directory /workspace/27.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/27.alert_handler_random_classes.2841183861
Short name T686
Test name
Test status
Simulation time 5485867833 ps
CPU time 82.12 seconds
Started Jul 22 07:19:07 PM PDT 24
Finished Jul 22 07:21:09 PM PDT 24
Peak memory 256424 kb
Host smart-e78c0100-0d2d-4369-a029-0c34816ba899
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28411
83861 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_classes.2841183861
Directory /workspace/27.alert_handler_random_classes/latest

Test location /workspace/coverage/default/27.alert_handler_sig_int_fail.3652858976
Short name T541
Test name
Test status
Simulation time 499233001 ps
CPU time 13.08 seconds
Started Jul 22 07:18:27 PM PDT 24
Finished Jul 22 07:19:30 PM PDT 24
Peak memory 249192 kb
Host smart-7a279761-d727-4c80-a384-b582b5f85168
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36528
58976 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_sig_int_fail.3652858976
Directory /workspace/27.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/27.alert_handler_smoke.3389893811
Short name T452
Test name
Test status
Simulation time 196776475 ps
CPU time 8.12 seconds
Started Jul 22 07:18:26 PM PDT 24
Finished Jul 22 07:19:25 PM PDT 24
Peak memory 248764 kb
Host smart-99023e59-08d1-425b-9254-cfa194851628
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33898
93811 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_smoke.3389893811
Directory /workspace/27.alert_handler_smoke/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all_with_rand_reset.3953585447
Short name T99
Test name
Test status
Simulation time 150361674276 ps
CPU time 3156.96 seconds
Started Jul 22 07:18:31 PM PDT 24
Finished Jul 22 08:11:58 PM PDT 24
Peak memory 314352 kb
Host smart-fb2273cf-e3f2-4966-9ed9-126c4941a813
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953585447 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.alert_handler_stress_all_with_rand_reset.3953585447
Directory /workspace/27.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.alert_handler_entropy.765292551
Short name T708
Test name
Test status
Simulation time 32234306731 ps
CPU time 1604.3 seconds
Started Jul 22 07:18:33 PM PDT 24
Finished Jul 22 07:46:07 PM PDT 24
Peak memory 289520 kb
Host smart-3394c98f-b493-4187-a771-f53051ad59c5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765292551 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_entropy.765292551
Directory /workspace/28.alert_handler_entropy/latest

Test location /workspace/coverage/default/28.alert_handler_esc_alert_accum.3076950296
Short name T473
Test name
Test status
Simulation time 1453053446 ps
CPU time 105.49 seconds
Started Jul 22 07:18:42 PM PDT 24
Finished Jul 22 07:21:14 PM PDT 24
Peak memory 250544 kb
Host smart-1d83ae3b-95b7-410b-8957-5c5185882f82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30769
50296 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_alert_accum.3076950296
Directory /workspace/28.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/28.alert_handler_esc_intr_timeout.178274546
Short name T584
Test name
Test status
Simulation time 3014274304 ps
CPU time 22.87 seconds
Started Jul 22 07:18:42 PM PDT 24
Finished Jul 22 07:19:52 PM PDT 24
Peak memory 255484 kb
Host smart-3572f9a0-c24d-49ff-96e0-f1390a40f905
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17827
4546 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_intr_timeout.178274546
Directory /workspace/28.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_lpg.4209413455
Short name T288
Test name
Test status
Simulation time 6417444223 ps
CPU time 594.25 seconds
Started Jul 22 07:18:31 PM PDT 24
Finished Jul 22 07:29:15 PM PDT 24
Peak memory 272424 kb
Host smart-7bde6b5b-c8ef-4daa-b991-3c9668bfd1ce
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4209413455 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg.4209413455
Directory /workspace/28.alert_handler_lpg/latest

Test location /workspace/coverage/default/28.alert_handler_lpg_stub_clk.504512326
Short name T560
Test name
Test status
Simulation time 49535143254 ps
CPU time 1287.22 seconds
Started Jul 22 07:18:35 PM PDT 24
Finished Jul 22 07:40:52 PM PDT 24
Peak memory 285224 kb
Host smart-8a04e6ed-9280-4f94-8c9c-741fb1a77e62
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504512326 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg_stub_clk.504512326
Directory /workspace/28.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/28.alert_handler_random_alerts.2574703266
Short name T216
Test name
Test status
Simulation time 158384591 ps
CPU time 11.93 seconds
Started Jul 22 07:18:45 PM PDT 24
Finished Jul 22 07:19:42 PM PDT 24
Peak memory 248644 kb
Host smart-54860f0d-db93-4dd4-82a2-46e8489baf2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25747
03266 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_alerts.2574703266
Directory /workspace/28.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/28.alert_handler_random_classes.1549630068
Short name T641
Test name
Test status
Simulation time 479437606 ps
CPU time 17.92 seconds
Started Jul 22 07:18:31 PM PDT 24
Finished Jul 22 07:19:38 PM PDT 24
Peak memory 248108 kb
Host smart-6396e204-5f5a-4a2a-b068-2b3117c28103
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15496
30068 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_classes.1549630068
Directory /workspace/28.alert_handler_random_classes/latest

Test location /workspace/coverage/default/28.alert_handler_sig_int_fail.118725632
Short name T90
Test name
Test status
Simulation time 852148012 ps
CPU time 31.44 seconds
Started Jul 22 07:18:45 PM PDT 24
Finished Jul 22 07:20:02 PM PDT 24
Peak memory 256360 kb
Host smart-3c813a4d-b6ec-4cff-b694-ace45f549788
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11872
5632 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_sig_int_fail.118725632
Directory /workspace/28.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/28.alert_handler_smoke.3268904822
Short name T425
Test name
Test status
Simulation time 362555076 ps
CPU time 31.24 seconds
Started Jul 22 07:18:32 PM PDT 24
Finished Jul 22 07:19:53 PM PDT 24
Peak memory 256284 kb
Host smart-a1cb4f2e-bfe0-46a9-a60c-42be82049f94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32689
04822 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_smoke.3268904822
Directory /workspace/28.alert_handler_smoke/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all.3395699490
Short name T103
Test name
Test status
Simulation time 27222777689 ps
CPU time 345.76 seconds
Started Jul 22 07:18:33 PM PDT 24
Finished Jul 22 07:25:08 PM PDT 24
Peak memory 255308 kb
Host smart-c39a4d0c-26c8-435c-ad57-ac57d88cb55f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395699490 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_ha
ndler_stress_all.3395699490
Directory /workspace/28.alert_handler_stress_all/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all_with_rand_reset.3893303684
Short name T272
Test name
Test status
Simulation time 27495930374 ps
CPU time 1912.71 seconds
Started Jul 22 07:18:46 PM PDT 24
Finished Jul 22 07:51:26 PM PDT 24
Peak memory 289188 kb
Host smart-e5d82842-bb20-4e94-93d6-81e949922e47
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893303684 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.alert_handler_stress_all_with_rand_reset.3893303684
Directory /workspace/28.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.alert_handler_entropy.3298153622
Short name T573
Test name
Test status
Simulation time 140289399188 ps
CPU time 828.17 seconds
Started Jul 22 07:18:45 PM PDT 24
Finished Jul 22 07:33:18 PM PDT 24
Peak memory 273184 kb
Host smart-cfd1e74b-2955-480a-920c-daf9063c8b9b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298153622 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_entropy.3298153622
Directory /workspace/29.alert_handler_entropy/latest

Test location /workspace/coverage/default/29.alert_handler_esc_alert_accum.1398935258
Short name T709
Test name
Test status
Simulation time 662488577 ps
CPU time 40.49 seconds
Started Jul 22 07:18:42 PM PDT 24
Finished Jul 22 07:20:09 PM PDT 24
Peak memory 256004 kb
Host smart-dd30f7d7-c264-4ffe-bd6d-378566e1665e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13989
35258 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_alert_accum.1398935258
Directory /workspace/29.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/29.alert_handler_esc_intr_timeout.2300545480
Short name T453
Test name
Test status
Simulation time 626136221 ps
CPU time 39.81 seconds
Started Jul 22 07:18:34 PM PDT 24
Finished Jul 22 07:20:04 PM PDT 24
Peak memory 255920 kb
Host smart-acf3ce6e-2d12-4646-8040-8652e6371bec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23005
45480 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_intr_timeout.2300545480
Directory /workspace/29.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_lpg.2828268759
Short name T204
Test name
Test status
Simulation time 33573601239 ps
CPU time 821.7 seconds
Started Jul 22 07:18:44 PM PDT 24
Finished Jul 22 07:33:11 PM PDT 24
Peak memory 272584 kb
Host smart-56047b4c-1c3d-4cf2-99e6-79e2bf404d1b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2828268759 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg.2828268759
Directory /workspace/29.alert_handler_lpg/latest

Test location /workspace/coverage/default/29.alert_handler_lpg_stub_clk.1993470542
Short name T381
Test name
Test status
Simulation time 41417063659 ps
CPU time 1203.76 seconds
Started Jul 22 07:18:45 PM PDT 24
Finished Jul 22 07:39:35 PM PDT 24
Peak memory 272800 kb
Host smart-af3cc69e-0299-4772-804f-a6bafdfb8f30
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993470542 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg_stub_clk.1993470542
Directory /workspace/29.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/29.alert_handler_ping_timeout.3899660957
Short name T543
Test name
Test status
Simulation time 20794922790 ps
CPU time 362.23 seconds
Started Jul 22 07:18:46 PM PDT 24
Finished Jul 22 07:25:35 PM PDT 24
Peak memory 256336 kb
Host smart-216be0f3-6a64-42fe-a8ff-1ff9a72156f0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899660957 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_ping_timeout.3899660957
Directory /workspace/29.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_random_alerts.1473400078
Short name T535
Test name
Test status
Simulation time 727965958 ps
CPU time 44.32 seconds
Started Jul 22 07:18:43 PM PDT 24
Finished Jul 22 07:20:13 PM PDT 24
Peak memory 248552 kb
Host smart-df51ca2e-b75c-4e62-8845-a0814ec87864
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14734
00078 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_alerts.1473400078
Directory /workspace/29.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/29.alert_handler_random_classes.2622856958
Short name T406
Test name
Test status
Simulation time 2710506733 ps
CPU time 46.45 seconds
Started Jul 22 07:18:44 PM PDT 24
Finished Jul 22 07:20:16 PM PDT 24
Peak memory 256652 kb
Host smart-2fcbf2c3-c980-4687-a6cf-6aceb9ab0bb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26228
56958 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_classes.2622856958
Directory /workspace/29.alert_handler_random_classes/latest

Test location /workspace/coverage/default/29.alert_handler_smoke.43680921
Short name T419
Test name
Test status
Simulation time 4876728413 ps
CPU time 55.64 seconds
Started Jul 22 07:18:45 PM PDT 24
Finished Jul 22 07:20:26 PM PDT 24
Peak memory 257024 kb
Host smart-7b29d1fe-9cc3-468b-acbc-b847cf3c19ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43680
921 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_smoke.43680921
Directory /workspace/29.alert_handler_smoke/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all.1249578092
Short name T695
Test name
Test status
Simulation time 14653966341 ps
CPU time 1512.53 seconds
Started Jul 22 07:18:44 PM PDT 24
Finished Jul 22 07:44:42 PM PDT 24
Peak memory 289620 kb
Host smart-48868ac1-fb19-4941-8b3a-6f1ef7cafd2a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249578092 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_ha
ndler_stress_all.1249578092
Directory /workspace/29.alert_handler_stress_all/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all_with_rand_reset.3065715994
Short name T198
Test name
Test status
Simulation time 87690020296 ps
CPU time 2805.54 seconds
Started Jul 22 07:18:33 PM PDT 24
Finished Jul 22 08:06:09 PM PDT 24
Peak memory 304828 kb
Host smart-e0d5d28c-4641-485d-9661-15acf0dc9bea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065715994 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 29.alert_handler_stress_all_with_rand_reset.3065715994
Directory /workspace/29.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.alert_handler_alert_accum_saturation.3427763926
Short name T234
Test name
Test status
Simulation time 211456302 ps
CPU time 3.49 seconds
Started Jul 22 07:16:54 PM PDT 24
Finished Jul 22 07:18:02 PM PDT 24
Peak memory 248852 kb
Host smart-fb83c614-80d1-43f5-a2bb-ddfbe5bd5aad
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3427763926 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_alert_accum_saturation.3427763926
Directory /workspace/3.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/3.alert_handler_entropy.2023032946
Short name T651
Test name
Test status
Simulation time 10507416590 ps
CPU time 1048.98 seconds
Started Jul 22 07:17:20 PM PDT 24
Finished Jul 22 07:35:50 PM PDT 24
Peak memory 289288 kb
Host smart-e8df9e20-f468-4694-b43b-6d9a8fa41690
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023032946 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy.2023032946
Directory /workspace/3.alert_handler_entropy/latest

Test location /workspace/coverage/default/3.alert_handler_entropy_stress.1335047365
Short name T250
Test name
Test status
Simulation time 192281559 ps
CPU time 11.14 seconds
Started Jul 22 07:17:20 PM PDT 24
Finished Jul 22 07:18:32 PM PDT 24
Peak memory 248528 kb
Host smart-6c29934d-bfec-4470-b01c-7e04e8630822
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1335047365 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy_stress.1335047365
Directory /workspace/3.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/3.alert_handler_esc_alert_accum.190980580
Short name T698
Test name
Test status
Simulation time 2634012370 ps
CPU time 59.95 seconds
Started Jul 22 07:16:54 PM PDT 24
Finished Jul 22 07:18:58 PM PDT 24
Peak memory 256304 kb
Host smart-910545b2-356f-4d56-be0f-b898324c1791
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19098
0580 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_alert_accum.190980580
Directory /workspace/3.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/3.alert_handler_esc_intr_timeout.2340667899
Short name T87
Test name
Test status
Simulation time 3016258120 ps
CPU time 44.06 seconds
Started Jul 22 07:17:20 PM PDT 24
Finished Jul 22 07:19:05 PM PDT 24
Peak memory 248540 kb
Host smart-fb5f7de7-7c2f-4c4a-9f48-6093f076335e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23406
67899 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_intr_timeout.2340667899
Directory /workspace/3.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_lpg.1259409887
Short name T654
Test name
Test status
Simulation time 26857133956 ps
CPU time 1527.38 seconds
Started Jul 22 07:16:54 PM PDT 24
Finished Jul 22 07:43:26 PM PDT 24
Peak memory 272936 kb
Host smart-185226c4-f458-40e3-a2f9-2bf37b5664be
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259409887 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg.1259409887
Directory /workspace/3.alert_handler_lpg/latest

Test location /workspace/coverage/default/3.alert_handler_lpg_stub_clk.4267076710
Short name T414
Test name
Test status
Simulation time 58335438487 ps
CPU time 2097.49 seconds
Started Jul 22 07:16:58 PM PDT 24
Finished Jul 22 07:52:58 PM PDT 24
Peak memory 286496 kb
Host smart-c88a8201-1409-4148-89d9-8c07ff0a0f8f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267076710 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg_stub_clk.4267076710
Directory /workspace/3.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/3.alert_handler_ping_timeout.3875300565
Short name T590
Test name
Test status
Simulation time 11966300834 ps
CPU time 252.84 seconds
Started Jul 22 07:16:57 PM PDT 24
Finished Jul 22 07:22:12 PM PDT 24
Peak memory 248660 kb
Host smart-7b7de92b-4193-4a95-b441-719f9b841311
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875300565 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_ping_timeout.3875300565
Directory /workspace/3.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_random_alerts.3132517155
Short name T666
Test name
Test status
Simulation time 3060505977 ps
CPU time 44.68 seconds
Started Jul 22 07:16:54 PM PDT 24
Finished Jul 22 07:18:43 PM PDT 24
Peak memory 255240 kb
Host smart-b442b9f6-ae68-4520-9931-e9b546f9da83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31325
17155 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_alerts.3132517155
Directory /workspace/3.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/3.alert_handler_random_classes.3779382727
Short name T438
Test name
Test status
Simulation time 697874379 ps
CPU time 37.16 seconds
Started Jul 22 07:16:59 PM PDT 24
Finished Jul 22 07:18:37 PM PDT 24
Peak memory 256692 kb
Host smart-2fdd5e96-86bd-47bd-a7bb-357fd93ec1aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37793
82727 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_classes.3779382727
Directory /workspace/3.alert_handler_random_classes/latest

Test location /workspace/coverage/default/3.alert_handler_sec_cm.626399421
Short name T10
Test name
Test status
Simulation time 539497998 ps
CPU time 26.31 seconds
Started Jul 22 07:16:52 PM PDT 24
Finished Jul 22 07:18:24 PM PDT 24
Peak memory 276044 kb
Host smart-382273f4-c0e1-4dfc-b10c-0f6c08e1daec
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=626399421 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sec_cm.626399421
Directory /workspace/3.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/3.alert_handler_sig_int_fail.2675208075
Short name T257
Test name
Test status
Simulation time 114475266 ps
CPU time 11.68 seconds
Started Jul 22 07:16:54 PM PDT 24
Finished Jul 22 07:18:10 PM PDT 24
Peak memory 255672 kb
Host smart-72792b54-4595-4ace-8ebb-ccae60c8549f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26752
08075 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sig_int_fail.2675208075
Directory /workspace/3.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/3.alert_handler_smoke.536097309
Short name T492
Test name
Test status
Simulation time 1609789592 ps
CPU time 28.61 seconds
Started Jul 22 07:16:41 PM PDT 24
Finished Jul 22 07:18:14 PM PDT 24
Peak memory 255644 kb
Host smart-b9451db0-c592-4912-84eb-3fe4df874fac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53609
7309 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_smoke.536097309
Directory /workspace/3.alert_handler_smoke/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all_with_rand_reset.1458502197
Short name T29
Test name
Test status
Simulation time 18498667207 ps
CPU time 583.94 seconds
Started Jul 22 07:16:51 PM PDT 24
Finished Jul 22 07:27:41 PM PDT 24
Peak memory 265332 kb
Host smart-9055f868-5f49-41a9-9c40-ae90d1f14804
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458502197 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.alert_handler_stress_all_with_rand_reset.1458502197
Directory /workspace/3.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.alert_handler_entropy.3693721620
Short name T433
Test name
Test status
Simulation time 185056348780 ps
CPU time 2666.31 seconds
Started Jul 22 07:18:46 PM PDT 24
Finished Jul 22 08:03:58 PM PDT 24
Peak memory 288300 kb
Host smart-514fad57-86d9-48d5-b452-3e9563752766
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693721620 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_entropy.3693721620
Directory /workspace/30.alert_handler_entropy/latest

Test location /workspace/coverage/default/30.alert_handler_esc_alert_accum.773421400
Short name T536
Test name
Test status
Simulation time 2912705166 ps
CPU time 180.23 seconds
Started Jul 22 07:18:45 PM PDT 24
Finished Jul 22 07:22:30 PM PDT 24
Peak memory 249764 kb
Host smart-ee938ea5-9960-4d3b-a227-f790f14b5158
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77342
1400 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_alert_accum.773421400
Directory /workspace/30.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/30.alert_handler_esc_intr_timeout.299578246
Short name T52
Test name
Test status
Simulation time 1956771362 ps
CPU time 33.32 seconds
Started Jul 22 07:18:45 PM PDT 24
Finished Jul 22 07:20:04 PM PDT 24
Peak memory 256356 kb
Host smart-aa1fa09e-3c14-4cef-8a6e-1e7a7a411771
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29957
8246 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_intr_timeout.299578246
Directory /workspace/30.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_lpg.467102692
Short name T349
Test name
Test status
Simulation time 36749187197 ps
CPU time 2404.7 seconds
Started Jul 22 07:18:44 PM PDT 24
Finished Jul 22 07:59:34 PM PDT 24
Peak memory 289324 kb
Host smart-1d905708-ee87-45a0-ac44-03e192cec9a7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=467102692 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg.467102692
Directory /workspace/30.alert_handler_lpg/latest

Test location /workspace/coverage/default/30.alert_handler_lpg_stub_clk.2341702219
Short name T688
Test name
Test status
Simulation time 456096556700 ps
CPU time 1777.87 seconds
Started Jul 22 07:18:41 PM PDT 24
Finished Jul 22 07:49:06 PM PDT 24
Peak memory 281444 kb
Host smart-832718e0-2578-4801-9a93-10f404ee3150
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341702219 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg_stub_clk.2341702219
Directory /workspace/30.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/30.alert_handler_ping_timeout.268566655
Short name T618
Test name
Test status
Simulation time 2056442805 ps
CPU time 67.16 seconds
Started Jul 22 07:18:41 PM PDT 24
Finished Jul 22 07:20:35 PM PDT 24
Peak memory 255468 kb
Host smart-45c63dbb-f45c-42cd-8bf0-06d1e39c23eb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=268566655 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_ping_timeout.268566655
Directory /workspace/30.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_random_alerts.2797314422
Short name T74
Test name
Test status
Simulation time 2384328201 ps
CPU time 43.54 seconds
Started Jul 22 07:18:41 PM PDT 24
Finished Jul 22 07:20:11 PM PDT 24
Peak memory 256040 kb
Host smart-45b15c38-7f34-416d-9140-7fc37f33bfcd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27973
14422 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_alerts.2797314422
Directory /workspace/30.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/30.alert_handler_random_classes.1486823063
Short name T46
Test name
Test status
Simulation time 862609782 ps
CPU time 56.87 seconds
Started Jul 22 07:18:45 PM PDT 24
Finished Jul 22 07:20:28 PM PDT 24
Peak memory 248492 kb
Host smart-469f9df1-0cd1-4593-a811-2dffa0848dc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14868
23063 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_classes.1486823063
Directory /workspace/30.alert_handler_random_classes/latest

Test location /workspace/coverage/default/30.alert_handler_sig_int_fail.3055081237
Short name T606
Test name
Test status
Simulation time 757031643 ps
CPU time 46.1 seconds
Started Jul 22 07:18:44 PM PDT 24
Finished Jul 22 07:20:16 PM PDT 24
Peak memory 256076 kb
Host smart-b8e48d7e-64af-43de-bfb3-8621daf62775
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30550
81237 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_sig_int_fail.3055081237
Directory /workspace/30.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/30.alert_handler_smoke.133539065
Short name T594
Test name
Test status
Simulation time 352668852 ps
CPU time 31.85 seconds
Started Jul 22 07:18:45 PM PDT 24
Finished Jul 22 07:20:03 PM PDT 24
Peak memory 256160 kb
Host smart-a7f927df-fef5-465d-8568-63f51c361d72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13353
9065 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_smoke.133539065
Directory /workspace/30.alert_handler_smoke/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all.607985666
Short name T503
Test name
Test status
Simulation time 378032510912 ps
CPU time 3472.92 seconds
Started Jul 22 07:18:46 PM PDT 24
Finished Jul 22 08:17:26 PM PDT 24
Peak memory 288872 kb
Host smart-7e4ffb67-1cf8-462d-95f7-0e769ac61a16
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607985666 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_han
dler_stress_all.607985666
Directory /workspace/30.alert_handler_stress_all/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all_with_rand_reset.2021503856
Short name T270
Test name
Test status
Simulation time 18437368151 ps
CPU time 1091.21 seconds
Started Jul 22 07:18:43 PM PDT 24
Finished Jul 22 07:37:41 PM PDT 24
Peak memory 268508 kb
Host smart-3330f08a-3285-4072-8410-b0ee40dea3dd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021503856 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.alert_handler_stress_all_with_rand_reset.2021503856
Directory /workspace/30.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.alert_handler_entropy.634550315
Short name T700
Test name
Test status
Simulation time 102651408943 ps
CPU time 2633.1 seconds
Started Jul 22 07:18:45 PM PDT 24
Finished Jul 22 08:03:24 PM PDT 24
Peak memory 289080 kb
Host smart-b27df8f5-f983-489a-9702-957b5afd3c82
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634550315 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_entropy.634550315
Directory /workspace/31.alert_handler_entropy/latest

Test location /workspace/coverage/default/31.alert_handler_esc_alert_accum.2032500273
Short name T546
Test name
Test status
Simulation time 7851754794 ps
CPU time 112.3 seconds
Started Jul 22 07:18:45 PM PDT 24
Finished Jul 22 07:21:23 PM PDT 24
Peak memory 249732 kb
Host smart-f73764d8-8ab3-4dfa-8332-6bd56ed786df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20325
00273 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_alert_accum.2032500273
Directory /workspace/31.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/31.alert_handler_esc_intr_timeout.1350303004
Short name T446
Test name
Test status
Simulation time 884274821 ps
CPU time 31.84 seconds
Started Jul 22 07:18:44 PM PDT 24
Finished Jul 22 07:20:01 PM PDT 24
Peak memory 248528 kb
Host smart-b0398059-7698-42cd-aa16-a316979dc9a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13503
03004 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_intr_timeout.1350303004
Directory /workspace/31.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_lpg.854048840
Short name T299
Test name
Test status
Simulation time 9773385403 ps
CPU time 768.55 seconds
Started Jul 22 07:18:44 PM PDT 24
Finished Jul 22 07:32:18 PM PDT 24
Peak memory 272712 kb
Host smart-4c03baa7-8632-45a8-a535-aa65004fb408
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854048840 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg.854048840
Directory /workspace/31.alert_handler_lpg/latest

Test location /workspace/coverage/default/31.alert_handler_lpg_stub_clk.776145499
Short name T713
Test name
Test status
Simulation time 105791802440 ps
CPU time 1681.6 seconds
Started Jul 22 07:18:45 PM PDT 24
Finished Jul 22 07:47:33 PM PDT 24
Peak memory 273472 kb
Host smart-d6c5de8d-2f2d-4361-b5c0-de11eab58ac5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=776145499 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg_stub_clk.776145499
Directory /workspace/31.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/31.alert_handler_random_alerts.1939454526
Short name T428
Test name
Test status
Simulation time 3146017698 ps
CPU time 64.39 seconds
Started Jul 22 07:18:45 PM PDT 24
Finished Jul 22 07:20:35 PM PDT 24
Peak memory 256420 kb
Host smart-c173da3f-6a05-4070-9ce5-247e05f1389d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19394
54526 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_alerts.1939454526
Directory /workspace/31.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/31.alert_handler_random_classes.2304731242
Short name T653
Test name
Test status
Simulation time 2901138853 ps
CPU time 17.8 seconds
Started Jul 22 07:18:45 PM PDT 24
Finished Jul 22 07:19:49 PM PDT 24
Peak memory 248448 kb
Host smart-c42522c5-617d-412c-97be-b35bcc3ce4ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23047
31242 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_classes.2304731242
Directory /workspace/31.alert_handler_random_classes/latest

Test location /workspace/coverage/default/31.alert_handler_sig_int_fail.3851990822
Short name T266
Test name
Test status
Simulation time 661043773 ps
CPU time 44.84 seconds
Started Jul 22 07:18:44 PM PDT 24
Finished Jul 22 07:20:14 PM PDT 24
Peak memory 248304 kb
Host smart-c13d8193-db2f-457c-9d3a-96cea83116f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38519
90822 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_sig_int_fail.3851990822
Directory /workspace/31.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/31.alert_handler_smoke.966344636
Short name T436
Test name
Test status
Simulation time 145976277 ps
CPU time 4.91 seconds
Started Jul 22 07:18:46 PM PDT 24
Finished Jul 22 07:19:38 PM PDT 24
Peak memory 250544 kb
Host smart-7d2fd90b-4bba-4873-a9ee-7847be7326f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96634
4636 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_smoke.966344636
Directory /workspace/31.alert_handler_smoke/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all.4019715882
Short name T485
Test name
Test status
Simulation time 21639036218 ps
CPU time 359.71 seconds
Started Jul 22 07:18:44 PM PDT 24
Finished Jul 22 07:25:30 PM PDT 24
Peak memory 265072 kb
Host smart-89d984e2-c0f9-46ba-aa0b-e010adcb831e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019715882 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_ha
ndler_stress_all.4019715882
Directory /workspace/31.alert_handler_stress_all/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all_with_rand_reset.1138974193
Short name T69
Test name
Test status
Simulation time 179546136044 ps
CPU time 4915.52 seconds
Started Jul 22 07:18:45 PM PDT 24
Finished Jul 22 08:41:28 PM PDT 24
Peak memory 370972 kb
Host smart-a3ba60ad-1989-4d94-a644-f25e9ae78705
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138974193 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 31.alert_handler_stress_all_with_rand_reset.1138974193
Directory /workspace/31.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.alert_handler_esc_alert_accum.2404327875
Short name T548
Test name
Test status
Simulation time 1562857937 ps
CPU time 126.53 seconds
Started Jul 22 07:18:32 PM PDT 24
Finished Jul 22 07:21:28 PM PDT 24
Peak memory 256908 kb
Host smart-a1c4182a-c960-4442-8825-d8a652bf6bea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24043
27875 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_alert_accum.2404327875
Directory /workspace/32.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/32.alert_handler_esc_intr_timeout.430149064
Short name T575
Test name
Test status
Simulation time 335936150 ps
CPU time 22.66 seconds
Started Jul 22 07:18:45 PM PDT 24
Finished Jul 22 07:19:53 PM PDT 24
Peak memory 256092 kb
Host smart-f4ac2c46-9ea2-421a-9b57-9b162952a8c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43014
9064 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_intr_timeout.430149064
Directory /workspace/32.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_lpg.3171819771
Short name T18
Test name
Test status
Simulation time 54080320242 ps
CPU time 1015.53 seconds
Started Jul 22 07:18:45 PM PDT 24
Finished Jul 22 07:36:26 PM PDT 24
Peak memory 272476 kb
Host smart-4397db26-d1b4-4c56-b3f5-08c44f318f43
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171819771 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg.3171819771
Directory /workspace/32.alert_handler_lpg/latest

Test location /workspace/coverage/default/32.alert_handler_lpg_stub_clk.1608391481
Short name T391
Test name
Test status
Simulation time 140731106265 ps
CPU time 2060.69 seconds
Started Jul 22 07:18:45 PM PDT 24
Finished Jul 22 07:53:51 PM PDT 24
Peak memory 273156 kb
Host smart-13ffc2d3-738d-4dcb-ab67-70c7064d7ac4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1608391481 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg_stub_clk.1608391481
Directory /workspace/32.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/32.alert_handler_ping_timeout.3012015182
Short name T326
Test name
Test status
Simulation time 21250444227 ps
CPU time 241.59 seconds
Started Jul 22 07:18:46 PM PDT 24
Finished Jul 22 07:23:34 PM PDT 24
Peak memory 248644 kb
Host smart-f32dedd1-2a24-445f-835d-2a6f451ff5d7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012015182 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_ping_timeout.3012015182
Directory /workspace/32.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_random_alerts.3496371729
Short name T589
Test name
Test status
Simulation time 1990234320 ps
CPU time 35.74 seconds
Started Jul 22 07:18:45 PM PDT 24
Finished Jul 22 07:20:07 PM PDT 24
Peak memory 248520 kb
Host smart-381f4d24-6540-4c2c-bdc9-3f3e5a61824b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34963
71729 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_alerts.3496371729
Directory /workspace/32.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/32.alert_handler_random_classes.70671
Short name T57
Test name
Test status
Simulation time 1191427940 ps
CPU time 72.92 seconds
Started Jul 22 07:18:45 PM PDT 24
Finished Jul 22 07:20:43 PM PDT 24
Peak memory 248852 kb
Host smart-eb6354c5-4e3b-4884-910c-93b0e59981d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70671
-assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_classes.70671
Directory /workspace/32.alert_handler_random_classes/latest

Test location /workspace/coverage/default/32.alert_handler_sig_int_fail.3670384669
Short name T595
Test name
Test status
Simulation time 1152824372 ps
CPU time 45.38 seconds
Started Jul 22 07:18:45 PM PDT 24
Finished Jul 22 07:20:16 PM PDT 24
Peak memory 248552 kb
Host smart-71a2c372-7bf1-4ecd-aa9f-7c3db1416437
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36703
84669 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_sig_int_fail.3670384669
Directory /workspace/32.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/32.alert_handler_smoke.56691135
Short name T521
Test name
Test status
Simulation time 673705851 ps
CPU time 17.48 seconds
Started Jul 22 07:18:45 PM PDT 24
Finished Jul 22 07:19:48 PM PDT 24
Peak memory 255336 kb
Host smart-bcc164b0-df02-45da-9690-63c8341475c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56691
135 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_smoke.56691135
Directory /workspace/32.alert_handler_smoke/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all.2679042161
Short name T33
Test name
Test status
Simulation time 5383678173 ps
CPU time 202.99 seconds
Started Jul 22 07:18:45 PM PDT 24
Finished Jul 22 07:22:53 PM PDT 24
Peak memory 256872 kb
Host smart-17587ff3-5273-403e-b913-96fb4ed5d206
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679042161 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_ha
ndler_stress_all.2679042161
Directory /workspace/32.alert_handler_stress_all/latest

Test location /workspace/coverage/default/33.alert_handler_entropy.4236683893
Short name T609
Test name
Test status
Simulation time 122156634789 ps
CPU time 1260.02 seconds
Started Jul 22 07:18:44 PM PDT 24
Finished Jul 22 07:40:30 PM PDT 24
Peak memory 272472 kb
Host smart-63cb83bf-36d1-42ab-adbb-57829ab575b0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236683893 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_entropy.4236683893
Directory /workspace/33.alert_handler_entropy/latest

Test location /workspace/coverage/default/33.alert_handler_esc_alert_accum.1449287141
Short name T75
Test name
Test status
Simulation time 14584344808 ps
CPU time 196.34 seconds
Started Jul 22 07:18:46 PM PDT 24
Finished Jul 22 07:22:50 PM PDT 24
Peak memory 256816 kb
Host smart-446b7f77-0e7a-4917-b96d-337ea29e652f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14492
87141 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_alert_accum.1449287141
Directory /workspace/33.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/33.alert_handler_esc_intr_timeout.1341252107
Short name T441
Test name
Test status
Simulation time 270964261 ps
CPU time 4.47 seconds
Started Jul 22 07:18:47 PM PDT 24
Finished Jul 22 07:19:38 PM PDT 24
Peak memory 249012 kb
Host smart-41f99aff-d76c-466d-ae70-a64d91273fa2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13412
52107 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_intr_timeout.1341252107
Directory /workspace/33.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_lpg_stub_clk.2069778004
Short name T445
Test name
Test status
Simulation time 206298490704 ps
CPU time 1493.78 seconds
Started Jul 22 07:18:45 PM PDT 24
Finished Jul 22 07:44:25 PM PDT 24
Peak memory 288780 kb
Host smart-a92d3aff-a909-4a81-abd8-5d43af52453b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069778004 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg_stub_clk.2069778004
Directory /workspace/33.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/33.alert_handler_random_alerts.2026228474
Short name T582
Test name
Test status
Simulation time 389424373 ps
CPU time 11.8 seconds
Started Jul 22 07:18:45 PM PDT 24
Finished Jul 22 07:19:43 PM PDT 24
Peak memory 256612 kb
Host smart-562f7fb5-3968-4258-a4e1-c8d35a3a882d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20262
28474 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_alerts.2026228474
Directory /workspace/33.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/33.alert_handler_random_classes.1344701101
Short name T62
Test name
Test status
Simulation time 1647621796 ps
CPU time 24.21 seconds
Started Jul 22 07:18:45 PM PDT 24
Finished Jul 22 07:19:55 PM PDT 24
Peak memory 248712 kb
Host smart-5af57753-0202-452b-b926-0c9935d2684f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13447
01101 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_classes.1344701101
Directory /workspace/33.alert_handler_random_classes/latest

Test location /workspace/coverage/default/33.alert_handler_sig_int_fail.2304063869
Short name T636
Test name
Test status
Simulation time 45976195 ps
CPU time 3.15 seconds
Started Jul 22 07:18:46 PM PDT 24
Finished Jul 22 07:19:36 PM PDT 24
Peak memory 239944 kb
Host smart-89a01079-a9b3-48ea-beab-80bd39864b77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23040
63869 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_sig_int_fail.2304063869
Directory /workspace/33.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/33.alert_handler_smoke.1182129415
Short name T497
Test name
Test status
Simulation time 1385265970 ps
CPU time 23.65 seconds
Started Jul 22 07:18:47 PM PDT 24
Finished Jul 22 07:19:57 PM PDT 24
Peak memory 256504 kb
Host smart-e394abaf-6196-44d7-adc4-0e4ca90f820e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11821
29415 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_smoke.1182129415
Directory /workspace/33.alert_handler_smoke/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all.3706073276
Short name T108
Test name
Test status
Simulation time 46147883306 ps
CPU time 2752.2 seconds
Started Jul 22 07:18:44 PM PDT 24
Finished Jul 22 08:05:22 PM PDT 24
Peak memory 305068 kb
Host smart-b74dd890-7433-4479-8eb5-2ad246f3af55
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706073276 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_ha
ndler_stress_all.3706073276
Directory /workspace/33.alert_handler_stress_all/latest

Test location /workspace/coverage/default/34.alert_handler_entropy.1890931821
Short name T561
Test name
Test status
Simulation time 26303433595 ps
CPU time 1599.27 seconds
Started Jul 22 07:18:59 PM PDT 24
Finished Jul 22 07:46:20 PM PDT 24
Peak memory 289008 kb
Host smart-84ebfc8f-ed58-4a3e-99ce-7da4080e3537
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890931821 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_entropy.1890931821
Directory /workspace/34.alert_handler_entropy/latest

Test location /workspace/coverage/default/34.alert_handler_esc_alert_accum.325712819
Short name T715
Test name
Test status
Simulation time 947099048 ps
CPU time 82.21 seconds
Started Jul 22 07:19:15 PM PDT 24
Finished Jul 22 07:21:12 PM PDT 24
Peak memory 256372 kb
Host smart-88a4384b-d984-4753-ac1a-eafcb503f617
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32571
2819 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_alert_accum.325712819
Directory /workspace/34.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/34.alert_handler_esc_intr_timeout.2312092754
Short name T603
Test name
Test status
Simulation time 1054933637 ps
CPU time 38.44 seconds
Started Jul 22 07:18:59 PM PDT 24
Finished Jul 22 07:20:20 PM PDT 24
Peak memory 256816 kb
Host smart-b4101c38-4332-4201-a3dd-58d1c5cfa34f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23120
92754 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_intr_timeout.2312092754
Directory /workspace/34.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_lpg.308047109
Short name T352
Test name
Test status
Simulation time 75346009820 ps
CPU time 1580.57 seconds
Started Jul 22 07:18:58 PM PDT 24
Finished Jul 22 07:46:01 PM PDT 24
Peak memory 272944 kb
Host smart-bf5d0765-87ed-407a-85b2-565e80454f4b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308047109 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg.308047109
Directory /workspace/34.alert_handler_lpg/latest

Test location /workspace/coverage/default/34.alert_handler_lpg_stub_clk.2264979169
Short name T649
Test name
Test status
Simulation time 23784644374 ps
CPU time 1438.43 seconds
Started Jul 22 07:18:58 PM PDT 24
Finished Jul 22 07:43:39 PM PDT 24
Peak memory 273224 kb
Host smart-eb89f12e-a898-4f8a-bdc5-90e9240f812b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264979169 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg_stub_clk.2264979169
Directory /workspace/34.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/34.alert_handler_ping_timeout.1042409818
Short name T631
Test name
Test status
Simulation time 14192340792 ps
CPU time 412.54 seconds
Started Jul 22 07:19:01 PM PDT 24
Finished Jul 22 07:26:35 PM PDT 24
Peak memory 255444 kb
Host smart-2ddfb792-3f83-40af-b6bb-a53fc3c69380
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042409818 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_ping_timeout.1042409818
Directory /workspace/34.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_random_alerts.1206756385
Short name T474
Test name
Test status
Simulation time 3276067113 ps
CPU time 56.56 seconds
Started Jul 22 07:18:47 PM PDT 24
Finished Jul 22 07:20:30 PM PDT 24
Peak memory 256908 kb
Host smart-7109610e-a804-4e9e-b20f-0527a171f6dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12067
56385 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_alerts.1206756385
Directory /workspace/34.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/34.alert_handler_random_classes.318022089
Short name T658
Test name
Test status
Simulation time 437094373 ps
CPU time 29.01 seconds
Started Jul 22 07:18:45 PM PDT 24
Finished Jul 22 07:20:00 PM PDT 24
Peak memory 255984 kb
Host smart-d5d889f3-9300-4bd6-b5fd-5a5b62ed6765
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31802
2089 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_classes.318022089
Directory /workspace/34.alert_handler_random_classes/latest

Test location /workspace/coverage/default/34.alert_handler_sig_int_fail.3271265435
Short name T577
Test name
Test status
Simulation time 461829478 ps
CPU time 23.75 seconds
Started Jul 22 07:19:00 PM PDT 24
Finished Jul 22 07:20:06 PM PDT 24
Peak memory 255396 kb
Host smart-f394fe87-e444-49e1-8b0b-fba5d7b823b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32712
65435 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_sig_int_fail.3271265435
Directory /workspace/34.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/34.alert_handler_smoke.1525777784
Short name T551
Test name
Test status
Simulation time 1391015450 ps
CPU time 41.64 seconds
Started Jul 22 07:18:46 PM PDT 24
Finished Jul 22 07:20:15 PM PDT 24
Peak memory 256192 kb
Host smart-266420a2-b3ac-439c-a872-97d67ca1457e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15257
77784 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_smoke.1525777784
Directory /workspace/34.alert_handler_smoke/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all.3103072509
Short name T632
Test name
Test status
Simulation time 59708115840 ps
CPU time 3639.3 seconds
Started Jul 22 07:18:57 PM PDT 24
Finished Jul 22 08:20:20 PM PDT 24
Peak memory 289636 kb
Host smart-89b03139-c175-48a2-b682-312af00b4cab
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103072509 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_ha
ndler_stress_all.3103072509
Directory /workspace/34.alert_handler_stress_all/latest

Test location /workspace/coverage/default/35.alert_handler_esc_alert_accum.203096783
Short name T558
Test name
Test status
Simulation time 9802059187 ps
CPU time 188.42 seconds
Started Jul 22 07:18:59 PM PDT 24
Finished Jul 22 07:22:49 PM PDT 24
Peak memory 256492 kb
Host smart-1e99bd0e-e136-4205-9833-523a46bf845c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20309
6783 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_alert_accum.203096783
Directory /workspace/35.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/35.alert_handler_esc_intr_timeout.3134073221
Short name T592
Test name
Test status
Simulation time 1340767696 ps
CPU time 34.8 seconds
Started Jul 22 07:18:59 PM PDT 24
Finished Jul 22 07:20:16 PM PDT 24
Peak memory 248708 kb
Host smart-edb87f2e-0499-45d8-9d89-5673a2e4d450
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31340
73221 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_intr_timeout.3134073221
Directory /workspace/35.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_lpg.2832263386
Short name T342
Test name
Test status
Simulation time 57986322861 ps
CPU time 2121.31 seconds
Started Jul 22 07:19:25 PM PDT 24
Finished Jul 22 07:55:16 PM PDT 24
Peak memory 273196 kb
Host smart-0eebdbea-bd0f-42f2-b4ba-530ae2240578
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832263386 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg.2832263386
Directory /workspace/35.alert_handler_lpg/latest

Test location /workspace/coverage/default/35.alert_handler_lpg_stub_clk.3709285165
Short name T400
Test name
Test status
Simulation time 40211525920 ps
CPU time 940.1 seconds
Started Jul 22 07:19:03 PM PDT 24
Finished Jul 22 07:35:24 PM PDT 24
Peak memory 281404 kb
Host smart-1b602a5e-004f-439e-9709-ee9f44aa4f81
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709285165 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg_stub_clk.3709285165
Directory /workspace/35.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/35.alert_handler_random_alerts.4119883408
Short name T287
Test name
Test status
Simulation time 1090696487 ps
CPU time 22.4 seconds
Started Jul 22 07:18:58 PM PDT 24
Finished Jul 22 07:20:03 PM PDT 24
Peak memory 248556 kb
Host smart-7b6ab102-ff34-4976-8eb7-89277db929b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41198
83408 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_alerts.4119883408
Directory /workspace/35.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/35.alert_handler_random_classes.4110409296
Short name T241
Test name
Test status
Simulation time 378918001 ps
CPU time 24.48 seconds
Started Jul 22 07:19:02 PM PDT 24
Finished Jul 22 07:20:07 PM PDT 24
Peak memory 248176 kb
Host smart-60fdb226-acf1-4d15-b63e-ca65670f6318
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41104
09296 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_classes.4110409296
Directory /workspace/35.alert_handler_random_classes/latest

Test location /workspace/coverage/default/35.alert_handler_sig_int_fail.1223998696
Short name T458
Test name
Test status
Simulation time 766299613 ps
CPU time 23.92 seconds
Started Jul 22 07:19:00 PM PDT 24
Finished Jul 22 07:20:05 PM PDT 24
Peak memory 248600 kb
Host smart-96be9215-4404-42c7-a689-400c12f808d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12239
98696 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_sig_int_fail.1223998696
Directory /workspace/35.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/35.alert_handler_smoke.612331757
Short name T576
Test name
Test status
Simulation time 819467125 ps
CPU time 44.21 seconds
Started Jul 22 07:19:05 PM PDT 24
Finished Jul 22 07:20:30 PM PDT 24
Peak memory 256716 kb
Host smart-fd3dc6a5-88bd-447f-89f8-319ffb1271b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61233
1757 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_smoke.612331757
Directory /workspace/35.alert_handler_smoke/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all.2815719850
Short name T26
Test name
Test status
Simulation time 62518555324 ps
CPU time 1688.6 seconds
Started Jul 22 07:19:01 PM PDT 24
Finished Jul 22 07:47:51 PM PDT 24
Peak memory 289488 kb
Host smart-9b645596-f2c6-4064-adb0-afde4b56a556
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815719850 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_ha
ndler_stress_all.2815719850
Directory /workspace/35.alert_handler_stress_all/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all_with_rand_reset.2222318203
Short name T122
Test name
Test status
Simulation time 28661860694 ps
CPU time 3143.08 seconds
Started Jul 22 07:19:00 PM PDT 24
Finished Jul 22 08:12:05 PM PDT 24
Peak memory 304640 kb
Host smart-c239cde1-c399-4fcf-b264-592bcac39b75
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222318203 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 35.alert_handler_stress_all_with_rand_reset.2222318203
Directory /workspace/35.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.alert_handler_entropy.1969661131
Short name T701
Test name
Test status
Simulation time 49138077263 ps
CPU time 2355.96 seconds
Started Jul 22 07:19:29 PM PDT 24
Finished Jul 22 07:59:10 PM PDT 24
Peak memory 288700 kb
Host smart-ccea13c4-1f8c-444b-ab75-1067100aad50
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1969661131 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_entropy.1969661131
Directory /workspace/36.alert_handler_entropy/latest

Test location /workspace/coverage/default/36.alert_handler_esc_alert_accum.3767616512
Short name T51
Test name
Test status
Simulation time 2523615361 ps
CPU time 42.53 seconds
Started Jul 22 07:19:12 PM PDT 24
Finished Jul 22 07:20:32 PM PDT 24
Peak memory 256792 kb
Host smart-6627fbb2-3544-4946-a3be-7c320f5386b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37676
16512 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_alert_accum.3767616512
Directory /workspace/36.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/36.alert_handler_esc_intr_timeout.3474172176
Short name T427
Test name
Test status
Simulation time 2469074346 ps
CPU time 18.77 seconds
Started Jul 22 07:19:21 PM PDT 24
Finished Jul 22 07:20:11 PM PDT 24
Peak memory 253060 kb
Host smart-2af33854-022c-4466-88f6-849f8827ae6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34741
72176 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_intr_timeout.3474172176
Directory /workspace/36.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_lpg.3916306390
Short name T687
Test name
Test status
Simulation time 12103551851 ps
CPU time 890.69 seconds
Started Jul 22 07:19:11 PM PDT 24
Finished Jul 22 07:34:40 PM PDT 24
Peak memory 272868 kb
Host smart-65ffe168-feb3-4248-8f74-77704e120a53
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916306390 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg.3916306390
Directory /workspace/36.alert_handler_lpg/latest

Test location /workspace/coverage/default/36.alert_handler_lpg_stub_clk.2516741610
Short name T663
Test name
Test status
Simulation time 86536416304 ps
CPU time 2659.48 seconds
Started Jul 22 07:19:13 PM PDT 24
Finished Jul 22 08:04:09 PM PDT 24
Peak memory 288544 kb
Host smart-2b073651-aa7f-42a1-8aec-1fc69c4a78e4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516741610 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg_stub_clk.2516741610
Directory /workspace/36.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/36.alert_handler_ping_timeout.221670489
Short name T6
Test name
Test status
Simulation time 20855759022 ps
CPU time 244.16 seconds
Started Jul 22 07:19:11 PM PDT 24
Finished Jul 22 07:23:53 PM PDT 24
Peak memory 255368 kb
Host smart-59776056-4917-449b-b769-afd72eda15f7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221670489 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_ping_timeout.221670489
Directory /workspace/36.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_random_alerts.2814817579
Short name T202
Test name
Test status
Simulation time 871645635 ps
CPU time 26.13 seconds
Started Jul 22 07:19:11 PM PDT 24
Finished Jul 22 07:20:15 PM PDT 24
Peak memory 256152 kb
Host smart-6f25c04b-d26e-45af-bee4-66ec235991ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28148
17579 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_alerts.2814817579
Directory /workspace/36.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/36.alert_handler_random_classes.3191744211
Short name T644
Test name
Test status
Simulation time 4658604469 ps
CPU time 55.92 seconds
Started Jul 22 07:19:12 PM PDT 24
Finished Jul 22 07:20:45 PM PDT 24
Peak memory 249180 kb
Host smart-05821949-bd69-4bac-a47b-32a12475e917
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31917
44211 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_classes.3191744211
Directory /workspace/36.alert_handler_random_classes/latest

Test location /workspace/coverage/default/36.alert_handler_sig_int_fail.900871563
Short name T85
Test name
Test status
Simulation time 1650450154 ps
CPU time 50.77 seconds
Started Jul 22 07:19:11 PM PDT 24
Finished Jul 22 07:20:40 PM PDT 24
Peak memory 248256 kb
Host smart-f203bfbf-755e-4ac1-b4aa-952e5fc83d35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90087
1563 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_sig_int_fail.900871563
Directory /workspace/36.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/36.alert_handler_smoke.2204473386
Short name T689
Test name
Test status
Simulation time 539139110 ps
CPU time 10.17 seconds
Started Jul 22 07:19:02 PM PDT 24
Finished Jul 22 07:19:53 PM PDT 24
Peak memory 254800 kb
Host smart-7a3d13e6-35f0-4eff-9839-3ab8866ecd36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22044
73386 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_smoke.2204473386
Directory /workspace/36.alert_handler_smoke/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all.12297913
Short name T556
Test name
Test status
Simulation time 35290110805 ps
CPU time 2327.61 seconds
Started Jul 22 07:19:12 PM PDT 24
Finished Jul 22 07:58:37 PM PDT 24
Peak memory 289640 kb
Host smart-9a8d8b59-c1a2-4f8c-9480-90bd6e03ff00
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12297913 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_hand
ler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_hand
ler_stress_all.12297913
Directory /workspace/36.alert_handler_stress_all/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all_with_rand_reset.2837493583
Short name T247
Test name
Test status
Simulation time 68553605872 ps
CPU time 1014.59 seconds
Started Jul 22 07:19:12 PM PDT 24
Finished Jul 22 07:36:44 PM PDT 24
Peak memory 270200 kb
Host smart-3d25c46b-fe3f-46f1-bc40-a23387f8a6e6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837493583 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 36.alert_handler_stress_all_with_rand_reset.2837493583
Directory /workspace/36.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.alert_handler_entropy.3703745698
Short name T508
Test name
Test status
Simulation time 135646802553 ps
CPU time 2663.01 seconds
Started Jul 22 07:19:41 PM PDT 24
Finished Jul 22 08:04:22 PM PDT 24
Peak memory 289032 kb
Host smart-86450c43-b95b-4401-8bcc-8125ef1d9d74
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703745698 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_entropy.3703745698
Directory /workspace/37.alert_handler_entropy/latest

Test location /workspace/coverage/default/37.alert_handler_esc_alert_accum.1855411598
Short name T399
Test name
Test status
Simulation time 7924591733 ps
CPU time 133.62 seconds
Started Jul 22 07:19:47 PM PDT 24
Finished Jul 22 07:22:13 PM PDT 24
Peak memory 256380 kb
Host smart-f4ac4338-aca6-41de-926a-905dd7ffdb54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18554
11598 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_alert_accum.1855411598
Directory /workspace/37.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/37.alert_handler_esc_intr_timeout.1329130757
Short name T94
Test name
Test status
Simulation time 2544373051 ps
CPU time 42.11 seconds
Started Jul 22 07:19:32 PM PDT 24
Finished Jul 22 07:20:37 PM PDT 24
Peak memory 256336 kb
Host smart-c9ebabb5-7e9d-4f82-bb5e-8c2f9fba68a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13291
30757 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_intr_timeout.1329130757
Directory /workspace/37.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_lpg_stub_clk.505838480
Short name T293
Test name
Test status
Simulation time 52182405041 ps
CPU time 2858.13 seconds
Started Jul 22 07:19:32 PM PDT 24
Finished Jul 22 08:07:34 PM PDT 24
Peak memory 288928 kb
Host smart-e14b735a-1a6b-4412-a813-e5eced355392
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505838480 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg_stub_clk.505838480
Directory /workspace/37.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/37.alert_handler_ping_timeout.1581704767
Short name T310
Test name
Test status
Simulation time 36424179733 ps
CPU time 415.95 seconds
Started Jul 22 07:19:51 PM PDT 24
Finished Jul 22 07:26:57 PM PDT 24
Peak memory 248616 kb
Host smart-31279ed8-0cc8-40fe-831b-ab0298f2c627
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581704767 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_ping_timeout.1581704767
Directory /workspace/37.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_random_alerts.3346196705
Short name T623
Test name
Test status
Simulation time 119964086 ps
CPU time 15.79 seconds
Started Jul 22 07:19:13 PM PDT 24
Finished Jul 22 07:20:05 PM PDT 24
Peak memory 248644 kb
Host smart-1de8fc26-04c0-4121-b249-4b96b8ea4c6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33461
96705 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_alerts.3346196705
Directory /workspace/37.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/37.alert_handler_random_classes.2726110071
Short name T585
Test name
Test status
Simulation time 1413799940 ps
CPU time 20.76 seconds
Started Jul 22 07:19:12 PM PDT 24
Finished Jul 22 07:20:10 PM PDT 24
Peak memory 255484 kb
Host smart-a8d397c6-0761-428b-b731-e0e47ac7c083
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27261
10071 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_classes.2726110071
Directory /workspace/37.alert_handler_random_classes/latest

Test location /workspace/coverage/default/37.alert_handler_smoke.2395100002
Short name T19
Test name
Test status
Simulation time 334103741 ps
CPU time 7.03 seconds
Started Jul 22 07:19:12 PM PDT 24
Finished Jul 22 07:19:56 PM PDT 24
Peak memory 251116 kb
Host smart-0360d056-ab9f-4ff6-9ee0-fcaecbbfd10b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23951
00002 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_smoke.2395100002
Directory /workspace/37.alert_handler_smoke/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all.373313888
Short name T583
Test name
Test status
Simulation time 1742967355 ps
CPU time 87.4 seconds
Started Jul 22 07:19:32 PM PDT 24
Finished Jul 22 07:21:23 PM PDT 24
Peak memory 256788 kb
Host smart-0797d851-0615-4eea-b52d-ec84be7b644d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373313888 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_han
dler_stress_all.373313888
Directory /workspace/37.alert_handler_stress_all/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all_with_rand_reset.715009226
Short name T70
Test name
Test status
Simulation time 12249804797 ps
CPU time 828.86 seconds
Started Jul 22 07:19:34 PM PDT 24
Finished Jul 22 07:33:45 PM PDT 24
Peak memory 273324 kb
Host smart-174b8988-a878-462c-b5ab-f38a9b8fe80f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715009226 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 37.alert_handler_stress_all_with_rand_reset.715009226
Directory /workspace/37.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.alert_handler_entropy.648253543
Short name T61
Test name
Test status
Simulation time 18220047819 ps
CPU time 1300.31 seconds
Started Jul 22 07:19:32 PM PDT 24
Finished Jul 22 07:41:36 PM PDT 24
Peak memory 288648 kb
Host smart-1043dd5b-b3b8-45f3-a02e-555872a014e5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=648253543 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_entropy.648253543
Directory /workspace/38.alert_handler_entropy/latest

Test location /workspace/coverage/default/38.alert_handler_esc_alert_accum.2678134990
Short name T498
Test name
Test status
Simulation time 342076089 ps
CPU time 22.78 seconds
Started Jul 22 07:19:32 PM PDT 24
Finished Jul 22 07:20:18 PM PDT 24
Peak memory 256240 kb
Host smart-72cbda78-db35-4772-bddf-0a0513254c1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26781
34990 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_alert_accum.2678134990
Directory /workspace/38.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/38.alert_handler_esc_intr_timeout.3169295969
Short name T385
Test name
Test status
Simulation time 119774565 ps
CPU time 4.21 seconds
Started Jul 22 07:19:34 PM PDT 24
Finished Jul 22 07:20:00 PM PDT 24
Peak memory 240316 kb
Host smart-e968f9b7-1560-4192-a5fa-e168d8ddf36c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31692
95969 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_intr_timeout.3169295969
Directory /workspace/38.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_lpg.2004414377
Short name T628
Test name
Test status
Simulation time 624498464809 ps
CPU time 2140.82 seconds
Started Jul 22 07:19:32 PM PDT 24
Finished Jul 22 07:55:37 PM PDT 24
Peak memory 285464 kb
Host smart-3500bde5-a46f-4d31-828f-4fa68f71cbaf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2004414377 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg.2004414377
Directory /workspace/38.alert_handler_lpg/latest

Test location /workspace/coverage/default/38.alert_handler_lpg_stub_clk.2685242649
Short name T625
Test name
Test status
Simulation time 17299792024 ps
CPU time 947.11 seconds
Started Jul 22 07:19:34 PM PDT 24
Finished Jul 22 07:35:43 PM PDT 24
Peak memory 281344 kb
Host smart-666cf8c9-4d87-44be-957c-34493ebfd163
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2685242649 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg_stub_clk.2685242649
Directory /workspace/38.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/38.alert_handler_random_alerts.1437493396
Short name T542
Test name
Test status
Simulation time 299804958 ps
CPU time 6.76 seconds
Started Jul 22 07:19:33 PM PDT 24
Finished Jul 22 07:20:02 PM PDT 24
Peak memory 240364 kb
Host smart-e716ef07-eae6-413e-9af9-3e5c200261c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14374
93396 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_alerts.1437493396
Directory /workspace/38.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/38.alert_handler_random_classes.1686360634
Short name T118
Test name
Test status
Simulation time 619198080 ps
CPU time 28.14 seconds
Started Jul 22 07:19:48 PM PDT 24
Finished Jul 22 07:20:28 PM PDT 24
Peak memory 248080 kb
Host smart-a87965ce-9a2c-4ee6-88af-205b37e8d346
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16863
60634 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_classes.1686360634
Directory /workspace/38.alert_handler_random_classes/latest

Test location /workspace/coverage/default/38.alert_handler_sig_int_fail.1815086502
Short name T559
Test name
Test status
Simulation time 395440391 ps
CPU time 34.02 seconds
Started Jul 22 07:19:34 PM PDT 24
Finished Jul 22 07:20:30 PM PDT 24
Peak memory 249088 kb
Host smart-c94c9a6d-4ead-400f-ac6a-ada1dfe57afb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18150
86502 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_sig_int_fail.1815086502
Directory /workspace/38.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/38.alert_handler_smoke.1694941742
Short name T505
Test name
Test status
Simulation time 347967618 ps
CPU time 7.5 seconds
Started Jul 22 07:19:32 PM PDT 24
Finished Jul 22 07:20:03 PM PDT 24
Peak memory 254816 kb
Host smart-ae0afd81-f563-48ce-8ad3-26225023ac3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16949
41742 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_smoke.1694941742
Directory /workspace/38.alert_handler_smoke/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all.4023465707
Short name T697
Test name
Test status
Simulation time 9708603660 ps
CPU time 1050.22 seconds
Started Jul 22 07:19:33 PM PDT 24
Finished Jul 22 07:37:26 PM PDT 24
Peak memory 288760 kb
Host smart-20060a2f-bfa3-440b-8605-c5def2fc90f1
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023465707 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_ha
ndler_stress_all.4023465707
Directory /workspace/38.alert_handler_stress_all/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all_with_rand_reset.622189766
Short name T273
Test name
Test status
Simulation time 47010575916 ps
CPU time 3197.1 seconds
Started Jul 22 07:19:33 PM PDT 24
Finished Jul 22 08:13:13 PM PDT 24
Peak memory 289660 kb
Host smart-8e43254c-5347-467e-9b6c-3d664db07253
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622189766 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 38.alert_handler_stress_all_with_rand_reset.622189766
Directory /workspace/38.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.alert_handler_entropy.2985060623
Short name T300
Test name
Test status
Simulation time 186473009633 ps
CPU time 2107.13 seconds
Started Jul 22 07:19:39 PM PDT 24
Finished Jul 22 07:55:05 PM PDT 24
Peak memory 289068 kb
Host smart-af0c2a2f-4bb8-48dd-837b-0b336da7297d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985060623 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_entropy.2985060623
Directory /workspace/39.alert_handler_entropy/latest

Test location /workspace/coverage/default/39.alert_handler_esc_alert_accum.751744470
Short name T500
Test name
Test status
Simulation time 3312032549 ps
CPU time 54.92 seconds
Started Jul 22 07:19:33 PM PDT 24
Finished Jul 22 07:20:51 PM PDT 24
Peak memory 256828 kb
Host smart-192606b8-2a86-42aa-94a3-a127081ec124
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75174
4470 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_alert_accum.751744470
Directory /workspace/39.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/39.alert_handler_esc_intr_timeout.3871793411
Short name T386
Test name
Test status
Simulation time 203935431 ps
CPU time 18.15 seconds
Started Jul 22 07:19:34 PM PDT 24
Finished Jul 22 07:20:14 PM PDT 24
Peak memory 256372 kb
Host smart-639ab391-90ac-469d-aaf6-3371e8c1862d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38717
93411 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_intr_timeout.3871793411
Directory /workspace/39.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_lpg.2128655479
Short name T345
Test name
Test status
Simulation time 27257787538 ps
CPU time 1060.41 seconds
Started Jul 22 07:19:32 PM PDT 24
Finished Jul 22 07:37:36 PM PDT 24
Peak memory 272412 kb
Host smart-cdc3e982-99c7-46b8-8865-5c54abceef38
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128655479 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg.2128655479
Directory /workspace/39.alert_handler_lpg/latest

Test location /workspace/coverage/default/39.alert_handler_lpg_stub_clk.1268054940
Short name T115
Test name
Test status
Simulation time 39918538494 ps
CPU time 2343.88 seconds
Started Jul 22 07:19:33 PM PDT 24
Finished Jul 22 07:59:00 PM PDT 24
Peak memory 282856 kb
Host smart-52375dc3-a6c1-46e5-a65f-1719c6ea6429
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1268054940 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg_stub_clk.1268054940
Directory /workspace/39.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/39.alert_handler_random_alerts.56158891
Short name T416
Test name
Test status
Simulation time 431033739 ps
CPU time 25.74 seconds
Started Jul 22 07:19:33 PM PDT 24
Finished Jul 22 07:20:22 PM PDT 24
Peak memory 248676 kb
Host smart-752245e4-69bb-496e-ae5a-6d9f0d8fe418
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56158
891 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_alerts.56158891
Directory /workspace/39.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/39.alert_handler_random_classes.3266209004
Short name T429
Test name
Test status
Simulation time 311598927 ps
CPU time 20.7 seconds
Started Jul 22 07:19:32 PM PDT 24
Finished Jul 22 07:20:16 PM PDT 24
Peak memory 254952 kb
Host smart-20daec4a-e48a-41aa-9c22-319db9a32095
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32662
09004 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_classes.3266209004
Directory /workspace/39.alert_handler_random_classes/latest

Test location /workspace/coverage/default/39.alert_handler_sig_int_fail.1926621550
Short name T263
Test name
Test status
Simulation time 423758688 ps
CPU time 36.28 seconds
Started Jul 22 07:19:32 PM PDT 24
Finished Jul 22 07:20:32 PM PDT 24
Peak memory 248564 kb
Host smart-85e807a2-f727-406f-99ed-e15f04b91fe1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19266
21550 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_sig_int_fail.1926621550
Directory /workspace/39.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/39.alert_handler_smoke.3118456549
Short name T665
Test name
Test status
Simulation time 1094519871 ps
CPU time 21.65 seconds
Started Jul 22 07:19:34 PM PDT 24
Finished Jul 22 07:20:18 PM PDT 24
Peak memory 255676 kb
Host smart-3881f6d6-b4b0-4600-95d2-a79b40cea76f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31184
56549 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_smoke.3118456549
Directory /workspace/39.alert_handler_smoke/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all.979333578
Short name T627
Test name
Test status
Simulation time 2097825030 ps
CPU time 67.46 seconds
Started Jul 22 07:19:32 PM PDT 24
Finished Jul 22 07:21:03 PM PDT 24
Peak memory 256808 kb
Host smart-f74dea30-951f-4420-a974-92cec3765881
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979333578 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_han
dler_stress_all.979333578
Directory /workspace/39.alert_handler_stress_all/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all_with_rand_reset.3668344317
Short name T54
Test name
Test status
Simulation time 236466136090 ps
CPU time 2764.26 seconds
Started Jul 22 07:19:32 PM PDT 24
Finished Jul 22 08:06:00 PM PDT 24
Peak memory 304956 kb
Host smart-c0589b65-00b0-4c34-86ab-50c118df635e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668344317 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.alert_handler_stress_all_with_rand_reset.3668344317
Directory /workspace/39.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.alert_handler_alert_accum_saturation.1537654738
Short name T229
Test name
Test status
Simulation time 21834377 ps
CPU time 2.25 seconds
Started Jul 22 07:16:55 PM PDT 24
Finished Jul 22 07:18:01 PM PDT 24
Peak memory 248908 kb
Host smart-d8088d46-aa6c-463c-af3f-cb931ebcc60b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1537654738 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_alert_accum_saturation.1537654738
Directory /workspace/4.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/4.alert_handler_entropy.219045189
Short name T105
Test name
Test status
Simulation time 30172183626 ps
CPU time 692.33 seconds
Started Jul 22 07:16:55 PM PDT 24
Finished Jul 22 07:29:31 PM PDT 24
Peak memory 272628 kb
Host smart-5261165f-2fca-473f-b87c-08ab38ffd569
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219045189 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy.219045189
Directory /workspace/4.alert_handler_entropy/latest

Test location /workspace/coverage/default/4.alert_handler_entropy_stress.2282380353
Short name T703
Test name
Test status
Simulation time 954119176 ps
CPU time 13.26 seconds
Started Jul 22 07:17:50 PM PDT 24
Finished Jul 22 07:18:57 PM PDT 24
Peak memory 248588 kb
Host smart-1bc991d8-caa1-4a1c-8f13-7573bb936182
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2282380353 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy_stress.2282380353
Directory /workspace/4.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/4.alert_handler_esc_alert_accum.3689707434
Short name T83
Test name
Test status
Simulation time 2341086540 ps
CPU time 129.36 seconds
Started Jul 22 07:17:20 PM PDT 24
Finished Jul 22 07:20:30 PM PDT 24
Peak memory 256332 kb
Host smart-490667c7-a180-4066-b50a-a2e825b78503
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36897
07434 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_alert_accum.3689707434
Directory /workspace/4.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/4.alert_handler_esc_intr_timeout.1294299489
Short name T532
Test name
Test status
Simulation time 310699707 ps
CPU time 17.12 seconds
Started Jul 22 07:16:53 PM PDT 24
Finished Jul 22 07:18:15 PM PDT 24
Peak memory 256432 kb
Host smart-d96ea8d6-38f2-4570-b4da-13f888128ffe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12942
99489 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_intr_timeout.1294299489
Directory /workspace/4.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_lpg.1007435375
Short name T355
Test name
Test status
Simulation time 8456951110 ps
CPU time 666.28 seconds
Started Jul 22 07:17:51 PM PDT 24
Finished Jul 22 07:29:50 PM PDT 24
Peak memory 273112 kb
Host smart-cc220ffe-533e-46db-a4b8-c7c08baa55d2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007435375 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg.1007435375
Directory /workspace/4.alert_handler_lpg/latest

Test location /workspace/coverage/default/4.alert_handler_lpg_stub_clk.3979460652
Short name T120
Test name
Test status
Simulation time 10352599562 ps
CPU time 874.98 seconds
Started Jul 22 07:16:55 PM PDT 24
Finished Jul 22 07:32:34 PM PDT 24
Peak memory 288720 kb
Host smart-60998bff-5fea-43e6-a2b6-64f75bd16b58
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979460652 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg_stub_clk.3979460652
Directory /workspace/4.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/4.alert_handler_random_alerts.3152232385
Short name T706
Test name
Test status
Simulation time 51234027 ps
CPU time 4.31 seconds
Started Jul 22 07:16:54 PM PDT 24
Finished Jul 22 07:18:02 PM PDT 24
Peak memory 248588 kb
Host smart-5e00a235-b7c0-47a1-8bca-4673b10e2af8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31522
32385 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_alerts.3152232385
Directory /workspace/4.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/4.alert_handler_random_classes.3594714990
Short name T670
Test name
Test status
Simulation time 466837576 ps
CPU time 28.48 seconds
Started Jul 22 07:16:54 PM PDT 24
Finished Jul 22 07:18:27 PM PDT 24
Peak memory 255808 kb
Host smart-eb4e61a4-f68a-4821-a9b7-af776073ed33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35947
14990 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_classes.3594714990
Directory /workspace/4.alert_handler_random_classes/latest

Test location /workspace/coverage/default/4.alert_handler_sec_cm.91480396
Short name T12
Test name
Test status
Simulation time 844301793 ps
CPU time 11.58 seconds
Started Jul 22 07:16:54 PM PDT 24
Finished Jul 22 07:18:10 PM PDT 24
Peak memory 277004 kb
Host smart-42ba5669-d6b8-457c-a8bc-9764dd3dcf25
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=91480396 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sec_cm.91480396
Directory /workspace/4.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/4.alert_handler_sig_int_fail.3544021099
Short name T571
Test name
Test status
Simulation time 3281575818 ps
CPU time 46.24 seconds
Started Jul 22 07:16:52 PM PDT 24
Finished Jul 22 07:18:44 PM PDT 24
Peak memory 248412 kb
Host smart-5839ed82-91ef-4b06-9c2d-39bb5a226f2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35440
21099 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sig_int_fail.3544021099
Directory /workspace/4.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/4.alert_handler_smoke.476649133
Short name T481
Test name
Test status
Simulation time 1289270741 ps
CPU time 25.92 seconds
Started Jul 22 07:16:52 PM PDT 24
Finished Jul 22 07:18:23 PM PDT 24
Peak memory 255816 kb
Host smart-0713d6b9-652f-430d-80a0-80e35b5c0249
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47664
9133 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_smoke.476649133
Directory /workspace/4.alert_handler_smoke/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all.550252472
Short name T507
Test name
Test status
Simulation time 59164880898 ps
CPU time 3423.29 seconds
Started Jul 22 07:17:32 PM PDT 24
Finished Jul 22 08:15:32 PM PDT 24
Peak memory 289208 kb
Host smart-959e573d-a41a-4e89-83a4-c716ba2e0a47
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550252472 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_hand
ler_stress_all.550252472
Directory /workspace/4.alert_handler_stress_all/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all_with_rand_reset.3467728865
Short name T246
Test name
Test status
Simulation time 33051084957 ps
CPU time 2076.32 seconds
Started Jul 22 07:16:54 PM PDT 24
Finished Jul 22 07:52:35 PM PDT 24
Peak memory 288936 kb
Host smart-642ce6d8-4e31-438c-b8f2-5f398fe7eec2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467728865 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.alert_handler_stress_all_with_rand_reset.3467728865
Directory /workspace/4.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.alert_handler_entropy.2751048381
Short name T128
Test name
Test status
Simulation time 25097834170 ps
CPU time 1453.97 seconds
Started Jul 22 07:20:16 PM PDT 24
Finished Jul 22 07:44:40 PM PDT 24
Peak memory 289216 kb
Host smart-d5616f77-0367-4408-972f-52d73dd46bbd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751048381 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_entropy.2751048381
Directory /workspace/40.alert_handler_entropy/latest

Test location /workspace/coverage/default/40.alert_handler_esc_alert_accum.3441713390
Short name T73
Test name
Test status
Simulation time 1645022329 ps
CPU time 63.65 seconds
Started Jul 22 07:20:15 PM PDT 24
Finished Jul 22 07:21:28 PM PDT 24
Peak memory 255876 kb
Host smart-3a002996-d29e-45ad-86c8-9be2b1465ead
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34417
13390 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_alert_accum.3441713390
Directory /workspace/40.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/40.alert_handler_esc_intr_timeout.4139944892
Short name T434
Test name
Test status
Simulation time 2638465370 ps
CPU time 38.76 seconds
Started Jul 22 07:20:20 PM PDT 24
Finished Jul 22 07:21:07 PM PDT 24
Peak memory 248260 kb
Host smart-f72459a1-227d-4ac7-b328-d5ebb0f4d062
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41399
44892 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_intr_timeout.4139944892
Directory /workspace/40.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_lpg.1485074289
Short name T132
Test name
Test status
Simulation time 46624517894 ps
CPU time 969 seconds
Started Jul 22 07:20:21 PM PDT 24
Finished Jul 22 07:36:38 PM PDT 24
Peak memory 272648 kb
Host smart-38fab214-c060-4a51-8217-406d980eccd4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485074289 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg.1485074289
Directory /workspace/40.alert_handler_lpg/latest

Test location /workspace/coverage/default/40.alert_handler_lpg_stub_clk.3157669388
Short name T527
Test name
Test status
Simulation time 36425507268 ps
CPU time 2175.55 seconds
Started Jul 22 07:20:17 PM PDT 24
Finished Jul 22 07:56:42 PM PDT 24
Peak memory 283424 kb
Host smart-8b24dd8a-509a-4f37-83ef-59af3f03194b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157669388 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg_stub_clk.3157669388
Directory /workspace/40.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/40.alert_handler_ping_timeout.3895082078
Short name T79
Test name
Test status
Simulation time 4531477213 ps
CPU time 206.96 seconds
Started Jul 22 07:20:16 PM PDT 24
Finished Jul 22 07:23:51 PM PDT 24
Peak memory 248664 kb
Host smart-fe08c7eb-8a2d-46fb-b79d-6c53e5edc725
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3895082078 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_ping_timeout.3895082078
Directory /workspace/40.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_random_alerts.3020241155
Short name T469
Test name
Test status
Simulation time 4340835994 ps
CPU time 66.33 seconds
Started Jul 22 07:20:21 PM PDT 24
Finished Jul 22 07:21:35 PM PDT 24
Peak memory 248788 kb
Host smart-6982cea8-0171-4069-8b64-48bd3f3518bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30202
41155 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_alerts.3020241155
Directory /workspace/40.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/40.alert_handler_random_classes.3177669585
Short name T574
Test name
Test status
Simulation time 393802423 ps
CPU time 18.47 seconds
Started Jul 22 07:21:46 PM PDT 24
Finished Jul 22 07:22:42 PM PDT 24
Peak memory 248604 kb
Host smart-9625e316-3495-43ee-a76c-2418e014aba4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31776
69585 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_classes.3177669585
Directory /workspace/40.alert_handler_random_classes/latest

Test location /workspace/coverage/default/40.alert_handler_sig_int_fail.2346173333
Short name T624
Test name
Test status
Simulation time 905048468 ps
CPU time 60.43 seconds
Started Jul 22 07:20:18 PM PDT 24
Finished Jul 22 07:21:28 PM PDT 24
Peak memory 256000 kb
Host smart-7b7e500a-81ac-48a0-a501-0550956fb2eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23461
73333 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_sig_int_fail.2346173333
Directory /workspace/40.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/40.alert_handler_smoke.397247717
Short name T412
Test name
Test status
Simulation time 2891858802 ps
CPU time 38.99 seconds
Started Jul 22 07:19:42 PM PDT 24
Finished Jul 22 07:20:38 PM PDT 24
Peak memory 256832 kb
Host smart-33805dd2-c644-4361-9ee3-8d879daf231f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39724
7717 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_smoke.397247717
Directory /workspace/40.alert_handler_smoke/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all.219401539
Short name T112
Test name
Test status
Simulation time 14415976680 ps
CPU time 1151.34 seconds
Started Jul 22 07:20:18 PM PDT 24
Finished Jul 22 07:39:39 PM PDT 24
Peak memory 287524 kb
Host smart-510ac482-efd3-43c9-aae9-80dcecc7d714
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219401539 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_han
dler_stress_all.219401539
Directory /workspace/40.alert_handler_stress_all/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all_with_rand_reset.2566787906
Short name T679
Test name
Test status
Simulation time 58555674641 ps
CPU time 6434.61 seconds
Started Jul 22 07:20:15 PM PDT 24
Finished Jul 22 09:07:40 PM PDT 24
Peak memory 347452 kb
Host smart-625fa4da-990d-4ce1-903a-20bde0f450ef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566787906 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 40.alert_handler_stress_all_with_rand_reset.2566787906
Directory /workspace/40.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.alert_handler_entropy.1997404953
Short name T523
Test name
Test status
Simulation time 58899358352 ps
CPU time 1368.35 seconds
Started Jul 22 07:20:15 PM PDT 24
Finished Jul 22 07:43:11 PM PDT 24
Peak memory 288800 kb
Host smart-50a78852-fa57-4e18-8c75-b150b98f50e8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997404953 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_entropy.1997404953
Directory /workspace/41.alert_handler_entropy/latest

Test location /workspace/coverage/default/41.alert_handler_esc_alert_accum.4013261964
Short name T379
Test name
Test status
Simulation time 20069207882 ps
CPU time 251.53 seconds
Started Jul 22 07:20:14 PM PDT 24
Finished Jul 22 07:24:29 PM PDT 24
Peak memory 256736 kb
Host smart-af6f4856-bcb2-4b7e-ab29-9e5dbfa44dea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40132
61964 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_alert_accum.4013261964
Directory /workspace/41.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/41.alert_handler_esc_intr_timeout.2822802410
Short name T567
Test name
Test status
Simulation time 242993804 ps
CPU time 21.08 seconds
Started Jul 22 07:20:29 PM PDT 24
Finished Jul 22 07:20:53 PM PDT 24
Peak memory 256480 kb
Host smart-95ba18ed-f209-4975-b194-40397c1afc9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28228
02410 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_intr_timeout.2822802410
Directory /workspace/41.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_lpg.920686796
Short name T125
Test name
Test status
Simulation time 15402044719 ps
CPU time 1298.37 seconds
Started Jul 22 07:20:08 PM PDT 24
Finished Jul 22 07:41:50 PM PDT 24
Peak memory 288484 kb
Host smart-00f8e4c6-597f-4dbe-957c-b2fde5a911ed
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920686796 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg.920686796
Directory /workspace/41.alert_handler_lpg/latest

Test location /workspace/coverage/default/41.alert_handler_lpg_stub_clk.2802904445
Short name T656
Test name
Test status
Simulation time 52364295435 ps
CPU time 2730.3 seconds
Started Jul 22 07:21:46 PM PDT 24
Finished Jul 22 08:07:54 PM PDT 24
Peak memory 289336 kb
Host smart-5f85d559-ec3d-4a02-ab01-05efa8fe3d4c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802904445 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg_stub_clk.2802904445
Directory /workspace/41.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/41.alert_handler_ping_timeout.1673699444
Short name T329
Test name
Test status
Simulation time 5041504874 ps
CPU time 113.77 seconds
Started Jul 22 07:20:17 PM PDT 24
Finished Jul 22 07:22:20 PM PDT 24
Peak memory 248644 kb
Host smart-590400c6-568b-4763-972f-b98639c970cf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673699444 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_ping_timeout.1673699444
Directory /workspace/41.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_random_alerts.2632297598
Short name T674
Test name
Test status
Simulation time 241595725 ps
CPU time 18.78 seconds
Started Jul 22 07:20:17 PM PDT 24
Finished Jul 22 07:20:46 PM PDT 24
Peak memory 253176 kb
Host smart-f42eb4e2-5170-490b-8734-9d00ed92f953
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26322
97598 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_alerts.2632297598
Directory /workspace/41.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/41.alert_handler_random_classes.2939049458
Short name T685
Test name
Test status
Simulation time 1704782023 ps
CPU time 51.41 seconds
Started Jul 22 07:20:18 PM PDT 24
Finished Jul 22 07:21:19 PM PDT 24
Peak memory 248160 kb
Host smart-ea33a060-162d-4323-a9be-bbf50bc405b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29390
49458 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_classes.2939049458
Directory /workspace/41.alert_handler_random_classes/latest

Test location /workspace/coverage/default/41.alert_handler_sig_int_fail.1158097385
Short name T520
Test name
Test status
Simulation time 560436846 ps
CPU time 35.28 seconds
Started Jul 22 07:20:16 PM PDT 24
Finished Jul 22 07:21:00 PM PDT 24
Peak memory 248984 kb
Host smart-0ec8b730-e807-4789-88a1-bb618853112e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11580
97385 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_sig_int_fail.1158097385
Directory /workspace/41.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/41.alert_handler_smoke.4006601966
Short name T401
Test name
Test status
Simulation time 2559777583 ps
CPU time 41.04 seconds
Started Jul 22 07:20:17 PM PDT 24
Finished Jul 22 07:21:08 PM PDT 24
Peak memory 256616 kb
Host smart-f7da2c23-337f-431a-a714-63bba9e48327
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40066
01966 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_smoke.4006601966
Directory /workspace/41.alert_handler_smoke/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all.2935747464
Short name T281
Test name
Test status
Simulation time 39705436944 ps
CPU time 2543.44 seconds
Started Jul 22 07:20:16 PM PDT 24
Finished Jul 22 08:02:49 PM PDT 24
Peak memory 289152 kb
Host smart-d5a95c09-8f62-4351-a541-31a566b967f2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935747464 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_ha
ndler_stress_all.2935747464
Directory /workspace/41.alert_handler_stress_all/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all_with_rand_reset.334560443
Short name T248
Test name
Test status
Simulation time 66697527982 ps
CPU time 1017.27 seconds
Started Jul 22 07:20:14 PM PDT 24
Finished Jul 22 07:37:20 PM PDT 24
Peak memory 282880 kb
Host smart-a9fb87dd-09d6-4e5a-9678-ed770b1f60b6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334560443 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 41.alert_handler_stress_all_with_rand_reset.334560443
Directory /workspace/41.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.alert_handler_entropy.834248883
Short name T513
Test name
Test status
Simulation time 146212278793 ps
CPU time 2278.68 seconds
Started Jul 22 07:20:18 PM PDT 24
Finished Jul 22 07:58:26 PM PDT 24
Peak memory 281408 kb
Host smart-a811ff29-3b33-4895-8d55-0520eca3bd19
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834248883 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_entropy.834248883
Directory /workspace/42.alert_handler_entropy/latest

Test location /workspace/coverage/default/42.alert_handler_esc_alert_accum.1195261603
Short name T524
Test name
Test status
Simulation time 12825258621 ps
CPU time 215.84 seconds
Started Jul 22 07:20:17 PM PDT 24
Finished Jul 22 07:24:02 PM PDT 24
Peak memory 256184 kb
Host smart-8efbd6d3-8bd4-4a16-a696-bb7de75b6a88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11952
61603 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_alert_accum.1195261603
Directory /workspace/42.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/42.alert_handler_esc_intr_timeout.243506856
Short name T81
Test name
Test status
Simulation time 169021350 ps
CPU time 3.99 seconds
Started Jul 22 07:20:20 PM PDT 24
Finished Jul 22 07:20:33 PM PDT 24
Peak memory 240312 kb
Host smart-260ed277-b1ce-48f7-be32-70f7266fc90a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24350
6856 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_intr_timeout.243506856
Directory /workspace/42.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_lpg.117000889
Short name T545
Test name
Test status
Simulation time 24269940608 ps
CPU time 1214.05 seconds
Started Jul 22 07:20:18 PM PDT 24
Finished Jul 22 07:40:42 PM PDT 24
Peak memory 289080 kb
Host smart-80deccd5-01cb-465d-ae1d-5b3b6e713f19
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117000889 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg.117000889
Directory /workspace/42.alert_handler_lpg/latest

Test location /workspace/coverage/default/42.alert_handler_lpg_stub_clk.3111371943
Short name T540
Test name
Test status
Simulation time 34605677278 ps
CPU time 1576.31 seconds
Started Jul 22 07:20:18 PM PDT 24
Finished Jul 22 07:46:44 PM PDT 24
Peak memory 287960 kb
Host smart-00d2e520-398f-430f-ad78-ae3243c5639b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111371943 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg_stub_clk.3111371943
Directory /workspace/42.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/42.alert_handler_ping_timeout.3326970464
Short name T328
Test name
Test status
Simulation time 24125121775 ps
CPU time 272.81 seconds
Started Jul 22 07:20:15 PM PDT 24
Finished Jul 22 07:24:56 PM PDT 24
Peak memory 248444 kb
Host smart-a8d631a5-b1b4-472c-a4c7-73182a64d631
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3326970464 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_ping_timeout.3326970464
Directory /workspace/42.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_random_alerts.688310114
Short name T467
Test name
Test status
Simulation time 706176961 ps
CPU time 5.9 seconds
Started Jul 22 07:20:16 PM PDT 24
Finished Jul 22 07:20:31 PM PDT 24
Peak memory 248688 kb
Host smart-41538d40-748a-439c-b0ed-d96e4685dd6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68831
0114 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_alerts.688310114
Directory /workspace/42.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/42.alert_handler_random_classes.2242166654
Short name T472
Test name
Test status
Simulation time 52833998 ps
CPU time 4.43 seconds
Started Jul 22 07:20:18 PM PDT 24
Finished Jul 22 07:20:32 PM PDT 24
Peak memory 249104 kb
Host smart-b585b1a8-c314-43c8-af77-279113cdee8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22421
66654 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_classes.2242166654
Directory /workspace/42.alert_handler_random_classes/latest

Test location /workspace/coverage/default/42.alert_handler_sig_int_fail.3734419912
Short name T716
Test name
Test status
Simulation time 133078067 ps
CPU time 6.29 seconds
Started Jul 22 07:20:16 PM PDT 24
Finished Jul 22 07:20:31 PM PDT 24
Peak memory 248148 kb
Host smart-79e2f695-0e30-4ae8-aa2e-92d2369858b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37344
19912 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_sig_int_fail.3734419912
Directory /workspace/42.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/42.alert_handler_smoke.1558739089
Short name T88
Test name
Test status
Simulation time 2118652779 ps
CPU time 33.8 seconds
Started Jul 22 07:20:16 PM PDT 24
Finished Jul 22 07:20:58 PM PDT 24
Peak memory 256300 kb
Host smart-d7717a55-9864-4dcb-b30c-c624d9d5e5f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15587
39089 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_smoke.1558739089
Directory /workspace/42.alert_handler_smoke/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all.3977400262
Short name T271
Test name
Test status
Simulation time 314066615628 ps
CPU time 1877.56 seconds
Started Jul 22 07:20:17 PM PDT 24
Finished Jul 22 07:51:45 PM PDT 24
Peak memory 272912 kb
Host smart-8b24640a-ee80-4953-a095-61944bae18e4
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977400262 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_ha
ndler_stress_all.3977400262
Directory /workspace/42.alert_handler_stress_all/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all_with_rand_reset.352802442
Short name T459
Test name
Test status
Simulation time 34578944609 ps
CPU time 3260.87 seconds
Started Jul 22 07:20:16 PM PDT 24
Finished Jul 22 08:14:47 PM PDT 24
Peak memory 322172 kb
Host smart-f21733f0-a694-4d65-80d3-a7ed0947848b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352802442 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 42.alert_handler_stress_all_with_rand_reset.352802442
Directory /workspace/42.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.alert_handler_entropy.901177231
Short name T714
Test name
Test status
Simulation time 71426453692 ps
CPU time 2480.66 seconds
Started Jul 22 07:20:18 PM PDT 24
Finished Jul 22 08:01:48 PM PDT 24
Peak memory 289572 kb
Host smart-7f92394c-af84-4522-a71a-9e30117df5d1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901177231 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_entropy.901177231
Directory /workspace/43.alert_handler_entropy/latest

Test location /workspace/coverage/default/43.alert_handler_esc_alert_accum.2438243352
Short name T710
Test name
Test status
Simulation time 1049036701 ps
CPU time 61.32 seconds
Started Jul 22 07:20:20 PM PDT 24
Finished Jul 22 07:21:30 PM PDT 24
Peak memory 256052 kb
Host smart-ab03c8f5-957e-443e-9c72-eb7a24f2b044
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24382
43352 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_alert_accum.2438243352
Directory /workspace/43.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/43.alert_handler_esc_intr_timeout.3240240191
Short name T409
Test name
Test status
Simulation time 1837583235 ps
CPU time 66.18 seconds
Started Jul 22 07:20:17 PM PDT 24
Finished Jul 22 07:21:32 PM PDT 24
Peak memory 248120 kb
Host smart-af0f0023-7fee-46b7-965e-c927e01a4abf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32402
40191 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_intr_timeout.3240240191
Directory /workspace/43.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_lpg.576328168
Short name T347
Test name
Test status
Simulation time 33209379119 ps
CPU time 2113.39 seconds
Started Jul 22 07:20:17 PM PDT 24
Finished Jul 22 07:55:40 PM PDT 24
Peak memory 284020 kb
Host smart-f67be143-3733-428e-8b62-0f13551519ad
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576328168 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg.576328168
Directory /workspace/43.alert_handler_lpg/latest

Test location /workspace/coverage/default/43.alert_handler_lpg_stub_clk.646553117
Short name T499
Test name
Test status
Simulation time 251267122930 ps
CPU time 1925.13 seconds
Started Jul 22 07:20:17 PM PDT 24
Finished Jul 22 07:52:32 PM PDT 24
Peak memory 272640 kb
Host smart-18112879-70ef-4444-859f-7d24b011f9b5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646553117 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg_stub_clk.646553117
Directory /workspace/43.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/43.alert_handler_ping_timeout.732248578
Short name T630
Test name
Test status
Simulation time 24399519112 ps
CPU time 507 seconds
Started Jul 22 07:20:14 PM PDT 24
Finished Jul 22 07:28:45 PM PDT 24
Peak memory 248644 kb
Host smart-053a3d23-91eb-488f-ac7c-a56887a7ac70
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732248578 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_ping_timeout.732248578
Directory /workspace/43.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_random_alerts.3761792351
Short name T579
Test name
Test status
Simulation time 183725526 ps
CPU time 19.28 seconds
Started Jul 22 07:20:21 PM PDT 24
Finished Jul 22 07:20:49 PM PDT 24
Peak memory 248720 kb
Host smart-67dbbd94-84e5-4e47-bdf9-253714c830e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37617
92351 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_alerts.3761792351
Directory /workspace/43.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/43.alert_handler_random_classes.4049507379
Short name T617
Test name
Test status
Simulation time 940441871 ps
CPU time 64.98 seconds
Started Jul 22 07:20:14 PM PDT 24
Finished Jul 22 07:21:25 PM PDT 24
Peak memory 256296 kb
Host smart-3d3aeed8-b4e8-4611-8629-e2735435c501
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40495
07379 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_classes.4049507379
Directory /workspace/43.alert_handler_random_classes/latest

Test location /workspace/coverage/default/43.alert_handler_sig_int_fail.2590451981
Short name T502
Test name
Test status
Simulation time 1041520088 ps
CPU time 34 seconds
Started Jul 22 07:20:16 PM PDT 24
Finished Jul 22 07:21:00 PM PDT 24
Peak memory 248544 kb
Host smart-987f319b-f522-4f21-ac38-20c4ba0714f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25904
51981 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_sig_int_fail.2590451981
Directory /workspace/43.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/43.alert_handler_smoke.2190230964
Short name T214
Test name
Test status
Simulation time 5370850520 ps
CPU time 37.85 seconds
Started Jul 22 07:20:21 PM PDT 24
Finished Jul 22 07:21:07 PM PDT 24
Peak memory 249000 kb
Host smart-d653e938-e6d7-4659-a09f-e75ab7273cf5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21902
30964 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_smoke.2190230964
Directory /workspace/43.alert_handler_smoke/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all.3774055820
Short name T511
Test name
Test status
Simulation time 43368353601 ps
CPU time 2651.55 seconds
Started Jul 22 07:20:19 PM PDT 24
Finished Jul 22 08:04:40 PM PDT 24
Peak memory 298112 kb
Host smart-4bd62e13-9047-4577-8f00-81839e44ae67
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774055820 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_ha
ndler_stress_all.3774055820
Directory /workspace/43.alert_handler_stress_all/latest

Test location /workspace/coverage/default/44.alert_handler_entropy.4243101475
Short name T398
Test name
Test status
Simulation time 59831308466 ps
CPU time 1132.01 seconds
Started Jul 22 07:20:17 PM PDT 24
Finished Jul 22 07:39:19 PM PDT 24
Peak memory 272588 kb
Host smart-b8f06bc4-2a55-42f3-940d-5bff095805a4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243101475 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_entropy.4243101475
Directory /workspace/44.alert_handler_entropy/latest

Test location /workspace/coverage/default/44.alert_handler_esc_alert_accum.3116117089
Short name T239
Test name
Test status
Simulation time 11016134949 ps
CPU time 158.15 seconds
Started Jul 22 07:20:17 PM PDT 24
Finished Jul 22 07:23:05 PM PDT 24
Peak memory 250716 kb
Host smart-bbc3b5f0-805f-488c-91f5-01d02f920a26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31161
17089 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_alert_accum.3116117089
Directory /workspace/44.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/44.alert_handler_esc_intr_timeout.3235847577
Short name T426
Test name
Test status
Simulation time 2142650805 ps
CPU time 29.99 seconds
Started Jul 22 07:20:20 PM PDT 24
Finished Jul 22 07:20:59 PM PDT 24
Peak memory 255892 kb
Host smart-c935bd09-1b25-488b-a811-0c82bbd3c206
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32358
47577 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_intr_timeout.3235847577
Directory /workspace/44.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_lpg_stub_clk.381434672
Short name T563
Test name
Test status
Simulation time 13138884970 ps
CPU time 810.28 seconds
Started Jul 22 07:20:18 PM PDT 24
Finished Jul 22 07:33:58 PM PDT 24
Peak memory 273124 kb
Host smart-38e401a9-4b9c-4390-a367-6c1c4003cfe3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381434672 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg_stub_clk.381434672
Directory /workspace/44.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/44.alert_handler_ping_timeout.1669909252
Short name T319
Test name
Test status
Simulation time 22717319646 ps
CPU time 472.99 seconds
Started Jul 22 07:20:18 PM PDT 24
Finished Jul 22 07:28:20 PM PDT 24
Peak memory 248616 kb
Host smart-f1b7556e-cbff-4e69-958f-d2d8c87e7ddb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1669909252 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_ping_timeout.1669909252
Directory /workspace/44.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_random_alerts.875779112
Short name T131
Test name
Test status
Simulation time 1348942140 ps
CPU time 32.06 seconds
Started Jul 22 07:20:16 PM PDT 24
Finished Jul 22 07:20:57 PM PDT 24
Peak memory 256824 kb
Host smart-b95ab935-2175-4756-8a20-cec3112ef55a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87577
9112 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_alerts.875779112
Directory /workspace/44.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/44.alert_handler_random_classes.2981121144
Short name T64
Test name
Test status
Simulation time 14600891446 ps
CPU time 51.34 seconds
Started Jul 22 07:20:14 PM PDT 24
Finished Jul 22 07:21:13 PM PDT 24
Peak memory 255796 kb
Host smart-894312ba-46b8-4a9f-ba53-e7fc2772a13d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29811
21144 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_classes.2981121144
Directory /workspace/44.alert_handler_random_classes/latest

Test location /workspace/coverage/default/44.alert_handler_sig_int_fail.3651586757
Short name T280
Test name
Test status
Simulation time 798753502 ps
CPU time 50.22 seconds
Started Jul 22 07:20:17 PM PDT 24
Finished Jul 22 07:21:16 PM PDT 24
Peak memory 248100 kb
Host smart-2dbf2ef9-e860-4cd7-b2bb-f2fca3baf730
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36515
86757 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_sig_int_fail.3651586757
Directory /workspace/44.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/44.alert_handler_smoke.3842685525
Short name T129
Test name
Test status
Simulation time 567495405 ps
CPU time 25.15 seconds
Started Jul 22 07:20:29 PM PDT 24
Finished Jul 22 07:20:57 PM PDT 24
Peak memory 256076 kb
Host smart-af189d04-a17b-4384-9fb6-d4fd8f679b46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38426
85525 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_smoke.3842685525
Directory /workspace/44.alert_handler_smoke/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all.2566920989
Short name T702
Test name
Test status
Simulation time 99086243386 ps
CPU time 2131.52 seconds
Started Jul 22 07:20:21 PM PDT 24
Finished Jul 22 07:56:01 PM PDT 24
Peak memory 304968 kb
Host smart-548aab0e-0a30-4b37-8e90-2b313a29cd88
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566920989 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_ha
ndler_stress_all.2566920989
Directory /workspace/44.alert_handler_stress_all/latest

Test location /workspace/coverage/default/45.alert_handler_entropy.1990298049
Short name T580
Test name
Test status
Simulation time 22003698842 ps
CPU time 1008.4 seconds
Started Jul 22 07:23:22 PM PDT 24
Finished Jul 22 07:40:30 PM PDT 24
Peak memory 284104 kb
Host smart-3b1afd55-77a3-4c99-a4ee-98277df6a82c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990298049 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_entropy.1990298049
Directory /workspace/45.alert_handler_entropy/latest

Test location /workspace/coverage/default/45.alert_handler_esc_alert_accum.2387519136
Short name T626
Test name
Test status
Simulation time 16845397659 ps
CPU time 114.13 seconds
Started Jul 22 07:20:15 PM PDT 24
Finished Jul 22 07:22:18 PM PDT 24
Peak memory 256872 kb
Host smart-1e6bc40b-1863-4c34-b07b-1a7bfb16b712
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23875
19136 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_alert_accum.2387519136
Directory /workspace/45.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/45.alert_handler_esc_intr_timeout.3975451253
Short name T432
Test name
Test status
Simulation time 202240927 ps
CPU time 26 seconds
Started Jul 22 07:20:18 PM PDT 24
Finished Jul 22 07:20:53 PM PDT 24
Peak memory 248596 kb
Host smart-5312be96-3ff7-49e3-a084-72a75d231062
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39754
51253 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_intr_timeout.3975451253
Directory /workspace/45.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_lpg.3237688692
Short name T348
Test name
Test status
Simulation time 102365131144 ps
CPU time 1352.79 seconds
Started Jul 22 07:20:21 PM PDT 24
Finished Jul 22 07:43:02 PM PDT 24
Peak memory 273332 kb
Host smart-0ff8b26e-0966-4956-be1b-3c316ea7db6d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237688692 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg.3237688692
Directory /workspace/45.alert_handler_lpg/latest

Test location /workspace/coverage/default/45.alert_handler_lpg_stub_clk.2398643291
Short name T411
Test name
Test status
Simulation time 5512434748 ps
CPU time 606.9 seconds
Started Jul 22 07:20:20 PM PDT 24
Finished Jul 22 07:30:36 PM PDT 24
Peak memory 272356 kb
Host smart-1cecff26-03e9-442e-9863-72dc165f9610
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398643291 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg_stub_clk.2398643291
Directory /workspace/45.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/45.alert_handler_ping_timeout.2446131969
Short name T331
Test name
Test status
Simulation time 7955478923 ps
CPU time 256.2 seconds
Started Jul 22 07:20:29 PM PDT 24
Finished Jul 22 07:24:48 PM PDT 24
Peak memory 248620 kb
Host smart-df6b9643-72eb-44fc-ad3b-9077253a18f8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446131969 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_ping_timeout.2446131969
Directory /workspace/45.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_random_alerts.1720818829
Short name T82
Test name
Test status
Simulation time 256806627 ps
CPU time 20.22 seconds
Started Jul 22 07:20:20 PM PDT 24
Finished Jul 22 07:20:48 PM PDT 24
Peak memory 248576 kb
Host smart-ac2174a0-58e8-4b95-a0c2-008f47eec38b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17208
18829 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_alerts.1720818829
Directory /workspace/45.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/45.alert_handler_random_classes.362454856
Short name T464
Test name
Test status
Simulation time 2934214104 ps
CPU time 26.24 seconds
Started Jul 22 07:21:46 PM PDT 24
Finished Jul 22 07:22:50 PM PDT 24
Peak memory 256128 kb
Host smart-9e8fe7c4-caa2-4cf5-b81f-83e2330693f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36245
4856 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_classes.362454856
Directory /workspace/45.alert_handler_random_classes/latest

Test location /workspace/coverage/default/45.alert_handler_sig_int_fail.3345072731
Short name T664
Test name
Test status
Simulation time 205765824 ps
CPU time 13.86 seconds
Started Jul 22 07:20:29 PM PDT 24
Finished Jul 22 07:20:46 PM PDT 24
Peak memory 248240 kb
Host smart-25918b43-5bf4-46df-88c8-11a398bd6076
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33450
72731 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_sig_int_fail.3345072731
Directory /workspace/45.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/45.alert_handler_smoke.942315235
Short name T525
Test name
Test status
Simulation time 6104730579 ps
CPU time 64.18 seconds
Started Jul 22 07:21:44 PM PDT 24
Finished Jul 22 07:23:27 PM PDT 24
Peak memory 256856 kb
Host smart-ec662005-4d54-44f3-8f65-a16f203c804a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94231
5235 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_smoke.942315235
Directory /workspace/45.alert_handler_smoke/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all.3419096239
Short name T96
Test name
Test status
Simulation time 43947393019 ps
CPU time 1552.21 seconds
Started Jul 22 07:20:21 PM PDT 24
Finished Jul 22 07:46:22 PM PDT 24
Peak memory 289164 kb
Host smart-a06eff49-dd33-4f8a-9133-cdac326a5905
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419096239 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_ha
ndler_stress_all.3419096239
Directory /workspace/45.alert_handler_stress_all/latest

Test location /workspace/coverage/default/46.alert_handler_entropy.3708293382
Short name T552
Test name
Test status
Simulation time 23128796980 ps
CPU time 651.77 seconds
Started Jul 22 07:20:45 PM PDT 24
Finished Jul 22 07:31:52 PM PDT 24
Peak memory 273268 kb
Host smart-2dbef4fc-defa-4c9c-9dd7-3eb0f29075e5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708293382 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_entropy.3708293382
Directory /workspace/46.alert_handler_entropy/latest

Test location /workspace/coverage/default/46.alert_handler_esc_alert_accum.1519477100
Short name T443
Test name
Test status
Simulation time 642879778 ps
CPU time 46.78 seconds
Started Jul 22 07:20:45 PM PDT 24
Finished Jul 22 07:21:46 PM PDT 24
Peak memory 256016 kb
Host smart-6b4729ef-6ab3-4fec-a227-0cfcedcf8247
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15194
77100 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_alert_accum.1519477100
Directory /workspace/46.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/46.alert_handler_esc_intr_timeout.2202355697
Short name T614
Test name
Test status
Simulation time 145071603 ps
CPU time 10.12 seconds
Started Jul 22 07:20:45 PM PDT 24
Finished Jul 22 07:21:09 PM PDT 24
Peak memory 248676 kb
Host smart-49c81cc4-edfc-4e55-9090-13ee405feb08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22023
55697 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_intr_timeout.2202355697
Directory /workspace/46.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_lpg.1007121954
Short name T358
Test name
Test status
Simulation time 215979892497 ps
CPU time 1890.02 seconds
Started Jul 22 07:20:45 PM PDT 24
Finished Jul 22 07:52:29 PM PDT 24
Peak memory 273244 kb
Host smart-b3b73c80-d76f-4864-95f0-9aace3e77c2e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007121954 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg.1007121954
Directory /workspace/46.alert_handler_lpg/latest

Test location /workspace/coverage/default/46.alert_handler_lpg_stub_clk.415039564
Short name T539
Test name
Test status
Simulation time 37708303946 ps
CPU time 907.2 seconds
Started Jul 22 07:20:43 PM PDT 24
Finished Jul 22 07:36:00 PM PDT 24
Peak memory 272528 kb
Host smart-07e4da49-6c40-4c74-8af1-d9ef9887a069
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415039564 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg_stub_clk.415039564
Directory /workspace/46.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/46.alert_handler_ping_timeout.989009600
Short name T324
Test name
Test status
Simulation time 7102794289 ps
CPU time 105.16 seconds
Started Jul 22 07:20:44 PM PDT 24
Finished Jul 22 07:22:43 PM PDT 24
Peak memory 248344 kb
Host smart-7cdc9465-675d-46f6-aaca-169511059cad
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989009600 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_ping_timeout.989009600
Directory /workspace/46.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_random_alerts.2522665035
Short name T596
Test name
Test status
Simulation time 1215012013 ps
CPU time 67.72 seconds
Started Jul 22 07:20:29 PM PDT 24
Finished Jul 22 07:21:40 PM PDT 24
Peak memory 256012 kb
Host smart-7748a4b8-f1a9-4eb3-b88f-b7acfd9cdaa5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25226
65035 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_alerts.2522665035
Directory /workspace/46.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/46.alert_handler_random_classes.78254406
Short name T50
Test name
Test status
Simulation time 780003456 ps
CPU time 36.52 seconds
Started Jul 22 07:20:16 PM PDT 24
Finished Jul 22 07:21:01 PM PDT 24
Peak memory 248524 kb
Host smart-ad357bfe-f5cc-4311-9d93-5c2f77a6fbf4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78254
406 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_classes.78254406
Directory /workspace/46.alert_handler_random_classes/latest

Test location /workspace/coverage/default/46.alert_handler_sig_int_fail.286051969
Short name T84
Test name
Test status
Simulation time 8189285551 ps
CPU time 44.91 seconds
Started Jul 22 07:20:46 PM PDT 24
Finished Jul 22 07:21:50 PM PDT 24
Peak memory 248656 kb
Host smart-54c2f39c-0031-4892-98bc-35c427ef7dac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28605
1969 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_sig_int_fail.286051969
Directory /workspace/46.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/46.alert_handler_smoke.479363729
Short name T415
Test name
Test status
Simulation time 773161040 ps
CPU time 46.89 seconds
Started Jul 22 07:20:18 PM PDT 24
Finished Jul 22 07:21:14 PM PDT 24
Peak memory 249072 kb
Host smart-0ccf81e9-fd21-4b11-b0b7-78411164ca37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47936
3729 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_smoke.479363729
Directory /workspace/46.alert_handler_smoke/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all.3696726601
Short name T97
Test name
Test status
Simulation time 51092811892 ps
CPU time 2722.72 seconds
Started Jul 22 07:20:46 PM PDT 24
Finished Jul 22 08:06:28 PM PDT 24
Peak memory 289708 kb
Host smart-9f186823-26a8-4d10-a148-996662da307d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696726601 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_ha
ndler_stress_all.3696726601
Directory /workspace/46.alert_handler_stress_all/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all_with_rand_reset.393550695
Short name T245
Test name
Test status
Simulation time 28940809572 ps
CPU time 1745.01 seconds
Started Jul 22 07:20:43 PM PDT 24
Finished Jul 22 07:50:01 PM PDT 24
Peak memory 272044 kb
Host smart-38e93c65-01cf-46b3-8d92-8325031c6f18
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393550695 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 46.alert_handler_stress_all_with_rand_reset.393550695
Directory /workspace/46.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.alert_handler_entropy.1701086282
Short name T237
Test name
Test status
Simulation time 143380192106 ps
CPU time 1976.08 seconds
Started Jul 22 07:20:48 PM PDT 24
Finished Jul 22 07:54:07 PM PDT 24
Peak memory 282952 kb
Host smart-b317b627-5d3b-4566-9d28-69f847712e5a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701086282 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_entropy.1701086282
Directory /workspace/47.alert_handler_entropy/latest

Test location /workspace/coverage/default/47.alert_handler_esc_alert_accum.2222641289
Short name T408
Test name
Test status
Simulation time 262268892 ps
CPU time 17.28 seconds
Started Jul 22 07:20:49 PM PDT 24
Finished Jul 22 07:21:28 PM PDT 24
Peak memory 256292 kb
Host smart-8bdb502f-e3ca-40bb-bbaf-3ea1bf799d19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22226
41289 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_alert_accum.2222641289
Directory /workspace/47.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/47.alert_handler_esc_intr_timeout.2224906735
Short name T591
Test name
Test status
Simulation time 379252807 ps
CPU time 39.16 seconds
Started Jul 22 07:20:53 PM PDT 24
Finished Jul 22 07:21:58 PM PDT 24
Peak memory 249640 kb
Host smart-f8175941-45eb-4809-aed9-068f13efb5f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22249
06735 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_intr_timeout.2224906735
Directory /workspace/47.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_lpg.3352582303
Short name T72
Test name
Test status
Simulation time 12407792595 ps
CPU time 1029.13 seconds
Started Jul 22 07:20:49 PM PDT 24
Finished Jul 22 07:38:21 PM PDT 24
Peak memory 273240 kb
Host smart-34ecc776-f776-4d45-9e47-e59bdd36774e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3352582303 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg.3352582303
Directory /workspace/47.alert_handler_lpg/latest

Test location /workspace/coverage/default/47.alert_handler_lpg_stub_clk.1618876571
Short name T712
Test name
Test status
Simulation time 28624969980 ps
CPU time 2128.19 seconds
Started Jul 22 07:20:50 PM PDT 24
Finished Jul 22 07:56:42 PM PDT 24
Peak memory 286332 kb
Host smart-52724ea6-e179-4d66-8099-2c83e1045d4e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618876571 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg_stub_clk.1618876571
Directory /workspace/47.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/47.alert_handler_ping_timeout.1905769258
Short name T691
Test name
Test status
Simulation time 54548273756 ps
CPU time 704.07 seconds
Started Jul 22 07:20:46 PM PDT 24
Finished Jul 22 07:32:50 PM PDT 24
Peak memory 248660 kb
Host smart-a8418927-61b5-429a-8789-7196af78b5fa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905769258 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_ping_timeout.1905769258
Directory /workspace/47.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_random_alerts.3023653436
Short name T491
Test name
Test status
Simulation time 2892217540 ps
CPU time 43.33 seconds
Started Jul 22 07:21:05 PM PDT 24
Finished Jul 22 07:22:27 PM PDT 24
Peak memory 256780 kb
Host smart-2ee58526-7eb0-440b-a938-5b520d7f2408
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30236
53436 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_alerts.3023653436
Directory /workspace/47.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/47.alert_handler_random_classes.1617108443
Short name T569
Test name
Test status
Simulation time 1745081337 ps
CPU time 32.76 seconds
Started Jul 22 07:21:04 PM PDT 24
Finished Jul 22 07:22:16 PM PDT 24
Peak memory 248180 kb
Host smart-3f63463f-adb9-4006-9c51-54b683467c03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16171
08443 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_classes.1617108443
Directory /workspace/47.alert_handler_random_classes/latest

Test location /workspace/coverage/default/47.alert_handler_sig_int_fail.1277402053
Short name T268
Test name
Test status
Simulation time 1507360777 ps
CPU time 30.67 seconds
Started Jul 22 07:20:48 PM PDT 24
Finished Jul 22 07:21:39 PM PDT 24
Peak memory 248080 kb
Host smart-3db5cb5b-062d-4efa-909d-5604f28822d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12774
02053 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_sig_int_fail.1277402053
Directory /workspace/47.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/47.alert_handler_smoke.2001096079
Short name T403
Test name
Test status
Simulation time 3068561724 ps
CPU time 44.6 seconds
Started Jul 22 07:20:43 PM PDT 24
Finished Jul 22 07:21:39 PM PDT 24
Peak memory 256848 kb
Host smart-9c02fce1-3801-43ab-ac95-a747ba9d81c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20010
96079 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_smoke.2001096079
Directory /workspace/47.alert_handler_smoke/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all.3989583048
Short name T642
Test name
Test status
Simulation time 91429497275 ps
CPU time 2689.61 seconds
Started Jul 22 07:23:43 PM PDT 24
Finished Jul 22 08:08:57 PM PDT 24
Peak memory 298412 kb
Host smart-2e48b954-6b91-403b-bdb8-81aa289652d8
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989583048 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_ha
ndler_stress_all.3989583048
Directory /workspace/47.alert_handler_stress_all/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all_with_rand_reset.1971672919
Short name T669
Test name
Test status
Simulation time 18138035502 ps
CPU time 700.36 seconds
Started Jul 22 07:20:52 PM PDT 24
Finished Jul 22 07:32:58 PM PDT 24
Peak memory 272048 kb
Host smart-e4344836-5a56-42af-9482-3b83fd76cadc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971672919 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 47.alert_handler_stress_all_with_rand_reset.1971672919
Directory /workspace/47.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.alert_handler_entropy.238196549
Short name T470
Test name
Test status
Simulation time 341803243426 ps
CPU time 3120.03 seconds
Started Jul 22 07:24:04 PM PDT 24
Finished Jul 22 08:16:41 PM PDT 24
Peak memory 289384 kb
Host smart-99aeb755-0efc-4ad0-97fa-3d747b809d4b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238196549 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_entropy.238196549
Directory /workspace/48.alert_handler_entropy/latest

Test location /workspace/coverage/default/48.alert_handler_esc_alert_accum.1357084084
Short name T647
Test name
Test status
Simulation time 11056603827 ps
CPU time 101.96 seconds
Started Jul 22 07:20:49 PM PDT 24
Finished Jul 22 07:22:53 PM PDT 24
Peak memory 255980 kb
Host smart-411c57cf-3adb-42f2-aa6f-b9f731d3ba7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13570
84084 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_alert_accum.1357084084
Directory /workspace/48.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/48.alert_handler_esc_intr_timeout.1594321380
Short name T53
Test name
Test status
Simulation time 567663343 ps
CPU time 25.54 seconds
Started Jul 22 07:20:53 PM PDT 24
Finished Jul 22 07:21:46 PM PDT 24
Peak memory 248796 kb
Host smart-e7fc50aa-cf60-4d08-a1d0-960f2b66c116
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15943
21380 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_intr_timeout.1594321380
Directory /workspace/48.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_lpg.113511670
Short name T346
Test name
Test status
Simulation time 127723819270 ps
CPU time 1804.83 seconds
Started Jul 22 07:23:43 PM PDT 24
Finished Jul 22 07:54:11 PM PDT 24
Peak memory 272620 kb
Host smart-f532ccd3-644e-4db7-92ec-117b6091ee79
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113511670 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg.113511670
Directory /workspace/48.alert_handler_lpg/latest

Test location /workspace/coverage/default/48.alert_handler_lpg_stub_clk.287201203
Short name T133
Test name
Test status
Simulation time 20865953985 ps
CPU time 1233.03 seconds
Started Jul 22 07:23:55 PM PDT 24
Finished Jul 22 07:44:55 PM PDT 24
Peak memory 271944 kb
Host smart-e614adb1-4148-48b3-9139-d6412704d7f7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287201203 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg_stub_clk.287201203
Directory /workspace/48.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/48.alert_handler_ping_timeout.2749775078
Short name T572
Test name
Test status
Simulation time 2626883402 ps
CPU time 60.26 seconds
Started Jul 22 07:23:41 PM PDT 24
Finished Jul 22 07:25:05 PM PDT 24
Peak memory 248400 kb
Host smart-bbc902b9-0abc-410d-949f-deb7737e357d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749775078 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_ping_timeout.2749775078
Directory /workspace/48.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_random_alerts.2649690835
Short name T486
Test name
Test status
Simulation time 536271766 ps
CPU time 30.05 seconds
Started Jul 22 07:20:54 PM PDT 24
Finished Jul 22 07:21:51 PM PDT 24
Peak memory 248592 kb
Host smart-35ce6157-8b80-46d6-b440-4feeba9016ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26496
90835 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_alerts.2649690835
Directory /workspace/48.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/48.alert_handler_random_classes.3503756068
Short name T107
Test name
Test status
Simulation time 845859972 ps
CPU time 38.75 seconds
Started Jul 22 07:20:53 PM PDT 24
Finished Jul 22 07:21:59 PM PDT 24
Peak memory 248472 kb
Host smart-9acec0e4-84cc-4b7a-a625-45f640bd4bdc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35037
56068 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_classes.3503756068
Directory /workspace/48.alert_handler_random_classes/latest

Test location /workspace/coverage/default/48.alert_handler_sig_int_fail.2184103640
Short name T21
Test name
Test status
Simulation time 605952405 ps
CPU time 46.87 seconds
Started Jul 22 07:24:05 PM PDT 24
Finished Jul 22 07:25:25 PM PDT 24
Peak memory 256292 kb
Host smart-2c11ec89-5843-4d6e-8f6e-28f82230f5d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21841
03640 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_sig_int_fail.2184103640
Directory /workspace/48.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/48.alert_handler_smoke.2631549374
Short name T437
Test name
Test status
Simulation time 175873613 ps
CPU time 18.88 seconds
Started Jul 22 07:20:49 PM PDT 24
Finished Jul 22 07:21:30 PM PDT 24
Peak memory 255956 kb
Host smart-0a700f62-cf73-41d1-a725-a11ec4f34c11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26315
49374 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_smoke.2631549374
Directory /workspace/48.alert_handler_smoke/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all.2824293441
Short name T262
Test name
Test status
Simulation time 678856604 ps
CPU time 38.48 seconds
Started Jul 22 07:20:49 PM PDT 24
Finished Jul 22 07:21:49 PM PDT 24
Peak memory 249792 kb
Host smart-25bcd969-04b0-4a11-b44b-4753699e8309
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824293441 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_ha
ndler_stress_all.2824293441
Directory /workspace/48.alert_handler_stress_all/latest

Test location /workspace/coverage/default/49.alert_handler_entropy.2723336733
Short name T98
Test name
Test status
Simulation time 21483685840 ps
CPU time 1135.34 seconds
Started Jul 22 07:20:57 PM PDT 24
Finished Jul 22 07:40:24 PM PDT 24
Peak memory 272428 kb
Host smart-f4976c69-1bbc-4fd8-bea7-07b7fcf1ef27
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723336733 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_entropy.2723336733
Directory /workspace/49.alert_handler_entropy/latest

Test location /workspace/coverage/default/49.alert_handler_esc_alert_accum.737522975
Short name T622
Test name
Test status
Simulation time 967490577 ps
CPU time 105.8 seconds
Started Jul 22 07:20:57 PM PDT 24
Finished Jul 22 07:23:14 PM PDT 24
Peak memory 256312 kb
Host smart-e684d7df-0b56-4f73-b22f-d947810be19f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73752
2975 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_alert_accum.737522975
Directory /workspace/49.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/49.alert_handler_esc_intr_timeout.196260074
Short name T639
Test name
Test status
Simulation time 158506210 ps
CPU time 14.47 seconds
Started Jul 22 07:20:46 PM PDT 24
Finished Jul 22 07:21:19 PM PDT 24
Peak memory 248632 kb
Host smart-6a9a55e0-029f-4a5c-a6ac-fad795c62968
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19626
0074 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_intr_timeout.196260074
Directory /workspace/49.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_lpg.296966106
Short name T320
Test name
Test status
Simulation time 14259328830 ps
CPU time 802.17 seconds
Started Jul 22 07:20:57 PM PDT 24
Finished Jul 22 07:34:51 PM PDT 24
Peak memory 272668 kb
Host smart-a2d55519-6b24-4c47-ba56-22d210ade904
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296966106 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg.296966106
Directory /workspace/49.alert_handler_lpg/latest

Test location /workspace/coverage/default/49.alert_handler_lpg_stub_clk.4206204408
Short name T566
Test name
Test status
Simulation time 9340163998 ps
CPU time 922.31 seconds
Started Jul 22 07:20:57 PM PDT 24
Finished Jul 22 07:36:51 PM PDT 24
Peak memory 273260 kb
Host smart-30e18e67-00f9-4ae4-bb82-448b0ad1e596
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4206204408 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg_stub_clk.4206204408
Directory /workspace/49.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/49.alert_handler_ping_timeout.1926917219
Short name T341
Test name
Test status
Simulation time 28984078752 ps
CPU time 320.8 seconds
Started Jul 22 07:20:46 PM PDT 24
Finished Jul 22 07:26:23 PM PDT 24
Peak memory 248580 kb
Host smart-12e37d52-ab01-43d0-afc9-e7c2d764d8a8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926917219 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_ping_timeout.1926917219
Directory /workspace/49.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_random_alerts.3357798320
Short name T597
Test name
Test status
Simulation time 1590041996 ps
CPU time 44.21 seconds
Started Jul 22 07:20:54 PM PDT 24
Finished Jul 22 07:22:07 PM PDT 24
Peak memory 248580 kb
Host smart-9b473206-129a-416f-914a-dac17bf3c495
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33577
98320 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_alerts.3357798320
Directory /workspace/49.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/49.alert_handler_random_classes.1118433112
Short name T447
Test name
Test status
Simulation time 1192133563 ps
CPU time 19.75 seconds
Started Jul 22 07:20:57 PM PDT 24
Finished Jul 22 07:21:48 PM PDT 24
Peak memory 248276 kb
Host smart-c20875a3-84cd-4947-9390-7c90d22278b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11184
33112 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_classes.1118433112
Directory /workspace/49.alert_handler_random_classes/latest

Test location /workspace/coverage/default/49.alert_handler_sig_int_fail.1757993598
Short name T694
Test name
Test status
Simulation time 734454911 ps
CPU time 50.02 seconds
Started Jul 22 07:20:57 PM PDT 24
Finished Jul 22 07:22:19 PM PDT 24
Peak memory 256072 kb
Host smart-0fa53ad9-b065-4076-a6fa-7bab84bdca67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17579
93598 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_sig_int_fail.1757993598
Directory /workspace/49.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/49.alert_handler_smoke.527312020
Short name T568
Test name
Test status
Simulation time 2469708288 ps
CPU time 43.27 seconds
Started Jul 22 07:20:56 PM PDT 24
Finished Jul 22 07:22:10 PM PDT 24
Peak memory 256196 kb
Host smart-d20a02d1-5d70-4c28-bc45-0c2263a722b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52731
2020 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_smoke.527312020
Directory /workspace/49.alert_handler_smoke/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all.909411538
Short name T517
Test name
Test status
Simulation time 45249790266 ps
CPU time 1284.75 seconds
Started Jul 22 07:24:45 PM PDT 24
Finished Jul 22 07:47:09 PM PDT 24
Peak memory 289436 kb
Host smart-4b2ec077-e96e-4982-bd09-90a908a7eeae
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909411538 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_han
dler_stress_all.909411538
Directory /workspace/49.alert_handler_stress_all/latest

Test location /workspace/coverage/default/5.alert_handler_alert_accum_saturation.763162036
Short name T232
Test name
Test status
Simulation time 59878830 ps
CPU time 4.24 seconds
Started Jul 22 07:16:53 PM PDT 24
Finished Jul 22 07:18:02 PM PDT 24
Peak memory 248928 kb
Host smart-cb92675c-8010-4377-bdf9-542a1bc878a9
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=763162036 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_alert_accum_saturation.763162036
Directory /workspace/5.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/5.alert_handler_entropy.3412197962
Short name T80
Test name
Test status
Simulation time 18529345980 ps
CPU time 798.16 seconds
Started Jul 22 07:16:53 PM PDT 24
Finished Jul 22 07:31:16 PM PDT 24
Peak memory 267160 kb
Host smart-fa38a41d-f4d7-4d56-ac0a-31f806951659
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412197962 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy.3412197962
Directory /workspace/5.alert_handler_entropy/latest

Test location /workspace/coverage/default/5.alert_handler_entropy_stress.1289117694
Short name T537
Test name
Test status
Simulation time 270637549 ps
CPU time 12.37 seconds
Started Jul 22 07:16:56 PM PDT 24
Finished Jul 22 07:18:11 PM PDT 24
Peak memory 248472 kb
Host smart-85c8b9f2-7c17-4d6d-a8a7-4e97a2d13617
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1289117694 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy_stress.1289117694
Directory /workspace/5.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/5.alert_handler_esc_alert_accum.2803871501
Short name T252
Test name
Test status
Simulation time 1850295399 ps
CPU time 98.6 seconds
Started Jul 22 07:16:56 PM PDT 24
Finished Jul 22 07:19:38 PM PDT 24
Peak memory 256168 kb
Host smart-19a54182-070a-4c82-83e1-97af5f876080
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28038
71501 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_alert_accum.2803871501
Directory /workspace/5.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/5.alert_handler_esc_intr_timeout.3047196033
Short name T89
Test name
Test status
Simulation time 974678510 ps
CPU time 26.87 seconds
Started Jul 22 07:16:52 PM PDT 24
Finished Jul 22 07:18:24 PM PDT 24
Peak memory 255132 kb
Host smart-1578ea0d-88ec-41fb-b541-33513e2d9a1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30471
96033 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_intr_timeout.3047196033
Directory /workspace/5.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_lpg.1603555679
Short name T339
Test name
Test status
Simulation time 154208970832 ps
CPU time 2143.59 seconds
Started Jul 22 07:16:50 PM PDT 24
Finished Jul 22 07:53:40 PM PDT 24
Peak memory 282024 kb
Host smart-2666bec2-641e-4e05-b178-de323e61823b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603555679 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg.1603555679
Directory /workspace/5.alert_handler_lpg/latest

Test location /workspace/coverage/default/5.alert_handler_lpg_stub_clk.298202378
Short name T382
Test name
Test status
Simulation time 152704603300 ps
CPU time 1044.98 seconds
Started Jul 22 07:16:55 PM PDT 24
Finished Jul 22 07:35:24 PM PDT 24
Peak memory 272208 kb
Host smart-6386d863-4116-4923-9911-81a0f733436a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=298202378 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg_stub_clk.298202378
Directory /workspace/5.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/5.alert_handler_ping_timeout.47892182
Short name T318
Test name
Test status
Simulation time 72632520389 ps
CPU time 272.79 seconds
Started Jul 22 07:17:20 PM PDT 24
Finished Jul 22 07:22:54 PM PDT 24
Peak memory 248556 kb
Host smart-e5bcc195-c2f5-4a3f-9a52-fcb6c6ddfd0b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47892182 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_ping_timeout.47892182
Directory /workspace/5.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_random_alerts.1815030872
Short name T390
Test name
Test status
Simulation time 1365376191 ps
CPU time 46.42 seconds
Started Jul 22 07:16:52 PM PDT 24
Finished Jul 22 07:18:44 PM PDT 24
Peak memory 248636 kb
Host smart-fbed1458-b4f3-4656-ada0-bdfab2431564
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18150
30872 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_alerts.1815030872
Directory /workspace/5.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/5.alert_handler_random_classes.204156914
Short name T526
Test name
Test status
Simulation time 2187974097 ps
CPU time 39.25 seconds
Started Jul 22 07:16:58 PM PDT 24
Finished Jul 22 07:18:39 PM PDT 24
Peak memory 248704 kb
Host smart-501d2506-98d4-4f8b-9990-16f993cbbb14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20415
6914 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_classes.204156914
Directory /workspace/5.alert_handler_random_classes/latest

Test location /workspace/coverage/default/5.alert_handler_sig_int_fail.1688266317
Short name T652
Test name
Test status
Simulation time 253514105 ps
CPU time 25.18 seconds
Started Jul 22 07:16:56 PM PDT 24
Finished Jul 22 07:18:24 PM PDT 24
Peak memory 256752 kb
Host smart-607077ef-8a61-4b0f-8335-c1f595933d72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16882
66317 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_sig_int_fail.1688266317
Directory /workspace/5.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/5.alert_handler_smoke.4066069262
Short name T444
Test name
Test status
Simulation time 864639726 ps
CPU time 51.64 seconds
Started Jul 22 07:16:57 PM PDT 24
Finished Jul 22 07:18:51 PM PDT 24
Peak memory 248552 kb
Host smart-be95ca4e-2302-49a8-8033-62f255f001d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40660
69262 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_smoke.4066069262
Directory /workspace/5.alert_handler_smoke/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all.4001417798
Short name T514
Test name
Test status
Simulation time 103190611696 ps
CPU time 2922.48 seconds
Started Jul 22 07:16:51 PM PDT 24
Finished Jul 22 08:06:40 PM PDT 24
Peak memory 281312 kb
Host smart-93df66ba-c967-4bad-a9cb-f1f6a2aff334
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001417798 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_han
dler_stress_all.4001417798
Directory /workspace/5.alert_handler_stress_all/latest

Test location /workspace/coverage/default/6.alert_handler_alert_accum_saturation.1765596226
Short name T124
Test name
Test status
Simulation time 73107827 ps
CPU time 2.78 seconds
Started Jul 22 07:17:10 PM PDT 24
Finished Jul 22 07:18:13 PM PDT 24
Peak memory 248860 kb
Host smart-bb7b3038-bb84-421d-9ec9-94732a2dfbbc
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1765596226 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_alert_accum_saturation.1765596226
Directory /workspace/6.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/6.alert_handler_entropy.2839257413
Short name T30
Test name
Test status
Simulation time 41212091053 ps
CPU time 1135.3 seconds
Started Jul 22 07:16:54 PM PDT 24
Finished Jul 22 07:36:54 PM PDT 24
Peak memory 272380 kb
Host smart-1ec0e730-ab93-48c6-a667-e53329da208b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839257413 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy.2839257413
Directory /workspace/6.alert_handler_entropy/latest

Test location /workspace/coverage/default/6.alert_handler_entropy_stress.4148340564
Short name T528
Test name
Test status
Simulation time 1833128911 ps
CPU time 39.3 seconds
Started Jul 22 07:17:07 PM PDT 24
Finished Jul 22 07:18:48 PM PDT 24
Peak memory 248600 kb
Host smart-ca748c34-494c-427b-b4e1-7e05864d2065
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4148340564 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy_stress.4148340564
Directory /workspace/6.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/6.alert_handler_esc_alert_accum.223443
Short name T410
Test name
Test status
Simulation time 4394905109 ps
CPU time 87.76 seconds
Started Jul 22 07:16:56 PM PDT 24
Finished Jul 22 07:19:27 PM PDT 24
Peak memory 256824 kb
Host smart-614bd30b-b2e9-47d2-b655-15471604e2ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22344
3 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_alert_accum.223443
Directory /workspace/6.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/6.alert_handler_esc_intr_timeout.2949746891
Short name T93
Test name
Test status
Simulation time 516030256 ps
CPU time 32.62 seconds
Started Jul 22 07:16:59 PM PDT 24
Finished Jul 22 07:18:33 PM PDT 24
Peak memory 256376 kb
Host smart-b4c4eba2-e228-463f-9fce-7948c502d30f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29497
46891 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_intr_timeout.2949746891
Directory /workspace/6.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_lpg.2950318263
Short name T337
Test name
Test status
Simulation time 38874073761 ps
CPU time 1994.76 seconds
Started Jul 22 07:16:54 PM PDT 24
Finished Jul 22 07:51:13 PM PDT 24
Peak memory 273160 kb
Host smart-8018e348-fd6c-44e7-839b-da760b72b98a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2950318263 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg.2950318263
Directory /workspace/6.alert_handler_lpg/latest

Test location /workspace/coverage/default/6.alert_handler_lpg_stub_clk.1221769660
Short name T119
Test name
Test status
Simulation time 114333020465 ps
CPU time 1666.15 seconds
Started Jul 22 07:17:25 PM PDT 24
Finished Jul 22 07:46:11 PM PDT 24
Peak memory 286228 kb
Host smart-112a8d42-226f-4508-a397-97659aaa9df2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221769660 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg_stub_clk.1221769660
Directory /workspace/6.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/6.alert_handler_ping_timeout.3847340020
Short name T314
Test name
Test status
Simulation time 36861626167 ps
CPU time 390.31 seconds
Started Jul 22 07:16:53 PM PDT 24
Finished Jul 22 07:24:28 PM PDT 24
Peak memory 248724 kb
Host smart-2d313262-6ee5-4d20-aeba-c30c8b7feda4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847340020 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_ping_timeout.3847340020
Directory /workspace/6.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_random_alerts.2971066561
Short name T388
Test name
Test status
Simulation time 1090984516 ps
CPU time 7.66 seconds
Started Jul 22 07:16:55 PM PDT 24
Finished Jul 22 07:18:06 PM PDT 24
Peak memory 254000 kb
Host smart-cc4e5706-7a3d-44a4-9cdc-22caa2ce752c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29710
66561 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_alerts.2971066561
Directory /workspace/6.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/6.alert_handler_sig_int_fail.2970896007
Short name T259
Test name
Test status
Simulation time 280783021 ps
CPU time 18.32 seconds
Started Jul 22 07:16:55 PM PDT 24
Finished Jul 22 07:18:17 PM PDT 24
Peak memory 256148 kb
Host smart-aea18b79-c54f-457b-959c-32cd5728d58c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29708
96007 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_sig_int_fail.2970896007
Directory /workspace/6.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/6.alert_handler_smoke.2329920517
Short name T578
Test name
Test status
Simulation time 340012457 ps
CPU time 22.18 seconds
Started Jul 22 07:16:56 PM PDT 24
Finished Jul 22 07:18:21 PM PDT 24
Peak memory 256776 kb
Host smart-bae82a71-bae6-458f-8efd-1de604ccc5c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23299
20517 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_smoke.2329920517
Directory /workspace/6.alert_handler_smoke/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all.1037542386
Short name T672
Test name
Test status
Simulation time 21312603611 ps
CPU time 221.16 seconds
Started Jul 22 07:17:08 PM PDT 24
Finished Jul 22 07:21:51 PM PDT 24
Peak memory 256880 kb
Host smart-aafb152b-4a71-4c2a-bfee-c45c774bacae
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037542386 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_han
dler_stress_all.1037542386
Directory /workspace/6.alert_handler_stress_all/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all_with_rand_reset.1001170714
Short name T65
Test name
Test status
Simulation time 258831505999 ps
CPU time 4482.79 seconds
Started Jul 22 07:17:07 PM PDT 24
Finished Jul 22 08:32:52 PM PDT 24
Peak memory 305756 kb
Host smart-7ba5ae5d-c968-453b-8542-364081e63c4a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001170714 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 6.alert_handler_stress_all_with_rand_reset.1001170714
Directory /workspace/6.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.alert_handler_alert_accum_saturation.2922701989
Short name T219
Test name
Test status
Simulation time 52072768 ps
CPU time 2.76 seconds
Started Jul 22 07:17:30 PM PDT 24
Finished Jul 22 07:18:30 PM PDT 24
Peak memory 248864 kb
Host smart-1f3fa614-4b82-487f-8656-57aced83534d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2922701989 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_alert_accum_saturation.2922701989
Directory /workspace/7.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/7.alert_handler_entropy.425192501
Short name T95
Test name
Test status
Simulation time 38983066657 ps
CPU time 2316.56 seconds
Started Jul 22 07:17:10 PM PDT 24
Finished Jul 22 07:56:47 PM PDT 24
Peak memory 288528 kb
Host smart-cbc57e3b-f9d1-43f2-becf-2045b7918c35
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=425192501 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy.425192501
Directory /workspace/7.alert_handler_entropy/latest

Test location /workspace/coverage/default/7.alert_handler_entropy_stress.417862288
Short name T42
Test name
Test status
Simulation time 1274277769 ps
CPU time 53.83 seconds
Started Jul 22 07:17:10 PM PDT 24
Finished Jul 22 07:19:05 PM PDT 24
Peak memory 248564 kb
Host smart-baf6a50c-6130-484e-b765-4185b53b8c00
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=417862288 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy_stress.417862288
Directory /workspace/7.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/7.alert_handler_esc_alert_accum.370937685
Short name T387
Test name
Test status
Simulation time 1805537492 ps
CPU time 34.17 seconds
Started Jul 22 07:17:09 PM PDT 24
Finished Jul 22 07:18:44 PM PDT 24
Peak memory 256680 kb
Host smart-4c333105-5c3e-4b16-92d5-214f98fc48cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37093
7685 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_alert_accum.370937685
Directory /workspace/7.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/7.alert_handler_esc_intr_timeout.3672483311
Short name T490
Test name
Test status
Simulation time 949461215 ps
CPU time 17.94 seconds
Started Jul 22 07:17:18 PM PDT 24
Finished Jul 22 07:18:34 PM PDT 24
Peak memory 248404 kb
Host smart-95f51381-dd80-4b0a-a793-c083e2e11456
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36724
83311 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_intr_timeout.3672483311
Directory /workspace/7.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_lpg.265046506
Short name T240
Test name
Test status
Simulation time 8407573840 ps
CPU time 711.6 seconds
Started Jul 22 07:17:07 PM PDT 24
Finished Jul 22 07:30:01 PM PDT 24
Peak memory 273176 kb
Host smart-cf85fa0e-027f-46a9-8bc8-8bc53726f07b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=265046506 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg.265046506
Directory /workspace/7.alert_handler_lpg/latest

Test location /workspace/coverage/default/7.alert_handler_lpg_stub_clk.3285385092
Short name T562
Test name
Test status
Simulation time 49475284885 ps
CPU time 1416.53 seconds
Started Jul 22 07:18:10 PM PDT 24
Finished Jul 22 07:42:37 PM PDT 24
Peak memory 271980 kb
Host smart-2cbdd9b4-f9ef-4334-86a3-91e935b39c6e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3285385092 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg_stub_clk.3285385092
Directory /workspace/7.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/7.alert_handler_ping_timeout.1499898031
Short name T251
Test name
Test status
Simulation time 36870828255 ps
CPU time 369.09 seconds
Started Jul 22 07:17:12 PM PDT 24
Finished Jul 22 07:24:21 PM PDT 24
Peak memory 248656 kb
Host smart-85aa1692-1299-465d-9dad-8326d271fa1c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1499898031 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_ping_timeout.1499898031
Directory /workspace/7.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_random_alerts.1320941048
Short name T47
Test name
Test status
Simulation time 1280091335 ps
CPU time 29.39 seconds
Started Jul 22 07:17:26 PM PDT 24
Finished Jul 22 07:18:55 PM PDT 24
Peak memory 256132 kb
Host smart-d72835bd-f352-495b-b185-eee45d37d7f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13209
41048 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_alerts.1320941048
Directory /workspace/7.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/7.alert_handler_random_classes.477754089
Short name T301
Test name
Test status
Simulation time 965344665 ps
CPU time 42.09 seconds
Started Jul 22 07:17:12 PM PDT 24
Finished Jul 22 07:18:53 PM PDT 24
Peak memory 256348 kb
Host smart-1a265147-5552-41ec-9ea3-d87db05f52e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47775
4089 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_classes.477754089
Directory /workspace/7.alert_handler_random_classes/latest

Test location /workspace/coverage/default/7.alert_handler_sig_int_fail.736837529
Short name T25
Test name
Test status
Simulation time 4394075909 ps
CPU time 62.26 seconds
Started Jul 22 07:17:26 PM PDT 24
Finished Jul 22 07:19:28 PM PDT 24
Peak memory 256520 kb
Host smart-a2679c69-9ca7-4c9c-9533-3f1025a417e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73683
7529 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_sig_int_fail.736837529
Directory /workspace/7.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/7.alert_handler_smoke.3322645710
Short name T378
Test name
Test status
Simulation time 4189052797 ps
CPU time 58.75 seconds
Started Jul 22 07:17:25 PM PDT 24
Finished Jul 22 07:19:23 PM PDT 24
Peak memory 256828 kb
Host smart-c46ed1d1-2b2b-4c02-bc30-91482b05eeb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33226
45710 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_smoke.3322645710
Directory /workspace/7.alert_handler_smoke/latest

Test location /workspace/coverage/default/8.alert_handler_alert_accum_saturation.1124377269
Short name T228
Test name
Test status
Simulation time 41832318 ps
CPU time 2.4 seconds
Started Jul 22 07:17:10 PM PDT 24
Finished Jul 22 07:18:13 PM PDT 24
Peak memory 248804 kb
Host smart-dbc481ea-0e8c-42d3-999e-22dc89d2666f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1124377269 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_alert_accum_saturation.1124377269
Directory /workspace/8.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/8.alert_handler_entropy.1733175099
Short name T516
Test name
Test status
Simulation time 146953883629 ps
CPU time 2272.2 seconds
Started Jul 22 07:17:06 PM PDT 24
Finished Jul 22 07:56:00 PM PDT 24
Peak memory 273196 kb
Host smart-eae1fdf2-a55e-44db-a92a-a13dc32824a3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733175099 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy.1733175099
Directory /workspace/8.alert_handler_entropy/latest

Test location /workspace/coverage/default/8.alert_handler_entropy_stress.2060842224
Short name T661
Test name
Test status
Simulation time 552228834 ps
CPU time 13.14 seconds
Started Jul 22 07:17:43 PM PDT 24
Finished Jul 22 07:18:49 PM PDT 24
Peak memory 248560 kb
Host smart-a60304bc-f451-4611-b9e4-35cf66de6207
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2060842224 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy_stress.2060842224
Directory /workspace/8.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/8.alert_handler_esc_alert_accum.884501475
Short name T421
Test name
Test status
Simulation time 66332044212 ps
CPU time 267.39 seconds
Started Jul 22 07:17:05 PM PDT 24
Finished Jul 22 07:22:35 PM PDT 24
Peak memory 256324 kb
Host smart-ad4c4fdd-a394-4190-b24c-4952e2f849ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88450
1475 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_alert_accum.884501475
Directory /workspace/8.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/8.alert_handler_esc_intr_timeout.3954526401
Short name T461
Test name
Test status
Simulation time 620252926 ps
CPU time 40.64 seconds
Started Jul 22 07:17:26 PM PDT 24
Finished Jul 22 07:19:06 PM PDT 24
Peak memory 256456 kb
Host smart-68015115-4e5b-4751-94b1-361ae4bcab6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39545
26401 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_intr_timeout.3954526401
Directory /workspace/8.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_lpg.1525293948
Short name T610
Test name
Test status
Simulation time 179419030948 ps
CPU time 1417.46 seconds
Started Jul 22 07:17:10 PM PDT 24
Finished Jul 22 07:41:48 PM PDT 24
Peak memory 289436 kb
Host smart-4bd35454-7d43-4d87-80b7-057ad5e08ba6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525293948 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg.1525293948
Directory /workspace/8.alert_handler_lpg/latest

Test location /workspace/coverage/default/8.alert_handler_lpg_stub_clk.3559628884
Short name T407
Test name
Test status
Simulation time 37353201736 ps
CPU time 2197.63 seconds
Started Jul 22 07:17:10 PM PDT 24
Finished Jul 22 07:54:49 PM PDT 24
Peak memory 287224 kb
Host smart-5eece7b0-64dc-48bf-9a9f-5eec2e3fb5ec
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559628884 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg_stub_clk.3559628884
Directory /workspace/8.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/8.alert_handler_ping_timeout.1489666024
Short name T718
Test name
Test status
Simulation time 3087868626 ps
CPU time 134.38 seconds
Started Jul 22 07:17:07 PM PDT 24
Finished Jul 22 07:20:23 PM PDT 24
Peak memory 248728 kb
Host smart-780b8baa-5614-48c7-986c-84e42c2f5e4f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489666024 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_ping_timeout.1489666024
Directory /workspace/8.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_random_alerts.2125515669
Short name T43
Test name
Test status
Simulation time 3017602439 ps
CPU time 37.99 seconds
Started Jul 22 07:17:06 PM PDT 24
Finished Jul 22 07:18:46 PM PDT 24
Peak memory 256884 kb
Host smart-eaea6d76-a5bd-42be-9ec1-69b0b871a715
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21255
15669 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_alerts.2125515669
Directory /workspace/8.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/8.alert_handler_random_classes.3623861128
Short name T707
Test name
Test status
Simulation time 412679278 ps
CPU time 10.21 seconds
Started Jul 22 07:17:44 PM PDT 24
Finished Jul 22 07:18:49 PM PDT 24
Peak memory 254668 kb
Host smart-a39af16d-201a-4c63-9a7d-fb19378e38e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36238
61128 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_classes.3623861128
Directory /workspace/8.alert_handler_random_classes/latest

Test location /workspace/coverage/default/8.alert_handler_sig_int_fail.1340476904
Short name T49
Test name
Test status
Simulation time 118628702 ps
CPU time 15.76 seconds
Started Jul 22 07:17:25 PM PDT 24
Finished Jul 22 07:18:39 PM PDT 24
Peak memory 256424 kb
Host smart-20ee8846-9431-4268-9834-d7456133bd87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13404
76904 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_sig_int_fail.1340476904
Directory /workspace/8.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/8.alert_handler_smoke.639731142
Short name T450
Test name
Test status
Simulation time 396660450 ps
CPU time 8.65 seconds
Started Jul 22 07:17:18 PM PDT 24
Finished Jul 22 07:18:25 PM PDT 24
Peak memory 252696 kb
Host smart-92517eba-49db-4122-b140-69f1e2dfb11f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63973
1142 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_smoke.639731142
Directory /workspace/8.alert_handler_smoke/latest

Test location /workspace/coverage/default/9.alert_handler_alert_accum_saturation.1527093139
Short name T222
Test name
Test status
Simulation time 16139057 ps
CPU time 2.21 seconds
Started Jul 22 07:17:13 PM PDT 24
Finished Jul 22 07:18:14 PM PDT 24
Peak memory 248940 kb
Host smart-e618a15a-4a2f-4112-9d97-504b00cef43e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1527093139 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_alert_accum_saturation.1527093139
Directory /workspace/9.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/9.alert_handler_entropy.2840277965
Short name T114
Test name
Test status
Simulation time 143285203231 ps
CPU time 1591.34 seconds
Started Jul 22 07:17:30 PM PDT 24
Finished Jul 22 07:44:58 PM PDT 24
Peak memory 272540 kb
Host smart-30329ce8-34ed-4980-9a19-2642d2586e31
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840277965 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy.2840277965
Directory /workspace/9.alert_handler_entropy/latest

Test location /workspace/coverage/default/9.alert_handler_entropy_stress.2395230568
Short name T478
Test name
Test status
Simulation time 4034518388 ps
CPU time 46.82 seconds
Started Jul 22 07:17:26 PM PDT 24
Finished Jul 22 07:19:12 PM PDT 24
Peak memory 248764 kb
Host smart-b643f41d-44e3-4bac-8e2c-d94b99195366
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2395230568 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy_stress.2395230568
Directory /workspace/9.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/9.alert_handler_esc_alert_accum.702341284
Short name T454
Test name
Test status
Simulation time 6761082293 ps
CPU time 144.77 seconds
Started Jul 22 07:17:12 PM PDT 24
Finished Jul 22 07:20:36 PM PDT 24
Peak memory 256876 kb
Host smart-aae10e18-2986-444b-b28d-69cb8935741e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70234
1284 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_alert_accum.702341284
Directory /workspace/9.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/9.alert_handler_esc_intr_timeout.1868017504
Short name T538
Test name
Test status
Simulation time 317454759 ps
CPU time 13.24 seconds
Started Jul 22 07:17:18 PM PDT 24
Finished Jul 22 07:18:29 PM PDT 24
Peak memory 256644 kb
Host smart-90acd126-2c37-417f-84cb-7751018ff176
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18680
17504 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_intr_timeout.1868017504
Directory /workspace/9.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_lpg.270853956
Short name T533
Test name
Test status
Simulation time 24623441999 ps
CPU time 949.43 seconds
Started Jul 22 07:17:04 PM PDT 24
Finished Jul 22 07:33:55 PM PDT 24
Peak memory 269156 kb
Host smart-c0533f10-da5e-4bbc-b316-8e39b8b8a0c6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=270853956 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg.270853956
Directory /workspace/9.alert_handler_lpg/latest

Test location /workspace/coverage/default/9.alert_handler_lpg_stub_clk.2755122735
Short name T442
Test name
Test status
Simulation time 56516995399 ps
CPU time 658.69 seconds
Started Jul 22 07:17:30 PM PDT 24
Finished Jul 22 07:29:26 PM PDT 24
Peak memory 273088 kb
Host smart-74899ffa-f5a2-4bde-9c72-fb6f57afa398
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755122735 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg_stub_clk.2755122735
Directory /workspace/9.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/9.alert_handler_ping_timeout.441882762
Short name T633
Test name
Test status
Simulation time 50838927822 ps
CPU time 274.6 seconds
Started Jul 22 07:17:10 PM PDT 24
Finished Jul 22 07:22:45 PM PDT 24
Peak memory 248736 kb
Host smart-1814ca75-b453-4785-8486-453a521faa7d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441882762 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_ping_timeout.441882762
Directory /workspace/9.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_random_alerts.3616625644
Short name T38
Test name
Test status
Simulation time 375388201 ps
CPU time 24.37 seconds
Started Jul 22 07:17:10 PM PDT 24
Finished Jul 22 07:18:34 PM PDT 24
Peak memory 256084 kb
Host smart-a65a4cb1-3b1c-49e2-9444-6ffcd4557a71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36166
25644 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_alerts.3616625644
Directory /workspace/9.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/9.alert_handler_random_classes.2999836144
Short name T286
Test name
Test status
Simulation time 1322270083 ps
CPU time 30.01 seconds
Started Jul 22 07:17:08 PM PDT 24
Finished Jul 22 07:18:40 PM PDT 24
Peak memory 248112 kb
Host smart-960da5b0-58be-4549-8ff8-a02fbcf87b41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29998
36144 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_classes.2999836144
Directory /workspace/9.alert_handler_random_classes/latest

Test location /workspace/coverage/default/9.alert_handler_sig_int_fail.1129960180
Short name T646
Test name
Test status
Simulation time 14309990873 ps
CPU time 44.88 seconds
Started Jul 22 07:17:10 PM PDT 24
Finished Jul 22 07:18:56 PM PDT 24
Peak memory 248776 kb
Host smart-e790f3cc-dc8c-41b1-a162-c22f1c72c847
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11299
60180 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_sig_int_fail.1129960180
Directory /workspace/9.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/9.alert_handler_smoke.548810715
Short name T392
Test name
Test status
Simulation time 1034898851 ps
CPU time 56.21 seconds
Started Jul 22 07:17:27 PM PDT 24
Finished Jul 22 07:19:22 PM PDT 24
Peak memory 248940 kb
Host smart-56860648-23ad-4747-9865-9f5d55f33110
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54881
0715 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_smoke.548810715
Directory /workspace/9.alert_handler_smoke/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all.1632829188
Short name T59
Test name
Test status
Simulation time 12402993412 ps
CPU time 1032.57 seconds
Started Jul 22 07:17:10 PM PDT 24
Finished Jul 22 07:35:23 PM PDT 24
Peak memory 283856 kb
Host smart-734dd123-ab5e-4f49-9ea4-a84283f2c886
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632829188 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_han
dler_stress_all.1632829188
Directory /workspace/9.alert_handler_stress_all/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all_with_rand_reset.3812935890
Short name T123
Test name
Test status
Simulation time 91573924141 ps
CPU time 2556.76 seconds
Started Jul 22 07:17:30 PM PDT 24
Finished Jul 22 08:01:04 PM PDT 24
Peak memory 305032 kb
Host smart-88b83f40-ac0c-469a-8692-0a836cb81625
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812935890 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 9.alert_handler_stress_all_with_rand_reset.3812935890
Directory /workspace/9.alert_handler_stress_all_with_rand_reset/latest
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