Group : alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg
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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 10 0 10 100.00
Crosses 16 0 16 100.00


Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
class_index_cp 4 0 4 100.00 100 1 1 0
esc_index_cp 4 0 4 100.00 100 1 1 0
loc_alert_cause_cp 2 0 2 100.00 100 1 1 0


Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
loc_alert_cause_cross_alert_index 8 0 8 100.00 100 1 1 0
loc_alert_cause_cross_class_index 8 0 8 100.00 100 1 1 0


Summary for Variable class_index_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 4 0 4 100.00


User Defined Bins for class_index_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
il 0 Illegal


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
class_i[0x0] 70241 1 T3 176 T20 86 T24 12
class_i[0x1] 57257 1 T4 7 T5 1 T24 10
class_i[0x2] 69700 1 T5 11 T44 1341 T14 342
class_i[0x3] 65196 1 T4 3311 T5 3934 T21 146



Summary for Variable esc_index_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 4 0 4 100.00


User Defined Bins for esc_index_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
il 0 Illegal


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
alert[0x0] 65272 1 T3 100 T4 858 T5 1014
alert[0x1] 65549 1 T3 18 T4 803 T5 925
alert[0x2] 67545 1 T3 29 T4 890 T5 1004
alert[0x3] 64028 1 T3 29 T4 767 T5 1003



Summary for Variable loc_alert_cause_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
il 0 Illegal


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
esc_integrity_fail 262101 1 T3 176 T4 3318 T5 3946
esc_ping_fail 293 1 T8 7 T9 6 T10 5



Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp esc_index_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 8 0 8 100.00


Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins
loc_alert_cause_cpesc_index_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
esc_integrity_fail alert[0x0] 65190 1 T3 100 T4 858 T5 1014
esc_integrity_fail alert[0x1] 65481 1 T3 18 T4 803 T5 925
esc_integrity_fail alert[0x2] 67470 1 T3 29 T4 890 T5 1004
esc_integrity_fail alert[0x3] 63960 1 T3 29 T4 767 T5 1003
esc_ping_fail alert[0x0] 82 1 T8 1 T9 1 T10 2
esc_ping_fail alert[0x1] 68 1 T8 2 T9 3 T10 1
esc_ping_fail alert[0x2] 75 1 T8 3 T9 1 T10 1
esc_ping_fail alert[0x3] 68 1 T8 1 T9 1 T10 1



Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 8 0 8 100.00


Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins
loc_alert_cause_cpclass_index_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
esc_integrity_fail class_i[0x0] 70159 1 T3 176 T20 86 T24 12
esc_integrity_fail class_i[0x1] 57202 1 T4 7 T5 1 T24 10
esc_integrity_fail class_i[0x2] 69639 1 T5 11 T44 1341 T14 342
esc_integrity_fail class_i[0x3] 65101 1 T4 3311 T5 3934 T21 146
esc_ping_fail class_i[0x0] 82 1 T9 2 T280 4 T226 1
esc_ping_fail class_i[0x1] 55 1 T8 7 T9 4 T258 3
esc_ping_fail class_i[0x2] 61 1 T10 5 T258 1 T260 10
esc_ping_fail class_i[0x3] 95 1 T260 1 T262 5 T67 4

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