Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.89	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	40	6	34	85.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
intr_timeout_cnt_cp	10	0	10	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	40	6	34	85.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	74	1			T3	2		T24	1		T75	1
class_index[0x1]	57	1			T14	1		T45	1		T66	2
class_index[0x2]	55	1			T3	1		T75	2		T81	1
class_index[0x3]	72	1			T3	2		T14	1		T66	1

---

Summary for Variable intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for intr_timeout_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
intr_timeout_cnt[0]	113	1			T3	2		T75	2		T81	1
intr_timeout_cnt[1]	54	1			T3	1		T14	1		T75	1
intr_timeout_cnt[2]	24	1			T14	1		T45	1		T66	1
intr_timeout_cnt[3]	28	1			T66	1		T85	1		T115	1
intr_timeout_cnt[4]	4	1			T36	1		T52	1		T108	1
intr_timeout_cnt[5]	11	1			T46	3		T233	1		T234	1
intr_timeout_cnt[6]	6	1			T24	1		T66	1		T76	2
intr_timeout_cnt[7]	7	1			T27	1		T121	2		T232	1
intr_timeout_cnt[8]	8	1			T3	1		T235	1		T223	2
intr_timeout_cnt[9]	3	1			T3	1		T223	2		-	-

---

Summary for Cross class_cnt_cross

Samples crossed: class_index_cp intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	6	34	85.00	6

Automatically Generated Cross Bins for class_cnt_cross

Uncovered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	NUMBER	STATUS
[class_index[0x0]]	[intr_timeout_cnt[9]]	0	1	1
[class_index[0x1]]	[intr_timeout_cnt[5]]	0	1	1
[class_index[0x1]]	[intr_timeout_cnt[8] , intr_timeout_cnt[9]]	--	--	2
[class_index[0x2]]	[intr_timeout_cnt[4]]	0	1	1
[class_index[0x2]]	[intr_timeout_cnt[7]]	0	1	1

Covered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	intr_timeout_cnt[0]	24	1			T3	1		T75	1		T85	1
class_index[0x0]	intr_timeout_cnt[1]	11	1			T236	1		T101	5		T237	1
class_index[0x0]	intr_timeout_cnt[2]	9	1			T83	1		T87	1		T236	1
class_index[0x0]	intr_timeout_cnt[3]	9	1			T238	1		T229	1		T239	1
class_index[0x0]	intr_timeout_cnt[4]	2	1			T36	1		T232	1		-	-
class_index[0x0]	intr_timeout_cnt[5]	9	1			T46	3		T233	1		T240	1
class_index[0x0]	intr_timeout_cnt[6]	2	1			T24	1		T241	1		-	-
class_index[0x0]	intr_timeout_cnt[7]	5	1			T121	2		T242	1		T243	1
class_index[0x0]	intr_timeout_cnt[8]	3	1			T3	1		T223	2		-	-
class_index[0x1]	intr_timeout_cnt[0]	30	1			T83	1		T87	1		T88	1
class_index[0x1]	intr_timeout_cnt[1]	9	1			T84	1		T52	2		T237	1
class_index[0x1]	intr_timeout_cnt[2]	5	1			T14	1		T45	1		T232	1
class_index[0x1]	intr_timeout_cnt[3]	10	1			T66	1		T86	1		T239	1
class_index[0x1]	intr_timeout_cnt[4]	1	1			T108	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[6]	1	1			T66	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[7]	1	1			T27	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[0]	23	1			T75	1		T81	1		T114	1
class_index[0x2]	intr_timeout_cnt[1]	16	1			T75	1		T48	3		T25	1
class_index[0x2]	intr_timeout_cnt[2]	5	1			T236	1		T235	1		T244	1
class_index[0x2]	intr_timeout_cnt[3]	5	1			T85	1		T115	1		T28	1
class_index[0x2]	intr_timeout_cnt[5]	1	1			T234	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[6]	1	1			T76	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[8]	3	1			T245	2		T246	1		-	-
class_index[0x2]	intr_timeout_cnt[9]	1	1			T3	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[0]	36	1			T3	1		T27	1		T100	4
class_index[0x3]	intr_timeout_cnt[1]	18	1			T3	1		T14	1		T31	2
class_index[0x3]	intr_timeout_cnt[2]	5	1			T66	1		T123	1		T234	1
class_index[0x3]	intr_timeout_cnt[3]	4	1			T108	1		T247	2		T248	1
class_index[0x3]	intr_timeout_cnt[4]	1	1			T52	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[5]	1	1			T242	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[6]	2	1			T76	1		T249	1		-	-
class_index[0x3]	intr_timeout_cnt[7]	1	1			T232	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[8]	2	1			T235	1		T250	1		-	-
class_index[0x3]	intr_timeout_cnt[9]	2	1			T223	2		-	-		-	-