Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	368262	1			T1	1285		T3	307		T4	1307
all_values[1]	368262	1			T1	1285		T3	307		T4	1307
all_values[2]	368262	1			T1	1285		T3	307		T4	1307
all_values[3]	368262	1			T1	1285		T3	307		T4	1307

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

731944

1

T1

2557

T3

635

T4

2642

auto[1]

741104

1

T1

2583

T3

593

T4

2586

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

890588

1

T1

3851

T3

762

T4

2650

auto[1]

582460

1

T1

1289

T3

466

T4

2578

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	105262	1			T1	397		T3	80		T4	335
all_values[0]	auto[0]	auto[1]	77361	1			T1	248		T3	72		T4	309
all_values[0]	auto[1]	auto[0]	107672	1			T1	406		T3	90		T4	340
all_values[0]	auto[1]	auto[1]	77967	1			T1	234		T3	65		T4	323
all_values[1]	auto[0]	auto[0]	112450	1			T1	620		T3	110		T4	334
all_values[1]	auto[0]	auto[1]	70326	1			T3	60		T4	327		T5	349
all_values[1]	auto[1]	auto[0]	114637	1			T1	664		T3	93		T4	330
all_values[1]	auto[1]	auto[1]	70849	1			T1	1		T3	44		T4	316
all_values[2]	auto[0]	auto[0]	112353	1			T1	478		T3	104		T4	344
all_values[2]	auto[0]	auto[1]	71073	1			T1	167		T3	59		T4	343
all_values[2]	auto[1]	auto[0]	113928	1			T1	481		T3	90		T4	312
all_values[2]	auto[1]	auto[1]	70908	1			T1	159		T3	54		T4	308
all_values[3]	auto[0]	auto[0]	111259	1			T1	405		T3	99		T4	326
all_values[3]	auto[0]	auto[1]	71860	1			T1	242		T3	51		T4	324
all_values[3]	auto[1]	auto[0]	113027	1			T1	400		T3	96		T4	329
all_values[3]	auto[1]	auto[1]	72116	1			T1	238		T3	61		T4	328