Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	4	0	4	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	368262	1			T1	1285		T3	307		T4	1307
all_pins[1]	368262	1			T1	1285		T3	307		T4	1307
all_pins[2]	368262	1			T1	1285		T3	307		T4	1307
all_pins[3]	368262	1			T1	1285		T3	307		T4	1307

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1181208	1			T1	4508		T3	1004		T4	3953
values[0x1]	291840	1			T1	632		T3	224		T4	1275
transitions[0x0=>0x1]	195045	1			T1	575		T3	145		T4	815
transitions[0x1=>0x0]	195294	1			T1	576		T3	146		T4	815

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	290295	1			T1	1051		T3	242		T4	984
all_pins[0]	values[0x1]	77967	1			T1	234		T3	65		T4	323
all_pins[0]	transitions[0x0=>0x1]	77342	1			T1	233		T3	60		T4	323
all_pins[0]	transitions[0x1=>0x0]	71740	1			T1	238		T3	57		T4	328
all_pins[1]	values[0x0]	297413	1			T1	1284		T3	263		T4	991
all_pins[1]	values[0x1]	70849	1			T1	1		T3	44		T4	316
all_pins[1]	transitions[0x0=>0x1]	38459	1			T1	1		T3	21		T4	160
all_pins[1]	transitions[0x1=>0x0]	45577	1			T1	234		T3	42		T4	167
all_pins[2]	values[0x0]	297354	1			T1	1126		T3	253		T4	999
all_pins[2]	values[0x1]	70908	1			T1	159		T3	54		T4	308
all_pins[2]	transitions[0x0=>0x1]	39051	1			T1	159		T3	36		T4	155
all_pins[2]	transitions[0x1=>0x0]	38992	1			T1	1		T3	26		T4	163
all_pins[3]	values[0x0]	296146	1			T1	1047		T3	246		T4	979
all_pins[3]	values[0x1]	72116	1			T1	238		T3	61		T4	328
all_pins[3]	transitions[0x0=>0x1]	40193	1			T1	182		T3	28		T4	177
all_pins[3]	transitions[0x1=>0x0]	38985	1			T1	103		T3	21		T4	157