Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	296	1			T164	7		T166	7		T218	4
all_values[1]	296	1			T164	7		T166	7		T218	4
all_values[2]	296	1			T164	7		T166	7		T218	4
all_values[3]	296	1			T164	7		T166	7		T218	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

638

1

T164

12

T166

6

T218

14

auto[1]

546

1

T164

16

T166

22

T218

2

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

454

1

T164

16

T166

8

T218

9

auto[1]

730

1

T164

12

T166

20

T218

7

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

683

1

T164

19

T166

17

T218

13

auto[1]

501

1

T164

9

T166

11

T218

3

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	24	0	24	100.00
Automatically Generated Cross Bins	24	0	24	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr

cp_intr_test

cp_intr_en

cp_intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_values[0]

auto[0]

auto[0]

auto[0]

63

1

T164

2

T166

1

T218

1

all_values[0]

auto[0]

auto[0]

auto[1]

30

1

T164

2

T218

2

T219

2

all_values[0]

auto[0]

auto[1]

auto[0]

46

1

T164

2

T166

3

T219

1

all_values[0]

auto[0]

auto[1]

auto[1]

31

1

T166

1

T333

3

T334

1

all_values[0]

auto[1]

auto[0]

auto[1]

69

1

T219

1

T335

3

T336

3

all_values[0]

auto[1]

auto[1]

auto[1]

57

1

T164

1

T166

2

T218

1

all_values[1]

auto[0]

auto[0]

auto[0]

56

1

T164

2

T218

3

T219

1

all_values[1]

auto[0]

auto[0]

auto[1]

15

1

T337

1

T338

3

T339

2

all_values[1]

auto[0]

auto[1]

auto[0]

68

1

T164

3

T219

1

T335

1

all_values[1]

auto[0]

auto[1]

auto[1]

34

1

T166

3

T219

1

T336

2

all_values[1]

auto[1]

auto[0]

auto[1]

66

1

T218

1

T219

2

T335

3

all_values[1]

auto[1]

auto[1]

auto[1]

57

1

T164

2

T166

4

T219

2

all_values[2]

auto[0]

auto[0]

auto[0]

63

1

T164

1

T166

3

T218

1

all_values[2]

auto[0]

auto[0]

auto[1]

32

1

T166

2

T218

2

T340

2

all_values[2]

auto[0]

auto[1]

auto[0]

42

1

T164

3

T166

1

T335

7

all_values[2]

auto[0]

auto[1]

auto[1]

30

1

T219

2

T336

1

T333

1

all_values[2]

auto[1]

auto[0]

auto[1]

78

1

T164

2

T219

3

T336

1

all_values[2]

auto[1]

auto[1]

auto[1]

51

1

T164

1

T166

1

T218

1

all_values[3]

auto[0]

auto[0]

auto[0]

68

1

T164

1

T218

4

T335

3

all_values[3]

auto[0]

auto[0]

auto[1]

29

1

T164

1

T219

1

T335

1

all_values[3]

auto[0]

auto[1]

auto[0]

48

1

T164

2

T219

3

T336

1

all_values[3]

auto[0]

auto[1]

auto[1]

28

1

T166

3

T219

1

T336

2

all_values[3]

auto[1]

auto[0]

auto[1]

69

1

T164

1

T219

1

T335

2

all_values[3]

auto[1]

auto[1]

auto[1]

54

1

T164

2

T166

4

T219

1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal