Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
accum_cnt_cp	6	0	6	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	24	0	24	100.00	100	1	1	0

Summary for Variable accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for accum_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
accum_cnt_2000	88596	1			T5	1803		T7	338		T44	118
accum_cnt_1000	240977	1			T1	1637		T3	16		T5	1780
accum_cnt_100	30974	1			T1	177		T3	47		T5	97
accum_cnt_50	73597	1			T1	113		T3	146		T4	966
accum_cnt_10	201557	1			T1	996		T3	251		T4	1933
accum_cnt_0	418214	1			T1	1001		T3	492		T4	969

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Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	271779	1			T1	981		T3	238		T4	967
class_index[0x1]	271779	1			T1	981		T3	238		T4	967
class_index[0x2]	271779	1			T1	981		T3	238		T4	967
class_index[0x3]	271779	1			T1	981		T3	238		T4	967

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Summary for Cross class_cnt_cross

Samples crossed: class_index_cp accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for class_cnt_cross

Bins

class_index_cp	accum_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	accum_cnt_2000	23484	1			T5	553		T17	314		T31	395
class_index[0x0]	accum_cnt_1000	72438	1			T1	822		T3	16		T5	478
class_index[0x0]	accum_cnt_100	9880	1			T1	85		T3	31		T5	26
class_index[0x0]	accum_cnt_50	26830	1			T1	57		T3	70		T5	21
class_index[0x0]	accum_cnt_10	46854	1			T1	14		T3	92		T4	967
class_index[0x0]	accum_cnt_0	83755	1			T1	3		T3	29		T5	1
class_index[0x1]	accum_cnt_2000	20919	1			T5	554		T30	511		T25	682
class_index[0x1]	accum_cnt_1000	51408	1			T5	524		T44	267		T14	112
class_index[0x1]	accum_cnt_100	5999	1			T5	27		T20	26		T44	81
class_index[0x1]	accum_cnt_50	15897	1			T4	965		T5	21		T20	14
class_index[0x1]	accum_cnt_10	46707	1			T3	98		T4	2		T5	4
class_index[0x1]	accum_cnt_0	122724	1			T1	981		T3	140		T20	145
class_index[0x2]	accum_cnt_2000	22332	1			T5	486		T44	118		T15	366
class_index[0x2]	accum_cnt_1000	62891	1			T5	591		T7	696		T44	1032
class_index[0x2]	accum_cnt_100	6726	1			T5	35		T20	24		T7	75
class_index[0x2]	accum_cnt_50	17995	1			T3	30		T4	1		T5	21
class_index[0x2]	accum_cnt_10	52873	1			T1	970		T3	32		T4	1
class_index[0x2]	accum_cnt_0	99905	1			T1	11		T3	176		T4	965
class_index[0x3]	accum_cnt_2000	21861	1			T5	210		T7	338		T17	384
class_index[0x3]	accum_cnt_1000	54240	1			T1	815		T5	187		T20	43
class_index[0x3]	accum_cnt_100	8369	1			T1	92		T3	16		T5	9
class_index[0x3]	accum_cnt_50	12875	1			T1	56		T3	46		T5	13
class_index[0x3]	accum_cnt_10	55123	1			T1	12		T3	29		T4	963
class_index[0x3]	accum_cnt_0	111830	1			T1	6		T3	147		T4	4