Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	71	0	71	100.00
Crosses	138	0	138	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
alert_index_cp	65	0	65	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	130	0	130	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for alert_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	2715	1			T14	1		T258	1		T123	27
alert[0x1]	8656	1			T20	18		T17	3332		T9	1
alert[0x2]	4796	1			T14	3		T25	39		T259	1346
alert[0x3]	2691	1			T20	25		T44	36		T17	11
alert[0x4]	4813	1			T20	33		T14	34		T17	813
alert[0x5]	3718	1			T4	4		T44	39		T45	3
alert[0x6]	9052	1			T44	10		T31	140		T25	4
alert[0x7]	3000	1			T44	54		T17	278		T31	81
alert[0x8]	2414	1			T4	2		T17	1688		T76	3
alert[0x9]	5645	1			T66	20		T17	136		T76	2
alert[0xa]	5116	1			T14	19		T17	870		T27	4
alert[0xb]	5906	1			T31	21		T25	148		T100	1
alert[0xc]	8753	1			T20	2		T8	1		T17	144
alert[0xd]	5546	1			T20	7		T14	310		T8	1
alert[0xe]	10319	1			T15	2		T17	682		T18	1
alert[0xf]	4453	1			T44	443		T9	1		T76	2
alert[0x10]	2913	1			T44	66		T8	1		T17	32
alert[0x11]	6170	1			T20	55		T44	1		T8	1
alert[0x12]	12316	1			T44	1		T17	17		T25	866
alert[0x13]	2797	1			T14	33		T8	1		T18	2
alert[0x14]	1517	1			T14	17		T8	1		T17	13
alert[0x15]	1932	1			T44	83		T45	3		T8	1
alert[0x16]	5242	1			T45	2		T15	7		T76	2
alert[0x17]	2797	1			T20	10		T44	8		T45	6
alert[0x18]	10193	1			T44	113		T14	3		T66	3
alert[0x19]	5447	1			T44	630		T15	2		T10	1
alert[0x1a]	4748	1			T46	18		T17	35		T31	1061
alert[0x1b]	7357	1			T20	10		T8	1		T15	17
alert[0x1c]	5834	1			T4	1		T44	7		T15	4
alert[0x1d]	2919	1			T14	24		T45	1		T8	1
alert[0x1e]	3797	1			T8	1		T17	3		T27	5
alert[0x1f]	4904	1			T14	2		T17	156		T31	100
alert[0x20]	13843	1			T44	49		T14	4		T8	2
alert[0x21]	5083	1			T14	19		T66	2		T10	1
alert[0x22]	2458	1			T44	139		T14	10		T8	1
alert[0x23]	5096	1			T44	52		T14	1		T9	1
alert[0x24]	5546	1			T15	4		T31	130		T260	2
alert[0x25]	4215	1			T14	12		T31	14		T260	1
alert[0x26]	7054	1			T44	37		T17	116		T9	1
alert[0x27]	1914	1			T14	4		T8	1		T17	188
alert[0x28]	4529	1			T17	32		T18	2		T113	1
alert[0x29]	4829	1			T4	12		T20	29		T44	36
alert[0x2a]	3056	1			T14	4		T31	58		T258	1
alert[0x2b]	4937	1			T14	1		T17	310		T27	1
alert[0x2c]	4949	1			T1	1		T20	22		T14	32
alert[0x2d]	4360	1			T14	19		T8	1		T31	91
alert[0x2e]	1737	1			T14	2		T8	1		T46	1
alert[0x2f]	7209	1			T20	1		T14	1		T226	1
alert[0x30]	2034	1			T14	3		T8	1		T31	27
alert[0x31]	5560	1			T17	626		T261	1		T262	1
alert[0x32]	4926	1			T20	91		T14	62		T8	1
alert[0x33]	2628	1			T45	1		T9	1		T31	13
alert[0x34]	4936	1			T76	1		T31	8		T123	2
alert[0x35]	3247	1			T44	43		T14	3		T8	1
alert[0x36]	5790	1			T45	2		T76	3		T25	521
alert[0x37]	12991	1			T44	100		T14	2		T45	1
alert[0x38]	3038	1			T15	2		T76	3		T78	2
alert[0x39]	5661	1			T44	44		T15	3		T31	36
alert[0x3a]	5420	1			T17	227		T10	1		T31	97
alert[0x3b]	3616	1			T44	54		T14	5		T31	21
alert[0x3c]	8009	1			T20	2		T8	1		T18	5
alert[0x3d]	2750	1			T20	16		T44	36		T14	3
alert[0x3e]	2873	1			T20	1		T17	25		T31	321
alert[0x3f]	6436	1			T14	1		T9	1		T31	3383
alert[0x40]	7256	1			T258	2		T123	4		T259	10

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	106067	1			T20	310		T44	2081		T14	582
class_i[0x1]	27672	1			T1	1		T4	7		T14	51
class_i[0x2]	91765	1			T4	12		T14	1		T8	18
class_i[0x3]	110958	1			T20	12		T66	25		T8	2

---

Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

alert_integrity_fail

335742

1

T4

19

T20

322

T44

2081

alert_ping_fail

720

1

T1

1

T8

22

T9

10

---

Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	0	130	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	alert_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	alert[0x0]	2707	1			T14	1		T123	27		T70	688
alert_integrity_fail	alert[0x1]	8645	1			T20	18		T17	3332		T76	4
alert_integrity_fail	alert[0x2]	4791	1			T14	3		T25	39		T259	1346
alert_integrity_fail	alert[0x3]	2680	1			T20	25		T44	36		T17	11
alert_integrity_fail	alert[0x4]	4796	1			T20	33		T14	34		T17	813
alert_integrity_fail	alert[0x5]	3705	1			T4	4		T44	39		T45	3
alert_integrity_fail	alert[0x6]	9047	1			T44	10		T31	140		T25	4
alert_integrity_fail	alert[0x7]	2986	1			T44	54		T17	278		T31	81
alert_integrity_fail	alert[0x8]	2394	1			T4	2		T17	1688		T76	3
alert_integrity_fail	alert[0x9]	5632	1			T66	20		T17	136		T76	2
alert_integrity_fail	alert[0xa]	5100	1			T14	19		T17	870		T27	4
alert_integrity_fail	alert[0xb]	5896	1			T31	21		T25	148		T100	1
alert_integrity_fail	alert[0xc]	8747	1			T20	2		T17	144		T18	1
alert_integrity_fail	alert[0xd]	5538	1			T20	7		T14	310		T31	51
alert_integrity_fail	alert[0xe]	10311	1			T15	2		T17	682		T18	1
alert_integrity_fail	alert[0xf]	4441	1			T44	443		T76	2		T31	82
alert_integrity_fail	alert[0x10]	2901	1			T44	66		T17	32		T123	1
alert_integrity_fail	alert[0x11]	6151	1			T20	55		T44	1		T76	1
alert_integrity_fail	alert[0x12]	12311	1			T44	1		T17	17		T25	866
alert_integrity_fail	alert[0x13]	2778	1			T14	33		T18	2		T76	8
alert_integrity_fail	alert[0x14]	1500	1			T14	17		T17	13		T49	13
alert_integrity_fail	alert[0x15]	1916	1			T44	83		T45	3		T76	10
alert_integrity_fail	alert[0x16]	5230	1			T45	2		T15	7		T76	2
alert_integrity_fail	alert[0x17]	2790	1			T20	10		T44	8		T45	6
alert_integrity_fail	alert[0x18]	10181	1			T44	113		T14	3		T66	3
alert_integrity_fail	alert[0x19]	5442	1			T44	630		T15	2		T78	51
alert_integrity_fail	alert[0x1a]	4735	1			T46	18		T17	35		T31	1061
alert_integrity_fail	alert[0x1b]	7342	1			T20	10		T15	17		T76	1
alert_integrity_fail	alert[0x1c]	5823	1			T4	1		T44	7		T15	4
alert_integrity_fail	alert[0x1d]	2913	1			T14	24		T45	1		T17	48
alert_integrity_fail	alert[0x1e]	3788	1			T17	3		T27	5		T76	1
alert_integrity_fail	alert[0x1f]	4890	1			T14	2		T17	156		T31	100
alert_integrity_fail	alert[0x20]	13833	1			T44	49		T14	4		T31	234
alert_integrity_fail	alert[0x21]	5071	1			T14	19		T66	2		T100	55
alert_integrity_fail	alert[0x22]	2448	1			T44	139		T14	10		T78	7
alert_integrity_fail	alert[0x23]	5083	1			T44	52		T14	1		T31	40
alert_integrity_fail	alert[0x24]	5537	1			T15	4		T31	130		T71	2
alert_integrity_fail	alert[0x25]	4201	1			T14	12		T31	14		T259	83
alert_integrity_fail	alert[0x26]	7042	1			T44	37		T17	116		T31	47
alert_integrity_fail	alert[0x27]	1902	1			T14	4		T17	188		T76	3
alert_integrity_fail	alert[0x28]	4516	1			T17	32		T18	2		T263	353
alert_integrity_fail	alert[0x29]	4821	1			T4	12		T20	29		T44	36
alert_integrity_fail	alert[0x2a]	3041	1			T14	4		T31	58		T263	207
alert_integrity_fail	alert[0x2b]	4922	1			T14	1		T17	310		T27	1
alert_integrity_fail	alert[0x2c]	4936	1			T20	22		T14	32		T45	4
alert_integrity_fail	alert[0x2d]	4351	1			T14	19		T31	91		T25	281
alert_integrity_fail	alert[0x2e]	1716	1			T14	2		T46	1		T17	63
alert_integrity_fail	alert[0x2f]	7201	1			T20	1		T14	1		T259	460
alert_integrity_fail	alert[0x30]	2016	1			T14	3		T31	27		T25	65
alert_integrity_fail	alert[0x31]	5550	1			T17	626		T28	3		T87	39
alert_integrity_fail	alert[0x32]	4920	1			T20	91		T14	62		T31	12
alert_integrity_fail	alert[0x33]	2622	1			T45	1		T31	13		T25	4
alert_integrity_fail	alert[0x34]	4926	1			T76	1		T31	8		T123	2
alert_integrity_fail	alert[0x35]	3236	1			T44	43		T14	3		T259	270
alert_integrity_fail	alert[0x36]	5777	1			T45	2		T76	3		T25	521
alert_integrity_fail	alert[0x37]	12980	1			T44	100		T14	2		T45	1
alert_integrity_fail	alert[0x38]	3030	1			T15	2		T76	3		T78	2
alert_integrity_fail	alert[0x39]	5653	1			T44	44		T15	3		T31	36
alert_integrity_fail	alert[0x3a]	5413	1			T17	227		T31	97		T25	72
alert_integrity_fail	alert[0x3b]	3609	1			T44	54		T14	5		T31	21
alert_integrity_fail	alert[0x3c]	7999	1			T20	2		T18	5		T25	36
alert_integrity_fail	alert[0x3d]	2740	1			T20	16		T44	36		T14	3
alert_integrity_fail	alert[0x3e]	2862	1			T20	1		T17	25		T31	321
alert_integrity_fail	alert[0x3f]	6433	1			T14	1		T31	3383		T263	23
alert_integrity_fail	alert[0x40]	7248	1			T123	4		T259	10		T49	6
alert_ping_fail	alert[0x0]	8	1			T258	1		T260	1		T67	1
alert_ping_fail	alert[0x1]	11	1			T9	1		T258	1		T38	1
alert_ping_fail	alert[0x2]	5	1			T264	1		T265	1		T266	1
alert_ping_fail	alert[0x3]	11	1			T267	1		T268	1		T265	2
alert_ping_fail	alert[0x4]	17	1			T10	1		T269	1		T38	1
alert_ping_fail	alert[0x5]	13	1			T9	1		T269	1		T270	1
alert_ping_fail	alert[0x6]	5	1			T261	2		T271	1		T272	1
alert_ping_fail	alert[0x7]	14	1			T260	1		T261	1		T273	1
alert_ping_fail	alert[0x8]	20	1			T38	1		T264	2		T274	1
alert_ping_fail	alert[0x9]	13	1			T226	1		T262	1		T268	2
alert_ping_fail	alert[0xa]	16	1			T256	1		T267	1		T275	1
alert_ping_fail	alert[0xb]	10	1			T226	1		T261	1		T276	1
alert_ping_fail	alert[0xc]	6	1			T8	1		T262	1		T277	1
alert_ping_fail	alert[0xd]	8	1			T8	1		T271	2		T273	1
alert_ping_fail	alert[0xe]	8	1			T10	1		T262	1		T264	1
alert_ping_fail	alert[0xf]	12	1			T9	1		T262	1		T67	1
alert_ping_fail	alert[0x10]	12	1			T8	1		T260	1		T267	1
alert_ping_fail	alert[0x11]	19	1			T8	1		T10	1		T262	2
alert_ping_fail	alert[0x12]	5	1			T276	1		T278	1		T279	1
alert_ping_fail	alert[0x13]	19	1			T8	1		T256	1		T260	1
alert_ping_fail	alert[0x14]	17	1			T8	1		T10	1		T255	1
alert_ping_fail	alert[0x15]	16	1			T8	1		T262	2		T264	1
alert_ping_fail	alert[0x16]	12	1			T10	1		T280	1		T260	1
alert_ping_fail	alert[0x17]	7	1			T10	1		T226	1		T67	1
alert_ping_fail	alert[0x18]	12	1			T280	1		T260	1		T261	1
alert_ping_fail	alert[0x19]	5	1			T10	1		T271	1		T264	1
alert_ping_fail	alert[0x1a]	13	1			T280	1		T260	2		T267	1
alert_ping_fail	alert[0x1b]	15	1			T8	1		T280	1		T260	2
alert_ping_fail	alert[0x1c]	11	1			T261	2		T262	1		T264	1
alert_ping_fail	alert[0x1d]	6	1			T8	1		T256	1		T260	1
alert_ping_fail	alert[0x1e]	9	1			T8	1		T267	1		T264	1
alert_ping_fail	alert[0x1f]	14	1			T262	1		T269	1		T265	1
alert_ping_fail	alert[0x20]	10	1			T8	2		T9	1		T260	1
alert_ping_fail	alert[0x21]	12	1			T10	1		T280	1		T262	1
alert_ping_fail	alert[0x22]	10	1			T8	1		T256	1		T275	1
alert_ping_fail	alert[0x23]	13	1			T9	1		T258	3		T261	1
alert_ping_fail	alert[0x24]	9	1			T260	2		T281	1		T117	1
alert_ping_fail	alert[0x25]	14	1			T260	1		T261	1		T262	1
alert_ping_fail	alert[0x26]	12	1			T9	1		T267	1		T274	1
alert_ping_fail	alert[0x27]	12	1			T8	1		T226	1		T260	1
alert_ping_fail	alert[0x28]	13	1			T113	1		T41	1		T274	2
alert_ping_fail	alert[0x29]	8	1			T10	1		T260	1		T261	1
alert_ping_fail	alert[0x2a]	15	1			T258	1		T226	1		T260	1
alert_ping_fail	alert[0x2b]	15	1			T258	1		T280	1		T260	1
alert_ping_fail	alert[0x2c]	13	1			T1	1		T280	1		T269	1
alert_ping_fail	alert[0x2d]	9	1			T8	1		T268	1		T276	1
alert_ping_fail	alert[0x2e]	21	1			T8	1		T280	1		T226	1
alert_ping_fail	alert[0x2f]	8	1			T226	1		T271	2		T282	1
alert_ping_fail	alert[0x30]	18	1			T8	1		T226	1		T254	1
alert_ping_fail	alert[0x31]	10	1			T261	1		T262	1		T271	1
alert_ping_fail	alert[0x32]	6	1			T8	1		T268	1		T283	1
alert_ping_fail	alert[0x33]	6	1			T9	1		T268	1		T284	1
alert_ping_fail	alert[0x34]	10	1			T260	1		T261	1		T67	1
alert_ping_fail	alert[0x35]	11	1			T8	1		T9	1		T67	1
alert_ping_fail	alert[0x36]	13	1			T271	1		T273	1		T285	1
alert_ping_fail	alert[0x37]	11	1			T8	1		T9	1		T276	1
alert_ping_fail	alert[0x38]	8	1			T261	1		T38	1		T285	1
alert_ping_fail	alert[0x39]	8	1			T117	3		T286	1		T287	1
alert_ping_fail	alert[0x3a]	7	1			T10	1		T274	1		T286	1
alert_ping_fail	alert[0x3b]	7	1			T265	1		T274	1		T281	1
alert_ping_fail	alert[0x3c]	10	1			T8	1		T264	1		T268	1
alert_ping_fail	alert[0x3d]	10	1			T8	1		T265	1		T273	1
alert_ping_fail	alert[0x3e]	11	1			T261	1		T264	1		T285	2
alert_ping_fail	alert[0x3f]	3	1			T9	1		T269	1		T274	1
alert_ping_fail	alert[0x40]	8	1			T258	2		T67	1		T264	1

---

Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	class_i[0x0]	105939	1			T20	310		T44	2081		T14	582
alert_integrity_fail	class_i[0x1]	27513	1			T4	7		T14	51		T15	16
alert_integrity_fail	class_i[0x2]	91565	1			T4	12		T14	1		T46	1
alert_integrity_fail	class_i[0x3]	110725	1			T20	12		T66	25		T18	15
alert_ping_fail	class_i[0x0]	128	1			T8	1		T9	2		T10	10
alert_ping_fail	class_i[0x1]	159	1			T1	1		T8	1		T9	2
alert_ping_fail	class_i[0x2]	200	1			T8	18		T9	3		T256	4
alert_ping_fail	class_i[0x3]	233	1			T8	2		T9	3		T258	1