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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.66 99.99 98.71 100.00 100.00 100.00 99.38 99.56


Total test records in report: 834
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html
T774 /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.2901480857 Jul 24 05:31:54 PM PDT 24 Jul 24 05:32:04 PM PDT 24 603358046 ps
T775 /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.1573826419 Jul 24 05:31:53 PM PDT 24 Jul 24 05:32:02 PM PDT 24 136877497 ps
T147 /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.1814245142 Jul 24 05:31:47 PM PDT 24 Jul 24 05:42:29 PM PDT 24 4515983792 ps
T776 /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.2519799168 Jul 24 05:31:32 PM PDT 24 Jul 24 05:31:42 PM PDT 24 328916236 ps
T777 /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.1969834547 Jul 24 05:31:14 PM PDT 24 Jul 24 05:31:25 PM PDT 24 540816063 ps
T167 /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.3611311232 Jul 24 05:31:55 PM PDT 24 Jul 24 05:32:32 PM PDT 24 1776469251 ps
T778 /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.2396750095 Jul 24 05:32:07 PM PDT 24 Jul 24 05:32:09 PM PDT 24 70163087 ps
T779 /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.3804594123 Jul 24 05:31:16 PM PDT 24 Jul 24 05:31:27 PM PDT 24 228799552 ps
T168 /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.2150240106 Jul 24 05:31:24 PM PDT 24 Jul 24 05:31:28 PM PDT 24 117753349 ps
T780 /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.2863350072 Jul 24 05:31:09 PM PDT 24 Jul 24 05:31:23 PM PDT 24 561535126 ps
T781 /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.1004953676 Jul 24 05:32:05 PM PDT 24 Jul 24 05:32:07 PM PDT 24 7998364 ps
T782 /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.3222731628 Jul 24 05:31:51 PM PDT 24 Jul 24 05:31:56 PM PDT 24 51740809 ps
T149 /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.1939021619 Jul 24 05:31:42 PM PDT 24 Jul 24 05:33:30 PM PDT 24 3266025429 ps
T783 /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.440440592 Jul 24 05:31:33 PM PDT 24 Jul 24 05:31:34 PM PDT 24 9328490 ps
T784 /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.3338490144 Jul 24 05:31:32 PM PDT 24 Jul 24 05:31:34 PM PDT 24 7262871 ps
T785 /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.773471485 Jul 24 05:31:16 PM PDT 24 Jul 24 05:36:02 PM PDT 24 28482734896 ps
T786 /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.2860678425 Jul 24 05:31:13 PM PDT 24 Jul 24 05:31:14 PM PDT 24 21870273 ps
T787 /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.1986979459 Jul 24 05:31:27 PM PDT 24 Jul 24 05:31:32 PM PDT 24 130898155 ps
T172 /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.222162280 Jul 24 05:31:12 PM PDT 24 Jul 24 05:31:18 PM PDT 24 114971469 ps
T150 /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.908711764 Jul 24 05:31:28 PM PDT 24 Jul 24 05:35:53 PM PDT 24 3814350415 ps
T788 /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.2848903084 Jul 24 05:31:38 PM PDT 24 Jul 24 05:31:43 PM PDT 24 52523477 ps
T789 /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.3766395004 Jul 24 05:31:44 PM PDT 24 Jul 24 05:31:53 PM PDT 24 130687627 ps
T790 /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.838644438 Jul 24 05:32:08 PM PDT 24 Jul 24 05:32:09 PM PDT 24 6762597 ps
T170 /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.192784315 Jul 24 05:31:57 PM PDT 24 Jul 24 05:32:46 PM PDT 24 2391147799 ps
T791 /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.435448107 Jul 24 05:31:17 PM PDT 24 Jul 24 05:31:27 PM PDT 24 104562499 ps
T138 /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.1672756824 Jul 24 05:31:28 PM PDT 24 Jul 24 05:36:03 PM PDT 24 9556456235 ps
T792 /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.2583073580 Jul 24 05:31:33 PM PDT 24 Jul 24 05:31:39 PM PDT 24 193939169 ps
T793 /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.323654105 Jul 24 05:31:22 PM PDT 24 Jul 24 05:31:24 PM PDT 24 13550993 ps
T175 /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.3823847639 Jul 24 05:31:26 PM PDT 24 Jul 24 05:32:04 PM PDT 24 1507380554 ps
T794 /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.582249188 Jul 24 05:31:35 PM PDT 24 Jul 24 05:31:43 PM PDT 24 89184179 ps
T795 /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.2260339659 Jul 24 05:31:23 PM PDT 24 Jul 24 05:31:25 PM PDT 24 11241845 ps
T796 /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.2532258319 Jul 24 05:31:39 PM PDT 24 Jul 24 05:31:40 PM PDT 24 25686041 ps
T797 /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.2655369349 Jul 24 05:32:04 PM PDT 24 Jul 24 05:32:06 PM PDT 24 17054828 ps
T146 /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.3271685797 Jul 24 05:31:41 PM PDT 24 Jul 24 05:35:06 PM PDT 24 2605231208 ps
T798 /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.2649416941 Jul 24 05:31:27 PM PDT 24 Jul 24 05:32:09 PM PDT 24 3017889303 ps
T799 /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.1300819315 Jul 24 05:31:25 PM PDT 24 Jul 24 05:31:49 PM PDT 24 347154035 ps
T156 /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.1948973522 Jul 24 05:31:57 PM PDT 24 Jul 24 05:40:08 PM PDT 24 24733498949 ps
T800 /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.336338001 Jul 24 05:30:54 PM PDT 24 Jul 24 05:30:58 PM PDT 24 38739202 ps
T801 /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.1639370907 Jul 24 05:31:32 PM PDT 24 Jul 24 05:31:34 PM PDT 24 7026704 ps
T142 /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.494499863 Jul 24 05:31:41 PM PDT 24 Jul 24 05:37:26 PM PDT 24 22175619027 ps
T153 /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.1197270825 Jul 24 05:31:38 PM PDT 24 Jul 24 05:50:44 PM PDT 24 102970843059 ps
T802 /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.1566500862 Jul 24 05:31:26 PM PDT 24 Jul 24 05:31:28 PM PDT 24 12018830 ps
T803 /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.2075271684 Jul 24 05:32:04 PM PDT 24 Jul 24 05:32:07 PM PDT 24 27319332 ps
T804 /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.4268132010 Jul 24 05:31:36 PM PDT 24 Jul 24 05:33:17 PM PDT 24 780545578 ps
T805 /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.3387993165 Jul 24 05:31:47 PM PDT 24 Jul 24 05:31:56 PM PDT 24 177688186 ps
T151 /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.3136587826 Jul 24 05:31:52 PM PDT 24 Jul 24 05:35:04 PM PDT 24 6764697206 ps
T806 /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.3246984755 Jul 24 05:31:22 PM PDT 24 Jul 24 05:31:35 PM PDT 24 818468790 ps
T807 /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.3727893843 Jul 24 05:31:22 PM PDT 24 Jul 24 05:31:30 PM PDT 24 182488101 ps
T179 /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.2642861435 Jul 24 05:31:04 PM PDT 24 Jul 24 05:32:21 PM PDT 24 1404944617 ps
T808 /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.1353658918 Jul 24 05:31:25 PM PDT 24 Jul 24 05:31:30 PM PDT 24 165678535 ps
T345 /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.3025854548 Jul 24 05:31:40 PM PDT 24 Jul 24 05:48:48 PM PDT 24 16231512981 ps
T809 /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.1366921464 Jul 24 05:31:37 PM PDT 24 Jul 24 05:32:12 PM PDT 24 1042850799 ps
T810 /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.2236004776 Jul 24 05:31:22 PM PDT 24 Jul 24 05:40:01 PM PDT 24 40683877477 ps
T811 /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.725597031 Jul 24 05:31:30 PM PDT 24 Jul 24 05:31:50 PM PDT 24 1274111877 ps
T812 /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.2051415063 Jul 24 05:31:54 PM PDT 24 Jul 24 05:31:56 PM PDT 24 7868119 ps
T813 /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.1225744681 Jul 24 05:31:48 PM PDT 24 Jul 24 05:31:50 PM PDT 24 10213873 ps
T814 /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.2912258061 Jul 24 05:31:10 PM PDT 24 Jul 24 05:31:18 PM PDT 24 218763436 ps
T815 /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.1020911232 Jul 24 05:31:55 PM PDT 24 Jul 24 05:31:56 PM PDT 24 7166391 ps
T148 /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.2318907680 Jul 24 05:31:30 PM PDT 24 Jul 24 05:41:21 PM PDT 24 7835116017 ps
T816 /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.3589187146 Jul 24 05:31:39 PM PDT 24 Jul 24 05:31:53 PM PDT 24 92796488 ps
T817 /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.2608245264 Jul 24 05:31:48 PM PDT 24 Jul 24 05:32:21 PM PDT 24 494548479 ps
T818 /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.627979766 Jul 24 05:31:36 PM PDT 24 Jul 24 05:31:59 PM PDT 24 1231852359 ps
T160 /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.3789277876 Jul 24 05:31:38 PM PDT 24 Jul 24 05:42:46 PM PDT 24 17203592201 ps
T819 /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.381422587 Jul 24 05:31:25 PM PDT 24 Jul 24 05:35:34 PM PDT 24 3889841432 ps
T820 /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.3813633702 Jul 24 05:31:39 PM PDT 24 Jul 24 05:31:50 PM PDT 24 138352278 ps
T159 /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.1811285798 Jul 24 05:31:36 PM PDT 24 Jul 24 05:37:10 PM PDT 24 38751606230 ps
T821 /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.418477937 Jul 24 05:31:16 PM PDT 24 Jul 24 05:31:20 PM PDT 24 35029526 ps
T822 /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.3924393084 Jul 24 05:31:26 PM PDT 24 Jul 24 05:31:52 PM PDT 24 1251117342 ps
T173 /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.1481290806 Jul 24 05:31:20 PM PDT 24 Jul 24 05:31:23 PM PDT 24 105642419 ps
T823 /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.1318489305 Jul 24 05:31:56 PM PDT 24 Jul 24 05:31:58 PM PDT 24 8892794 ps
T824 /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.2852887433 Jul 24 05:31:38 PM PDT 24 Jul 24 05:31:46 PM PDT 24 99037116 ps
T825 /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.913834102 Jul 24 05:31:56 PM PDT 24 Jul 24 05:32:04 PM PDT 24 398746022 ps
T826 /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.4007650023 Jul 24 05:31:27 PM PDT 24 Jul 24 05:31:33 PM PDT 24 77788289 ps
T157 /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.2222040852 Jul 24 05:31:49 PM PDT 24 Jul 24 05:34:34 PM PDT 24 1973237874 ps
T827 /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.2875225227 Jul 24 05:31:21 PM PDT 24 Jul 24 05:31:29 PM PDT 24 122134780 ps
T154 /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.1510377984 Jul 24 05:31:48 PM PDT 24 Jul 24 05:43:58 PM PDT 24 4644076979 ps
T828 /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.200477308 Jul 24 05:32:05 PM PDT 24 Jul 24 05:32:06 PM PDT 24 19966032 ps
T829 /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.4175924588 Jul 24 05:31:31 PM PDT 24 Jul 24 05:34:24 PM PDT 24 2529361287 ps
T830 /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.4017879506 Jul 24 05:31:51 PM PDT 24 Jul 24 05:31:53 PM PDT 24 17848842 ps
T158 /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.4177218444 Jul 24 05:31:18 PM PDT 24 Jul 24 05:34:35 PM PDT 24 3386270629 ps
T831 /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.1310055250 Jul 24 05:32:13 PM PDT 24 Jul 24 05:32:15 PM PDT 24 29266793 ps
T832 /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.853432877 Jul 24 05:31:38 PM PDT 24 Jul 24 05:31:57 PM PDT 24 262722299 ps
T833 /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.1210029073 Jul 24 05:31:17 PM PDT 24 Jul 24 05:38:52 PM PDT 24 37165107435 ps
T834 /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.90284696 Jul 24 05:31:57 PM PDT 24 Jul 24 05:31:58 PM PDT 24 19230303 ps

Test location /workspace/coverage/default/18.alert_handler_stress_all_with_rand_reset.776028623
Short name T20
Test name
Test status
Simulation time 10313291052 ps
CPU time 950.77 seconds
Started Jul 24 05:34:00 PM PDT 24
Finished Jul 24 05:49:52 PM PDT 24
Peak memory 271688 kb
Host smart-68f0d397-9206-44f8-b62a-dcb83af66272
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776028623 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 18.alert_handler_stress_all_with_rand_reset.776028623
Directory /workspace/18.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all_with_rand_reset.1285507072
Short name T14
Test name
Test status
Simulation time 99311167250 ps
CPU time 3158.34 seconds
Started Jul 24 05:34:23 PM PDT 24
Finished Jul 24 06:27:02 PM PDT 24
Peak memory 305568 kb
Host smart-25109481-e2c8-44c1-a485-5b4c41e701bb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285507072 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 24.alert_handler_stress_all_with_rand_reset.1285507072
Directory /workspace/24.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.alert_handler_sec_cm.773491700
Short name T12
Test name
Test status
Simulation time 635746098 ps
CPU time 27.49 seconds
Started Jul 24 05:33:33 PM PDT 24
Finished Jul 24 05:34:01 PM PDT 24
Peak memory 267088 kb
Host smart-fd81655f-2be0-4aa0-900c-639e0ecf76c0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=773491700 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sec_cm.773491700
Directory /workspace/2.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/18.alert_handler_entropy_stress.1028213506
Short name T222
Test name
Test status
Simulation time 580053318 ps
CPU time 16.04 seconds
Started Jul 24 05:34:04 PM PDT 24
Finished Jul 24 05:34:20 PM PDT 24
Peak memory 248596 kb
Host smart-1dc41f76-db4b-4bb6-9f62-58802d1255df
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1028213506 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy_stress.1028213506
Directory /workspace/18.alert_handler_entropy_stress/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.4046585147
Short name T161
Test name
Test status
Simulation time 2004240719 ps
CPU time 33.08 seconds
Started Jul 24 05:31:58 PM PDT 24
Finished Jul 24 05:32:31 PM PDT 24
Peak memory 240964 kb
Host smart-15584b76-9ac4-49fc-85d8-fd35827a2ece
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4046585147 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_intg_err.4046585147
Directory /workspace/19.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all.1013210921
Short name T3
Test name
Test status
Simulation time 37629484936 ps
CPU time 559.03 seconds
Started Jul 24 05:34:03 PM PDT 24
Finished Jul 24 05:43:22 PM PDT 24
Peak memory 256808 kb
Host smart-0cf3e37d-b694-40f4-b97d-321929879d9e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013210921 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_ha
ndler_stress_all.1013210921
Directory /workspace/19.alert_handler_stress_all/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all_with_rand_reset.2211955702
Short name T232
Test name
Test status
Simulation time 90385875882 ps
CPU time 3251.86 seconds
Started Jul 24 05:33:33 PM PDT 24
Finished Jul 24 06:27:45 PM PDT 24
Peak memory 305192 kb
Host smart-5049803a-c86d-477c-b012-2944204ae06b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211955702 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.alert_handler_stress_all_with_rand_reset.2211955702
Directory /workspace/1.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all_with_rand_reset.2308762389
Short name T572
Test name
Test status
Simulation time 171840827149 ps
CPU time 5157.15 seconds
Started Jul 24 05:33:43 PM PDT 24
Finished Jul 24 06:59:41 PM PDT 24
Peak memory 371512 kb
Host smart-909aa3d7-bcbf-410d-8be4-b585db91df3e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308762389 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 7.alert_handler_stress_all_with_rand_reset.2308762389
Directory /workspace/7.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.1127839105
Short name T127
Test name
Test status
Simulation time 4222403606 ps
CPU time 293.87 seconds
Started Jul 24 05:31:07 PM PDT 24
Finished Jul 24 05:36:01 PM PDT 24
Peak memory 273500 kb
Host smart-4c4bb556-056c-41ad-b946-69e961f14e50
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1127839105 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shadow_reg_erro
rs.1127839105
Directory /workspace/1.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/9.alert_handler_lpg.80289514
Short name T256
Test name
Test status
Simulation time 55440829738 ps
CPU time 3170.89 seconds
Started Jul 24 05:33:45 PM PDT 24
Finished Jul 24 06:26:37 PM PDT 24
Peak memory 288432 kb
Host smart-4e58febb-a6f3-4d31-a341-11324f2087e0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80289514 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg.80289514
Directory /workspace/9.alert_handler_lpg/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all.1083051318
Short name T31
Test name
Test status
Simulation time 9932255092 ps
CPU time 1043.45 seconds
Started Jul 24 05:34:00 PM PDT 24
Finished Jul 24 05:51:24 PM PDT 24
Peak memory 284072 kb
Host smart-02d25f53-8648-4db3-9d81-d26b7322af98
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083051318 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_ha
ndler_stress_all.1083051318
Directory /workspace/16.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.3279032936
Short name T126
Test name
Test status
Simulation time 17696674898 ps
CPU time 1125.64 seconds
Started Jul 24 05:31:20 PM PDT 24
Finished Jul 24 05:50:06 PM PDT 24
Peak memory 273240 kb
Host smart-61ca5c6e-37fc-40fa-9fed-ec8fe1a65a89
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279032936 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.alert_handler_shadow_reg_errors_with_csr_rw.3279032936
Directory /workspace/5.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/28.alert_handler_lpg.2844032269
Short name T95
Test name
Test status
Simulation time 232451820142 ps
CPU time 1245.4 seconds
Started Jul 24 05:34:30 PM PDT 24
Finished Jul 24 05:55:16 PM PDT 24
Peak memory 271424 kb
Host smart-27cbb338-8b66-4a99-aad1-e3a8c342720e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844032269 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg.2844032269
Directory /workspace/28.alert_handler_lpg/latest

Test location /workspace/coverage/default/13.alert_handler_sig_int_fail.279685563
Short name T27
Test name
Test status
Simulation time 3458598123 ps
CPU time 45.36 seconds
Started Jul 24 05:33:58 PM PDT 24
Finished Jul 24 05:34:44 PM PDT 24
Peak memory 248364 kb
Host smart-978a90fa-abdf-4280-94e2-ebff45aa3f81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27968
5563 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_sig_int_fail.279685563
Directory /workspace/13.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all_with_rand_reset.544154174
Short name T28
Test name
Test status
Simulation time 87761608371 ps
CPU time 4708.21 seconds
Started Jul 24 05:34:33 PM PDT 24
Finished Jul 24 06:53:02 PM PDT 24
Peak memory 338304 kb
Host smart-e28d6668-c416-4869-8188-f90c2d47f093
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544154174 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 27.alert_handler_stress_all_with_rand_reset.544154174
Directory /workspace/27.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.3271685797
Short name T146
Test name
Test status
Simulation time 2605231208 ps
CPU time 204.87 seconds
Started Jul 24 05:31:41 PM PDT 24
Finished Jul 24 05:35:06 PM PDT 24
Peak memory 266060 kb
Host smart-574c3ede-7509-4483-9957-11e0c4664188
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3271685797 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shadow_reg_err
ors.3271685797
Directory /workspace/11.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/49.alert_handler_entropy.909870732
Short name T25
Test name
Test status
Simulation time 53405787906 ps
CPU time 3066.17 seconds
Started Jul 24 05:35:40 PM PDT 24
Finished Jul 24 06:26:47 PM PDT 24
Peak memory 289500 kb
Host smart-ca4f5bfc-bde6-4a54-8b89-5b870aa6b490
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909870732 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_entropy.909870732
Directory /workspace/49.alert_handler_entropy/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.3211670003
Short name T125
Test name
Test status
Simulation time 31553228004 ps
CPU time 1084.29 seconds
Started Jul 24 05:31:34 PM PDT 24
Finished Jul 24 05:49:39 PM PDT 24
Peak memory 266032 kb
Host smart-296c12b5-1766-46ad-ad88-3a3fde5d9b1f
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211670003 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.alert_handler_shadow_reg_errors_with_csr_rw.3211670003
Directory /workspace/7.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/33.alert_handler_ping_timeout.555267624
Short name T8
Test name
Test status
Simulation time 56811787305 ps
CPU time 524.44 seconds
Started Jul 24 05:34:44 PM PDT 24
Finished Jul 24 05:43:29 PM PDT 24
Peak memory 255360 kb
Host smart-854b9520-6738-44c3-9227-3d36306ef7b7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555267624 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_ping_timeout.555267624
Directory /workspace/33.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.1495392893
Short name T219
Test name
Test status
Simulation time 11837647 ps
CPU time 1.45 seconds
Started Jul 24 05:31:59 PM PDT 24
Finished Jul 24 05:32:01 PM PDT 24
Peak memory 237172 kb
Host smart-35a35e95-ef7c-4152-94c7-44fbbdd23021
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1495392893 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.alert_handler_intr_test.1495392893
Directory /workspace/47.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.3347324154
Short name T136
Test name
Test status
Simulation time 16847450144 ps
CPU time 279.9 seconds
Started Jul 24 05:31:37 PM PDT 24
Finished Jul 24 05:36:17 PM PDT 24
Peak memory 266064 kb
Host smart-a08a497f-8734-4b07-bd03-7e527e0a6863
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3347324154 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shadow_reg_err
ors.3347324154
Directory /workspace/13.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/4.alert_handler_lpg.3788401879
Short name T254
Test name
Test status
Simulation time 55054477301 ps
CPU time 3156.69 seconds
Started Jul 24 05:33:48 PM PDT 24
Finished Jul 24 06:26:26 PM PDT 24
Peak memory 288844 kb
Host smart-fabf3c52-183f-464c-a506-f8112ec0af40
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788401879 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg.3788401879
Directory /workspace/4.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.2239738462
Short name T131
Test name
Test status
Simulation time 12808675753 ps
CPU time 1022.26 seconds
Started Jul 24 05:31:10 PM PDT 24
Finished Jul 24 05:48:13 PM PDT 24
Peak memory 274204 kb
Host smart-93c82062-3e27-450c-8fa8-88d7fef66e0d
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239738462 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.alert_handler_shadow_reg_errors_with_csr_rw.2239738462
Directory /workspace/2.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/46.alert_handler_ping_timeout.670081066
Short name T261
Test name
Test status
Simulation time 10580321645 ps
CPU time 450 seconds
Started Jul 24 05:35:29 PM PDT 24
Finished Jul 24 05:42:59 PM PDT 24
Peak memory 248508 kb
Host smart-7fd22be5-e272-42cf-9c92-72cd691a00e3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670081066 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_ping_timeout.670081066
Directory /workspace/46.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all_with_rand_reset.136391360
Short name T123
Test name
Test status
Simulation time 101364628036 ps
CPU time 2474.67 seconds
Started Jul 24 05:33:37 PM PDT 24
Finished Jul 24 06:14:52 PM PDT 24
Peak memory 305996 kb
Host smart-a7797fc3-0b03-4357-b1d1-6f0457610240
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136391360 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 3.alert_handler_stress_all_with_rand_reset.136391360
Directory /workspace/3.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all_with_rand_reset.861160525
Short name T57
Test name
Test status
Simulation time 50527608573 ps
CPU time 5073.9 seconds
Started Jul 24 05:34:00 PM PDT 24
Finished Jul 24 06:58:35 PM PDT 24
Peak memory 350416 kb
Host smart-48672b51-f0ed-4391-9292-17fa6457eee1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861160525 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 14.alert_handler_stress_all_with_rand_reset.861160525
Directory /workspace/14.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.834683113
Short name T145
Test name
Test status
Simulation time 9384551256 ps
CPU time 120.33 seconds
Started Jul 24 05:31:54 PM PDT 24
Finished Jul 24 05:33:54 PM PDT 24
Peak memory 265904 kb
Host smart-f3ac8b27-fc03-40bb-9780-dba0c7b4036b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=834683113 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shadow_reg_erro
rs.834683113
Directory /workspace/19.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/3.alert_handler_ping_timeout.444858388
Short name T513
Test name
Test status
Simulation time 55546108853 ps
CPU time 568.49 seconds
Started Jul 24 05:33:32 PM PDT 24
Finished Jul 24 05:43:01 PM PDT 24
Peak memory 248476 kb
Host smart-4103d406-ddca-4ec1-80a7-aea01d5cd549
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444858388 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_ping_timeout.444858388
Directory /workspace/3.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_lpg.2350412671
Short name T272
Test name
Test status
Simulation time 279689043002 ps
CPU time 2655.85 seconds
Started Jul 24 05:34:58 PM PDT 24
Finished Jul 24 06:19:14 PM PDT 24
Peak memory 287816 kb
Host smart-faa8e66a-0409-42ad-a4c8-fc3316c8d9ab
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350412671 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg.2350412671
Directory /workspace/37.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.1749679072
Short name T132
Test name
Test status
Simulation time 2923593720 ps
CPU time 187.95 seconds
Started Jul 24 05:31:19 PM PDT 24
Finished Jul 24 05:34:27 PM PDT 24
Peak memory 266284 kb
Host smart-966a184f-e0f5-4e53-92a3-c0e4e48792ba
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1749679072 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shadow_reg_erro
rs.1749679072
Directory /workspace/3.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.3597136715
Short name T177
Test name
Test status
Simulation time 474397279 ps
CPU time 36.32 seconds
Started Jul 24 05:31:15 PM PDT 24
Finished Jul 24 05:31:51 PM PDT 24
Peak memory 249256 kb
Host smart-edf01e0a-d8c9-4c03-ad06-cadb4509f524
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3597136715 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_intg_err.3597136715
Directory /workspace/5.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all_with_rand_reset.1365974997
Short name T236
Test name
Test status
Simulation time 315278338323 ps
CPU time 5586.58 seconds
Started Jul 24 05:33:59 PM PDT 24
Finished Jul 24 07:07:06 PM PDT 24
Peak memory 314380 kb
Host smart-bd2a80b9-37c3-488f-bfbc-2384ef23cf9c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365974997 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 15.alert_handler_stress_all_with_rand_reset.1365974997
Directory /workspace/15.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.alert_handler_lpg.431168893
Short name T16
Test name
Test status
Simulation time 10581785665 ps
CPU time 870.57 seconds
Started Jul 24 05:35:00 PM PDT 24
Finished Jul 24 05:49:30 PM PDT 24
Peak memory 272284 kb
Host smart-10d94c44-c457-4279-9d4d-aeddaaf9c89b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431168893 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg.431168893
Directory /workspace/34.alert_handler_lpg/latest

Test location /workspace/coverage/default/37.alert_handler_ping_timeout.2830991345
Short name T274
Test name
Test status
Simulation time 136613216880 ps
CPU time 545.25 seconds
Started Jul 24 05:34:59 PM PDT 24
Finished Jul 24 05:44:05 PM PDT 24
Peak memory 248624 kb
Host smart-4f71015d-393d-4ee3-bdcc-474a4e155b68
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830991345 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_ping_timeout.2830991345
Directory /workspace/37.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all_with_rand_reset.416767953
Short name T76
Test name
Test status
Simulation time 6050054825 ps
CPU time 417.14 seconds
Started Jul 24 05:34:34 PM PDT 24
Finished Jul 24 05:41:31 PM PDT 24
Peak memory 266256 kb
Host smart-ab4133b4-65eb-451e-aac6-9114b0572418
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416767953 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 30.alert_handler_stress_all_with_rand_reset.416767953
Directory /workspace/30.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.1939021619
Short name T149
Test name
Test status
Simulation time 3266025429 ps
CPU time 107.82 seconds
Started Jul 24 05:31:42 PM PDT 24
Finished Jul 24 05:33:30 PM PDT 24
Peak memory 266088 kb
Host smart-57db304d-8e72-45dc-bb33-159455976a78
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1939021619 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shadow_reg_err
ors.1939021619
Directory /workspace/14.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.3025854548
Short name T345
Test name
Test status
Simulation time 16231512981 ps
CPU time 1027.27 seconds
Started Jul 24 05:31:40 PM PDT 24
Finished Jul 24 05:48:48 PM PDT 24
Peak memory 273468 kb
Host smart-476cc2bc-4f1e-42e9-9844-a4db7f2ffac4
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025854548 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.alert_handler_shadow_reg_errors_with_csr_rw.3025854548
Directory /workspace/8.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all.3970779822
Short name T52
Test name
Test status
Simulation time 51887199982 ps
CPU time 2140.26 seconds
Started Jul 24 05:34:43 PM PDT 24
Finished Jul 24 06:10:24 PM PDT 24
Peak memory 286476 kb
Host smart-d1e40f46-cc38-4ae1-96b7-91ec467f553f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970779822 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_ha
ndler_stress_all.3970779822
Directory /workspace/32.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.455629788
Short name T337
Test name
Test status
Simulation time 11484817 ps
CPU time 1.68 seconds
Started Jul 24 05:31:47 PM PDT 24
Finished Jul 24 05:31:49 PM PDT 24
Peak memory 237120 kb
Host smart-b4d3140a-3301-4463-93aa-13431d7ce548
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=455629788 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_intr_test.455629788
Directory /workspace/11.alert_handler_intr_test/latest

Test location /workspace/coverage/default/14.alert_handler_ping_timeout.3930430564
Short name T280
Test name
Test status
Simulation time 5137479557 ps
CPU time 206.48 seconds
Started Jul 24 05:34:00 PM PDT 24
Finished Jul 24 05:37:27 PM PDT 24
Peak memory 248852 kb
Host smart-d5a355dc-0df0-45f4-9c22-538ed094ecce
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930430564 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_ping_timeout.3930430564
Directory /workspace/14.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_lpg.3194420752
Short name T326
Test name
Test status
Simulation time 32205616720 ps
CPU time 1926.89 seconds
Started Jul 24 05:34:56 PM PDT 24
Finished Jul 24 06:07:03 PM PDT 24
Peak memory 273108 kb
Host smart-2377a5fa-023a-4cf4-8320-c373c358246c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3194420752 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg.3194420752
Directory /workspace/36.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.285721096
Short name T130
Test name
Test status
Simulation time 92741849308 ps
CPU time 1258.69 seconds
Started Jul 24 05:31:17 PM PDT 24
Finished Jul 24 05:52:16 PM PDT 24
Peak memory 274252 kb
Host smart-36bb8cd3-6663-4ab8-b0f5-6d19d86d2ddc
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285721096 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.alert_handler_shadow_reg_errors_with_csr_rw.285721096
Directory /workspace/3.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all.1277103156
Short name T242
Test name
Test status
Simulation time 5624852870 ps
CPU time 320.14 seconds
Started Jul 24 05:33:43 PM PDT 24
Finished Jul 24 05:39:04 PM PDT 24
Peak memory 256880 kb
Host smart-b034b706-ccff-4630-9aee-c314a101bb7a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277103156 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_han
dler_stress_all.1277103156
Directory /workspace/8.alert_handler_stress_all/latest

Test location /workspace/coverage/default/23.alert_handler_ping_timeout.2394600706
Short name T117
Test name
Test status
Simulation time 6426716989 ps
CPU time 258.29 seconds
Started Jul 24 05:34:14 PM PDT 24
Finished Jul 24 05:38:32 PM PDT 24
Peak memory 247480 kb
Host smart-dcb67551-e2fd-40a3-88a6-7b0c7d0e7037
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394600706 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_ping_timeout.2394600706
Directory /workspace/23.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_ping_timeout.3821588168
Short name T278
Test name
Test status
Simulation time 8111025614 ps
CPU time 307.89 seconds
Started Jul 24 05:34:38 PM PDT 24
Finished Jul 24 05:39:46 PM PDT 24
Peak memory 248428 kb
Host smart-a2fcc92f-afa7-475e-820b-d237066b736a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821588168 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_ping_timeout.3821588168
Directory /workspace/31.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all_with_rand_reset.378843197
Short name T301
Test name
Test status
Simulation time 63422505002 ps
CPU time 4638.13 seconds
Started Jul 24 05:35:02 PM PDT 24
Finished Jul 24 06:52:21 PM PDT 24
Peak memory 306012 kb
Host smart-42f33a7e-8a26-4389-9857-121865dbc8f4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378843197 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 39.alert_handler_stress_all_with_rand_reset.378843197
Directory /workspace/39.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.2150240106
Short name T168
Test name
Test status
Simulation time 117753349 ps
CPU time 3.38 seconds
Started Jul 24 05:31:24 PM PDT 24
Finished Jul 24 05:31:28 PM PDT 24
Peak memory 238016 kb
Host smart-f487d896-40f3-4dca-8e15-056bbc8e472c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2150240106 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_intg_err.2150240106
Directory /workspace/10.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.1811285798
Short name T159
Test name
Test status
Simulation time 38751606230 ps
CPU time 334.59 seconds
Started Jul 24 05:31:36 PM PDT 24
Finished Jul 24 05:37:10 PM PDT 24
Peak memory 266096 kb
Host smart-7522652f-c2f9-4d43-b168-bf7bee12cf99
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1811285798 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shadow_reg_err
ors.1811285798
Directory /workspace/10.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/0.alert_handler_alert_accum_saturation.4164199812
Short name T203
Test name
Test status
Simulation time 63695246 ps
CPU time 3.89 seconds
Started Jul 24 05:33:43 PM PDT 24
Finished Jul 24 05:33:47 PM PDT 24
Peak memory 248632 kb
Host smart-0658a5b6-da3d-4bef-a537-0222afb2343d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4164199812 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_alert_accum_saturation.4164199812
Directory /workspace/0.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/1.alert_handler_alert_accum_saturation.1195091396
Short name T202
Test name
Test status
Simulation time 16457617 ps
CPU time 2.6 seconds
Started Jul 24 05:33:30 PM PDT 24
Finished Jul 24 05:33:33 PM PDT 24
Peak memory 248820 kb
Host smart-3b977fe0-ee06-47df-a06f-c846f2bdb7de
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1195091396 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_alert_accum_saturation.1195091396
Directory /workspace/1.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/13.alert_handler_alert_accum_saturation.223800629
Short name T198
Test name
Test status
Simulation time 20913189 ps
CPU time 2.36 seconds
Started Jul 24 05:33:59 PM PDT 24
Finished Jul 24 05:34:02 PM PDT 24
Peak memory 248852 kb
Host smart-59add9b5-f2e1-4cf4-8282-4ea1640a0f1c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=223800629 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_alert_accum_saturation.223800629
Directory /workspace/13.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/16.alert_handler_alert_accum_saturation.3682318569
Short name T204
Test name
Test status
Simulation time 339828778 ps
CPU time 3.57 seconds
Started Jul 24 05:34:00 PM PDT 24
Finished Jul 24 05:34:04 PM PDT 24
Peak memory 248852 kb
Host smart-6dbbfc46-47ba-4f1e-a83c-61fa966caa75
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3682318569 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_alert_accum_saturation.3682318569
Directory /workspace/16.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/11.alert_handler_lpg_stub_clk.2834638994
Short name T30
Test name
Test status
Simulation time 163551351508 ps
CPU time 1099.45 seconds
Started Jul 24 05:33:46 PM PDT 24
Finished Jul 24 05:52:06 PM PDT 24
Peak memory 288584 kb
Host smart-dfa7dc28-1ba2-43cd-a764-36e0f923ca3f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2834638994 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg_stub_clk.2834638994
Directory /workspace/11.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/18.alert_handler_ping_timeout.2964755999
Short name T284
Test name
Test status
Simulation time 31944364375 ps
CPU time 364.3 seconds
Started Jul 24 05:34:02 PM PDT 24
Finished Jul 24 05:40:07 PM PDT 24
Peak memory 255596 kb
Host smart-4cd425f2-c9fb-4919-ac4a-2e62fe1b64cf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964755999 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_ping_timeout.2964755999
Directory /workspace/18.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_lpg.2400323057
Short name T332
Test name
Test status
Simulation time 43970227021 ps
CPU time 2119.27 seconds
Started Jul 24 05:34:00 PM PDT 24
Finished Jul 24 06:09:20 PM PDT 24
Peak memory 288932 kb
Host smart-c32faf16-0de6-4af7-a29d-f2ac9f73b4b5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400323057 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg.2400323057
Directory /workspace/19.alert_handler_lpg/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all_with_rand_reset.364073834
Short name T108
Test name
Test status
Simulation time 61324126788 ps
CPU time 5876.7 seconds
Started Jul 24 05:34:26 PM PDT 24
Finished Jul 24 07:12:24 PM PDT 24
Peak memory 354348 kb
Host smart-c1d748c0-fb0d-45e1-9b3d-2f5aa9f81100
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364073834 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 26.alert_handler_stress_all_with_rand_reset.364073834
Directory /workspace/26.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all.1504462791
Short name T235
Test name
Test status
Simulation time 64117583003 ps
CPU time 4023.37 seconds
Started Jul 24 05:33:35 PM PDT 24
Finished Jul 24 06:40:39 PM PDT 24
Peak memory 297816 kb
Host smart-e0c3f08d-63dc-4f45-9039-9b485792709b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504462791 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_han
dler_stress_all.1504462791
Directory /workspace/3.alert_handler_stress_all/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all.1984254163
Short name T241
Test name
Test status
Simulation time 44684651915 ps
CPU time 1382.57 seconds
Started Jul 24 05:34:52 PM PDT 24
Finished Jul 24 05:57:55 PM PDT 24
Peak memory 285492 kb
Host smart-dea6a74e-db25-44cc-966a-a2cd679abf69
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984254163 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_ha
ndler_stress_all.1984254163
Directory /workspace/34.alert_handler_stress_all/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all_with_rand_reset.111047195
Short name T225
Test name
Test status
Simulation time 54565314646 ps
CPU time 1652.78 seconds
Started Jul 24 05:35:30 PM PDT 24
Finished Jul 24 06:03:04 PM PDT 24
Peak memory 288560 kb
Host smart-f30755fb-219b-49c5-8e5b-f958e1f9aa2b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111047195 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 47.alert_handler_stress_all_with_rand_reset.111047195
Directory /workspace/47.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.alert_handler_ping_timeout.3507185386
Short name T271
Test name
Test status
Simulation time 5181122603 ps
CPU time 215.38 seconds
Started Jul 24 05:35:34 PM PDT 24
Finished Jul 24 05:39:09 PM PDT 24
Peak memory 248532 kb
Host smart-0600cc37-bf25-488a-8612-0681d1f059ab
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507185386 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_ping_timeout.3507185386
Directory /workspace/48.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.4177218444
Short name T158
Test name
Test status
Simulation time 3386270629 ps
CPU time 196.56 seconds
Started Jul 24 05:31:18 PM PDT 24
Finished Jul 24 05:34:35 PM PDT 24
Peak memory 266072 kb
Host smart-e2abe1b8-9f5e-427c-88f2-a9323567766d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4177218444 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shadow_reg_erro
rs.4177218444
Directory /workspace/4.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.4058580555
Short name T124
Test name
Test status
Simulation time 4903197895 ps
CPU time 580.26 seconds
Started Jul 24 05:31:34 PM PDT 24
Finished Jul 24 05:41:15 PM PDT 24
Peak memory 266088 kb
Host smart-c0d26328-388f-418a-9f05-f77792011c24
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058580555 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 12.alert_handler_shadow_reg_errors_with_csr_rw.4058580555
Directory /workspace/12.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.3523017952
Short name T745
Test name
Test status
Simulation time 13309385 ps
CPU time 1.71 seconds
Started Jul 24 05:31:13 PM PDT 24
Finished Jul 24 05:31:15 PM PDT 24
Peak memory 237148 kb
Host smart-a2b71787-3128-4d07-ac06-97cc3e1073c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3523017952 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_intr_test.3523017952
Directory /workspace/0.alert_handler_intr_test/latest

Test location /workspace/coverage/default/0.alert_handler_lpg.2723271432
Short name T275
Test name
Test status
Simulation time 15062982028 ps
CPU time 1426.02 seconds
Started Jul 24 05:33:25 PM PDT 24
Finished Jul 24 05:57:12 PM PDT 24
Peak memory 287560 kb
Host smart-4b9518ea-fb1a-4619-bd3f-0eb88422e53e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723271432 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg.2723271432
Directory /workspace/0.alert_handler_lpg/latest

Test location /workspace/coverage/default/10.alert_handler_lpg.2695547992
Short name T317
Test name
Test status
Simulation time 400654005783 ps
CPU time 1842.88 seconds
Started Jul 24 05:33:51 PM PDT 24
Finished Jul 24 06:04:34 PM PDT 24
Peak memory 288980 kb
Host smart-5bc25e94-219c-4cb5-b782-c640c15f7741
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695547992 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg.2695547992
Directory /workspace/10.alert_handler_lpg/latest

Test location /workspace/coverage/default/12.alert_handler_lpg.2775318103
Short name T700
Test name
Test status
Simulation time 177142961239 ps
CPU time 1998.54 seconds
Started Jul 24 05:33:59 PM PDT 24
Finished Jul 24 06:07:18 PM PDT 24
Peak memory 282760 kb
Host smart-1ab32253-6cf0-4aa8-b1e2-f84b1edcde9c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775318103 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg.2775318103
Directory /workspace/12.alert_handler_lpg/latest

Test location /workspace/coverage/default/13.alert_handler_random_classes.1571381393
Short name T290
Test name
Test status
Simulation time 233406957 ps
CPU time 19.27 seconds
Started Jul 24 05:33:57 PM PDT 24
Finished Jul 24 05:34:17 PM PDT 24
Peak memory 256328 kb
Host smart-49854727-e4cc-4184-b1e3-794f18b7db47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15713
81393 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_classes.1571381393
Directory /workspace/13.alert_handler_random_classes/latest

Test location /workspace/coverage/default/14.alert_handler_lpg.3119875092
Short name T316
Test name
Test status
Simulation time 44053349139 ps
CPU time 2714.25 seconds
Started Jul 24 05:33:48 PM PDT 24
Finished Jul 24 06:19:03 PM PDT 24
Peak memory 284016 kb
Host smart-38a9e724-6d43-4028-af90-2fab2c5607c1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119875092 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg.3119875092
Directory /workspace/14.alert_handler_lpg/latest

Test location /workspace/coverage/default/14.alert_handler_sig_int_fail.80168638
Short name T234
Test name
Test status
Simulation time 148946225 ps
CPU time 8.46 seconds
Started Jul 24 05:33:50 PM PDT 24
Finished Jul 24 05:33:58 PM PDT 24
Peak memory 254188 kb
Host smart-27f2c103-5523-428e-bd47-93296997b070
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80168
638 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_sig_int_fail.80168638
Directory /workspace/14.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all.2764663469
Short name T246
Test name
Test status
Simulation time 46617108305 ps
CPU time 3013.67 seconds
Started Jul 24 05:34:04 PM PDT 24
Finished Jul 24 06:24:19 PM PDT 24
Peak memory 298804 kb
Host smart-3f122d6a-7a0c-4372-83e0-8ba2a4a4f07e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764663469 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_ha
ndler_stress_all.2764663469
Directory /workspace/17.alert_handler_stress_all/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all_with_rand_reset.231648513
Short name T223
Test name
Test status
Simulation time 42786940591 ps
CPU time 2616.07 seconds
Started Jul 24 05:34:19 PM PDT 24
Finished Jul 24 06:17:55 PM PDT 24
Peak memory 281552 kb
Host smart-99e1d04c-67d5-4a3b-acdf-ab498925f1f0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231648513 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 25.alert_handler_stress_all_with_rand_reset.231648513
Directory /workspace/25.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.alert_handler_sig_int_fail.2188589900
Short name T314
Test name
Test status
Simulation time 170721092 ps
CPU time 15.25 seconds
Started Jul 24 05:34:33 PM PDT 24
Finished Jul 24 05:34:48 PM PDT 24
Peak memory 248048 kb
Host smart-703ce345-378f-4bae-ab24-b44fd2f496dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21885
89900 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_sig_int_fail.2188589900
Directory /workspace/28.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/30.alert_handler_lpg.1845159752
Short name T40
Test name
Test status
Simulation time 124136415716 ps
CPU time 1760.36 seconds
Started Jul 24 05:34:34 PM PDT 24
Finished Jul 24 06:03:55 PM PDT 24
Peak memory 289016 kb
Host smart-6d1919bf-6f52-4d09-9628-1e3a43c0df80
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845159752 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg.1845159752
Directory /workspace/30.alert_handler_lpg/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all_with_rand_reset.3123473888
Short name T93
Test name
Test status
Simulation time 368877177779 ps
CPU time 9522.14 seconds
Started Jul 24 05:34:57 PM PDT 24
Finished Jul 24 08:13:41 PM PDT 24
Peak memory 371364 kb
Host smart-5e47323e-9009-4bd8-b6da-f3254f7a2e95
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123473888 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 35.alert_handler_stress_all_with_rand_reset.3123473888
Directory /workspace/35.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all_with_rand_reset.2108139567
Short name T313
Test name
Test status
Simulation time 95827515622 ps
CPU time 3347.07 seconds
Started Jul 24 05:35:40 PM PDT 24
Finished Jul 24 06:31:28 PM PDT 24
Peak memory 289620 kb
Host smart-2d1819b5-adfc-4820-a13f-6a622c5f8e84
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108139567 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 48.alert_handler_stress_all_with_rand_reset.2108139567
Directory /workspace/48.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all.2986465723
Short name T54
Test name
Test status
Simulation time 134195742636 ps
CPU time 2014.63 seconds
Started Jul 24 05:35:48 PM PDT 24
Finished Jul 24 06:09:23 PM PDT 24
Peak memory 283936 kb
Host smart-581a75ce-2494-4c8c-91d6-03eb06bcf178
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986465723 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_ha
ndler_stress_all.2986465723
Directory /workspace/49.alert_handler_stress_all/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all.2974994122
Short name T303
Test name
Test status
Simulation time 14665427886 ps
CPU time 1308.22 seconds
Started Jul 24 05:33:46 PM PDT 24
Finished Jul 24 05:55:34 PM PDT 24
Peak memory 281380 kb
Host smart-1b8cef69-1b09-45a3-b204-88e5b9d387b9
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974994122 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_han
dler_stress_all.2974994122
Directory /workspace/5.alert_handler_stress_all/latest

Test location /workspace/coverage/default/7.alert_handler_sig_int_fail.1074414020
Short name T66
Test name
Test status
Simulation time 1285709863 ps
CPU time 12.79 seconds
Started Jul 24 05:33:43 PM PDT 24
Finished Jul 24 05:33:56 PM PDT 24
Peak memory 248188 kb
Host smart-7220f963-fa7f-4b3d-9a94-20912690f372
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10744
14020 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_sig_int_fail.1074414020
Directory /workspace/7.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/0.alert_handler_sec_cm.391372882
Short name T13
Test name
Test status
Simulation time 681232558 ps
CPU time 11.27 seconds
Started Jul 24 05:33:28 PM PDT 24
Finished Jul 24 05:33:40 PM PDT 24
Peak memory 278664 kb
Host smart-fb1286c7-778c-408c-baa6-4e23dd5e13d3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=391372882 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sec_cm.391372882
Directory /workspace/0.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/11.alert_handler_random_classes.2789629826
Short name T29
Test name
Test status
Simulation time 84125233 ps
CPU time 4.01 seconds
Started Jul 24 05:33:47 PM PDT 24
Finished Jul 24 05:33:51 PM PDT 24
Peak memory 240412 kb
Host smart-0c505afb-08f9-4511-ab64-57bdc696f75f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27896
29826 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_classes.2789629826
Directory /workspace/11.alert_handler_random_classes/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.222162280
Short name T172
Test name
Test status
Simulation time 114971469 ps
CPU time 5.9 seconds
Started Jul 24 05:31:12 PM PDT 24
Finished Jul 24 05:31:18 PM PDT 24
Peak memory 238316 kb
Host smart-683c0ad5-8c87-4768-b173-7f7611315f41
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=222162280 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_intg_err.222162280
Directory /workspace/1.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.1182433294
Short name T134
Test name
Test status
Simulation time 3824368567 ps
CPU time 126.54 seconds
Started Jul 24 05:31:38 PM PDT 24
Finished Jul 24 05:33:45 PM PDT 24
Peak memory 266068 kb
Host smart-1475b12b-a690-4f51-bd74-a6541ea321ce
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1182433294 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shadow_reg_err
ors.1182433294
Directory /workspace/16.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.2642861435
Short name T179
Test name
Test status
Simulation time 1404944617 ps
CPU time 76.71 seconds
Started Jul 24 05:31:04 PM PDT 24
Finished Jul 24 05:32:21 PM PDT 24
Peak memory 241032 kb
Host smart-c8d5c321-5e84-4a6c-b6f1-7d06ffb3c6ff
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2642861435 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_intg_err.2642861435
Directory /workspace/0.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.1053718157
Short name T162
Test name
Test status
Simulation time 435209038 ps
CPU time 3.06 seconds
Started Jul 24 05:31:54 PM PDT 24
Finished Jul 24 05:31:57 PM PDT 24
Peak memory 237924 kb
Host smart-e9b0099e-e680-4cee-91bc-bc9edd4ebcac
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1053718157 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_intg_err.1053718157
Directory /workspace/16.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.192784315
Short name T170
Test name
Test status
Simulation time 2391147799 ps
CPU time 49.08 seconds
Started Jul 24 05:31:57 PM PDT 24
Finished Jul 24 05:32:46 PM PDT 24
Peak memory 238312 kb
Host smart-8a622d53-ba0f-45ba-83ff-e1fe3f71da4f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=192784315 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_intg_err.192784315
Directory /workspace/17.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.3823847639
Short name T175
Test name
Test status
Simulation time 1507380554 ps
CPU time 37.91 seconds
Started Jul 24 05:31:26 PM PDT 24
Finished Jul 24 05:32:04 PM PDT 24
Peak memory 240936 kb
Host smart-cef3eae9-bbcd-4f19-a700-af79eb91b0fb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3823847639 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_intg_err.3823847639
Directory /workspace/6.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_intg_err.1228861223
Short name T174
Test name
Test status
Simulation time 316161018 ps
CPU time 50.57 seconds
Started Jul 24 05:31:32 PM PDT 24
Finished Jul 24 05:32:23 PM PDT 24
Peak memory 240208 kb
Host smart-ba34add0-7c17-4a33-934d-1e4777c62548
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1228861223 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_intg_err.1228861223
Directory /workspace/12.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.3783672144
Short name T181
Test name
Test status
Simulation time 64525401 ps
CPU time 4.8 seconds
Started Jul 24 05:31:33 PM PDT 24
Finished Jul 24 05:31:38 PM PDT 24
Peak memory 238316 kb
Host smart-2ff389f1-aaca-48cd-b94a-f2338dff4f02
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3783672144 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_intg_err.3783672144
Directory /workspace/13.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.3928616963
Short name T171
Test name
Test status
Simulation time 719686195 ps
CPU time 49.27 seconds
Started Jul 24 05:31:37 PM PDT 24
Finished Jul 24 05:32:27 PM PDT 24
Peak memory 249252 kb
Host smart-a5a2a42a-fc9d-4401-8cf4-c919c35ed040
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3928616963 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_intg_err.3928616963
Directory /workspace/14.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.1525659221
Short name T163
Test name
Test status
Simulation time 1063992049 ps
CPU time 69.78 seconds
Started Jul 24 05:31:41 PM PDT 24
Finished Jul 24 05:32:51 PM PDT 24
Peak memory 238088 kb
Host smart-e43d2163-cb6a-4c8f-9f56-b0f0cd476874
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1525659221 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_intg_err.1525659221
Directory /workspace/15.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.3616495424
Short name T176
Test name
Test status
Simulation time 217945980 ps
CPU time 4.27 seconds
Started Jul 24 05:31:18 PM PDT 24
Finished Jul 24 05:31:22 PM PDT 24
Peak memory 237996 kb
Host smart-1c8de423-9508-475b-b798-e57b0da743f2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3616495424 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_intg_err.3616495424
Directory /workspace/3.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.4082888191
Short name T169
Test name
Test status
Simulation time 39619548 ps
CPU time 2.31 seconds
Started Jul 24 05:31:28 PM PDT 24
Finished Jul 24 05:31:30 PM PDT 24
Peak memory 239112 kb
Host smart-c9213cd3-dad6-486b-868a-999ad4ffd032
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4082888191 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_intg_err.4082888191
Directory /workspace/11.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.3611311232
Short name T167
Test name
Test status
Simulation time 1776469251 ps
CPU time 37.46 seconds
Started Jul 24 05:31:55 PM PDT 24
Finished Jul 24 05:32:32 PM PDT 24
Peak memory 240984 kb
Host smart-d96e2d56-226d-42d5-81fe-208cd6e199b0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3611311232 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_intg_err.3611311232
Directory /workspace/18.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.1481290806
Short name T173
Test name
Test status
Simulation time 105642419 ps
CPU time 2.78 seconds
Started Jul 24 05:31:20 PM PDT 24
Finished Jul 24 05:31:23 PM PDT 24
Peak memory 239096 kb
Host smart-6bc97452-993f-4e16-a54e-1d2d666de0a9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1481290806 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_intg_err.1481290806
Directory /workspace/2.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/23.alert_handler_esc_intr_timeout.1070217095
Short name T26
Test name
Test status
Simulation time 1502901751 ps
CPU time 35.27 seconds
Started Jul 24 05:34:10 PM PDT 24
Finished Jul 24 05:34:45 PM PDT 24
Peak memory 248608 kb
Host smart-d7948d30-a69e-4095-9f78-53544b16c343
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10702
17095 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_intr_timeout.1070217095
Directory /workspace/23.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.430061
Short name T769
Test name
Test status
Simulation time 4261074514 ps
CPU time 142.73 seconds
Started Jul 24 05:31:08 PM PDT 24
Finished Jul 24 05:33:31 PM PDT 24
Peak memory 241960 kb
Host smart-878aafe6-9d24-406a-8d72-cafc07181470
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=430061 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_aliasing.430061
Directory /workspace/0.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.2236004776
Short name T810
Test name
Test status
Simulation time 40683877477 ps
CPU time 518.05 seconds
Started Jul 24 05:31:22 PM PDT 24
Finished Jul 24 05:40:01 PM PDT 24
Peak memory 241024 kb
Host smart-d35bcf9e-c0c3-4b0f-847f-8a4cccb3fadc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2236004776 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_bit_bash.2236004776
Directory /workspace/0.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.3997556552
Short name T764
Test name
Test status
Simulation time 152226322 ps
CPU time 5.92 seconds
Started Jul 24 05:31:14 PM PDT 24
Finished Jul 24 05:31:20 PM PDT 24
Peak memory 249176 kb
Host smart-3439d967-a4d2-477b-9fdd-c06b7c58b626
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3997556552 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_hw_reset.3997556552
Directory /workspace/0.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.3958149176
Short name T770
Test name
Test status
Simulation time 741922798 ps
CPU time 13.39 seconds
Started Jul 24 05:31:05 PM PDT 24
Finished Jul 24 05:31:19 PM PDT 24
Peak memory 249308 kb
Host smart-5a4bb9fa-ccf0-45f3-8368-4b8221ce4f17
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958149176 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 0.alert_handler_csr_mem_rw_with_rand_reset.3958149176
Directory /workspace/0.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.1469428172
Short name T763
Test name
Test status
Simulation time 302625330 ps
CPU time 5.57 seconds
Started Jul 24 05:31:15 PM PDT 24
Finished Jul 24 05:31:21 PM PDT 24
Peak memory 237952 kb
Host smart-679aa09a-8df2-42bc-aa09-22e9c69bac3d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1469428172 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_rw.1469428172
Directory /workspace/0.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.1586189110
Short name T725
Test name
Test status
Simulation time 377010047 ps
CPU time 10.4 seconds
Started Jul 24 05:31:12 PM PDT 24
Finished Jul 24 05:31:22 PM PDT 24
Peak memory 245300 kb
Host smart-93483985-265b-4319-bf17-0332f6561f72
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1586189110 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_same_csr_out
standing.1586189110
Directory /workspace/0.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.1804131030
Short name T144
Test name
Test status
Simulation time 7580666274 ps
CPU time 103.63 seconds
Started Jul 24 05:31:07 PM PDT 24
Finished Jul 24 05:32:50 PM PDT 24
Peak memory 265884 kb
Host smart-29605c2b-b5ac-4d9d-9a8d-23a20c0f15fd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1804131030 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shadow_reg_erro
rs.1804131030
Directory /workspace/0.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.4084153268
Short name T152
Test name
Test status
Simulation time 4732536344 ps
CPU time 333.28 seconds
Started Jul 24 05:31:10 PM PDT 24
Finished Jul 24 05:36:44 PM PDT 24
Peak memory 266024 kb
Host smart-b2852a62-b11e-424f-950c-cefd4eae4851
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084153268 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.alert_handler_shadow_reg_errors_with_csr_rw.4084153268
Directory /workspace/0.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.1293277257
Short name T737
Test name
Test status
Simulation time 225563201 ps
CPU time 15.88 seconds
Started Jul 24 05:31:11 PM PDT 24
Finished Jul 24 05:31:27 PM PDT 24
Peak memory 249316 kb
Host smart-a9494343-92e2-4770-acc5-1c2045b72a21
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1293277257 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_errors.1293277257
Directory /workspace/0.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.3770477214
Short name T723
Test name
Test status
Simulation time 2896220863 ps
CPU time 154.99 seconds
Started Jul 24 05:31:03 PM PDT 24
Finished Jul 24 05:33:39 PM PDT 24
Peak memory 241104 kb
Host smart-1da80219-602e-4ed8-9e4f-9e176d227a45
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3770477214 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_aliasing.3770477214
Directory /workspace/1.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.1387510534
Short name T747
Test name
Test status
Simulation time 9299565471 ps
CPU time 463.79 seconds
Started Jul 24 05:31:13 PM PDT 24
Finished Jul 24 05:38:57 PM PDT 24
Peak memory 238196 kb
Host smart-7cca7892-31d7-4b77-863a-5d3e13aa8311
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1387510534 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_bit_bash.1387510534
Directory /workspace/1.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.3611235778
Short name T165
Test name
Test status
Simulation time 101249580 ps
CPU time 10.24 seconds
Started Jul 24 05:31:06 PM PDT 24
Finished Jul 24 05:31:16 PM PDT 24
Peak memory 249180 kb
Host smart-4b911f01-0569-408d-8fbb-4eb338c03f90
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3611235778 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_hw_reset.3611235778
Directory /workspace/1.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.336338001
Short name T800
Test name
Test status
Simulation time 38739202 ps
CPU time 3.57 seconds
Started Jul 24 05:30:54 PM PDT 24
Finished Jul 24 05:30:58 PM PDT 24
Peak memory 240252 kb
Host smart-6add42f3-2b17-4a17-b6f6-a59a7a57a499
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336338001 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 1.alert_handler_csr_mem_rw_with_rand_reset.336338001
Directory /workspace/1.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.2912258061
Short name T814
Test name
Test status
Simulation time 218763436 ps
CPU time 7.87 seconds
Started Jul 24 05:31:10 PM PDT 24
Finished Jul 24 05:31:18 PM PDT 24
Peak memory 237108 kb
Host smart-ed816d4e-83ae-4637-b2fa-97d0a53f0b9d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2912258061 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_rw.2912258061
Directory /workspace/1.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.1910228571
Short name T333
Test name
Test status
Simulation time 13889820 ps
CPU time 1.3 seconds
Started Jul 24 05:30:51 PM PDT 24
Finished Jul 24 05:30:53 PM PDT 24
Peak memory 236188 kb
Host smart-c2fc124c-81aa-44ed-a314-35ca8604c949
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1910228571 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_intr_test.1910228571
Directory /workspace/1.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.4102767293
Short name T187
Test name
Test status
Simulation time 279124255 ps
CPU time 20.6 seconds
Started Jul 24 05:30:53 PM PDT 24
Finished Jul 24 05:31:14 PM PDT 24
Peak memory 246276 kb
Host smart-4aa1abb0-3038-4718-bdd5-6c5ae41c15e0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4102767293 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_same_csr_out
standing.4102767293
Directory /workspace/1.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.2762170287
Short name T129
Test name
Test status
Simulation time 16389348777 ps
CPU time 1233.32 seconds
Started Jul 24 05:31:10 PM PDT 24
Finished Jul 24 05:51:44 PM PDT 24
Peak memory 266020 kb
Host smart-7084cd71-3037-4c97-b93e-72a674fbb07a
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762170287 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.alert_handler_shadow_reg_errors_with_csr_rw.2762170287
Directory /workspace/1.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.332252796
Short name T755
Test name
Test status
Simulation time 365008795 ps
CPU time 22.7 seconds
Started Jul 24 05:31:05 PM PDT 24
Finished Jul 24 05:31:28 PM PDT 24
Peak memory 255132 kb
Host smart-7c76b485-7f21-4167-9589-7345e5b589ba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=332252796 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_errors.332252796
Directory /workspace/1.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.2848903084
Short name T788
Test name
Test status
Simulation time 52523477 ps
CPU time 4.54 seconds
Started Jul 24 05:31:38 PM PDT 24
Finished Jul 24 05:31:43 PM PDT 24
Peak memory 238152 kb
Host smart-f14f65a4-100c-4416-90e2-e93541b4eb18
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848903084 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 10.alert_handler_csr_mem_rw_with_rand_reset.2848903084
Directory /workspace/10.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.2521920648
Short name T731
Test name
Test status
Simulation time 21729362 ps
CPU time 3.71 seconds
Started Jul 24 05:31:36 PM PDT 24
Finished Jul 24 05:31:40 PM PDT 24
Peak memory 238028 kb
Host smart-2cdb3615-7cf1-4081-8dc1-01f1b8d07659
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2521920648 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_csr_rw.2521920648
Directory /workspace/10.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.3338490144
Short name T784
Test name
Test status
Simulation time 7262871 ps
CPU time 1.45 seconds
Started Jul 24 05:31:32 PM PDT 24
Finished Jul 24 05:31:34 PM PDT 24
Peak memory 237184 kb
Host smart-414eff7e-c79e-4029-b7b4-739c64c538ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3338490144 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_intr_test.3338490144
Directory /workspace/10.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.292434798
Short name T736
Test name
Test status
Simulation time 257613326 ps
CPU time 18.18 seconds
Started Jul 24 05:31:33 PM PDT 24
Finished Jul 24 05:31:51 PM PDT 24
Peak memory 240996 kb
Host smart-7e713157-a309-47e9-b361-079556f001bd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=292434798 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_same_csr_out
standing.292434798
Directory /workspace/10.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.2318907680
Short name T148
Test name
Test status
Simulation time 7835116017 ps
CPU time 591.43 seconds
Started Jul 24 05:31:30 PM PDT 24
Finished Jul 24 05:41:21 PM PDT 24
Peak memory 266032 kb
Host smart-6acc3a50-e38a-4f48-9e11-e801fc79d8c0
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318907680 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 10.alert_handler_shadow_reg_errors_with_csr_rw.2318907680
Directory /workspace/10.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.982339922
Short name T717
Test name
Test status
Simulation time 479884208 ps
CPU time 9.34 seconds
Started Jul 24 05:31:38 PM PDT 24
Finished Jul 24 05:31:48 PM PDT 24
Peak memory 250228 kb
Host smart-1614c28c-c402-4678-a012-838f1179329b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=982339922 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_errors.982339922
Directory /workspace/10.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.2702789105
Short name T735
Test name
Test status
Simulation time 402840195 ps
CPU time 6.28 seconds
Started Jul 24 05:31:27 PM PDT 24
Finished Jul 24 05:31:34 PM PDT 24
Peak memory 241580 kb
Host smart-2ac70a17-1477-4b94-8c6d-91eac99909e9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702789105 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 11.alert_handler_csr_mem_rw_with_rand_reset.2702789105
Directory /workspace/11.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.2486402390
Short name T183
Test name
Test status
Simulation time 71959181 ps
CPU time 3.77 seconds
Started Jul 24 05:31:39 PM PDT 24
Finished Jul 24 05:31:43 PM PDT 24
Peak memory 238036 kb
Host smart-a7200795-ec1f-42c5-b1ea-e24c4c002cea
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2486402390 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_csr_rw.2486402390
Directory /workspace/11.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.1403340933
Short name T730
Test name
Test status
Simulation time 1469201585 ps
CPU time 26.18 seconds
Started Jul 24 05:31:35 PM PDT 24
Finished Jul 24 05:32:01 PM PDT 24
Peak memory 249140 kb
Host smart-b978cd15-718b-4135-9daa-8d7121451347
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1403340933 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_same_csr_ou
tstanding.1403340933
Directory /workspace/11.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.1197270825
Short name T153
Test name
Test status
Simulation time 102970843059 ps
CPU time 1146.54 seconds
Started Jul 24 05:31:38 PM PDT 24
Finished Jul 24 05:50:44 PM PDT 24
Peak memory 266020 kb
Host smart-fa9add4b-06b1-4862-b664-7d80a5b0bc49
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197270825 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 11.alert_handler_shadow_reg_errors_with_csr_rw.1197270825
Directory /workspace/11.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.3877952867
Short name T718
Test name
Test status
Simulation time 391909969 ps
CPU time 8.09 seconds
Started Jul 24 05:31:38 PM PDT 24
Finished Jul 24 05:31:46 PM PDT 24
Peak memory 254644 kb
Host smart-6ec4ffa1-3458-4530-85b5-ef7673600c5f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3877952867 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_errors.3877952867
Directory /workspace/11.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.988113287
Short name T719
Test name
Test status
Simulation time 294447346 ps
CPU time 7.44 seconds
Started Jul 24 05:31:41 PM PDT 24
Finished Jul 24 05:31:48 PM PDT 24
Peak memory 241072 kb
Host smart-03531ded-247d-4d2b-a4f6-27f18d6cc71a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988113287 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 12.alert_handler_csr_mem_rw_with_rand_reset.988113287
Directory /workspace/12.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.2519799168
Short name T776
Test name
Test status
Simulation time 328916236 ps
CPU time 8.82 seconds
Started Jul 24 05:31:32 PM PDT 24
Finished Jul 24 05:31:42 PM PDT 24
Peak memory 240976 kb
Host smart-96b4f4bd-00b8-4834-b917-f6b6f23cb668
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2519799168 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_csr_rw.2519799168
Directory /workspace/12.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.2532258319
Short name T796
Test name
Test status
Simulation time 25686041 ps
CPU time 1.47 seconds
Started Jul 24 05:31:39 PM PDT 24
Finished Jul 24 05:31:40 PM PDT 24
Peak memory 238108 kb
Host smart-934510cb-5787-4508-9cdb-00428986d510
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2532258319 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_intr_test.2532258319
Directory /workspace/12.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.373023698
Short name T738
Test name
Test status
Simulation time 692757562 ps
CPU time 23.52 seconds
Started Jul 24 05:31:37 PM PDT 24
Finished Jul 24 05:32:01 PM PDT 24
Peak memory 240964 kb
Host smart-2cb39780-a225-41a3-8e80-392fd01cff04
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=373023698 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_same_csr_out
standing.373023698
Directory /workspace/12.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.4175924588
Short name T829
Test name
Test status
Simulation time 2529361287 ps
CPU time 172.66 seconds
Started Jul 24 05:31:31 PM PDT 24
Finished Jul 24 05:34:24 PM PDT 24
Peak memory 257848 kb
Host smart-c7aa8077-7482-4bb5-96ea-15efe6da5037
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4175924588 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shadow_reg_err
ors.4175924588
Directory /workspace/12.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.627979766
Short name T818
Test name
Test status
Simulation time 1231852359 ps
CPU time 22.86 seconds
Started Jul 24 05:31:36 PM PDT 24
Finished Jul 24 05:31:59 PM PDT 24
Peak memory 249264 kb
Host smart-6d54fb35-d3ac-4a26-b47f-19f727d5aaaa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=627979766 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_errors.627979766
Directory /workspace/12.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.562105016
Short name T342
Test name
Test status
Simulation time 997910881 ps
CPU time 5.22 seconds
Started Jul 24 05:31:40 PM PDT 24
Finished Jul 24 05:31:46 PM PDT 24
Peak memory 239456 kb
Host smart-4dd1f4c3-ad5e-49fe-a820-bf5ae1d2bc20
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562105016 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 13.alert_handler_csr_mem_rw_with_rand_reset.562105016
Directory /workspace/13.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.2583073580
Short name T792
Test name
Test status
Simulation time 193939169 ps
CPU time 6 seconds
Started Jul 24 05:31:33 PM PDT 24
Finished Jul 24 05:31:39 PM PDT 24
Peak memory 238060 kb
Host smart-6f15d9f6-d551-453c-b0ce-82e075eb9fe4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2583073580 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_csr_rw.2583073580
Directory /workspace/13.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.440440592
Short name T783
Test name
Test status
Simulation time 9328490 ps
CPU time 1.54 seconds
Started Jul 24 05:31:33 PM PDT 24
Finished Jul 24 05:31:34 PM PDT 24
Peak memory 238100 kb
Host smart-f7f982cf-bc1a-4c3d-89e8-718a87aefc1d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=440440592 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_intr_test.440440592
Directory /workspace/13.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.208358395
Short name T188
Test name
Test status
Simulation time 655403501 ps
CPU time 23.1 seconds
Started Jul 24 05:31:40 PM PDT 24
Finished Jul 24 05:32:04 PM PDT 24
Peak memory 246264 kb
Host smart-2f58a72e-b1a4-43b3-b2f0-10548a2ad961
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=208358395 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_same_csr_out
standing.208358395
Directory /workspace/13.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.3789277876
Short name T160
Test name
Test status
Simulation time 17203592201 ps
CPU time 667.48 seconds
Started Jul 24 05:31:38 PM PDT 24
Finished Jul 24 05:42:46 PM PDT 24
Peak memory 266120 kb
Host smart-2a2f7a91-0ff3-43a7-976f-a1956fe75ca2
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789277876 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 13.alert_handler_shadow_reg_errors_with_csr_rw.3789277876
Directory /workspace/13.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.3813633702
Short name T820
Test name
Test status
Simulation time 138352278 ps
CPU time 10.08 seconds
Started Jul 24 05:31:39 PM PDT 24
Finished Jul 24 05:31:50 PM PDT 24
Peak memory 248580 kb
Host smart-2c5f81ee-8036-4c0f-85b0-996c9d5fdd30
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3813633702 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_errors.3813633702
Directory /workspace/13.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.2616136785
Short name T180
Test name
Test status
Simulation time 204994687 ps
CPU time 9.8 seconds
Started Jul 24 05:31:47 PM PDT 24
Finished Jul 24 05:31:57 PM PDT 24
Peak memory 253244 kb
Host smart-969e0589-f686-4f47-8ab8-e5d8d5fb0af9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616136785 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 14.alert_handler_csr_mem_rw_with_rand_reset.2616136785
Directory /workspace/14.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.3569584758
Short name T742
Test name
Test status
Simulation time 24032533 ps
CPU time 3.64 seconds
Started Jul 24 05:31:49 PM PDT 24
Finished Jul 24 05:31:53 PM PDT 24
Peak memory 238028 kb
Host smart-93439b50-1dfc-4e70-bed3-ae6a43837c49
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3569584758 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_csr_rw.3569584758
Directory /workspace/14.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.2039648489
Short name T756
Test name
Test status
Simulation time 14804300 ps
CPU time 1.75 seconds
Started Jul 24 05:31:42 PM PDT 24
Finished Jul 24 05:31:44 PM PDT 24
Peak memory 238112 kb
Host smart-500c406f-7ff8-4e6c-9843-e4fd4f87f4ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2039648489 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_intr_test.2039648489
Directory /workspace/14.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.3298466684
Short name T759
Test name
Test status
Simulation time 2357170298 ps
CPU time 55.64 seconds
Started Jul 24 05:31:39 PM PDT 24
Finished Jul 24 05:32:35 PM PDT 24
Peak memory 246436 kb
Host smart-1e66dae5-ca3f-4d37-bfe1-0cd8911cbaa5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3298466684 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_same_csr_ou
tstanding.3298466684
Directory /workspace/14.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.211227339
Short name T155
Test name
Test status
Simulation time 8288847741 ps
CPU time 502.4 seconds
Started Jul 24 05:31:55 PM PDT 24
Finished Jul 24 05:40:18 PM PDT 24
Peak memory 266296 kb
Host smart-0d3ea913-d930-4347-9e52-b5bf692f165e
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211227339 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 14.alert_handler_shadow_reg_errors_with_csr_rw.211227339
Directory /workspace/14.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.3766395004
Short name T789
Test name
Test status
Simulation time 130687627 ps
CPU time 9.59 seconds
Started Jul 24 05:31:44 PM PDT 24
Finished Jul 24 05:31:53 PM PDT 24
Peak memory 249184 kb
Host smart-c40a6650-e05f-45c2-b567-523e279ebe44
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3766395004 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_errors.3766395004
Directory /workspace/14.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.3501432665
Short name T758
Test name
Test status
Simulation time 125179572 ps
CPU time 8.8 seconds
Started Jul 24 05:31:41 PM PDT 24
Finished Jul 24 05:31:50 PM PDT 24
Peak memory 257036 kb
Host smart-f400cf11-f7bc-49d7-b393-dd080f9391ee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501432665 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 15.alert_handler_csr_mem_rw_with_rand_reset.3501432665
Directory /workspace/15.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.1669951717
Short name T733
Test name
Test status
Simulation time 126478807 ps
CPU time 6.46 seconds
Started Jul 24 05:31:48 PM PDT 24
Finished Jul 24 05:31:55 PM PDT 24
Peak memory 238260 kb
Host smart-e2432214-f78e-4166-9e2e-a09469c6df93
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1669951717 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_csr_rw.1669951717
Directory /workspace/15.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.4017879506
Short name T830
Test name
Test status
Simulation time 17848842 ps
CPU time 1.39 seconds
Started Jul 24 05:31:51 PM PDT 24
Finished Jul 24 05:31:53 PM PDT 24
Peak memory 238112 kb
Host smart-69b82b1c-a310-4335-8ef0-24e6a7dcc1c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4017879506 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_intr_test.4017879506
Directory /workspace/15.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.3589187146
Short name T816
Test name
Test status
Simulation time 92796488 ps
CPU time 13.5 seconds
Started Jul 24 05:31:39 PM PDT 24
Finished Jul 24 05:31:53 PM PDT 24
Peak memory 246208 kb
Host smart-527473c7-439a-4325-99e2-20ec2db58733
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3589187146 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_same_csr_ou
tstanding.3589187146
Directory /workspace/15.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.2222040852
Short name T157
Test name
Test status
Simulation time 1973237874 ps
CPU time 164.46 seconds
Started Jul 24 05:31:49 PM PDT 24
Finished Jul 24 05:34:34 PM PDT 24
Peak memory 269228 kb
Host smart-e3b80c60-5a03-4625-ade5-ee4592080f57
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2222040852 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shadow_reg_err
ors.2222040852
Directory /workspace/15.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.494499863
Short name T142
Test name
Test status
Simulation time 22175619027 ps
CPU time 344.51 seconds
Started Jul 24 05:31:41 PM PDT 24
Finished Jul 24 05:37:26 PM PDT 24
Peak memory 266044 kb
Host smart-d27ba9d1-5025-4d17-a818-4cb16ee352fa
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494499863 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 15.alert_handler_shadow_reg_errors_with_csr_rw.494499863
Directory /workspace/15.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.705220442
Short name T761
Test name
Test status
Simulation time 98349210 ps
CPU time 10.77 seconds
Started Jul 24 05:31:43 PM PDT 24
Finished Jul 24 05:31:54 PM PDT 24
Peak memory 249156 kb
Host smart-722ba385-5a06-4afa-a753-d7077a098de0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=705220442 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_errors.705220442
Directory /workspace/15.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.1461834515
Short name T191
Test name
Test status
Simulation time 110090237 ps
CPU time 4.77 seconds
Started Jul 24 05:31:51 PM PDT 24
Finished Jul 24 05:31:56 PM PDT 24
Peak memory 241480 kb
Host smart-07fe9ef3-1c9f-4f8c-a5ff-e898b26b0537
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461834515 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 16.alert_handler_csr_mem_rw_with_rand_reset.1461834515
Directory /workspace/16.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.3387993165
Short name T805
Test name
Test status
Simulation time 177688186 ps
CPU time 9.39 seconds
Started Jul 24 05:31:47 PM PDT 24
Finished Jul 24 05:31:56 PM PDT 24
Peak memory 238076 kb
Host smart-1d1e472b-1213-44a9-98db-20b56de89dfc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3387993165 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_csr_rw.3387993165
Directory /workspace/16.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.1225744681
Short name T813
Test name
Test status
Simulation time 10213873 ps
CPU time 1.7 seconds
Started Jul 24 05:31:48 PM PDT 24
Finished Jul 24 05:31:50 PM PDT 24
Peak memory 237284 kb
Host smart-ceddcdd2-c564-4769-a4da-afc39c845dfa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1225744681 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_intr_test.1225744681
Directory /workspace/16.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.2608245264
Short name T817
Test name
Test status
Simulation time 494548479 ps
CPU time 32.65 seconds
Started Jul 24 05:31:48 PM PDT 24
Finished Jul 24 05:32:21 PM PDT 24
Peak memory 249148 kb
Host smart-dbcdfe79-137d-4307-a90e-acda4b9075ab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2608245264 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_same_csr_ou
tstanding.2608245264
Directory /workspace/16.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.1510377984
Short name T154
Test name
Test status
Simulation time 4644076979 ps
CPU time 728.82 seconds
Started Jul 24 05:31:48 PM PDT 24
Finished Jul 24 05:43:58 PM PDT 24
Peak memory 266128 kb
Host smart-bcf9479f-e435-4743-9b7f-1078fd7ba22f
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510377984 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 16.alert_handler_shadow_reg_errors_with_csr_rw.1510377984
Directory /workspace/16.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.2281564597
Short name T734
Test name
Test status
Simulation time 961468895 ps
CPU time 17.11 seconds
Started Jul 24 05:31:51 PM PDT 24
Finished Jul 24 05:32:08 PM PDT 24
Peak memory 249072 kb
Host smart-316a8c1f-86bc-42a9-b563-0a8cc1d0c485
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2281564597 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_errors.2281564597
Directory /workspace/16.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.435324333
Short name T192
Test name
Test status
Simulation time 229080234 ps
CPU time 8.95 seconds
Started Jul 24 05:31:48 PM PDT 24
Finished Jul 24 05:31:57 PM PDT 24
Peak memory 257404 kb
Host smart-72e0eb49-fbd9-44c5-ade8-99db9b09e382
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435324333 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 17.alert_handler_csr_mem_rw_with_rand_reset.435324333
Directory /workspace/17.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.3839772380
Short name T184
Test name
Test status
Simulation time 68143764 ps
CPU time 3.13 seconds
Started Jul 24 05:31:46 PM PDT 24
Finished Jul 24 05:31:49 PM PDT 24
Peak memory 237092 kb
Host smart-5006be02-0670-43c5-b269-11ce752bea47
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3839772380 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_csr_rw.3839772380
Directory /workspace/17.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.3067441462
Short name T751
Test name
Test status
Simulation time 12765412 ps
CPU time 1.5 seconds
Started Jul 24 05:31:48 PM PDT 24
Finished Jul 24 05:31:50 PM PDT 24
Peak memory 237136 kb
Host smart-f4346d8b-b529-4a17-bf56-adfe3d92c0ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3067441462 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_intr_test.3067441462
Directory /workspace/17.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.2901480857
Short name T774
Test name
Test status
Simulation time 603358046 ps
CPU time 10.71 seconds
Started Jul 24 05:31:54 PM PDT 24
Finished Jul 24 05:32:04 PM PDT 24
Peak memory 240984 kb
Host smart-b9f96d94-ff1c-4708-9be9-9fe26204f5e7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2901480857 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_same_csr_ou
tstanding.2901480857
Directory /workspace/17.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.3136587826
Short name T151
Test name
Test status
Simulation time 6764697206 ps
CPU time 191.64 seconds
Started Jul 24 05:31:52 PM PDT 24
Finished Jul 24 05:35:04 PM PDT 24
Peak memory 273516 kb
Host smart-3f08f4f0-4121-46c4-a9b1-6db48b841429
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3136587826 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shadow_reg_err
ors.3136587826
Directory /workspace/17.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.1068096316
Short name T137
Test name
Test status
Simulation time 15213810001 ps
CPU time 546.85 seconds
Started Jul 24 05:31:49 PM PDT 24
Finished Jul 24 05:40:56 PM PDT 24
Peak memory 270124 kb
Host smart-1e77a1f0-24e3-40c2-80a9-d7c13e855a4f
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068096316 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 17.alert_handler_shadow_reg_errors_with_csr_rw.1068096316
Directory /workspace/17.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.2404146467
Short name T729
Test name
Test status
Simulation time 465287421 ps
CPU time 5.63 seconds
Started Jul 24 05:31:49 PM PDT 24
Finished Jul 24 05:31:55 PM PDT 24
Peak memory 249332 kb
Host smart-378a483c-dcaf-4fee-b979-33976bc5502a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2404146467 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_errors.2404146467
Directory /workspace/17.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.3110013093
Short name T727
Test name
Test status
Simulation time 415734532 ps
CPU time 8.81 seconds
Started Jul 24 05:31:55 PM PDT 24
Finished Jul 24 05:32:04 PM PDT 24
Peak memory 257172 kb
Host smart-b4da5211-706b-4250-871d-3df59ba000ea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110013093 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 18.alert_handler_csr_mem_rw_with_rand_reset.3110013093
Directory /workspace/18.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.913834102
Short name T825
Test name
Test status
Simulation time 398746022 ps
CPU time 7.46 seconds
Started Jul 24 05:31:56 PM PDT 24
Finished Jul 24 05:32:04 PM PDT 24
Peak memory 237104 kb
Host smart-70be07c8-5859-4287-a86c-137bccfad9b5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=913834102 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_csr_rw.913834102
Directory /workspace/18.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.2266434978
Short name T339
Test name
Test status
Simulation time 12077826 ps
CPU time 1.32 seconds
Started Jul 24 05:31:53 PM PDT 24
Finished Jul 24 05:31:54 PM PDT 24
Peak memory 237196 kb
Host smart-27cbf4e6-961c-4789-bbfb-ccabb25b3fcd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2266434978 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_intr_test.2266434978
Directory /workspace/18.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.3340900457
Short name T762
Test name
Test status
Simulation time 1142275603 ps
CPU time 16.41 seconds
Started Jul 24 05:31:56 PM PDT 24
Finished Jul 24 05:32:12 PM PDT 24
Peak memory 245300 kb
Host smart-fe0d2ce1-411c-4c4a-a510-7958eb1e2fb3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3340900457 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_same_csr_ou
tstanding.3340900457
Directory /workspace/18.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.868731758
Short name T140
Test name
Test status
Simulation time 3247203369 ps
CPU time 256.9 seconds
Started Jul 24 05:31:47 PM PDT 24
Finished Jul 24 05:36:04 PM PDT 24
Peak memory 266084 kb
Host smart-12b4c542-1fca-4e55-baa7-477f57c43d64
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=868731758 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shadow_reg_erro
rs.868731758
Directory /workspace/18.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.1814245142
Short name T147
Test name
Test status
Simulation time 4515983792 ps
CPU time 642.23 seconds
Started Jul 24 05:31:47 PM PDT 24
Finished Jul 24 05:42:29 PM PDT 24
Peak memory 266020 kb
Host smart-fa7acb46-b5d2-4476-a714-633704aeb685
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814245142 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 18.alert_handler_shadow_reg_errors_with_csr_rw.1814245142
Directory /workspace/18.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.3895332279
Short name T722
Test name
Test status
Simulation time 133927272 ps
CPU time 7.42 seconds
Started Jul 24 05:31:53 PM PDT 24
Finished Jul 24 05:32:00 PM PDT 24
Peak memory 249252 kb
Host smart-ee08faa0-a1f7-422c-a690-1a9a0550ec50
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3895332279 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_errors.3895332279
Directory /workspace/18.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.52983816
Short name T752
Test name
Test status
Simulation time 325087630 ps
CPU time 11.9 seconds
Started Jul 24 05:31:55 PM PDT 24
Finished Jul 24 05:32:07 PM PDT 24
Peak memory 252288 kb
Host smart-ce5d02d5-25f8-44d5-8598-05827b8bf947
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52983816 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 19.alert_handler_csr_mem_rw_with_rand_reset.52983816
Directory /workspace/19.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.3222731628
Short name T782
Test name
Test status
Simulation time 51740809 ps
CPU time 4.63 seconds
Started Jul 24 05:31:51 PM PDT 24
Finished Jul 24 05:31:56 PM PDT 24
Peak memory 238012 kb
Host smart-936c91ad-6e54-45cb-a6bb-a8d1c4aff98c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3222731628 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_csr_rw.3222731628
Directory /workspace/19.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.1968926850
Short name T750
Test name
Test status
Simulation time 9720646 ps
CPU time 1.63 seconds
Started Jul 24 05:31:54 PM PDT 24
Finished Jul 24 05:31:56 PM PDT 24
Peak memory 237164 kb
Host smart-4651aa67-e352-4480-a220-8d02b26334be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1968926850 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_intr_test.1968926850
Directory /workspace/19.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.691457535
Short name T189
Test name
Test status
Simulation time 169999478 ps
CPU time 22.22 seconds
Started Jul 24 05:31:55 PM PDT 24
Finished Jul 24 05:32:17 PM PDT 24
Peak memory 246228 kb
Host smart-411a062c-11aa-42a1-af07-37caa92c988d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=691457535 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_same_csr_out
standing.691457535
Directory /workspace/19.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.1948973522
Short name T156
Test name
Test status
Simulation time 24733498949 ps
CPU time 490.81 seconds
Started Jul 24 05:31:57 PM PDT 24
Finished Jul 24 05:40:08 PM PDT 24
Peak memory 266160 kb
Host smart-d8598f4d-60ca-4bb5-ba76-534711174c30
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948973522 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 19.alert_handler_shadow_reg_errors_with_csr_rw.1948973522
Directory /workspace/19.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.1573826419
Short name T775
Test name
Test status
Simulation time 136877497 ps
CPU time 9.04 seconds
Started Jul 24 05:31:53 PM PDT 24
Finished Jul 24 05:32:02 PM PDT 24
Peak memory 255252 kb
Host smart-37396ad1-4c4c-4750-8dc8-8e40306c1bd7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1573826419 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_errors.1573826419
Directory /workspace/19.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.381422587
Short name T819
Test name
Test status
Simulation time 3889841432 ps
CPU time 249.12 seconds
Started Jul 24 05:31:25 PM PDT 24
Finished Jul 24 05:35:34 PM PDT 24
Peak memory 241180 kb
Host smart-26d3323f-8025-4c14-891d-86e8b6d7194e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=381422587 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_aliasing.381422587
Directory /workspace/2.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.1210029073
Short name T833
Test name
Test status
Simulation time 37165107435 ps
CPU time 453.94 seconds
Started Jul 24 05:31:17 PM PDT 24
Finished Jul 24 05:38:52 PM PDT 24
Peak memory 237188 kb
Host smart-753cd450-4e85-4300-813e-8b2be792d104
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1210029073 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_bit_bash.1210029073
Directory /workspace/2.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.3036220490
Short name T772
Test name
Test status
Simulation time 284609767 ps
CPU time 9.6 seconds
Started Jul 24 05:31:22 PM PDT 24
Finished Jul 24 05:31:31 PM PDT 24
Peak memory 249200 kb
Host smart-8d3b6f5e-1b00-49e7-a5a6-c85a04922976
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3036220490 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_hw_reset.3036220490
Directory /workspace/2.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.2440566032
Short name T346
Test name
Test status
Simulation time 111121001 ps
CPU time 9.24 seconds
Started Jul 24 05:31:16 PM PDT 24
Finished Jul 24 05:31:26 PM PDT 24
Peak memory 241004 kb
Host smart-c49039da-8d19-4c4b-8d78-8e8ebb0e758e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440566032 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 2.alert_handler_csr_mem_rw_with_rand_reset.2440566032
Directory /workspace/2.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.4201975209
Short name T186
Test name
Test status
Simulation time 228439904 ps
CPU time 4.61 seconds
Started Jul 24 05:31:14 PM PDT 24
Finished Jul 24 05:31:19 PM PDT 24
Peak memory 237040 kb
Host smart-48f9756b-de5d-461a-a22e-404c8277e536
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4201975209 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_rw.4201975209
Directory /workspace/2.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.2860678425
Short name T786
Test name
Test status
Simulation time 21870273 ps
CPU time 1.28 seconds
Started Jul 24 05:31:13 PM PDT 24
Finished Jul 24 05:31:14 PM PDT 24
Peak memory 238124 kb
Host smart-29e72455-e346-4bcf-858c-5a4b2a4b2043
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2860678425 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_intr_test.2860678425
Directory /workspace/2.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.3225395227
Short name T744
Test name
Test status
Simulation time 1007470904 ps
CPU time 19.47 seconds
Started Jul 24 05:31:16 PM PDT 24
Finished Jul 24 05:31:35 PM PDT 24
Peak memory 246164 kb
Host smart-dfc59b5d-4834-4cf6-b4a8-789ba03d5800
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3225395227 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_same_csr_out
standing.3225395227
Directory /workspace/2.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.435339270
Short name T139
Test name
Test status
Simulation time 2149710377 ps
CPU time 146.33 seconds
Started Jul 24 05:31:20 PM PDT 24
Finished Jul 24 05:33:47 PM PDT 24
Peak memory 266044 kb
Host smart-f433f816-98cd-484f-b3b0-5034003b0f5b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=435339270 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shadow_reg_error
s.435339270
Directory /workspace/2.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.2875225227
Short name T827
Test name
Test status
Simulation time 122134780 ps
CPU time 8.02 seconds
Started Jul 24 05:31:21 PM PDT 24
Finished Jul 24 05:31:29 PM PDT 24
Peak memory 249244 kb
Host smart-c66c963e-4aa9-4f3a-a420-ac89dbf68261
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2875225227 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_errors.2875225227
Directory /workspace/2.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.103561177
Short name T335
Test name
Test status
Simulation time 8937382 ps
CPU time 1.68 seconds
Started Jul 24 05:31:52 PM PDT 24
Finished Jul 24 05:31:54 PM PDT 24
Peak memory 237232 kb
Host smart-b6f3f638-faff-485d-865c-d4e36c321c40
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=103561177 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.alert_handler_intr_test.103561177
Directory /workspace/20.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.1318489305
Short name T823
Test name
Test status
Simulation time 8892794 ps
CPU time 1.64 seconds
Started Jul 24 05:31:56 PM PDT 24
Finished Jul 24 05:31:58 PM PDT 24
Peak memory 238056 kb
Host smart-e27edc0d-2534-49a2-a70e-fe84e5ec01a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1318489305 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.alert_handler_intr_test.1318489305
Directory /workspace/21.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.1525475044
Short name T218
Test name
Test status
Simulation time 7813218 ps
CPU time 1.4 seconds
Started Jul 24 05:31:55 PM PDT 24
Finished Jul 24 05:31:56 PM PDT 24
Peak memory 238140 kb
Host smart-48216ace-f472-4386-8ca6-f2eac517f831
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1525475044 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.alert_handler_intr_test.1525475044
Directory /workspace/22.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.1937342936
Short name T746
Test name
Test status
Simulation time 9706924 ps
CPU time 1.36 seconds
Started Jul 24 05:31:54 PM PDT 24
Finished Jul 24 05:31:56 PM PDT 24
Peak memory 236180 kb
Host smart-69b740a6-70e2-481e-9621-57c1b8279f23
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1937342936 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.alert_handler_intr_test.1937342936
Directory /workspace/23.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.2253396997
Short name T334
Test name
Test status
Simulation time 10559847 ps
CPU time 1.35 seconds
Started Jul 24 05:32:01 PM PDT 24
Finished Jul 24 05:32:02 PM PDT 24
Peak memory 238048 kb
Host smart-f81224b3-cb00-4e54-8cc3-5689f5deece0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2253396997 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.alert_handler_intr_test.2253396997
Directory /workspace/24.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.2051415063
Short name T812
Test name
Test status
Simulation time 7868119 ps
CPU time 1.53 seconds
Started Jul 24 05:31:54 PM PDT 24
Finished Jul 24 05:31:56 PM PDT 24
Peak memory 238192 kb
Host smart-d6d33775-1c12-4f38-b516-654bf4734be3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2051415063 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.alert_handler_intr_test.2051415063
Directory /workspace/25.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.1020911232
Short name T815
Test name
Test status
Simulation time 7166391 ps
CPU time 1.4 seconds
Started Jul 24 05:31:55 PM PDT 24
Finished Jul 24 05:31:56 PM PDT 24
Peak memory 238100 kb
Host smart-cf1bf221-b209-47fc-a92b-0c733894b61a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1020911232 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.alert_handler_intr_test.1020911232
Directory /workspace/26.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.1757657694
Short name T336
Test name
Test status
Simulation time 8633289 ps
CPU time 1.39 seconds
Started Jul 24 05:31:56 PM PDT 24
Finished Jul 24 05:31:58 PM PDT 24
Peak memory 237184 kb
Host smart-eccc49b7-b28d-4853-9554-1e38e9baed9d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1757657694 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.alert_handler_intr_test.1757657694
Directory /workspace/27.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.90284696
Short name T834
Test name
Test status
Simulation time 19230303 ps
CPU time 1.33 seconds
Started Jul 24 05:31:57 PM PDT 24
Finished Jul 24 05:31:58 PM PDT 24
Peak memory 238136 kb
Host smart-599f4d82-cc52-410f-a7e5-bbbd1c4f63a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=90284696 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.alert_handler_intr_test.90284696
Directory /workspace/28.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.1174421454
Short name T728
Test name
Test status
Simulation time 7187946 ps
CPU time 1.27 seconds
Started Jul 24 05:31:59 PM PDT 24
Finished Jul 24 05:32:00 PM PDT 24
Peak memory 235984 kb
Host smart-69f5c8d4-e47c-4e86-8a26-576f4e876927
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1174421454 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.alert_handler_intr_test.1174421454
Directory /workspace/29.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.2608939700
Short name T185
Test name
Test status
Simulation time 18334981202 ps
CPU time 317.26 seconds
Started Jul 24 05:31:11 PM PDT 24
Finished Jul 24 05:36:29 PM PDT 24
Peak memory 241092 kb
Host smart-3552ea64-a922-4245-b58a-2397155734d7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2608939700 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_aliasing.2608939700
Directory /workspace/3.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.3377963845
Short name T347
Test name
Test status
Simulation time 11919231590 ps
CPU time 200.44 seconds
Started Jul 24 05:31:24 PM PDT 24
Finished Jul 24 05:34:44 PM PDT 24
Peak memory 238184 kb
Host smart-58713ae9-21cf-4cf4-9024-0c19f6bca6b9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3377963845 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_bit_bash.3377963845
Directory /workspace/3.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.435448107
Short name T791
Test name
Test status
Simulation time 104562499 ps
CPU time 9.45 seconds
Started Jul 24 05:31:17 PM PDT 24
Finished Jul 24 05:31:27 PM PDT 24
Peak memory 241044 kb
Host smart-28563f4b-71bb-4001-aeff-cffb8311bb10
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=435448107 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_hw_reset.435448107
Directory /workspace/3.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.3804594123
Short name T779
Test name
Test status
Simulation time 228799552 ps
CPU time 10.82 seconds
Started Jul 24 05:31:16 PM PDT 24
Finished Jul 24 05:31:27 PM PDT 24
Peak memory 244368 kb
Host smart-75a22a6c-b414-49d2-83f7-c50bc800cd96
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804594123 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 3.alert_handler_csr_mem_rw_with_rand_reset.3804594123
Directory /workspace/3.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.418477937
Short name T821
Test name
Test status
Simulation time 35029526 ps
CPU time 3.61 seconds
Started Jul 24 05:31:16 PM PDT 24
Finished Jul 24 05:31:20 PM PDT 24
Peak memory 240936 kb
Host smart-181d1927-6d6f-4f07-8aa3-52f0aa63dc5c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=418477937 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_rw.418477937
Directory /workspace/3.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.3013304623
Short name T754
Test name
Test status
Simulation time 7400976 ps
CPU time 1.45 seconds
Started Jul 24 05:31:19 PM PDT 24
Finished Jul 24 05:31:21 PM PDT 24
Peak memory 238096 kb
Host smart-3d8823e7-2195-42e5-8103-906f6acfa5ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3013304623 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_intr_test.3013304623
Directory /workspace/3.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.231898521
Short name T739
Test name
Test status
Simulation time 4353327859 ps
CPU time 48.4 seconds
Started Jul 24 05:31:19 PM PDT 24
Finished Jul 24 05:32:07 PM PDT 24
Peak memory 246412 kb
Host smart-902d4af1-7a97-4327-a13c-4abd61635b0a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=231898521 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_same_csr_outs
tanding.231898521
Directory /workspace/3.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.2863350072
Short name T780
Test name
Test status
Simulation time 561535126 ps
CPU time 14.5 seconds
Started Jul 24 05:31:09 PM PDT 24
Finished Jul 24 05:31:23 PM PDT 24
Peak memory 249196 kb
Host smart-ed707e25-e307-4d76-b439-2a283e098a66
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2863350072 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_errors.2863350072
Directory /workspace/3.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.93642776
Short name T760
Test name
Test status
Simulation time 8587756 ps
CPU time 1.52 seconds
Started Jul 24 05:31:57 PM PDT 24
Finished Jul 24 05:31:58 PM PDT 24
Peak memory 238136 kb
Host smart-915f56c2-0066-4374-91f6-6e4bc4a444de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=93642776 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.alert_handler_intr_test.93642776
Directory /workspace/30.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.1901066952
Short name T166
Test name
Test status
Simulation time 9570671 ps
CPU time 1.69 seconds
Started Jul 24 05:31:57 PM PDT 24
Finished Jul 24 05:31:59 PM PDT 24
Peak memory 237172 kb
Host smart-b2858a6a-3053-480b-ada0-a713589e7ea5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1901066952 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.alert_handler_intr_test.1901066952
Directory /workspace/31.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.276411928
Short name T164
Test name
Test status
Simulation time 27920046 ps
CPU time 1.34 seconds
Started Jul 24 05:31:56 PM PDT 24
Finished Jul 24 05:31:57 PM PDT 24
Peak memory 238144 kb
Host smart-eb6fd87b-9929-43e3-833e-616088ea33a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=276411928 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.alert_handler_intr_test.276411928
Directory /workspace/32.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.alert_handler_intr_test.2686026391
Short name T743
Test name
Test status
Simulation time 11960412 ps
CPU time 1.5 seconds
Started Jul 24 05:32:06 PM PDT 24
Finished Jul 24 05:32:07 PM PDT 24
Peak memory 237156 kb
Host smart-790597a8-7cf5-4ec4-a03c-5a499455b911
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2686026391 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.alert_handler_intr_test.2686026391
Directory /workspace/33.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.1946217421
Short name T740
Test name
Test status
Simulation time 8945294 ps
CPU time 1.41 seconds
Started Jul 24 05:32:05 PM PDT 24
Finished Jul 24 05:32:06 PM PDT 24
Peak memory 237396 kb
Host smart-dedc6ba7-1e22-42ac-b1c9-4a12d93f1b32
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1946217421 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.alert_handler_intr_test.1946217421
Directory /workspace/34.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.200477308
Short name T828
Test name
Test status
Simulation time 19966032 ps
CPU time 1.43 seconds
Started Jul 24 05:32:05 PM PDT 24
Finished Jul 24 05:32:06 PM PDT 24
Peak memory 238144 kb
Host smart-f4f27b74-5421-4f7a-af8f-d71e171764e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=200477308 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.alert_handler_intr_test.200477308
Directory /workspace/35.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.2075271684
Short name T803
Test name
Test status
Simulation time 27319332 ps
CPU time 2.22 seconds
Started Jul 24 05:32:04 PM PDT 24
Finished Jul 24 05:32:07 PM PDT 24
Peak memory 238144 kb
Host smart-77e604fe-cfb7-446c-a81e-dccd250030b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2075271684 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.alert_handler_intr_test.2075271684
Directory /workspace/36.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.1310055250
Short name T831
Test name
Test status
Simulation time 29266793 ps
CPU time 1.46 seconds
Started Jul 24 05:32:13 PM PDT 24
Finished Jul 24 05:32:15 PM PDT 24
Peak memory 238096 kb
Host smart-e7ddca0f-6667-4126-a89f-2896437d200a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1310055250 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.alert_handler_intr_test.1310055250
Directory /workspace/37.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.1830459608
Short name T771
Test name
Test status
Simulation time 8933994 ps
CPU time 1.5 seconds
Started Jul 24 05:32:09 PM PDT 24
Finished Jul 24 05:32:10 PM PDT 24
Peak memory 238104 kb
Host smart-a2f2b9da-9fc6-4588-a58d-38016267a683
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1830459608 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.alert_handler_intr_test.1830459608
Directory /workspace/38.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.2655369349
Short name T797
Test name
Test status
Simulation time 17054828 ps
CPU time 1.84 seconds
Started Jul 24 05:32:04 PM PDT 24
Finished Jul 24 05:32:06 PM PDT 24
Peak memory 236148 kb
Host smart-4f4fe203-0136-49d1-9ef0-f43253961136
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2655369349 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.alert_handler_intr_test.2655369349
Directory /workspace/39.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.3292485086
Short name T765
Test name
Test status
Simulation time 9064350731 ps
CPU time 155.98 seconds
Started Jul 24 05:31:26 PM PDT 24
Finished Jul 24 05:34:02 PM PDT 24
Peak memory 241108 kb
Host smart-6f0c6307-d374-4f54-b2fe-ceb974faa3b8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3292485086 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_aliasing.3292485086
Directory /workspace/4.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.773471485
Short name T785
Test name
Test status
Simulation time 28482734896 ps
CPU time 285.32 seconds
Started Jul 24 05:31:16 PM PDT 24
Finished Jul 24 05:36:02 PM PDT 24
Peak memory 241036 kb
Host smart-3b5ccd4b-22bd-40f5-abba-7b6262d2ccdc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=773471485 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_bit_bash.773471485
Directory /workspace/4.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.1969834547
Short name T777
Test name
Test status
Simulation time 540816063 ps
CPU time 10.02 seconds
Started Jul 24 05:31:14 PM PDT 24
Finished Jul 24 05:31:25 PM PDT 24
Peak memory 249664 kb
Host smart-9c0dd372-25dd-4ce3-9c36-2d03c51b643e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1969834547 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_hw_reset.1969834547
Directory /workspace/4.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.2529249915
Short name T720
Test name
Test status
Simulation time 56541271 ps
CPU time 5.66 seconds
Started Jul 24 05:31:17 PM PDT 24
Finished Jul 24 05:31:22 PM PDT 24
Peak memory 240816 kb
Host smart-5444cac6-dd37-4fc6-8e4f-37bf6db3146e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529249915 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 4.alert_handler_csr_mem_rw_with_rand_reset.2529249915
Directory /workspace/4.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.1986979459
Short name T787
Test name
Test status
Simulation time 130898155 ps
CPU time 5.14 seconds
Started Jul 24 05:31:27 PM PDT 24
Finished Jul 24 05:31:32 PM PDT 24
Peak memory 237076 kb
Host smart-a5e14211-df7a-43af-ae2f-a7520d91c07b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1986979459 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_rw.1986979459
Directory /workspace/4.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.323654105
Short name T793
Test name
Test status
Simulation time 13550993 ps
CPU time 1.51 seconds
Started Jul 24 05:31:22 PM PDT 24
Finished Jul 24 05:31:24 PM PDT 24
Peak memory 236200 kb
Host smart-07e5079d-5cd4-4171-9eda-ad723e881785
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=323654105 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_intr_test.323654105
Directory /workspace/4.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.1093831335
Short name T768
Test name
Test status
Simulation time 984744459 ps
CPU time 22.6 seconds
Started Jul 24 05:31:23 PM PDT 24
Finished Jul 24 05:31:46 PM PDT 24
Peak memory 246288 kb
Host smart-5ddaf96f-6e6f-41da-9849-4fdb8f0909c3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1093831335 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_same_csr_out
standing.1093831335
Directory /workspace/4.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.3258100094
Short name T143
Test name
Test status
Simulation time 4427878374 ps
CPU time 646.57 seconds
Started Jul 24 05:31:19 PM PDT 24
Finished Jul 24 05:42:05 PM PDT 24
Peak memory 266060 kb
Host smart-8118f696-557e-4bdd-86d9-cbc738c04247
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258100094 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.alert_handler_shadow_reg_errors_with_csr_rw.3258100094
Directory /workspace/4.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.1184190174
Short name T724
Test name
Test status
Simulation time 111636067 ps
CPU time 8.7 seconds
Started Jul 24 05:31:21 PM PDT 24
Finished Jul 24 05:31:30 PM PDT 24
Peak memory 254468 kb
Host smart-fa2450ba-5f3e-417e-9a3f-4b4210ca9d2b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1184190174 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_errors.1184190174
Directory /workspace/4.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.2959142689
Short name T251
Test name
Test status
Simulation time 301227677 ps
CPU time 19.28 seconds
Started Jul 24 05:31:20 PM PDT 24
Finished Jul 24 05:31:39 PM PDT 24
Peak memory 238260 kb
Host smart-834553c2-0898-4959-b640-3122517a27ec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2959142689 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_intg_err.2959142689
Directory /workspace/4.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.3946220848
Short name T757
Test name
Test status
Simulation time 8306850 ps
CPU time 1.52 seconds
Started Jul 24 05:32:05 PM PDT 24
Finished Jul 24 05:32:06 PM PDT 24
Peak memory 236064 kb
Host smart-55bbf47b-db3b-4989-a79a-32f54a44df44
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3946220848 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.alert_handler_intr_test.3946220848
Directory /workspace/40.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.1004953676
Short name T781
Test name
Test status
Simulation time 7998364 ps
CPU time 1.4 seconds
Started Jul 24 05:32:05 PM PDT 24
Finished Jul 24 05:32:07 PM PDT 24
Peak memory 238136 kb
Host smart-68e8ed6f-0a93-4a9e-9834-f5bc2edaf0ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1004953676 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.alert_handler_intr_test.1004953676
Directory /workspace/41.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.4293096895
Short name T338
Test name
Test status
Simulation time 12681545 ps
CPU time 1.72 seconds
Started Jul 24 05:32:04 PM PDT 24
Finished Jul 24 05:32:06 PM PDT 24
Peak memory 238196 kb
Host smart-dd07beda-043a-4c95-a5df-fac5893b41f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4293096895 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.alert_handler_intr_test.4293096895
Directory /workspace/42.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.838644438
Short name T790
Test name
Test status
Simulation time 6762597 ps
CPU time 1.48 seconds
Started Jul 24 05:32:08 PM PDT 24
Finished Jul 24 05:32:09 PM PDT 24
Peak memory 238108 kb
Host smart-3c0be25f-818a-4ace-94bb-5bf94c55d3f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=838644438 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.alert_handler_intr_test.838644438
Directory /workspace/43.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.985717154
Short name T766
Test name
Test status
Simulation time 9409831 ps
CPU time 1.38 seconds
Started Jul 24 05:32:12 PM PDT 24
Finished Jul 24 05:32:13 PM PDT 24
Peak memory 238112 kb
Host smart-eeeb7a26-6192-4d60-8e83-a3693fd1fd31
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=985717154 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.alert_handler_intr_test.985717154
Directory /workspace/44.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.687303891
Short name T732
Test name
Test status
Simulation time 23212607 ps
CPU time 1.29 seconds
Started Jul 24 05:32:04 PM PDT 24
Finished Jul 24 05:32:06 PM PDT 24
Peak memory 237016 kb
Host smart-85dc8dfd-218b-430e-971e-1369025bc63b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=687303891 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.alert_handler_intr_test.687303891
Directory /workspace/45.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.1625503171
Short name T767
Test name
Test status
Simulation time 17705257 ps
CPU time 1.78 seconds
Started Jul 24 05:32:09 PM PDT 24
Finished Jul 24 05:32:11 PM PDT 24
Peak memory 237136 kb
Host smart-afeebae4-438d-45f0-a8cb-9f45f54af77e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1625503171 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.alert_handler_intr_test.1625503171
Directory /workspace/46.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.817624425
Short name T340
Test name
Test status
Simulation time 10667354 ps
CPU time 1.41 seconds
Started Jul 24 05:32:08 PM PDT 24
Finished Jul 24 05:32:09 PM PDT 24
Peak memory 237168 kb
Host smart-f975ab14-f1d9-4984-85e4-53d1d0521f16
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=817624425 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.alert_handler_intr_test.817624425
Directory /workspace/48.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.2396750095
Short name T778
Test name
Test status
Simulation time 70163087 ps
CPU time 1.51 seconds
Started Jul 24 05:32:07 PM PDT 24
Finished Jul 24 05:32:09 PM PDT 24
Peak memory 238096 kb
Host smart-56d11698-dbc1-43ec-b911-7206ea21ea82
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2396750095 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.alert_handler_intr_test.2396750095
Directory /workspace/49.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.3557559029
Short name T753
Test name
Test status
Simulation time 238411181 ps
CPU time 12.16 seconds
Started Jul 24 05:31:22 PM PDT 24
Finished Jul 24 05:31:35 PM PDT 24
Peak memory 250564 kb
Host smart-3a9cbe7a-8df5-4791-8704-905621b46c74
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557559029 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 5.alert_handler_csr_mem_rw_with_rand_reset.3557559029
Directory /workspace/5.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.1007985126
Short name T178
Test name
Test status
Simulation time 34958278 ps
CPU time 5.37 seconds
Started Jul 24 05:31:18 PM PDT 24
Finished Jul 24 05:31:23 PM PDT 24
Peak memory 240940 kb
Host smart-b471d2d5-7833-423a-beee-7f46a0bf0046
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1007985126 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_csr_rw.1007985126
Directory /workspace/5.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.644057898
Short name T749
Test name
Test status
Simulation time 11978517 ps
CPU time 1.47 seconds
Started Jul 24 05:31:17 PM PDT 24
Finished Jul 24 05:31:19 PM PDT 24
Peak memory 237164 kb
Host smart-8f5dbdc5-1ca2-44e5-a21d-6744e9e49803
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=644057898 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_intr_test.644057898
Directory /workspace/5.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.4281690752
Short name T721
Test name
Test status
Simulation time 504270985 ps
CPU time 35.49 seconds
Started Jul 24 05:31:24 PM PDT 24
Finished Jul 24 05:31:59 PM PDT 24
Peak memory 249204 kb
Host smart-aa0187fc-f4d6-42d6-8a72-73dc898e5d21
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4281690752 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_same_csr_out
standing.4281690752
Directory /workspace/5.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.1540649471
Short name T128
Test name
Test status
Simulation time 15425943919 ps
CPU time 300.25 seconds
Started Jul 24 05:31:22 PM PDT 24
Finished Jul 24 05:36:22 PM PDT 24
Peak memory 266072 kb
Host smart-8b960ec7-a179-40a0-8b95-4be167e5a0b5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1540649471 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shadow_reg_erro
rs.1540649471
Directory /workspace/5.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.3246984755
Short name T806
Test name
Test status
Simulation time 818468790 ps
CPU time 12.87 seconds
Started Jul 24 05:31:22 PM PDT 24
Finished Jul 24 05:31:35 PM PDT 24
Peak memory 249172 kb
Host smart-884d99d3-6953-4e23-ae96-a1fe50e1cb2c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3246984755 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_errors.3246984755
Directory /workspace/5.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.332656049
Short name T344
Test name
Test status
Simulation time 273884704 ps
CPU time 5.46 seconds
Started Jul 24 05:31:21 PM PDT 24
Finished Jul 24 05:31:27 PM PDT 24
Peak memory 249292 kb
Host smart-ee4cee47-33d3-460c-b31d-452a227fa263
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332656049 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 6.alert_handler_csr_mem_rw_with_rand_reset.332656049
Directory /workspace/6.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.3727893843
Short name T807
Test name
Test status
Simulation time 182488101 ps
CPU time 8.69 seconds
Started Jul 24 05:31:22 PM PDT 24
Finished Jul 24 05:31:30 PM PDT 24
Peak memory 238040 kb
Host smart-68e3ef68-6085-452b-86a1-1e21d8fcf4e2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3727893843 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_csr_rw.3727893843
Directory /workspace/6.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.2260339659
Short name T795
Test name
Test status
Simulation time 11241845 ps
CPU time 1.69 seconds
Started Jul 24 05:31:23 PM PDT 24
Finished Jul 24 05:31:25 PM PDT 24
Peak memory 238096 kb
Host smart-80c66342-5b1f-46bb-bcd2-683225f74cfa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2260339659 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_intr_test.2260339659
Directory /workspace/6.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.552846833
Short name T182
Test name
Test status
Simulation time 188975814 ps
CPU time 28.76 seconds
Started Jul 24 05:31:24 PM PDT 24
Finished Jul 24 05:31:53 PM PDT 24
Peak memory 246332 kb
Host smart-36087809-d530-471d-8364-ad43c4b52917
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=552846833 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_same_csr_outs
tanding.552846833
Directory /workspace/6.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.4268132010
Short name T804
Test name
Test status
Simulation time 780545578 ps
CPU time 100.03 seconds
Started Jul 24 05:31:36 PM PDT 24
Finished Jul 24 05:33:17 PM PDT 24
Peak memory 265968 kb
Host smart-3ae72e37-b7bb-4bbc-8982-0eb2beea765b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4268132010 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shadow_reg_erro
rs.4268132010
Directory /workspace/6.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.1672756824
Short name T138
Test name
Test status
Simulation time 9556456235 ps
CPU time 274.9 seconds
Started Jul 24 05:31:28 PM PDT 24
Finished Jul 24 05:36:03 PM PDT 24
Peak memory 265876 kb
Host smart-32fbbccf-90ee-428a-b136-fed628427b64
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672756824 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.alert_handler_shadow_reg_errors_with_csr_rw.1672756824
Directory /workspace/6.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.1300819315
Short name T799
Test name
Test status
Simulation time 347154035 ps
CPU time 23.16 seconds
Started Jul 24 05:31:25 PM PDT 24
Finished Jul 24 05:31:49 PM PDT 24
Peak memory 248948 kb
Host smart-d5abf0fd-2ec8-4042-9258-90e1a64c7484
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1300819315 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_errors.1300819315
Directory /workspace/6.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.3547102637
Short name T343
Test name
Test status
Simulation time 55478188 ps
CPU time 9.06 seconds
Started Jul 24 05:31:32 PM PDT 24
Finished Jul 24 05:31:42 PM PDT 24
Peak memory 253136 kb
Host smart-acc36fe4-9db8-4fed-913e-de6c17f8d578
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547102637 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 7.alert_handler_csr_mem_rw_with_rand_reset.3547102637
Directory /workspace/7.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.351870096
Short name T726
Test name
Test status
Simulation time 34020113 ps
CPU time 5.4 seconds
Started Jul 24 05:31:29 PM PDT 24
Finished Jul 24 05:31:35 PM PDT 24
Peak memory 240964 kb
Host smart-49372990-0b4a-4eca-b6d2-d149c8764213
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=351870096 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_csr_rw.351870096
Directory /workspace/7.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.1639370907
Short name T801
Test name
Test status
Simulation time 7026704 ps
CPU time 1.51 seconds
Started Jul 24 05:31:32 PM PDT 24
Finished Jul 24 05:31:34 PM PDT 24
Peak memory 238204 kb
Host smart-56bcec37-a746-4596-980b-81dbf6caee29
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1639370907 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_intr_test.1639370907
Directory /workspace/7.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.2649416941
Short name T798
Test name
Test status
Simulation time 3017889303 ps
CPU time 41.91 seconds
Started Jul 24 05:31:27 PM PDT 24
Finished Jul 24 05:32:09 PM PDT 24
Peak memory 249312 kb
Host smart-c9abe505-aac4-419f-b9e3-e8814e4a79ea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2649416941 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_same_csr_out
standing.2649416941
Directory /workspace/7.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.1341168516
Short name T133
Test name
Test status
Simulation time 3484116867 ps
CPU time 163.39 seconds
Started Jul 24 05:31:26 PM PDT 24
Finished Jul 24 05:34:09 PM PDT 24
Peak memory 266024 kb
Host smart-e2ba1d2e-2f00-4d9f-bd08-053d387190b3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1341168516 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shadow_reg_erro
rs.1341168516
Directory /workspace/7.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.3924393084
Short name T822
Test name
Test status
Simulation time 1251117342 ps
CPU time 25.65 seconds
Started Jul 24 05:31:26 PM PDT 24
Finished Jul 24 05:31:52 PM PDT 24
Peak memory 256136 kb
Host smart-e37b22a1-e8cb-4adf-a032-0d138ee79b13
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3924393084 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_errors.3924393084
Directory /workspace/7.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.2537088967
Short name T252
Test name
Test status
Simulation time 54723366 ps
CPU time 2.63 seconds
Started Jul 24 05:31:18 PM PDT 24
Finished Jul 24 05:31:20 PM PDT 24
Peak memory 238392 kb
Host smart-cc3cc0d9-91d4-4665-862b-e6d324a680a6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2537088967 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_intg_err.2537088967
Directory /workspace/7.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.4007650023
Short name T826
Test name
Test status
Simulation time 77788289 ps
CPU time 5.42 seconds
Started Jul 24 05:31:27 PM PDT 24
Finished Jul 24 05:31:33 PM PDT 24
Peak memory 241076 kb
Host smart-d3ca3572-6fb4-4239-9d9b-686a1c499794
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007650023 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 8.alert_handler_csr_mem_rw_with_rand_reset.4007650023
Directory /workspace/8.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.2607940863
Short name T773
Test name
Test status
Simulation time 35279657 ps
CPU time 5.86 seconds
Started Jul 24 05:31:29 PM PDT 24
Finished Jul 24 05:31:35 PM PDT 24
Peak memory 238032 kb
Host smart-b462b7ba-e8c5-4be5-a5a3-268921b2c9fa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2607940863 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_csr_rw.2607940863
Directory /workspace/8.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.1566500862
Short name T802
Test name
Test status
Simulation time 12018830 ps
CPU time 1.63 seconds
Started Jul 24 05:31:26 PM PDT 24
Finished Jul 24 05:31:28 PM PDT 24
Peak memory 238140 kb
Host smart-636e36da-d794-425b-b746-bf70122992a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1566500862 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_intr_test.1566500862
Directory /workspace/8.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.725597031
Short name T811
Test name
Test status
Simulation time 1274111877 ps
CPU time 20.66 seconds
Started Jul 24 05:31:30 PM PDT 24
Finished Jul 24 05:31:50 PM PDT 24
Peak memory 245516 kb
Host smart-385c9d61-a321-45d7-9d44-be395d4de01f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=725597031 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_same_csr_outs
tanding.725597031
Directory /workspace/8.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.2935737294
Short name T135
Test name
Test status
Simulation time 5152073596 ps
CPU time 358.25 seconds
Started Jul 24 05:31:23 PM PDT 24
Finished Jul 24 05:37:21 PM PDT 24
Peak memory 267184 kb
Host smart-eda55742-b30b-4c7d-aa59-9b2d7b45d0de
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2935737294 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shadow_reg_erro
rs.2935737294
Directory /workspace/8.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.2607521923
Short name T741
Test name
Test status
Simulation time 227265612 ps
CPU time 8.78 seconds
Started Jul 24 05:31:38 PM PDT 24
Finished Jul 24 05:31:47 PM PDT 24
Peak memory 249312 kb
Host smart-2c021466-13e9-418f-9597-46ac274b8d1d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2607521923 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_errors.2607521923
Directory /workspace/8.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.2940015186
Short name T253
Test name
Test status
Simulation time 466986030 ps
CPU time 40.84 seconds
Started Jul 24 05:31:30 PM PDT 24
Finished Jul 24 05:32:11 PM PDT 24
Peak memory 249116 kb
Host smart-6c617dfd-8fc7-4dfd-bb55-2b5e1df12fc1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2940015186 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_intg_err.2940015186
Directory /workspace/8.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.2852887433
Short name T824
Test name
Test status
Simulation time 99037116 ps
CPU time 7.06 seconds
Started Jul 24 05:31:38 PM PDT 24
Finished Jul 24 05:31:46 PM PDT 24
Peak memory 256384 kb
Host smart-14f399a1-c94d-4a10-b356-de522affe31a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852887433 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 9.alert_handler_csr_mem_rw_with_rand_reset.2852887433
Directory /workspace/9.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.1353658918
Short name T808
Test name
Test status
Simulation time 165678535 ps
CPU time 5.08 seconds
Started Jul 24 05:31:25 PM PDT 24
Finished Jul 24 05:31:30 PM PDT 24
Peak memory 237080 kb
Host smart-1a182432-8b71-44a2-bfdb-0cc613a68999
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1353658918 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_csr_rw.1353658918
Directory /workspace/9.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.1373617352
Short name T748
Test name
Test status
Simulation time 25225506 ps
CPU time 1.76 seconds
Started Jul 24 05:31:26 PM PDT 24
Finished Jul 24 05:31:28 PM PDT 24
Peak memory 237164 kb
Host smart-2a94b230-dc91-46ec-bb19-77c45bb706c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1373617352 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_intr_test.1373617352
Directory /workspace/9.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.1366921464
Short name T809
Test name
Test status
Simulation time 1042850799 ps
CPU time 34.28 seconds
Started Jul 24 05:31:37 PM PDT 24
Finished Jul 24 05:32:12 PM PDT 24
Peak memory 245280 kb
Host smart-b96a4d33-b7e9-4d99-a037-5f639c5fba90
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1366921464 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_same_csr_out
standing.1366921464
Directory /workspace/9.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.908711764
Short name T150
Test name
Test status
Simulation time 3814350415 ps
CPU time 264.58 seconds
Started Jul 24 05:31:28 PM PDT 24
Finished Jul 24 05:35:53 PM PDT 24
Peak memory 272076 kb
Host smart-158b8449-fc71-4cc7-9ce3-d4f7b5b951dc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=908711764 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shadow_reg_error
s.908711764
Directory /workspace/9.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.2741987594
Short name T141
Test name
Test status
Simulation time 4509855248 ps
CPU time 344.22 seconds
Started Jul 24 05:31:33 PM PDT 24
Finished Jul 24 05:37:18 PM PDT 24
Peak memory 266076 kb
Host smart-b3093d9a-5e02-4ca8-ae5a-e479a9ee0939
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741987594 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.alert_handler_shadow_reg_errors_with_csr_rw.2741987594
Directory /workspace/9.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.853432877
Short name T832
Test name
Test status
Simulation time 262722299 ps
CPU time 19.07 seconds
Started Jul 24 05:31:38 PM PDT 24
Finished Jul 24 05:31:57 PM PDT 24
Peak memory 251620 kb
Host smart-bee50252-5e1a-4fff-a090-bd51c7beee15
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=853432877 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_errors.853432877
Directory /workspace/9.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.582249188
Short name T794
Test name
Test status
Simulation time 89184179 ps
CPU time 2.41 seconds
Started Jul 24 05:31:35 PM PDT 24
Finished Jul 24 05:31:43 PM PDT 24
Peak memory 238472 kb
Host smart-ecad2fed-501b-422f-9623-7bc67a0739b4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=582249188 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_intg_err.582249188
Directory /workspace/9.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/0.alert_handler_entropy.784013811
Short name T60
Test name
Test status
Simulation time 11106362057 ps
CPU time 1267.89 seconds
Started Jul 24 05:33:43 PM PDT 24
Finished Jul 24 05:54:51 PM PDT 24
Peak memory 289232 kb
Host smart-8c21e1a6-546b-4b08-94c5-abfb1777e828
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784013811 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy.784013811
Directory /workspace/0.alert_handler_entropy/latest

Test location /workspace/coverage/default/0.alert_handler_entropy_stress.2928244109
Short name T668
Test name
Test status
Simulation time 157807292 ps
CPU time 10.09 seconds
Started Jul 24 05:34:09 PM PDT 24
Finished Jul 24 05:34:19 PM PDT 24
Peak memory 248548 kb
Host smart-5b0bb335-7f82-430e-a195-a5e5895fc41a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2928244109 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy_stress.2928244109
Directory /workspace/0.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/0.alert_handler_esc_alert_accum.283207314
Short name T551
Test name
Test status
Simulation time 3246262954 ps
CPU time 187.08 seconds
Started Jul 24 05:33:30 PM PDT 24
Finished Jul 24 05:36:38 PM PDT 24
Peak memory 256752 kb
Host smart-c34dabc7-8701-44f0-9c5b-986f91729ed6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28320
7314 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_alert_accum.283207314
Directory /workspace/0.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/0.alert_handler_esc_intr_timeout.2173792657
Short name T510
Test name
Test status
Simulation time 753127801 ps
CPU time 43.87 seconds
Started Jul 24 05:33:29 PM PDT 24
Finished Jul 24 05:34:13 PM PDT 24
Peak memory 248156 kb
Host smart-e707b620-b7bd-4104-ab5e-3f05120e2265
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21737
92657 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_intr_timeout.2173792657
Directory /workspace/0.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_lpg_stub_clk.2259176922
Short name T409
Test name
Test status
Simulation time 126933793132 ps
CPU time 1986.45 seconds
Started Jul 24 05:33:28 PM PDT 24
Finished Jul 24 06:06:34 PM PDT 24
Peak memory 273220 kb
Host smart-8a42854d-fe67-42c7-a122-d3eea3337f0b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259176922 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg_stub_clk.2259176922
Directory /workspace/0.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/0.alert_handler_ping_timeout.2847492381
Short name T67
Test name
Test status
Simulation time 23743985724 ps
CPU time 254.95 seconds
Started Jul 24 05:33:29 PM PDT 24
Finished Jul 24 05:37:44 PM PDT 24
Peak memory 256888 kb
Host smart-5c6dc792-1ab0-4b61-a093-c558de5b7647
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847492381 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_ping_timeout.2847492381
Directory /workspace/0.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_random_alerts.856097510
Short name T358
Test name
Test status
Simulation time 30810891 ps
CPU time 2.93 seconds
Started Jul 24 05:33:32 PM PDT 24
Finished Jul 24 05:33:35 PM PDT 24
Peak memory 248592 kb
Host smart-12a7d293-dbaa-4e14-a042-01969a523a37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85609
7510 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_alerts.856097510
Directory /workspace/0.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/0.alert_handler_random_classes.2351533251
Short name T79
Test name
Test status
Simulation time 2935055461 ps
CPU time 65.14 seconds
Started Jul 24 05:33:28 PM PDT 24
Finished Jul 24 05:34:33 PM PDT 24
Peak memory 256148 kb
Host smart-ca59b6df-fb0f-4f49-9b20-b9ee82894b0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23515
33251 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_classes.2351533251
Directory /workspace/0.alert_handler_random_classes/latest

Test location /workspace/coverage/default/0.alert_handler_sig_int_fail.1088058651
Short name T46
Test name
Test status
Simulation time 567863707 ps
CPU time 28.27 seconds
Started Jul 24 05:33:31 PM PDT 24
Finished Jul 24 05:34:00 PM PDT 24
Peak memory 247984 kb
Host smart-3b4a644e-f4f3-4504-a91c-397efd8a66ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10880
58651 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sig_int_fail.1088058651
Directory /workspace/0.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/0.alert_handler_smoke.590901182
Short name T351
Test name
Test status
Simulation time 1121220699 ps
CPU time 31.58 seconds
Started Jul 24 05:33:25 PM PDT 24
Finished Jul 24 05:33:57 PM PDT 24
Peak memory 255804 kb
Host smart-806ef21c-84fb-43b0-9181-7d7997e7e7f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59090
1182 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_smoke.590901182
Directory /workspace/0.alert_handler_smoke/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all.662146980
Short name T416
Test name
Test status
Simulation time 326171035 ps
CPU time 20.32 seconds
Started Jul 24 05:33:23 PM PDT 24
Finished Jul 24 05:33:44 PM PDT 24
Peak memory 256732 kb
Host smart-6be1bb6a-2c62-4335-bfdf-7b81655e7c05
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662146980 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_hand
ler_stress_all.662146980
Directory /workspace/0.alert_handler_stress_all/latest

Test location /workspace/coverage/default/1.alert_handler_entropy.1803813489
Short name T592
Test name
Test status
Simulation time 52392513421 ps
CPU time 3400.31 seconds
Started Jul 24 05:33:31 PM PDT 24
Finished Jul 24 06:30:12 PM PDT 24
Peak memory 288688 kb
Host smart-f2c917f8-686e-4374-9e5a-efaf3daf688c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803813489 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy.1803813489
Directory /workspace/1.alert_handler_entropy/latest

Test location /workspace/coverage/default/1.alert_handler_entropy_stress.4118064868
Short name T453
Test name
Test status
Simulation time 190561864 ps
CPU time 10.25 seconds
Started Jul 24 05:33:31 PM PDT 24
Finished Jul 24 05:33:42 PM PDT 24
Peak memory 248624 kb
Host smart-d4863428-94a8-40d3-a397-ec56e98954ec
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4118064868 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy_stress.4118064868
Directory /workspace/1.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/1.alert_handler_esc_alert_accum.2346573084
Short name T292
Test name
Test status
Simulation time 2676057729 ps
CPU time 66.58 seconds
Started Jul 24 05:33:28 PM PDT 24
Finished Jul 24 05:34:35 PM PDT 24
Peak memory 249680 kb
Host smart-12b61bec-fdd0-4e5d-93dd-a3da72fba0e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23465
73084 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_alert_accum.2346573084
Directory /workspace/1.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/1.alert_handler_esc_intr_timeout.1480518509
Short name T360
Test name
Test status
Simulation time 972203549 ps
CPU time 35.74 seconds
Started Jul 24 05:33:26 PM PDT 24
Finished Jul 24 05:34:02 PM PDT 24
Peak memory 248380 kb
Host smart-47e4ec20-8d8d-4f64-aa6b-2d60a6c67cea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14805
18509 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_intr_timeout.1480518509
Directory /workspace/1.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_lpg.2594388577
Short name T1
Test name
Test status
Simulation time 77114663542 ps
CPU time 949.24 seconds
Started Jul 24 05:33:41 PM PDT 24
Finished Jul 24 05:49:31 PM PDT 24
Peak memory 272600 kb
Host smart-3c89be35-d5e5-48c5-8e51-7e10a3bcdb28
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2594388577 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg.2594388577
Directory /workspace/1.alert_handler_lpg/latest

Test location /workspace/coverage/default/1.alert_handler_lpg_stub_clk.70130450
Short name T92
Test name
Test status
Simulation time 12371352554 ps
CPU time 1174.32 seconds
Started Jul 24 05:33:31 PM PDT 24
Finished Jul 24 05:53:06 PM PDT 24
Peak memory 273208 kb
Host smart-139c73c8-c4d4-4206-b928-6dfe0fcb2d8f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70130450 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg_stub_clk.70130450
Directory /workspace/1.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/1.alert_handler_ping_timeout.1071457451
Short name T266
Test name
Test status
Simulation time 20445722289 ps
CPU time 360.57 seconds
Started Jul 24 05:33:42 PM PDT 24
Finished Jul 24 05:39:43 PM PDT 24
Peak memory 248520 kb
Host smart-92628c60-38e7-42ed-b2fa-119be568a89b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071457451 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_ping_timeout.1071457451
Directory /workspace/1.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_random_alerts.2939012811
Short name T388
Test name
Test status
Simulation time 749067675 ps
CPU time 51.58 seconds
Started Jul 24 05:33:28 PM PDT 24
Finished Jul 24 05:34:20 PM PDT 24
Peak memory 256128 kb
Host smart-35e02987-9ee1-4e62-970b-f25d73d4fc6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29390
12811 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_alerts.2939012811
Directory /workspace/1.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/1.alert_handler_random_classes.3960704014
Short name T638
Test name
Test status
Simulation time 103432202 ps
CPU time 15.23 seconds
Started Jul 24 05:33:26 PM PDT 24
Finished Jul 24 05:33:41 PM PDT 24
Peak memory 256348 kb
Host smart-fc3ac45b-f383-4c1c-a01d-24055080b5fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39607
04014 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_classes.3960704014
Directory /workspace/1.alert_handler_random_classes/latest

Test location /workspace/coverage/default/1.alert_handler_sec_cm.3694244463
Short name T32
Test name
Test status
Simulation time 1872445529 ps
CPU time 25.02 seconds
Started Jul 24 05:33:41 PM PDT 24
Finished Jul 24 05:34:06 PM PDT 24
Peak memory 270204 kb
Host smart-dcc51b10-7ccb-43fc-9d05-2f049948acfd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3694244463 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sec_cm.3694244463
Directory /workspace/1.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/1.alert_handler_sig_int_fail.1154925193
Short name T299
Test name
Test status
Simulation time 649267795 ps
CPU time 42.54 seconds
Started Jul 24 05:33:28 PM PDT 24
Finished Jul 24 05:34:11 PM PDT 24
Peak memory 248160 kb
Host smart-21652c7c-96dd-4b80-a9f8-8c427cd86888
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11549
25193 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sig_int_fail.1154925193
Directory /workspace/1.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/1.alert_handler_smoke.2520329069
Short name T593
Test name
Test status
Simulation time 241421784 ps
CPU time 8.72 seconds
Started Jul 24 05:33:28 PM PDT 24
Finished Jul 24 05:33:37 PM PDT 24
Peak memory 254168 kb
Host smart-05f6b0f4-25d8-4516-ab23-c2789c439384
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25203
29069 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_smoke.2520329069
Directory /workspace/1.alert_handler_smoke/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all.4040438130
Short name T422
Test name
Test status
Simulation time 625740045 ps
CPU time 33.88 seconds
Started Jul 24 05:33:33 PM PDT 24
Finished Jul 24 05:34:07 PM PDT 24
Peak memory 256700 kb
Host smart-630f2944-c24d-47fb-9372-9784a65bd165
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040438130 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_han
dler_stress_all.4040438130
Directory /workspace/1.alert_handler_stress_all/latest

Test location /workspace/coverage/default/10.alert_handler_alert_accum_saturation.2742480484
Short name T195
Test name
Test status
Simulation time 21149018 ps
CPU time 2.78 seconds
Started Jul 24 05:33:59 PM PDT 24
Finished Jul 24 05:34:02 PM PDT 24
Peak memory 248920 kb
Host smart-c20de388-8235-4e2c-98dc-b70727bdc1cd
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2742480484 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_alert_accum_saturation.2742480484
Directory /workspace/10.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/10.alert_handler_entropy.2695245186
Short name T445
Test name
Test status
Simulation time 106220462881 ps
CPU time 1595.23 seconds
Started Jul 24 05:33:51 PM PDT 24
Finished Jul 24 06:00:27 PM PDT 24
Peak memory 272732 kb
Host smart-cae47f1a-be8c-4ea1-ad49-661cc3177057
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695245186 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy.2695245186
Directory /workspace/10.alert_handler_entropy/latest

Test location /workspace/coverage/default/10.alert_handler_entropy_stress.461242463
Short name T378
Test name
Test status
Simulation time 509167246 ps
CPU time 12.38 seconds
Started Jul 24 05:33:53 PM PDT 24
Finished Jul 24 05:34:06 PM PDT 24
Peak memory 248460 kb
Host smart-df8e3ddb-5679-4c89-aca6-3fcb60508afb
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=461242463 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy_stress.461242463
Directory /workspace/10.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/10.alert_handler_esc_alert_accum.2953160430
Short name T488
Test name
Test status
Simulation time 2277453344 ps
CPU time 65.91 seconds
Started Jul 24 05:33:58 PM PDT 24
Finished Jul 24 05:35:04 PM PDT 24
Peak memory 256880 kb
Host smart-31598dcd-5af1-44a0-aaa1-9b81ed619e54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29531
60430 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_alert_accum.2953160430
Directory /workspace/10.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/10.alert_handler_esc_intr_timeout.2293818543
Short name T705
Test name
Test status
Simulation time 77788214 ps
CPU time 8.5 seconds
Started Jul 24 05:33:47 PM PDT 24
Finished Jul 24 05:33:55 PM PDT 24
Peak memory 248164 kb
Host smart-5135b413-6677-49e4-8881-7a5f2d22df42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22938
18543 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_intr_timeout.2293818543
Directory /workspace/10.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_lpg_stub_clk.1297106569
Short name T375
Test name
Test status
Simulation time 114083381560 ps
CPU time 1884.09 seconds
Started Jul 24 05:33:47 PM PDT 24
Finished Jul 24 06:05:12 PM PDT 24
Peak memory 285576 kb
Host smart-a8a33abb-2884-4944-b3e3-a29b6eb6ffe5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1297106569 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg_stub_clk.1297106569
Directory /workspace/10.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/10.alert_handler_ping_timeout.1024488086
Short name T606
Test name
Test status
Simulation time 10157811508 ps
CPU time 417.83 seconds
Started Jul 24 05:33:51 PM PDT 24
Finished Jul 24 05:40:49 PM PDT 24
Peak memory 248584 kb
Host smart-4a430925-9c7a-40f7-80da-db4be7946000
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024488086 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_ping_timeout.1024488086
Directory /workspace/10.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_random_alerts.202866841
Short name T527
Test name
Test status
Simulation time 285698343 ps
CPU time 27.34 seconds
Started Jul 24 05:33:46 PM PDT 24
Finished Jul 24 05:34:14 PM PDT 24
Peak memory 248564 kb
Host smart-a7bac6d4-9cb5-4d66-9e7d-1bff922d4853
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20286
6841 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_alerts.202866841
Directory /workspace/10.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/10.alert_handler_random_classes.41456298
Short name T618
Test name
Test status
Simulation time 749573559 ps
CPU time 41.2 seconds
Started Jul 24 05:33:55 PM PDT 24
Finished Jul 24 05:34:37 PM PDT 24
Peak memory 249016 kb
Host smart-90b8497d-2cfc-421c-ae81-07c2679e4ff0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41456
298 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_classes.41456298
Directory /workspace/10.alert_handler_random_classes/latest

Test location /workspace/coverage/default/10.alert_handler_sig_int_fail.2376551000
Short name T121
Test name
Test status
Simulation time 667952048 ps
CPU time 50.82 seconds
Started Jul 24 05:33:55 PM PDT 24
Finished Jul 24 05:34:46 PM PDT 24
Peak memory 248648 kb
Host smart-c940cd56-556b-4af2-bac5-37b40d1bbbf4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23765
51000 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_sig_int_fail.2376551000
Directory /workspace/10.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/10.alert_handler_smoke.1464895209
Short name T629
Test name
Test status
Simulation time 3959407114 ps
CPU time 58.44 seconds
Started Jul 24 05:33:47 PM PDT 24
Finished Jul 24 05:34:46 PM PDT 24
Peak memory 256840 kb
Host smart-01cd5a2d-2984-4625-a9eb-ffe7cbfabb26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14648
95209 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_smoke.1464895209
Directory /workspace/10.alert_handler_smoke/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all.1070954620
Short name T642
Test name
Test status
Simulation time 1763283653 ps
CPU time 53.13 seconds
Started Jul 24 05:33:45 PM PDT 24
Finished Jul 24 05:34:38 PM PDT 24
Peak memory 255720 kb
Host smart-a8546a5b-7ee4-465d-a366-19cde5a43dcc
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070954620 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_ha
ndler_stress_all.1070954620
Directory /workspace/10.alert_handler_stress_all/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all_with_rand_reset.1273057069
Short name T96
Test name
Test status
Simulation time 26944897770 ps
CPU time 1938.87 seconds
Started Jul 24 05:33:45 PM PDT 24
Finished Jul 24 06:06:04 PM PDT 24
Peak memory 281572 kb
Host smart-9407f689-5fdf-4ef3-8570-5eacc0e32d95
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273057069 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 10.alert_handler_stress_all_with_rand_reset.1273057069
Directory /workspace/10.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.alert_handler_alert_accum_saturation.3026686617
Short name T197
Test name
Test status
Simulation time 107593952 ps
CPU time 3.29 seconds
Started Jul 24 05:33:49 PM PDT 24
Finished Jul 24 05:33:52 PM PDT 24
Peak memory 248860 kb
Host smart-c153640f-40ba-458d-bd07-929ba895f991
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3026686617 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_alert_accum_saturation.3026686617
Directory /workspace/11.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/11.alert_handler_entropy.3101792126
Short name T259
Test name
Test status
Simulation time 196628978038 ps
CPU time 3128.98 seconds
Started Jul 24 05:33:47 PM PDT 24
Finished Jul 24 06:25:56 PM PDT 24
Peak memory 289588 kb
Host smart-98bcea69-f913-4c9c-a484-a2886513a2d3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101792126 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy.3101792126
Directory /workspace/11.alert_handler_entropy/latest

Test location /workspace/coverage/default/11.alert_handler_entropy_stress.3046878669
Short name T472
Test name
Test status
Simulation time 1926347973 ps
CPU time 16.75 seconds
Started Jul 24 05:33:58 PM PDT 24
Finished Jul 24 05:34:15 PM PDT 24
Peak memory 248612 kb
Host smart-3c05f014-1cf4-4cd5-94d7-6b38ad896930
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3046878669 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy_stress.3046878669
Directory /workspace/11.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/11.alert_handler_esc_alert_accum.1743652571
Short name T350
Test name
Test status
Simulation time 19424371409 ps
CPU time 316.27 seconds
Started Jul 24 05:33:47 PM PDT 24
Finished Jul 24 05:39:04 PM PDT 24
Peak memory 256164 kb
Host smart-37f85ee7-ca2a-49c3-ba9e-89cce1a92aee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17436
52571 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_alert_accum.1743652571
Directory /workspace/11.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/11.alert_handler_esc_intr_timeout.1597469213
Short name T583
Test name
Test status
Simulation time 146083771 ps
CPU time 13.55 seconds
Started Jul 24 05:33:56 PM PDT 24
Finished Jul 24 05:34:10 PM PDT 24
Peak memory 248572 kb
Host smart-45a2b7d9-8aaf-4f67-a834-6329921adc2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15974
69213 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_intr_timeout.1597469213
Directory /workspace/11.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_lpg.265189247
Short name T595
Test name
Test status
Simulation time 22926607519 ps
CPU time 1725.33 seconds
Started Jul 24 05:33:59 PM PDT 24
Finished Jul 24 06:02:45 PM PDT 24
Peak memory 289024 kb
Host smart-9097bdde-3a1f-4948-bb77-a84a92cbbdd4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=265189247 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg.265189247
Directory /workspace/11.alert_handler_lpg/latest

Test location /workspace/coverage/default/11.alert_handler_ping_timeout.1780967069
Short name T575
Test name
Test status
Simulation time 7716626162 ps
CPU time 164.83 seconds
Started Jul 24 05:33:58 PM PDT 24
Finished Jul 24 05:36:43 PM PDT 24
Peak memory 248656 kb
Host smart-b568cfa4-1e75-451c-99ce-aaa9e9846239
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780967069 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_ping_timeout.1780967069
Directory /workspace/11.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_random_alerts.4211655022
Short name T554
Test name
Test status
Simulation time 277858380 ps
CPU time 29.12 seconds
Started Jul 24 05:33:56 PM PDT 24
Finished Jul 24 05:34:25 PM PDT 24
Peak memory 255772 kb
Host smart-4fc41616-62d0-4274-960a-9165f2ae1317
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42116
55022 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_alerts.4211655022
Directory /workspace/11.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/11.alert_handler_sig_int_fail.1675913344
Short name T247
Test name
Test status
Simulation time 2241231986 ps
CPU time 27.71 seconds
Started Jul 24 05:33:56 PM PDT 24
Finished Jul 24 05:34:23 PM PDT 24
Peak memory 248820 kb
Host smart-ebc36612-0245-486e-b007-99c449468d6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16759
13344 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_sig_int_fail.1675913344
Directory /workspace/11.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/11.alert_handler_smoke.1072292494
Short name T367
Test name
Test status
Simulation time 691482571 ps
CPU time 17.01 seconds
Started Jul 24 05:33:49 PM PDT 24
Finished Jul 24 05:34:06 PM PDT 24
Peak memory 248828 kb
Host smart-355931d6-efb0-4ed7-be90-81ce4842ff20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10722
92494 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_smoke.1072292494
Directory /workspace/11.alert_handler_smoke/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all.4061196555
Short name T531
Test name
Test status
Simulation time 63833641525 ps
CPU time 3822.03 seconds
Started Jul 24 05:33:50 PM PDT 24
Finished Jul 24 06:37:32 PM PDT 24
Peak memory 298476 kb
Host smart-5c022e37-f28a-49b1-9838-905cb62e4024
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061196555 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_ha
ndler_stress_all.4061196555
Directory /workspace/11.alert_handler_stress_all/latest

Test location /workspace/coverage/default/12.alert_handler_alert_accum_saturation.4239032198
Short name T196
Test name
Test status
Simulation time 97495658 ps
CPU time 2.96 seconds
Started Jul 24 05:34:03 PM PDT 24
Finished Jul 24 05:34:06 PM PDT 24
Peak memory 248784 kb
Host smart-5ea766f5-35c4-45e8-91c6-ad2c756bc693
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4239032198 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_alert_accum_saturation.4239032198
Directory /workspace/12.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/12.alert_handler_entropy.3217800705
Short name T712
Test name
Test status
Simulation time 245630461462 ps
CPU time 1446.8 seconds
Started Jul 24 05:33:51 PM PDT 24
Finished Jul 24 05:57:59 PM PDT 24
Peak memory 272748 kb
Host smart-74038f65-7e5e-4775-b8a7-cebb6cb7108e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217800705 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy.3217800705
Directory /workspace/12.alert_handler_entropy/latest

Test location /workspace/coverage/default/12.alert_handler_entropy_stress.4049114960
Short name T641
Test name
Test status
Simulation time 394262315 ps
CPU time 10.91 seconds
Started Jul 24 05:33:54 PM PDT 24
Finished Jul 24 05:34:05 PM PDT 24
Peak memory 248540 kb
Host smart-c6703b80-657d-4bfe-b305-7785c0b7a75f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4049114960 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy_stress.4049114960
Directory /workspace/12.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/12.alert_handler_esc_alert_accum.4044486415
Short name T307
Test name
Test status
Simulation time 6697936963 ps
CPU time 243.38 seconds
Started Jul 24 05:33:46 PM PDT 24
Finished Jul 24 05:37:50 PM PDT 24
Peak memory 256204 kb
Host smart-c46819bb-952d-4b5a-bfd9-0531dd4c1ef4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40444
86415 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_alert_accum.4044486415
Directory /workspace/12.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/12.alert_handler_esc_intr_timeout.3572996035
Short name T687
Test name
Test status
Simulation time 130849169 ps
CPU time 7.05 seconds
Started Jul 24 05:33:47 PM PDT 24
Finished Jul 24 05:33:54 PM PDT 24
Peak memory 253452 kb
Host smart-0a5fd31e-1c9e-43b7-8212-4c9d0e401735
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35729
96035 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_intr_timeout.3572996035
Directory /workspace/12.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_lpg_stub_clk.2673605378
Short name T454
Test name
Test status
Simulation time 10966379745 ps
CPU time 1251.08 seconds
Started Jul 24 05:34:02 PM PDT 24
Finished Jul 24 05:54:54 PM PDT 24
Peak memory 285304 kb
Host smart-29c13fa2-9198-443b-a421-5ca3367bbaa2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673605378 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg_stub_clk.2673605378
Directory /workspace/12.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/12.alert_handler_ping_timeout.3915365697
Short name T283
Test name
Test status
Simulation time 25753355311 ps
CPU time 299.87 seconds
Started Jul 24 05:33:55 PM PDT 24
Finished Jul 24 05:38:55 PM PDT 24
Peak memory 248616 kb
Host smart-5b264794-64ca-4bab-8ffd-9803bf32feeb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915365697 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_ping_timeout.3915365697
Directory /workspace/12.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_random_alerts.1511644896
Short name T410
Test name
Test status
Simulation time 158720887 ps
CPU time 12.59 seconds
Started Jul 24 05:33:46 PM PDT 24
Finished Jul 24 05:33:59 PM PDT 24
Peak memory 256680 kb
Host smart-6bfd11ae-be89-4604-9790-39e9a7723118
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15116
44896 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_alerts.1511644896
Directory /workspace/12.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/12.alert_handler_random_classes.410083428
Short name T105
Test name
Test status
Simulation time 591351606 ps
CPU time 23.56 seconds
Started Jul 24 05:33:58 PM PDT 24
Finished Jul 24 05:34:21 PM PDT 24
Peak memory 248032 kb
Host smart-1bc0113a-5fab-4a4b-baa8-11265a4e6508
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41008
3428 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_classes.410083428
Directory /workspace/12.alert_handler_random_classes/latest

Test location /workspace/coverage/default/12.alert_handler_sig_int_fail.1173955355
Short name T423
Test name
Test status
Simulation time 122596768 ps
CPU time 4.62 seconds
Started Jul 24 05:33:45 PM PDT 24
Finished Jul 24 05:33:50 PM PDT 24
Peak memory 248532 kb
Host smart-22023d75-a8ce-4214-90b0-788351c380c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11739
55355 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_sig_int_fail.1173955355
Directory /workspace/12.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/12.alert_handler_smoke.2132250413
Short name T468
Test name
Test status
Simulation time 331187628 ps
CPU time 24.4 seconds
Started Jul 24 05:33:58 PM PDT 24
Finished Jul 24 05:34:23 PM PDT 24
Peak memory 248480 kb
Host smart-ca7969de-f221-4793-a24a-f520bef72cfe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21322
50413 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_smoke.2132250413
Directory /workspace/12.alert_handler_smoke/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all.521155446
Short name T549
Test name
Test status
Simulation time 135051426024 ps
CPU time 2279.29 seconds
Started Jul 24 05:33:59 PM PDT 24
Finished Jul 24 06:11:59 PM PDT 24
Peak memory 289052 kb
Host smart-70d1d4c0-94a0-4000-a25a-8e6869428c47
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521155446 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_han
dler_stress_all.521155446
Directory /workspace/12.alert_handler_stress_all/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all_with_rand_reset.3488172928
Short name T190
Test name
Test status
Simulation time 83191914836 ps
CPU time 4692.98 seconds
Started Jul 24 05:33:55 PM PDT 24
Finished Jul 24 06:52:09 PM PDT 24
Peak memory 370964 kb
Host smart-7b2871fb-663d-4191-b95b-42ab583b8fc2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488172928 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.alert_handler_stress_all_with_rand_reset.3488172928
Directory /workspace/12.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.alert_handler_entropy.2331187698
Short name T683
Test name
Test status
Simulation time 9127740711 ps
CPU time 865.63 seconds
Started Jul 24 05:33:51 PM PDT 24
Finished Jul 24 05:48:17 PM PDT 24
Peak memory 266036 kb
Host smart-106d4a15-01d8-4201-af23-ab0fbf36a7ae
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331187698 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy.2331187698
Directory /workspace/13.alert_handler_entropy/latest

Test location /workspace/coverage/default/13.alert_handler_entropy_stress.3382651442
Short name T349
Test name
Test status
Simulation time 432602287 ps
CPU time 11.8 seconds
Started Jul 24 05:33:53 PM PDT 24
Finished Jul 24 05:34:04 PM PDT 24
Peak memory 248508 kb
Host smart-a2835742-6fd0-4e5f-8b04-ede3fab6a6b8
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3382651442 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy_stress.3382651442
Directory /workspace/13.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/13.alert_handler_esc_alert_accum.3335178408
Short name T72
Test name
Test status
Simulation time 10313067071 ps
CPU time 106.22 seconds
Started Jul 24 05:34:01 PM PDT 24
Finished Jul 24 05:35:47 PM PDT 24
Peak memory 256412 kb
Host smart-d4fdf2fe-b719-4350-b35b-4cd18e7319b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33351
78408 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_alert_accum.3335178408
Directory /workspace/13.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/13.alert_handler_esc_intr_timeout.884335465
Short name T369
Test name
Test status
Simulation time 3221245808 ps
CPU time 41.7 seconds
Started Jul 24 05:33:54 PM PDT 24
Finished Jul 24 05:34:36 PM PDT 24
Peak memory 256128 kb
Host smart-581b9688-79cf-460f-97c1-eb48f7e0fab3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88433
5465 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_intr_timeout.884335465
Directory /workspace/13.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_lpg.294115383
Short name T331
Test name
Test status
Simulation time 169659152718 ps
CPU time 2384.32 seconds
Started Jul 24 05:33:56 PM PDT 24
Finished Jul 24 06:13:41 PM PDT 24
Peak memory 288620 kb
Host smart-5a934848-522a-4d65-9f5e-2d6b9c87e4f7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294115383 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg.294115383
Directory /workspace/13.alert_handler_lpg/latest

Test location /workspace/coverage/default/13.alert_handler_lpg_stub_clk.3019955354
Short name T305
Test name
Test status
Simulation time 32484709169 ps
CPU time 789.66 seconds
Started Jul 24 05:34:03 PM PDT 24
Finished Jul 24 05:47:13 PM PDT 24
Peak memory 266032 kb
Host smart-e504c664-1db2-4c9e-954e-57df241e5f72
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3019955354 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg_stub_clk.3019955354
Directory /workspace/13.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/13.alert_handler_ping_timeout.2199229955
Short name T258
Test name
Test status
Simulation time 13851874081 ps
CPU time 289.31 seconds
Started Jul 24 05:33:48 PM PDT 24
Finished Jul 24 05:38:37 PM PDT 24
Peak memory 248680 kb
Host smart-6ba985f9-0ee9-430a-bd37-dc93407c882c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2199229955 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_ping_timeout.2199229955
Directory /workspace/13.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_random_alerts.3761961867
Short name T465
Test name
Test status
Simulation time 1421794313 ps
CPU time 16.45 seconds
Started Jul 24 05:33:49 PM PDT 24
Finished Jul 24 05:34:06 PM PDT 24
Peak memory 248640 kb
Host smart-fb2c0c03-3f2d-41dd-9843-e2d69b1bf5ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37619
61867 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_alerts.3761961867
Directory /workspace/13.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/13.alert_handler_smoke.1507333764
Short name T553
Test name
Test status
Simulation time 964235851 ps
CPU time 34.19 seconds
Started Jul 24 05:34:05 PM PDT 24
Finished Jul 24 05:34:39 PM PDT 24
Peak memory 255884 kb
Host smart-966eb642-654e-4a01-8e41-56842f1d6cb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15073
33764 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_smoke.1507333764
Directory /workspace/13.alert_handler_smoke/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all.495445888
Short name T248
Test name
Test status
Simulation time 92261510973 ps
CPU time 2078.62 seconds
Started Jul 24 05:34:03 PM PDT 24
Finished Jul 24 06:08:42 PM PDT 24
Peak memory 304728 kb
Host smart-79f3e471-d5e9-41c3-be89-4af76f7e42f8
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495445888 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_han
dler_stress_all.495445888
Directory /workspace/13.alert_handler_stress_all/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all_with_rand_reset.1560419632
Short name T616
Test name
Test status
Simulation time 34773583107 ps
CPU time 2420.84 seconds
Started Jul 24 05:33:49 PM PDT 24
Finished Jul 24 06:14:10 PM PDT 24
Peak memory 289356 kb
Host smart-2194db90-87fa-4a48-8370-66d34741846b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560419632 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.alert_handler_stress_all_with_rand_reset.1560419632
Directory /workspace/13.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.alert_handler_alert_accum_saturation.446984307
Short name T201
Test name
Test status
Simulation time 61684544 ps
CPU time 2.25 seconds
Started Jul 24 05:33:50 PM PDT 24
Finished Jul 24 05:33:52 PM PDT 24
Peak memory 248904 kb
Host smart-1caa416d-5237-43c5-92ed-34f8cff6a0ec
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=446984307 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_alert_accum_saturation.446984307
Directory /workspace/14.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/14.alert_handler_entropy.1539205185
Short name T541
Test name
Test status
Simulation time 43314640224 ps
CPU time 1151.55 seconds
Started Jul 24 05:33:58 PM PDT 24
Finished Jul 24 05:53:10 PM PDT 24
Peak memory 273148 kb
Host smart-cf9c4d6c-d330-47c7-b1c6-f3b564853778
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1539205185 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy.1539205185
Directory /workspace/14.alert_handler_entropy/latest

Test location /workspace/coverage/default/14.alert_handler_entropy_stress.3903703958
Short name T470
Test name
Test status
Simulation time 584018892 ps
CPU time 24.97 seconds
Started Jul 24 05:33:55 PM PDT 24
Finished Jul 24 05:34:20 PM PDT 24
Peak memory 248528 kb
Host smart-b4fd91d3-622c-4b30-b450-f20b26f0aaf2
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3903703958 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy_stress.3903703958
Directory /workspace/14.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/14.alert_handler_esc_alert_accum.326219748
Short name T656
Test name
Test status
Simulation time 751179288 ps
CPU time 31.46 seconds
Started Jul 24 05:34:02 PM PDT 24
Finished Jul 24 05:34:34 PM PDT 24
Peak memory 256352 kb
Host smart-3ba7a81d-f1de-4c7f-9a8e-f7b36cc5a758
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32621
9748 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_alert_accum.326219748
Directory /workspace/14.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/14.alert_handler_esc_intr_timeout.3568065751
Short name T6
Test name
Test status
Simulation time 1192509113 ps
CPU time 57.1 seconds
Started Jul 24 05:33:59 PM PDT 24
Finished Jul 24 05:34:56 PM PDT 24
Peak memory 255844 kb
Host smart-e6490609-8e1d-47ac-bd53-6ceef810cf7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35680
65751 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_intr_timeout.3568065751
Directory /workspace/14.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_lpg_stub_clk.2385923367
Short name T653
Test name
Test status
Simulation time 43525271226 ps
CPU time 2415.32 seconds
Started Jul 24 05:33:55 PM PDT 24
Finished Jul 24 06:14:11 PM PDT 24
Peak memory 281356 kb
Host smart-6e8e07dd-1d1a-4416-938c-96b5f0d8379c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385923367 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg_stub_clk.2385923367
Directory /workspace/14.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/14.alert_handler_random_alerts.579999892
Short name T69
Test name
Test status
Simulation time 1894505028 ps
CPU time 52.88 seconds
Started Jul 24 05:34:02 PM PDT 24
Finished Jul 24 05:34:55 PM PDT 24
Peak memory 255956 kb
Host smart-930e703b-e81d-4987-b8ea-14a7c4abfe0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57999
9892 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_alerts.579999892
Directory /workspace/14.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/14.alert_handler_random_classes.816843070
Short name T395
Test name
Test status
Simulation time 1368763760 ps
CPU time 36.69 seconds
Started Jul 24 05:33:49 PM PDT 24
Finished Jul 24 05:34:26 PM PDT 24
Peak memory 249164 kb
Host smart-6b9571ea-592c-4767-914c-666851055c7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81684
3070 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_classes.816843070
Directory /workspace/14.alert_handler_random_classes/latest

Test location /workspace/coverage/default/14.alert_handler_smoke.3328907389
Short name T664
Test name
Test status
Simulation time 3457680137 ps
CPU time 48.83 seconds
Started Jul 24 05:33:58 PM PDT 24
Finished Jul 24 05:34:47 PM PDT 24
Peak memory 256780 kb
Host smart-4dc58b05-61d3-47b6-992c-d39c2618c14b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33289
07389 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_smoke.3328907389
Directory /workspace/14.alert_handler_smoke/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all.2790316851
Short name T435
Test name
Test status
Simulation time 5713835196 ps
CPU time 319.06 seconds
Started Jul 24 05:33:49 PM PDT 24
Finished Jul 24 05:39:09 PM PDT 24
Peak memory 256868 kb
Host smart-0db88a84-a52b-4b91-80d6-d8d6dbe6e993
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790316851 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_ha
ndler_stress_all.2790316851
Directory /workspace/14.alert_handler_stress_all/latest

Test location /workspace/coverage/default/15.alert_handler_alert_accum_saturation.2492382511
Short name T19
Test name
Test status
Simulation time 226442812 ps
CPU time 3.07 seconds
Started Jul 24 05:34:07 PM PDT 24
Finished Jul 24 05:34:10 PM PDT 24
Peak memory 248940 kb
Host smart-e3b629c0-27ca-40ab-b47b-52c4352ab2f0
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2492382511 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_alert_accum_saturation.2492382511
Directory /workspace/15.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/15.alert_handler_entropy.2946250591
Short name T455
Test name
Test status
Simulation time 60055201380 ps
CPU time 1597.87 seconds
Started Jul 24 05:34:02 PM PDT 24
Finished Jul 24 06:00:40 PM PDT 24
Peak memory 282400 kb
Host smart-3cecebef-58b8-4a58-9860-66ddeb28b72d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2946250591 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy.2946250591
Directory /workspace/15.alert_handler_entropy/latest

Test location /workspace/coverage/default/15.alert_handler_entropy_stress.788248509
Short name T341
Test name
Test status
Simulation time 421514035 ps
CPU time 11.43 seconds
Started Jul 24 05:33:59 PM PDT 24
Finished Jul 24 05:34:11 PM PDT 24
Peak memory 248528 kb
Host smart-61a270b3-5a91-461a-a9d5-6c84489b3f72
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=788248509 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy_stress.788248509
Directory /workspace/15.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/15.alert_handler_esc_alert_accum.368350981
Short name T386
Test name
Test status
Simulation time 5128883635 ps
CPU time 124.07 seconds
Started Jul 24 05:33:59 PM PDT 24
Finished Jul 24 05:36:04 PM PDT 24
Peak memory 256196 kb
Host smart-540b6fc5-ed61-456d-8f22-27a248cc2e71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36835
0981 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_alert_accum.368350981
Directory /workspace/15.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/15.alert_handler_esc_intr_timeout.1473592117
Short name T458
Test name
Test status
Simulation time 922298039 ps
CPU time 23.93 seconds
Started Jul 24 05:33:56 PM PDT 24
Finished Jul 24 05:34:20 PM PDT 24
Peak memory 248604 kb
Host smart-3eed7313-0b61-4468-a3ef-3155ba199090
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14735
92117 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_intr_timeout.1473592117
Directory /workspace/15.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_lpg.3219882173
Short name T212
Test name
Test status
Simulation time 97308082670 ps
CPU time 1704.59 seconds
Started Jul 24 05:33:59 PM PDT 24
Finished Jul 24 06:02:24 PM PDT 24
Peak memory 281720 kb
Host smart-00d6b8cf-75c7-4b51-9b94-8224fb84c840
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219882173 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg.3219882173
Directory /workspace/15.alert_handler_lpg/latest

Test location /workspace/coverage/default/15.alert_handler_lpg_stub_clk.2147654126
Short name T690
Test name
Test status
Simulation time 74153349502 ps
CPU time 2100.76 seconds
Started Jul 24 05:34:00 PM PDT 24
Finished Jul 24 06:09:01 PM PDT 24
Peak memory 289552 kb
Host smart-7d12ae6b-2ff3-438a-bc20-009ad65b2d69
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147654126 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg_stub_clk.2147654126
Directory /workspace/15.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/15.alert_handler_ping_timeout.747274083
Short name T624
Test name
Test status
Simulation time 53650159354 ps
CPU time 610.56 seconds
Started Jul 24 05:34:00 PM PDT 24
Finished Jul 24 05:44:11 PM PDT 24
Peak memory 256532 kb
Host smart-f3c67d8f-f8c9-40f3-aef5-bb09cb624bab
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747274083 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_ping_timeout.747274083
Directory /workspace/15.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_random_alerts.3294220638
Short name T697
Test name
Test status
Simulation time 9068184677 ps
CPU time 46.82 seconds
Started Jul 24 05:33:55 PM PDT 24
Finished Jul 24 05:34:42 PM PDT 24
Peak memory 248636 kb
Host smart-a0c951d4-c999-4b30-b61d-10c42b0b41eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32942
20638 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_alerts.3294220638
Directory /workspace/15.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/15.alert_handler_random_classes.1212891476
Short name T296
Test name
Test status
Simulation time 1575029615 ps
CPU time 51.37 seconds
Started Jul 24 05:33:51 PM PDT 24
Finished Jul 24 05:34:43 PM PDT 24
Peak memory 248504 kb
Host smart-5646308c-82bb-425b-bbb8-4e9915d50af4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12128
91476 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_classes.1212891476
Directory /workspace/15.alert_handler_random_classes/latest

Test location /workspace/coverage/default/15.alert_handler_sig_int_fail.835196290
Short name T55
Test name
Test status
Simulation time 11007903184 ps
CPU time 48.05 seconds
Started Jul 24 05:34:03 PM PDT 24
Finished Jul 24 05:34:52 PM PDT 24
Peak memory 248648 kb
Host smart-5597b2e7-5bcf-4b84-aa88-f1972b01edcb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83519
6290 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_sig_int_fail.835196290
Directory /workspace/15.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/15.alert_handler_smoke.1058084336
Short name T657
Test name
Test status
Simulation time 296620800 ps
CPU time 17.71 seconds
Started Jul 24 05:33:56 PM PDT 24
Finished Jul 24 05:34:14 PM PDT 24
Peak memory 254468 kb
Host smart-e7d11182-2b56-4697-a3bb-154cc5f80974
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10580
84336 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_smoke.1058084336
Directory /workspace/15.alert_handler_smoke/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all.1875095870
Short name T99
Test name
Test status
Simulation time 72031022099 ps
CPU time 1652.44 seconds
Started Jul 24 05:34:00 PM PDT 24
Finished Jul 24 06:01:33 PM PDT 24
Peak memory 306036 kb
Host smart-21c59d94-8234-47c0-ade9-f6eb426c89f0
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875095870 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_ha
ndler_stress_all.1875095870
Directory /workspace/15.alert_handler_stress_all/latest

Test location /workspace/coverage/default/16.alert_handler_entropy.1516943583
Short name T578
Test name
Test status
Simulation time 105889256016 ps
CPU time 823.93 seconds
Started Jul 24 05:34:04 PM PDT 24
Finished Jul 24 05:47:48 PM PDT 24
Peak memory 272588 kb
Host smart-1da2db34-6fb4-4406-9e07-bd4036fc958a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1516943583 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy.1516943583
Directory /workspace/16.alert_handler_entropy/latest

Test location /workspace/coverage/default/16.alert_handler_entropy_stress.1442607910
Short name T477
Test name
Test status
Simulation time 2941725017 ps
CPU time 62.9 seconds
Started Jul 24 05:33:56 PM PDT 24
Finished Jul 24 05:34:59 PM PDT 24
Peak memory 248620 kb
Host smart-252d4b17-148b-4385-9065-80fbbbeb691f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1442607910 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy_stress.1442607910
Directory /workspace/16.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/16.alert_handler_esc_alert_accum.983607042
Short name T663
Test name
Test status
Simulation time 10110693781 ps
CPU time 87.76 seconds
Started Jul 24 05:33:56 PM PDT 24
Finished Jul 24 05:35:24 PM PDT 24
Peak memory 256840 kb
Host smart-32c36410-ec24-41b1-b438-5cc8010229d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98360
7042 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_alert_accum.983607042
Directory /workspace/16.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/16.alert_handler_esc_intr_timeout.1976418257
Short name T562
Test name
Test status
Simulation time 3138721112 ps
CPU time 53.08 seconds
Started Jul 24 05:34:00 PM PDT 24
Finished Jul 24 05:34:54 PM PDT 24
Peak memory 248668 kb
Host smart-afda3fce-323a-4dd8-ae30-bf53b191537b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19764
18257 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_intr_timeout.1976418257
Directory /workspace/16.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_lpg.3052575246
Short name T590
Test name
Test status
Simulation time 307800406921 ps
CPU time 2666.44 seconds
Started Jul 24 05:34:04 PM PDT 24
Finished Jul 24 06:18:31 PM PDT 24
Peak memory 288564 kb
Host smart-7f22bfb6-d50c-4cc0-aaa7-24f6707cc2cb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052575246 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg.3052575246
Directory /workspace/16.alert_handler_lpg/latest

Test location /workspace/coverage/default/16.alert_handler_lpg_stub_clk.1681986285
Short name T589
Test name
Test status
Simulation time 217062488460 ps
CPU time 3417.04 seconds
Started Jul 24 05:33:58 PM PDT 24
Finished Jul 24 06:30:56 PM PDT 24
Peak memory 289504 kb
Host smart-cf761fc8-127b-4438-9172-27ed6fc49dee
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1681986285 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg_stub_clk.1681986285
Directory /workspace/16.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/16.alert_handler_ping_timeout.2633711147
Short name T707
Test name
Test status
Simulation time 27002652514 ps
CPU time 387.34 seconds
Started Jul 24 05:33:58 PM PDT 24
Finished Jul 24 05:40:26 PM PDT 24
Peak memory 248620 kb
Host smart-afcf144f-7ac0-4df2-86f1-149c8bd2d516
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633711147 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_ping_timeout.2633711147
Directory /workspace/16.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_random_alerts.294558783
Short name T466
Test name
Test status
Simulation time 579393415 ps
CPU time 30.21 seconds
Started Jul 24 05:34:01 PM PDT 24
Finished Jul 24 05:34:31 PM PDT 24
Peak memory 256012 kb
Host smart-91e4e472-b282-4620-b36e-9385d3144361
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29455
8783 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_alerts.294558783
Directory /workspace/16.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/16.alert_handler_random_classes.2067326926
Short name T659
Test name
Test status
Simulation time 286009754 ps
CPU time 21.03 seconds
Started Jul 24 05:33:59 PM PDT 24
Finished Jul 24 05:34:20 PM PDT 24
Peak memory 248292 kb
Host smart-2ccdb7b1-ec32-4f3f-b9ee-5de071d29b93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20673
26926 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_classes.2067326926
Directory /workspace/16.alert_handler_random_classes/latest

Test location /workspace/coverage/default/16.alert_handler_sig_int_fail.3418860657
Short name T698
Test name
Test status
Simulation time 178115012 ps
CPU time 8.31 seconds
Started Jul 24 05:34:01 PM PDT 24
Finished Jul 24 05:34:10 PM PDT 24
Peak memory 248108 kb
Host smart-9c897114-b92c-4fc1-91d9-d96097316889
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34188
60657 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_sig_int_fail.3418860657
Directory /workspace/16.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/16.alert_handler_smoke.1574718972
Short name T692
Test name
Test status
Simulation time 1867846357 ps
CPU time 13.34 seconds
Started Jul 24 05:34:05 PM PDT 24
Finished Jul 24 05:34:18 PM PDT 24
Peak memory 254496 kb
Host smart-b1bb001b-13eb-4804-9f1f-eb469472731e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15747
18972 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_smoke.1574718972
Directory /workspace/16.alert_handler_smoke/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all_with_rand_reset.3782897059
Short name T250
Test name
Test status
Simulation time 55090758535 ps
CPU time 5953.64 seconds
Started Jul 24 05:34:03 PM PDT 24
Finished Jul 24 07:13:17 PM PDT 24
Peak memory 368104 kb
Host smart-e220737a-2ece-4466-9d8e-0d30990c6b95
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782897059 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 16.alert_handler_stress_all_with_rand_reset.3782897059
Directory /workspace/16.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.alert_handler_alert_accum_saturation.73293891
Short name T2
Test name
Test status
Simulation time 154393894 ps
CPU time 3.61 seconds
Started Jul 24 05:33:59 PM PDT 24
Finished Jul 24 05:34:03 PM PDT 24
Peak memory 248884 kb
Host smart-dab57a6a-4d4a-4960-abe0-71a6fc89336e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=73293891 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_alert_accum_saturation.73293891
Directory /workspace/17.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/17.alert_handler_entropy.1645792118
Short name T413
Test name
Test status
Simulation time 56595843091 ps
CPU time 3398.03 seconds
Started Jul 24 05:34:04 PM PDT 24
Finished Jul 24 06:30:42 PM PDT 24
Peak memory 289348 kb
Host smart-bd538596-a18a-4792-8f59-235bc6507e69
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645792118 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy.1645792118
Directory /workspace/17.alert_handler_entropy/latest

Test location /workspace/coverage/default/17.alert_handler_entropy_stress.1280325512
Short name T497
Test name
Test status
Simulation time 431468785 ps
CPU time 19.95 seconds
Started Jul 24 05:34:04 PM PDT 24
Finished Jul 24 05:34:25 PM PDT 24
Peak memory 248316 kb
Host smart-2421cfa8-a97d-4c1a-9b08-88736d0ccac1
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1280325512 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy_stress.1280325512
Directory /workspace/17.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/17.alert_handler_esc_alert_accum.1376599835
Short name T434
Test name
Test status
Simulation time 1287842920 ps
CPU time 101.7 seconds
Started Jul 24 05:34:02 PM PDT 24
Finished Jul 24 05:35:44 PM PDT 24
Peak memory 256172 kb
Host smart-32f7d7d3-c681-463a-8a84-84587a4f3b89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13765
99835 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_alert_accum.1376599835
Directory /workspace/17.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/17.alert_handler_esc_intr_timeout.1353128451
Short name T237
Test name
Test status
Simulation time 1717971423 ps
CPU time 56.01 seconds
Started Jul 24 05:33:59 PM PDT 24
Finished Jul 24 05:34:55 PM PDT 24
Peak memory 249256 kb
Host smart-f795fa2d-ccbd-4252-b5c9-f8b21b6beaa5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13531
28451 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_intr_timeout.1353128451
Directory /workspace/17.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_lpg.4234873780
Short name T471
Test name
Test status
Simulation time 51382632248 ps
CPU time 677.38 seconds
Started Jul 24 05:34:10 PM PDT 24
Finished Jul 24 05:45:28 PM PDT 24
Peak memory 265068 kb
Host smart-91ea4399-dd92-4aad-98bc-492f3d370fcb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234873780 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg.4234873780
Directory /workspace/17.alert_handler_lpg/latest

Test location /workspace/coverage/default/17.alert_handler_lpg_stub_clk.2245692242
Short name T433
Test name
Test status
Simulation time 25457845409 ps
CPU time 1571.6 seconds
Started Jul 24 05:33:58 PM PDT 24
Finished Jul 24 06:00:11 PM PDT 24
Peak memory 289244 kb
Host smart-0d70564f-42d0-45fb-a4ef-e4a6a1c94b6e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2245692242 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg_stub_clk.2245692242
Directory /workspace/17.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/17.alert_handler_ping_timeout.3845321222
Short name T260
Test name
Test status
Simulation time 12874369966 ps
CPU time 515.19 seconds
Started Jul 24 05:34:03 PM PDT 24
Finished Jul 24 05:42:38 PM PDT 24
Peak memory 256840 kb
Host smart-4617d450-ecea-4ef1-a704-636bf09dd7e3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845321222 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_ping_timeout.3845321222
Directory /workspace/17.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_random_alerts.3268590938
Short name T211
Test name
Test status
Simulation time 3040684504 ps
CPU time 41.11 seconds
Started Jul 24 05:34:01 PM PDT 24
Finished Jul 24 05:34:43 PM PDT 24
Peak memory 256212 kb
Host smart-0a5dbe90-e3aa-4cc3-89f4-cb47ad738661
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32685
90938 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_alerts.3268590938
Directory /workspace/17.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/17.alert_handler_random_classes.369260305
Short name T441
Test name
Test status
Simulation time 41429842 ps
CPU time 3.54 seconds
Started Jul 24 05:34:01 PM PDT 24
Finished Jul 24 05:34:05 PM PDT 24
Peak memory 239740 kb
Host smart-b95b8036-6601-4c24-ab5d-740e673d64d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36926
0305 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_classes.369260305
Directory /workspace/17.alert_handler_random_classes/latest

Test location /workspace/coverage/default/17.alert_handler_sig_int_fail.741932026
Short name T354
Test name
Test status
Simulation time 1432262393 ps
CPU time 46.08 seconds
Started Jul 24 05:33:58 PM PDT 24
Finished Jul 24 05:34:45 PM PDT 24
Peak memory 248776 kb
Host smart-db102074-3674-4a76-a7d9-30cff00bdfca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74193
2026 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_sig_int_fail.741932026
Directory /workspace/17.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/17.alert_handler_smoke.4214282298
Short name T427
Test name
Test status
Simulation time 125568054 ps
CPU time 12.29 seconds
Started Jul 24 05:34:02 PM PDT 24
Finished Jul 24 05:34:14 PM PDT 24
Peak memory 256508 kb
Host smart-7eb82d00-2384-4a09-af07-0863e6877b9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42142
82298 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_smoke.4214282298
Directory /workspace/17.alert_handler_smoke/latest

Test location /workspace/coverage/default/18.alert_handler_alert_accum_saturation.2088377099
Short name T208
Test name
Test status
Simulation time 103015016 ps
CPU time 3.08 seconds
Started Jul 24 05:34:02 PM PDT 24
Finished Jul 24 05:34:06 PM PDT 24
Peak memory 248836 kb
Host smart-49605875-e774-473a-b174-3cbcfdb66f83
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2088377099 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_alert_accum_saturation.2088377099
Directory /workspace/18.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/18.alert_handler_entropy.2861527618
Short name T602
Test name
Test status
Simulation time 31771498075 ps
CPU time 2066.52 seconds
Started Jul 24 05:34:03 PM PDT 24
Finished Jul 24 06:08:30 PM PDT 24
Peak memory 273236 kb
Host smart-544c7523-d400-408a-8f57-f5b02db19cf8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861527618 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy.2861527618
Directory /workspace/18.alert_handler_entropy/latest

Test location /workspace/coverage/default/18.alert_handler_esc_alert_accum.2539119210
Short name T650
Test name
Test status
Simulation time 4632086046 ps
CPU time 116.6 seconds
Started Jul 24 05:34:01 PM PDT 24
Finished Jul 24 05:35:57 PM PDT 24
Peak memory 256812 kb
Host smart-d0384b24-e083-421a-8c80-de95e5f53d03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25391
19210 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_alert_accum.2539119210
Directory /workspace/18.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/18.alert_handler_esc_intr_timeout.774538268
Short name T364
Test name
Test status
Simulation time 6724480542 ps
CPU time 23.74 seconds
Started Jul 24 05:34:05 PM PDT 24
Finished Jul 24 05:34:29 PM PDT 24
Peak memory 255900 kb
Host smart-92491e37-a53f-4855-a749-b21800526ca8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77453
8268 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_intr_timeout.774538268
Directory /workspace/18.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_lpg.876625094
Short name T487
Test name
Test status
Simulation time 15062015728 ps
CPU time 761.63 seconds
Started Jul 24 05:34:03 PM PDT 24
Finished Jul 24 05:46:45 PM PDT 24
Peak memory 272956 kb
Host smart-3bc2e748-eda8-4a0c-8c02-76f78ea02c73
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876625094 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg.876625094
Directory /workspace/18.alert_handler_lpg/latest

Test location /workspace/coverage/default/18.alert_handler_lpg_stub_clk.1983701116
Short name T596
Test name
Test status
Simulation time 43644569768 ps
CPU time 3157.93 seconds
Started Jul 24 05:34:03 PM PDT 24
Finished Jul 24 06:26:42 PM PDT 24
Peak memory 289572 kb
Host smart-00d90160-4d1d-440a-9d0b-aa430e034cd6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983701116 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg_stub_clk.1983701116
Directory /workspace/18.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/18.alert_handler_random_alerts.757845155
Short name T639
Test name
Test status
Simulation time 1137320671 ps
CPU time 62.8 seconds
Started Jul 24 05:34:01 PM PDT 24
Finished Jul 24 05:35:04 PM PDT 24
Peak memory 247572 kb
Host smart-f37ebe80-d409-4160-96e5-74e44320da40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75784
5155 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_alerts.757845155
Directory /workspace/18.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/18.alert_handler_random_classes.3308825193
Short name T528
Test name
Test status
Simulation time 388045856 ps
CPU time 12.09 seconds
Started Jul 24 05:34:00 PM PDT 24
Finished Jul 24 05:34:12 PM PDT 24
Peak memory 248508 kb
Host smart-a0deb675-362d-4408-8465-cb1052e36207
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33088
25193 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_classes.3308825193
Directory /workspace/18.alert_handler_random_classes/latest

Test location /workspace/coverage/default/18.alert_handler_sig_int_fail.1360785722
Short name T309
Test name
Test status
Simulation time 245798539 ps
CPU time 24.14 seconds
Started Jul 24 05:34:01 PM PDT 24
Finished Jul 24 05:34:26 PM PDT 24
Peak memory 255140 kb
Host smart-634b0f6f-dcf1-4768-b5e0-8914e25ad1c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13607
85722 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_sig_int_fail.1360785722
Directory /workspace/18.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/18.alert_handler_smoke.3601562411
Short name T523
Test name
Test status
Simulation time 1496674364 ps
CPU time 32.55 seconds
Started Jul 24 05:34:03 PM PDT 24
Finished Jul 24 05:34:36 PM PDT 24
Peak memory 248844 kb
Host smart-97440351-43a5-4109-85cc-27428bcd795a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36015
62411 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_smoke.3601562411
Directory /workspace/18.alert_handler_smoke/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all.1688039179
Short name T518
Test name
Test status
Simulation time 61416781577 ps
CPU time 2297.95 seconds
Started Jul 24 05:34:04 PM PDT 24
Finished Jul 24 06:12:23 PM PDT 24
Peak memory 288848 kb
Host smart-fe0625dd-f331-420c-9138-7df2ef1593ea
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688039179 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_ha
ndler_stress_all.1688039179
Directory /workspace/18.alert_handler_stress_all/latest

Test location /workspace/coverage/default/19.alert_handler_alert_accum_saturation.2432731906
Short name T43
Test name
Test status
Simulation time 14513919 ps
CPU time 2.37 seconds
Started Jul 24 05:34:00 PM PDT 24
Finished Jul 24 05:34:03 PM PDT 24
Peak memory 248880 kb
Host smart-d0a2a329-0973-4953-baf3-33091443a2ac
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2432731906 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_alert_accum_saturation.2432731906
Directory /workspace/19.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/19.alert_handler_entropy.3229298777
Short name T393
Test name
Test status
Simulation time 171650039856 ps
CPU time 2536.8 seconds
Started Jul 24 05:33:59 PM PDT 24
Finished Jul 24 06:16:17 PM PDT 24
Peak memory 281420 kb
Host smart-873549ab-09e6-45e0-8bb2-91be20cd52a4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229298777 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy.3229298777
Directory /workspace/19.alert_handler_entropy/latest

Test location /workspace/coverage/default/19.alert_handler_entropy_stress.3446275985
Short name T220
Test name
Test status
Simulation time 1951932099 ps
CPU time 15.29 seconds
Started Jul 24 05:34:04 PM PDT 24
Finished Jul 24 05:34:20 PM PDT 24
Peak memory 248316 kb
Host smart-c42c1de2-32bc-4058-9eb9-7938e05dd6a6
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3446275985 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy_stress.3446275985
Directory /workspace/19.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/19.alert_handler_esc_alert_accum.114673564
Short name T609
Test name
Test status
Simulation time 2208190855 ps
CPU time 120.97 seconds
Started Jul 24 05:34:01 PM PDT 24
Finished Jul 24 05:36:02 PM PDT 24
Peak memory 256388 kb
Host smart-79d0e30e-24cc-4b2d-a68c-cbdf97497c93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11467
3564 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_alert_accum.114673564
Directory /workspace/19.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/19.alert_handler_esc_intr_timeout.1705403890
Short name T374
Test name
Test status
Simulation time 947840102 ps
CPU time 54.88 seconds
Started Jul 24 05:34:02 PM PDT 24
Finished Jul 24 05:34:58 PM PDT 24
Peak memory 248412 kb
Host smart-b2ebd752-87a4-4ffa-8434-b26607ce1da4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17054
03890 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_intr_timeout.1705403890
Directory /workspace/19.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_lpg_stub_clk.1227514279
Short name T98
Test name
Test status
Simulation time 13906649346 ps
CPU time 1072.81 seconds
Started Jul 24 05:34:00 PM PDT 24
Finished Jul 24 05:51:53 PM PDT 24
Peak memory 272648 kb
Host smart-34ce03dd-0d55-4be2-880e-1d74afb1aff1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1227514279 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg_stub_clk.1227514279
Directory /workspace/19.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/19.alert_handler_ping_timeout.3176214417
Short name T285
Test name
Test status
Simulation time 38797148406 ps
CPU time 400.22 seconds
Started Jul 24 05:34:01 PM PDT 24
Finished Jul 24 05:40:42 PM PDT 24
Peak memory 247556 kb
Host smart-c7f7d404-d2a5-4983-9603-9ff7d783378a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176214417 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_ping_timeout.3176214417
Directory /workspace/19.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_random_alerts.2770741587
Short name T694
Test name
Test status
Simulation time 993039089 ps
CPU time 28.24 seconds
Started Jul 24 05:34:09 PM PDT 24
Finished Jul 24 05:34:37 PM PDT 24
Peak memory 255956 kb
Host smart-dcf80ce3-8faf-4c4b-baa7-95974dbcc0ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27707
41587 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_alerts.2770741587
Directory /workspace/19.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/19.alert_handler_random_classes.2396028893
Short name T215
Test name
Test status
Simulation time 1803677142 ps
CPU time 24.29 seconds
Started Jul 24 05:34:08 PM PDT 24
Finished Jul 24 05:34:32 PM PDT 24
Peak memory 248828 kb
Host smart-420666ab-21cf-4040-b97b-3f29b6738094
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23960
28893 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_classes.2396028893
Directory /workspace/19.alert_handler_random_classes/latest

Test location /workspace/coverage/default/19.alert_handler_sig_int_fail.2548487758
Short name T245
Test name
Test status
Simulation time 3786068655 ps
CPU time 59.97 seconds
Started Jul 24 05:34:04 PM PDT 24
Finished Jul 24 05:35:05 PM PDT 24
Peak memory 248596 kb
Host smart-f11f21a4-1648-4262-b8c2-152242532e31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25484
87758 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_sig_int_fail.2548487758
Directory /workspace/19.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/19.alert_handler_smoke.325901636
Short name T588
Test name
Test status
Simulation time 792967941 ps
CPU time 23.74 seconds
Started Jul 24 05:34:05 PM PDT 24
Finished Jul 24 05:34:29 PM PDT 24
Peak memory 256784 kb
Host smart-c99e0403-515c-4b36-a759-58574c6606d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32590
1636 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_smoke.325901636
Directory /workspace/19.alert_handler_smoke/latest

Test location /workspace/coverage/default/2.alert_handler_alert_accum_saturation.1742779633
Short name T205
Test name
Test status
Simulation time 19787194 ps
CPU time 3 seconds
Started Jul 24 05:33:31 PM PDT 24
Finished Jul 24 05:33:35 PM PDT 24
Peak memory 248924 kb
Host smart-e03e84fb-055f-428a-96c1-cacba2f996c8
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1742779633 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_alert_accum_saturation.1742779633
Directory /workspace/2.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/2.alert_handler_entropy.764979059
Short name T5
Test name
Test status
Simulation time 13336809891 ps
CPU time 1353.98 seconds
Started Jul 24 05:33:37 PM PDT 24
Finished Jul 24 05:56:12 PM PDT 24
Peak memory 285256 kb
Host smart-3d81ecbb-253f-4d15-a96f-b9883aeec71c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764979059 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy.764979059
Directory /workspace/2.alert_handler_entropy/latest

Test location /workspace/coverage/default/2.alert_handler_entropy_stress.2723653510
Short name T221
Test name
Test status
Simulation time 497704578 ps
CPU time 8.21 seconds
Started Jul 24 05:33:30 PM PDT 24
Finished Jul 24 05:33:38 PM PDT 24
Peak memory 248524 kb
Host smart-30706980-173b-4afa-8c58-71d36af50d86
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2723653510 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy_stress.2723653510
Directory /workspace/2.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/2.alert_handler_esc_alert_accum.555197693
Short name T362
Test name
Test status
Simulation time 10579922767 ps
CPU time 174.71 seconds
Started Jul 24 05:33:32 PM PDT 24
Finished Jul 24 05:36:27 PM PDT 24
Peak memory 249716 kb
Host smart-83637fd8-73de-410a-8036-3424851decbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55519
7693 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_alert_accum.555197693
Directory /workspace/2.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/2.alert_handler_esc_intr_timeout.1112475403
Short name T217
Test name
Test status
Simulation time 2906044651 ps
CPU time 39.32 seconds
Started Jul 24 05:33:35 PM PDT 24
Finished Jul 24 05:34:15 PM PDT 24
Peak memory 256884 kb
Host smart-7d984cc1-24bf-475f-bf5f-abc4fd76af56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11124
75403 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_intr_timeout.1112475403
Directory /workspace/2.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_lpg.3659371519
Short name T674
Test name
Test status
Simulation time 198925740542 ps
CPU time 2706.16 seconds
Started Jul 24 05:33:38 PM PDT 24
Finished Jul 24 06:18:44 PM PDT 24
Peak memory 288552 kb
Host smart-52f78629-3cc3-47f1-8f52-05fcbff64b8f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659371519 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg.3659371519
Directory /workspace/2.alert_handler_lpg/latest

Test location /workspace/coverage/default/2.alert_handler_lpg_stub_clk.1156053948
Short name T524
Test name
Test status
Simulation time 28922214887 ps
CPU time 1693.87 seconds
Started Jul 24 05:33:31 PM PDT 24
Finished Jul 24 06:01:46 PM PDT 24
Peak memory 281408 kb
Host smart-34d33766-f4a7-4a1e-8167-f55610e26671
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1156053948 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg_stub_clk.1156053948
Directory /workspace/2.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/2.alert_handler_ping_timeout.2873773818
Short name T539
Test name
Test status
Simulation time 22963690002 ps
CPU time 382.44 seconds
Started Jul 24 05:33:36 PM PDT 24
Finished Jul 24 05:39:59 PM PDT 24
Peak memory 248588 kb
Host smart-7b513ac1-1e8b-4bce-9583-cbcd873d7138
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2873773818 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_ping_timeout.2873773818
Directory /workspace/2.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_random_alerts.567279398
Short name T654
Test name
Test status
Simulation time 2535247590 ps
CPU time 33.5 seconds
Started Jul 24 05:33:31 PM PDT 24
Finished Jul 24 05:34:04 PM PDT 24
Peak memory 248472 kb
Host smart-6456368a-2532-425f-a81b-98fd95554108
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56727
9398 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_alerts.567279398
Directory /workspace/2.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/2.alert_handler_random_classes.3923688274
Short name T492
Test name
Test status
Simulation time 8670495866 ps
CPU time 62.67 seconds
Started Jul 24 05:33:30 PM PDT 24
Finished Jul 24 05:34:33 PM PDT 24
Peak memory 256164 kb
Host smart-ebe41ae8-764e-4ca7-b2ee-7e6c5444cd97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39236
88274 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_classes.3923688274
Directory /workspace/2.alert_handler_random_classes/latest

Test location /workspace/coverage/default/2.alert_handler_sig_int_fail.2444666065
Short name T238
Test name
Test status
Simulation time 125088675 ps
CPU time 10.81 seconds
Started Jul 24 05:33:40 PM PDT 24
Finished Jul 24 05:33:51 PM PDT 24
Peak memory 247992 kb
Host smart-baf0a0ab-e78f-45e2-8997-bdb4d4eab498
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24446
66065 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sig_int_fail.2444666065
Directory /workspace/2.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/2.alert_handler_smoke.2036625451
Short name T515
Test name
Test status
Simulation time 824633171 ps
CPU time 32.75 seconds
Started Jul 24 05:33:31 PM PDT 24
Finished Jul 24 05:34:04 PM PDT 24
Peak memory 256220 kb
Host smart-8feb6736-9ab5-4d16-a83f-33f8477f587a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20366
25451 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_smoke.2036625451
Directory /workspace/2.alert_handler_smoke/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all.231500436
Short name T493
Test name
Test status
Simulation time 11490000371 ps
CPU time 236.71 seconds
Started Jul 24 05:33:42 PM PDT 24
Finished Jul 24 05:37:40 PM PDT 24
Peak memory 255848 kb
Host smart-5af4e61f-0d61-4008-aa61-b5cbce86fe3e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231500436 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_hand
ler_stress_all.231500436
Directory /workspace/2.alert_handler_stress_all/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all_with_rand_reset.1774900309
Short name T87
Test name
Test status
Simulation time 45287017134 ps
CPU time 2191.16 seconds
Started Jul 24 05:33:30 PM PDT 24
Finished Jul 24 06:10:01 PM PDT 24
Peak memory 314260 kb
Host smart-bae1dcc6-63d0-464c-aecf-5ac285488eb5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774900309 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.alert_handler_stress_all_with_rand_reset.1774900309
Directory /workspace/2.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.alert_handler_entropy.75261333
Short name T263
Test name
Test status
Simulation time 41317895241 ps
CPU time 2365.98 seconds
Started Jul 24 05:34:02 PM PDT 24
Finished Jul 24 06:13:29 PM PDT 24
Peak memory 281376 kb
Host smart-3b656e87-2325-4155-920e-d71887248677
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75261333 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_entropy.75261333
Directory /workspace/20.alert_handler_entropy/latest

Test location /workspace/coverage/default/20.alert_handler_esc_alert_accum.238123244
Short name T617
Test name
Test status
Simulation time 3104562067 ps
CPU time 41.5 seconds
Started Jul 24 05:34:12 PM PDT 24
Finished Jul 24 05:34:54 PM PDT 24
Peak memory 256008 kb
Host smart-23489220-1083-4d80-bbbd-8cf94d670755
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23812
3244 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_alert_accum.238123244
Directory /workspace/20.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/20.alert_handler_esc_intr_timeout.3231401729
Short name T526
Test name
Test status
Simulation time 549515940 ps
CPU time 10.79 seconds
Started Jul 24 05:34:04 PM PDT 24
Finished Jul 24 05:34:15 PM PDT 24
Peak memory 249180 kb
Host smart-5d5e331a-3305-43db-8788-2613be23819b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32314
01729 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_intr_timeout.3231401729
Directory /workspace/20.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_lpg.1389259005
Short name T255
Test name
Test status
Simulation time 134664381097 ps
CPU time 1950.85 seconds
Started Jul 24 05:34:07 PM PDT 24
Finished Jul 24 06:06:38 PM PDT 24
Peak memory 286276 kb
Host smart-ac0d32bc-76a9-47d5-9651-81ce2c2462ba
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389259005 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg.1389259005
Directory /workspace/20.alert_handler_lpg/latest

Test location /workspace/coverage/default/20.alert_handler_lpg_stub_clk.2734933705
Short name T476
Test name
Test status
Simulation time 17620296008 ps
CPU time 1441.48 seconds
Started Jul 24 05:34:04 PM PDT 24
Finished Jul 24 05:58:06 PM PDT 24
Peak memory 281384 kb
Host smart-c62d9602-d851-4e79-ac5d-419117bbd782
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734933705 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg_stub_clk.2734933705
Directory /workspace/20.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/20.alert_handler_ping_timeout.3341070588
Short name T628
Test name
Test status
Simulation time 23125519694 ps
CPU time 249.72 seconds
Started Jul 24 05:34:06 PM PDT 24
Finished Jul 24 05:38:16 PM PDT 24
Peak memory 247512 kb
Host smart-0e3e801d-f485-407d-9bda-0d5dd13f5e18
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341070588 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_ping_timeout.3341070588
Directory /workspace/20.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_random_alerts.486394958
Short name T569
Test name
Test status
Simulation time 339687486 ps
CPU time 21.27 seconds
Started Jul 24 05:34:08 PM PDT 24
Finished Jul 24 05:34:29 PM PDT 24
Peak memory 248636 kb
Host smart-fe66bba5-f080-469f-ba52-d25a77bcf615
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48639
4958 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_alerts.486394958
Directory /workspace/20.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/20.alert_handler_random_classes.193703911
Short name T576
Test name
Test status
Simulation time 71040332 ps
CPU time 5.67 seconds
Started Jul 24 05:34:06 PM PDT 24
Finished Jul 24 05:34:12 PM PDT 24
Peak memory 240368 kb
Host smart-9b9140fd-19bc-4545-a7d7-37a1776d4e68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19370
3911 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_classes.193703911
Directory /workspace/20.alert_handler_random_classes/latest

Test location /workspace/coverage/default/20.alert_handler_sig_int_fail.3207206401
Short name T382
Test name
Test status
Simulation time 87561639 ps
CPU time 9 seconds
Started Jul 24 05:34:11 PM PDT 24
Finished Jul 24 05:34:20 PM PDT 24
Peak memory 249136 kb
Host smart-3b40dc6f-8d9d-406f-a5ee-2120dda28b46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32072
06401 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_sig_int_fail.3207206401
Directory /workspace/20.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/20.alert_handler_smoke.2743465171
Short name T556
Test name
Test status
Simulation time 442643190 ps
CPU time 26.85 seconds
Started Jul 24 05:34:12 PM PDT 24
Finished Jul 24 05:34:39 PM PDT 24
Peak memory 255592 kb
Host smart-c4df8b87-3733-4dcd-b119-e68d68a37698
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27434
65171 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_smoke.2743465171
Directory /workspace/20.alert_handler_smoke/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all.1109108093
Short name T584
Test name
Test status
Simulation time 52809519359 ps
CPU time 1377.97 seconds
Started Jul 24 05:34:05 PM PDT 24
Finished Jul 24 05:57:04 PM PDT 24
Peak memory 289152 kb
Host smart-d3bed4af-6b22-4dd9-8cbd-d711b2474799
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109108093 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_ha
ndler_stress_all.1109108093
Directory /workspace/20.alert_handler_stress_all/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all_with_rand_reset.2305899333
Short name T61
Test name
Test status
Simulation time 60777067624 ps
CPU time 6671.59 seconds
Started Jul 24 05:34:05 PM PDT 24
Finished Jul 24 07:25:18 PM PDT 24
Peak memory 353912 kb
Host smart-4030858e-a1ce-4a0f-9bd5-d0250165a733
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305899333 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 20.alert_handler_stress_all_with_rand_reset.2305899333
Directory /workspace/20.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.alert_handler_entropy.1247148831
Short name T446
Test name
Test status
Simulation time 199318087405 ps
CPU time 3008.71 seconds
Started Jul 24 05:34:01 PM PDT 24
Finished Jul 24 06:24:11 PM PDT 24
Peak memory 289084 kb
Host smart-f8b8646d-519b-4cb0-80a4-0275ee9884df
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1247148831 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_entropy.1247148831
Directory /workspace/21.alert_handler_entropy/latest

Test location /workspace/coverage/default/21.alert_handler_esc_alert_accum.3326990892
Short name T408
Test name
Test status
Simulation time 44985350449 ps
CPU time 362.51 seconds
Started Jul 24 05:34:01 PM PDT 24
Finished Jul 24 05:40:04 PM PDT 24
Peak memory 256908 kb
Host smart-f7e2b5f0-1d52-4a87-aaed-d5542717ae92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33269
90892 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_alert_accum.3326990892
Directory /workspace/21.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/21.alert_handler_esc_intr_timeout.3861583648
Short name T372
Test name
Test status
Simulation time 88794968 ps
CPU time 10.87 seconds
Started Jul 24 05:34:17 PM PDT 24
Finished Jul 24 05:34:28 PM PDT 24
Peak memory 253628 kb
Host smart-6e11c028-dd51-4941-927e-2fbffe241fab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38615
83648 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_intr_timeout.3861583648
Directory /workspace/21.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_lpg.768749667
Short name T328
Test name
Test status
Simulation time 154440666905 ps
CPU time 1820.31 seconds
Started Jul 24 05:34:04 PM PDT 24
Finished Jul 24 06:04:25 PM PDT 24
Peak memory 272576 kb
Host smart-4b66277a-a74a-43c0-95a4-506aedf59bfa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=768749667 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg.768749667
Directory /workspace/21.alert_handler_lpg/latest

Test location /workspace/coverage/default/21.alert_handler_lpg_stub_clk.1079961707
Short name T80
Test name
Test status
Simulation time 16999791244 ps
CPU time 1459.28 seconds
Started Jul 24 05:34:12 PM PDT 24
Finished Jul 24 05:58:32 PM PDT 24
Peak memory 288508 kb
Host smart-cb9234b1-fd95-4ee6-91d8-9f92daa96d26
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079961707 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg_stub_clk.1079961707
Directory /workspace/21.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/21.alert_handler_ping_timeout.3494268795
Short name T665
Test name
Test status
Simulation time 8528260615 ps
CPU time 382.23 seconds
Started Jul 24 05:34:04 PM PDT 24
Finished Jul 24 05:40:27 PM PDT 24
Peak memory 248660 kb
Host smart-3c408c30-2927-4ff0-b2ce-6964ec275f9f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494268795 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_ping_timeout.3494268795
Directory /workspace/21.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_random_alerts.2270355395
Short name T479
Test name
Test status
Simulation time 312251354 ps
CPU time 12.79 seconds
Started Jul 24 05:34:07 PM PDT 24
Finished Jul 24 05:34:19 PM PDT 24
Peak memory 248632 kb
Host smart-4186c900-4cb0-46e9-b344-f2f6164f72cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22703
55395 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_alerts.2270355395
Directory /workspace/21.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/21.alert_handler_random_classes.116915353
Short name T387
Test name
Test status
Simulation time 3471701347 ps
CPU time 21.03 seconds
Started Jul 24 05:34:07 PM PDT 24
Finished Jul 24 05:34:28 PM PDT 24
Peak memory 247936 kb
Host smart-bd388241-4a6c-45dc-96af-5a06ded7e807
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11691
5353 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_classes.116915353
Directory /workspace/21.alert_handler_random_classes/latest

Test location /workspace/coverage/default/21.alert_handler_sig_int_fail.1681381646
Short name T391
Test name
Test status
Simulation time 671166606 ps
CPU time 7.64 seconds
Started Jul 24 05:34:08 PM PDT 24
Finished Jul 24 05:34:16 PM PDT 24
Peak memory 253596 kb
Host smart-2cfa256c-01b1-4690-9d2a-58c5b4d7dd9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16813
81646 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_sig_int_fail.1681381646
Directory /workspace/21.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/21.alert_handler_smoke.902027271
Short name T580
Test name
Test status
Simulation time 1174884774 ps
CPU time 29.06 seconds
Started Jul 24 05:34:04 PM PDT 24
Finished Jul 24 05:34:33 PM PDT 24
Peak memory 256708 kb
Host smart-3d222b0d-ae1e-409a-896b-524f06ea5e88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90202
7271 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_smoke.902027271
Directory /workspace/21.alert_handler_smoke/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all.1704776875
Short name T636
Test name
Test status
Simulation time 58644135288 ps
CPU time 3714.46 seconds
Started Jul 24 05:34:08 PM PDT 24
Finished Jul 24 06:36:03 PM PDT 24
Peak memory 305960 kb
Host smart-bc2566c3-c453-4025-bf4e-94a5092af62e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704776875 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_ha
ndler_stress_all.1704776875
Directory /workspace/21.alert_handler_stress_all/latest

Test location /workspace/coverage/default/22.alert_handler_entropy.4175025626
Short name T463
Test name
Test status
Simulation time 42781245574 ps
CPU time 2599.94 seconds
Started Jul 24 05:34:08 PM PDT 24
Finished Jul 24 06:17:28 PM PDT 24
Peak memory 289612 kb
Host smart-855af5d6-7833-4661-9e62-5a5b891e7364
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175025626 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_entropy.4175025626
Directory /workspace/22.alert_handler_entropy/latest

Test location /workspace/coverage/default/22.alert_handler_esc_alert_accum.1808925849
Short name T302
Test name
Test status
Simulation time 1274404281 ps
CPU time 146.54 seconds
Started Jul 24 05:34:08 PM PDT 24
Finished Jul 24 05:36:34 PM PDT 24
Peak memory 256336 kb
Host smart-73409fcc-084c-4170-8369-d8209567c11f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18089
25849 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_alert_accum.1808925849
Directory /workspace/22.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/22.alert_handler_esc_intr_timeout.3883378878
Short name T403
Test name
Test status
Simulation time 560262151 ps
CPU time 23.73 seconds
Started Jul 24 05:34:10 PM PDT 24
Finished Jul 24 05:34:34 PM PDT 24
Peak memory 256836 kb
Host smart-a58c9d58-5ef9-44b0-b996-5cd41ecacd2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38833
78878 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_intr_timeout.3883378878
Directory /workspace/22.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_lpg.210212946
Short name T327
Test name
Test status
Simulation time 158597510225 ps
CPU time 1830.48 seconds
Started Jul 24 05:34:11 PM PDT 24
Finished Jul 24 06:04:42 PM PDT 24
Peak memory 283980 kb
Host smart-ef373509-756f-4b41-9cb3-e39c59fc424d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210212946 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg.210212946
Directory /workspace/22.alert_handler_lpg/latest

Test location /workspace/coverage/default/22.alert_handler_lpg_stub_clk.282774720
Short name T495
Test name
Test status
Simulation time 123084759832 ps
CPU time 1758.05 seconds
Started Jul 24 05:34:07 PM PDT 24
Finished Jul 24 06:03:26 PM PDT 24
Peak memory 273196 kb
Host smart-2a4c2fdc-c0b3-4642-8813-33aab23f7b58
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=282774720 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg_stub_clk.282774720
Directory /workspace/22.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/22.alert_handler_ping_timeout.1721260280
Short name T286
Test name
Test status
Simulation time 49819630916 ps
CPU time 524.72 seconds
Started Jul 24 05:34:08 PM PDT 24
Finished Jul 24 05:42:53 PM PDT 24
Peak memory 255340 kb
Host smart-ccf980da-b06c-4d02-9e9c-eb02c9a0c0a0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721260280 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_ping_timeout.1721260280
Directory /workspace/22.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_random_alerts.4036227985
Short name T630
Test name
Test status
Simulation time 314575973 ps
CPU time 10.79 seconds
Started Jul 24 05:34:06 PM PDT 24
Finished Jul 24 05:34:17 PM PDT 24
Peak memory 254940 kb
Host smart-4b031ef3-6834-402d-aee2-ceebfff40e43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40362
27985 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_alerts.4036227985
Directory /workspace/22.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/22.alert_handler_random_classes.112484718
Short name T107
Test name
Test status
Simulation time 251770945 ps
CPU time 24.3 seconds
Started Jul 24 05:34:05 PM PDT 24
Finished Jul 24 05:34:30 PM PDT 24
Peak memory 248192 kb
Host smart-cabebc57-27ae-469e-bad6-ec443f99b1fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11248
4718 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_classes.112484718
Directory /workspace/22.alert_handler_random_classes/latest

Test location /workspace/coverage/default/22.alert_handler_sig_int_fail.2919568486
Short name T669
Test name
Test status
Simulation time 1831956484 ps
CPU time 38.52 seconds
Started Jul 24 05:34:11 PM PDT 24
Finished Jul 24 05:34:50 PM PDT 24
Peak memory 248368 kb
Host smart-61e84ef7-2ac4-444e-bb0d-7b6f91500fb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29195
68486 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_sig_int_fail.2919568486
Directory /workspace/22.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/22.alert_handler_smoke.1774948744
Short name T401
Test name
Test status
Simulation time 377110000 ps
CPU time 20.53 seconds
Started Jul 24 05:34:04 PM PDT 24
Finished Jul 24 05:34:25 PM PDT 24
Peak memory 248572 kb
Host smart-aca2fa16-8140-46e5-b700-18e2f375189a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17749
48744 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_smoke.1774948744
Directory /workspace/22.alert_handler_smoke/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all.2014735228
Short name T714
Test name
Test status
Simulation time 30709428766 ps
CPU time 1337.91 seconds
Started Jul 24 05:34:09 PM PDT 24
Finished Jul 24 05:56:27 PM PDT 24
Peak memory 289276 kb
Host smart-16521b9d-016d-4709-b836-bcf46fdf3bf0
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014735228 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_ha
ndler_stress_all.2014735228
Directory /workspace/22.alert_handler_stress_all/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all_with_rand_reset.862953158
Short name T613
Test name
Test status
Simulation time 60216744682 ps
CPU time 5826.25 seconds
Started Jul 24 05:34:09 PM PDT 24
Finished Jul 24 07:11:16 PM PDT 24
Peak memory 367296 kb
Host smart-ff1e5b6f-5203-41d4-b247-3c98cf4c6094
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862953158 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 22.alert_handler_stress_all_with_rand_reset.862953158
Directory /workspace/22.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.alert_handler_entropy.2567012282
Short name T619
Test name
Test status
Simulation time 49306115435 ps
CPU time 2638.56 seconds
Started Jul 24 05:34:09 PM PDT 24
Finished Jul 24 06:18:08 PM PDT 24
Peak memory 288828 kb
Host smart-959cfa42-9275-4bbe-9606-b83c817d0da5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567012282 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_entropy.2567012282
Directory /workspace/23.alert_handler_entropy/latest

Test location /workspace/coverage/default/23.alert_handler_esc_alert_accum.1870414068
Short name T444
Test name
Test status
Simulation time 9406216231 ps
CPU time 178.45 seconds
Started Jul 24 05:34:10 PM PDT 24
Finished Jul 24 05:37:09 PM PDT 24
Peak memory 256352 kb
Host smart-20f7a7e7-5885-47f4-83fb-d749d0651168
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18704
14068 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_alert_accum.1870414068
Directory /workspace/23.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/23.alert_handler_lpg.1127402518
Short name T587
Test name
Test status
Simulation time 75746016654 ps
CPU time 1569.9 seconds
Started Jul 24 05:34:13 PM PDT 24
Finished Jul 24 06:00:23 PM PDT 24
Peak memory 288244 kb
Host smart-0604a1f0-3609-42e8-86c1-264462d9e793
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127402518 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg.1127402518
Directory /workspace/23.alert_handler_lpg/latest

Test location /workspace/coverage/default/23.alert_handler_lpg_stub_clk.1132519918
Short name T482
Test name
Test status
Simulation time 35809713540 ps
CPU time 720.45 seconds
Started Jul 24 05:34:15 PM PDT 24
Finished Jul 24 05:46:16 PM PDT 24
Peak memory 273016 kb
Host smart-5c926a83-3f61-4f0a-b3a8-96557d7bdea0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132519918 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg_stub_clk.1132519918
Directory /workspace/23.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/23.alert_handler_random_alerts.934367177
Short name T293
Test name
Test status
Simulation time 2040982495 ps
CPU time 64.6 seconds
Started Jul 24 05:34:13 PM PDT 24
Finished Jul 24 05:35:18 PM PDT 24
Peak memory 256100 kb
Host smart-66699c91-7dee-45b8-ba6c-906002167c63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93436
7177 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_alerts.934367177
Directory /workspace/23.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/23.alert_handler_random_classes.3586110171
Short name T601
Test name
Test status
Simulation time 1088623096 ps
CPU time 23.02 seconds
Started Jul 24 05:34:19 PM PDT 24
Finished Jul 24 05:34:42 PM PDT 24
Peak memory 248180 kb
Host smart-c1e975ea-21c3-4489-ae91-cd73e0a4e388
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35861
10171 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_classes.3586110171
Directory /workspace/23.alert_handler_random_classes/latest

Test location /workspace/coverage/default/23.alert_handler_sig_int_fail.1291821234
Short name T512
Test name
Test status
Simulation time 203990647 ps
CPU time 25.81 seconds
Started Jul 24 05:34:11 PM PDT 24
Finished Jul 24 05:34:37 PM PDT 24
Peak memory 255900 kb
Host smart-d6f70b6d-3792-4b1a-a6ac-0ef8f3d4882b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12918
21234 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_sig_int_fail.1291821234
Directory /workspace/23.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/23.alert_handler_smoke.1131778016
Short name T646
Test name
Test status
Simulation time 727233549 ps
CPU time 13.95 seconds
Started Jul 24 05:34:10 PM PDT 24
Finished Jul 24 05:34:24 PM PDT 24
Peak memory 255920 kb
Host smart-99b3a77e-7e9b-4b25-95e1-43aa25e4f1fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11317
78016 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_smoke.1131778016
Directory /workspace/23.alert_handler_smoke/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all.622729111
Short name T229
Test name
Test status
Simulation time 18169078657 ps
CPU time 957.83 seconds
Started Jul 24 05:34:19 PM PDT 24
Finished Jul 24 05:50:17 PM PDT 24
Peak memory 265076 kb
Host smart-6843df7a-ce7d-407d-a073-9969d1776d40
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622729111 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_han
dler_stress_all.622729111
Directory /workspace/23.alert_handler_stress_all/latest

Test location /workspace/coverage/default/24.alert_handler_entropy.3705834347
Short name T525
Test name
Test status
Simulation time 9432386147 ps
CPU time 817.94 seconds
Started Jul 24 05:34:17 PM PDT 24
Finished Jul 24 05:47:55 PM PDT 24
Peak memory 272596 kb
Host smart-0d22be5d-116b-4d39-b48b-8e54d8e1affa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705834347 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_entropy.3705834347
Directory /workspace/24.alert_handler_entropy/latest

Test location /workspace/coverage/default/24.alert_handler_esc_alert_accum.3782019632
Short name T503
Test name
Test status
Simulation time 6780638535 ps
CPU time 218.3 seconds
Started Jul 24 05:34:17 PM PDT 24
Finished Jul 24 05:37:56 PM PDT 24
Peak memory 256488 kb
Host smart-9218bb38-74ae-4208-98cc-0086839a555d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37820
19632 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_alert_accum.3782019632
Directory /workspace/24.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/24.alert_handler_esc_intr_timeout.4098208487
Short name T312
Test name
Test status
Simulation time 5071629449 ps
CPU time 79.63 seconds
Started Jul 24 05:34:18 PM PDT 24
Finished Jul 24 05:35:38 PM PDT 24
Peak memory 255900 kb
Host smart-002269f1-a99a-4d8a-b0eb-6e2503d2a105
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40982
08487 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_intr_timeout.4098208487
Directory /workspace/24.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_lpg.3654304149
Short name T73
Test name
Test status
Simulation time 70439346203 ps
CPU time 1601.72 seconds
Started Jul 24 05:34:20 PM PDT 24
Finished Jul 24 06:01:02 PM PDT 24
Peak memory 288928 kb
Host smart-0457d1ed-9872-4775-b81a-9e6d139c45e7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654304149 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg.3654304149
Directory /workspace/24.alert_handler_lpg/latest

Test location /workspace/coverage/default/24.alert_handler_lpg_stub_clk.98386063
Short name T543
Test name
Test status
Simulation time 237078648373 ps
CPU time 2028.42 seconds
Started Jul 24 05:34:21 PM PDT 24
Finished Jul 24 06:08:09 PM PDT 24
Peak memory 281428 kb
Host smart-965febdd-d0a1-486d-a1fb-8801621330bd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98386063 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg_stub_clk.98386063
Directory /workspace/24.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/24.alert_handler_ping_timeout.2850185107
Short name T281
Test name
Test status
Simulation time 8258342571 ps
CPU time 334.87 seconds
Started Jul 24 05:34:21 PM PDT 24
Finished Jul 24 05:39:56 PM PDT 24
Peak memory 247544 kb
Host smart-504d6c7e-31c4-4575-8174-a719ebef48c1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850185107 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_ping_timeout.2850185107
Directory /workspace/24.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_random_alerts.333101453
Short name T91
Test name
Test status
Simulation time 283308598 ps
CPU time 28.97 seconds
Started Jul 24 05:34:16 PM PDT 24
Finished Jul 24 05:34:45 PM PDT 24
Peak memory 255816 kb
Host smart-2e7eb9fc-7f73-4798-84d1-67fbb5f4e2d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33310
1453 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_alerts.333101453
Directory /workspace/24.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/24.alert_handler_random_classes.1762540503
Short name T452
Test name
Test status
Simulation time 418998303 ps
CPU time 40.22 seconds
Started Jul 24 05:34:17 PM PDT 24
Finished Jul 24 05:34:57 PM PDT 24
Peak memory 248648 kb
Host smart-d7e731cb-0549-4372-9ed7-6bdc3494ca11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17625
40503 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_classes.1762540503
Directory /workspace/24.alert_handler_random_classes/latest

Test location /workspace/coverage/default/24.alert_handler_sig_int_fail.963541412
Short name T86
Test name
Test status
Simulation time 270303910 ps
CPU time 21.81 seconds
Started Jul 24 05:34:18 PM PDT 24
Finished Jul 24 05:34:40 PM PDT 24
Peak memory 255972 kb
Host smart-36242910-87ce-43ab-90dd-32f406d46f25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96354
1412 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_sig_int_fail.963541412
Directory /workspace/24.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/24.alert_handler_smoke.2577981414
Short name T415
Test name
Test status
Simulation time 139130403 ps
CPU time 4.46 seconds
Started Jul 24 05:34:16 PM PDT 24
Finished Jul 24 05:34:21 PM PDT 24
Peak memory 250352 kb
Host smart-26d33726-a84f-4622-afe0-c1607c1dd835
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25779
81414 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_smoke.2577981414
Directory /workspace/24.alert_handler_smoke/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all.773666027
Short name T18
Test name
Test status
Simulation time 53608250355 ps
CPU time 3158.33 seconds
Started Jul 24 05:34:27 PM PDT 24
Finished Jul 24 06:27:06 PM PDT 24
Peak memory 288672 kb
Host smart-b52ff4ab-ac68-43c2-afa6-2d9c67f4ed99
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773666027 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_han
dler_stress_all.773666027
Directory /workspace/24.alert_handler_stress_all/latest

Test location /workspace/coverage/default/25.alert_handler_entropy.3589427916
Short name T489
Test name
Test status
Simulation time 39032176850 ps
CPU time 2475.02 seconds
Started Jul 24 05:34:20 PM PDT 24
Finished Jul 24 06:15:36 PM PDT 24
Peak memory 282172 kb
Host smart-f36c020a-bf75-4d7e-8ecc-5897c8144019
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589427916 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_entropy.3589427916
Directory /workspace/25.alert_handler_entropy/latest

Test location /workspace/coverage/default/25.alert_handler_esc_alert_accum.2904803427
Short name T379
Test name
Test status
Simulation time 1198464588 ps
CPU time 23.58 seconds
Started Jul 24 05:34:19 PM PDT 24
Finished Jul 24 05:34:42 PM PDT 24
Peak memory 256120 kb
Host smart-ce29f8db-0cfb-4e4c-9e48-02bcced83798
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29048
03427 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_alert_accum.2904803427
Directory /workspace/25.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/25.alert_handler_esc_intr_timeout.1498001147
Short name T308
Test name
Test status
Simulation time 1088042384 ps
CPU time 62.21 seconds
Started Jul 24 05:34:22 PM PDT 24
Finished Jul 24 05:35:24 PM PDT 24
Peak memory 248116 kb
Host smart-26a0eca1-e0a6-4ba7-bc92-85debad284cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14980
01147 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_intr_timeout.1498001147
Directory /workspace/25.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_lpg.1360061896
Short name T257
Test name
Test status
Simulation time 10345182265 ps
CPU time 865.96 seconds
Started Jul 24 05:34:20 PM PDT 24
Finished Jul 24 05:48:47 PM PDT 24
Peak memory 272416 kb
Host smart-8b171388-f472-4e96-911d-10f7509c2030
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360061896 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg.1360061896
Directory /workspace/25.alert_handler_lpg/latest

Test location /workspace/coverage/default/25.alert_handler_lpg_stub_clk.3913891052
Short name T496
Test name
Test status
Simulation time 6853861110 ps
CPU time 782.16 seconds
Started Jul 24 05:34:23 PM PDT 24
Finished Jul 24 05:47:25 PM PDT 24
Peak memory 273132 kb
Host smart-0a04ee02-a2f7-4734-aee5-fb55620af530
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913891052 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg_stub_clk.3913891052
Directory /workspace/25.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/25.alert_handler_ping_timeout.1812573465
Short name T214
Test name
Test status
Simulation time 6703562749 ps
CPU time 150.05 seconds
Started Jul 24 05:34:18 PM PDT 24
Finished Jul 24 05:36:48 PM PDT 24
Peak memory 255288 kb
Host smart-395fb9b7-ddc3-4442-8c6c-f54148249592
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812573465 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_ping_timeout.1812573465
Directory /workspace/25.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_random_alerts.1217611527
Short name T557
Test name
Test status
Simulation time 811181946 ps
CPU time 26.45 seconds
Started Jul 24 05:34:21 PM PDT 24
Finished Jul 24 05:34:47 PM PDT 24
Peak memory 256692 kb
Host smart-13168f01-3f8f-4a29-829d-3b34df39948a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12176
11527 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_alerts.1217611527
Directory /workspace/25.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/25.alert_handler_random_classes.2200646364
Short name T103
Test name
Test status
Simulation time 84651945 ps
CPU time 7.81 seconds
Started Jul 24 05:34:21 PM PDT 24
Finished Jul 24 05:34:29 PM PDT 24
Peak memory 248184 kb
Host smart-5266632d-50da-4777-b172-03ba4066e1fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22006
46364 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_classes.2200646364
Directory /workspace/25.alert_handler_random_classes/latest

Test location /workspace/coverage/default/25.alert_handler_sig_int_fail.4275808659
Short name T244
Test name
Test status
Simulation time 4434471074 ps
CPU time 53.06 seconds
Started Jul 24 05:34:20 PM PDT 24
Finished Jul 24 05:35:13 PM PDT 24
Peak memory 248396 kb
Host smart-2fd55f6f-2816-40b8-9af1-9d9666d996da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42758
08659 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_sig_int_fail.4275808659
Directory /workspace/25.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/25.alert_handler_smoke.1271467952
Short name T352
Test name
Test status
Simulation time 406912059 ps
CPU time 19.48 seconds
Started Jul 24 05:34:18 PM PDT 24
Finished Jul 24 05:34:38 PM PDT 24
Peak memory 255088 kb
Host smart-47f0741b-7e14-44e9-950b-cd91ba136602
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12714
67952 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_smoke.1271467952
Directory /workspace/25.alert_handler_smoke/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all.2828255147
Short name T520
Test name
Test status
Simulation time 844373249 ps
CPU time 48.44 seconds
Started Jul 24 05:34:20 PM PDT 24
Finished Jul 24 05:35:08 PM PDT 24
Peak memory 256840 kb
Host smart-7a9b3c94-e31f-4dbb-871f-0e6c79768b5e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828255147 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_ha
ndler_stress_all.2828255147
Directory /workspace/25.alert_handler_stress_all/latest

Test location /workspace/coverage/default/26.alert_handler_entropy.1605128751
Short name T481
Test name
Test status
Simulation time 8541356356 ps
CPU time 875.89 seconds
Started Jul 24 05:34:25 PM PDT 24
Finished Jul 24 05:49:01 PM PDT 24
Peak memory 269192 kb
Host smart-c85c4b8e-ba25-4ed1-84ff-70ebf0efc160
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605128751 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_entropy.1605128751
Directory /workspace/26.alert_handler_entropy/latest

Test location /workspace/coverage/default/26.alert_handler_esc_alert_accum.279003250
Short name T231
Test name
Test status
Simulation time 39615991731 ps
CPU time 264.24 seconds
Started Jul 24 05:34:25 PM PDT 24
Finished Jul 24 05:38:50 PM PDT 24
Peak memory 256796 kb
Host smart-5abb7143-7a2c-46db-94a4-df6bf0604190
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27900
3250 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_alert_accum.279003250
Directory /workspace/26.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/26.alert_handler_esc_intr_timeout.1545222098
Short name T84
Test name
Test status
Simulation time 1575446993 ps
CPU time 49.91 seconds
Started Jul 24 05:34:27 PM PDT 24
Finished Jul 24 05:35:17 PM PDT 24
Peak memory 248372 kb
Host smart-f455f0b4-c499-4697-bad7-38ff5bad023c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15452
22098 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_intr_timeout.1545222098
Directory /workspace/26.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_lpg.2995820953
Short name T322
Test name
Test status
Simulation time 143213699445 ps
CPU time 2244.57 seconds
Started Jul 24 05:34:24 PM PDT 24
Finished Jul 24 06:11:50 PM PDT 24
Peak memory 288772 kb
Host smart-42732a51-bed1-4307-be5f-c78c75b7d748
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995820953 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg.2995820953
Directory /workspace/26.alert_handler_lpg/latest

Test location /workspace/coverage/default/26.alert_handler_lpg_stub_clk.2257041844
Short name T407
Test name
Test status
Simulation time 26260944311 ps
CPU time 861.7 seconds
Started Jul 24 05:34:24 PM PDT 24
Finished Jul 24 05:48:46 PM PDT 24
Peak memory 269132 kb
Host smart-810e5d2f-631a-4038-ac38-6533128e38fc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257041844 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg_stub_clk.2257041844
Directory /workspace/26.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/26.alert_handler_ping_timeout.2942384931
Short name T529
Test name
Test status
Simulation time 22609090134 ps
CPU time 229.48 seconds
Started Jul 24 05:34:24 PM PDT 24
Finished Jul 24 05:38:14 PM PDT 24
Peak memory 248676 kb
Host smart-53a5e078-e5b6-4637-80cc-3f7c23fd7911
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942384931 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_ping_timeout.2942384931
Directory /workspace/26.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_random_alerts.506668652
Short name T417
Test name
Test status
Simulation time 46597691 ps
CPU time 6.73 seconds
Started Jul 24 05:34:21 PM PDT 24
Finished Jul 24 05:34:28 PM PDT 24
Peak memory 248576 kb
Host smart-3893ff85-ba0b-4f2f-8aba-1bdf95a82abb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50666
8652 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_alerts.506668652
Directory /workspace/26.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/26.alert_handler_random_classes.3286217371
Short name T536
Test name
Test status
Simulation time 1202682021 ps
CPU time 18.32 seconds
Started Jul 24 05:34:27 PM PDT 24
Finished Jul 24 05:34:46 PM PDT 24
Peak memory 248200 kb
Host smart-fb59015c-150a-438a-8e7f-0e36713ef3a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32862
17371 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_classes.3286217371
Directory /workspace/26.alert_handler_random_classes/latest

Test location /workspace/coverage/default/26.alert_handler_sig_int_fail.620271331
Short name T233
Test name
Test status
Simulation time 1140144982 ps
CPU time 21.45 seconds
Started Jul 24 05:34:30 PM PDT 24
Finished Jul 24 05:34:52 PM PDT 24
Peak memory 255956 kb
Host smart-9a2b3ada-bb6a-4fbf-9534-4042fd051e06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62027
1331 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_sig_int_fail.620271331
Directory /workspace/26.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/26.alert_handler_smoke.3934091417
Short name T689
Test name
Test status
Simulation time 2461445191 ps
CPU time 34.49 seconds
Started Jul 24 05:34:21 PM PDT 24
Finished Jul 24 05:34:55 PM PDT 24
Peak memory 249100 kb
Host smart-997eb83a-355e-434c-bf72-a8bd16fc18ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39340
91417 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_smoke.3934091417
Directory /workspace/26.alert_handler_smoke/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all.743011726
Short name T651
Test name
Test status
Simulation time 2899922682 ps
CPU time 62.41 seconds
Started Jul 24 05:34:26 PM PDT 24
Finished Jul 24 05:35:29 PM PDT 24
Peak memory 256852 kb
Host smart-e4056d25-8167-430d-8c14-90e927faf00b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743011726 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_han
dler_stress_all.743011726
Directory /workspace/26.alert_handler_stress_all/latest

Test location /workspace/coverage/default/27.alert_handler_entropy.2143729628
Short name T594
Test name
Test status
Simulation time 11677849122 ps
CPU time 1317.35 seconds
Started Jul 24 05:34:28 PM PDT 24
Finished Jul 24 05:56:26 PM PDT 24
Peak memory 289672 kb
Host smart-0b175f8f-20ec-451c-b366-48c3def313d3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2143729628 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_entropy.2143729628
Directory /workspace/27.alert_handler_entropy/latest

Test location /workspace/coverage/default/27.alert_handler_esc_alert_accum.3575376534
Short name T627
Test name
Test status
Simulation time 1695982080 ps
CPU time 151.73 seconds
Started Jul 24 05:34:25 PM PDT 24
Finished Jul 24 05:36:57 PM PDT 24
Peak memory 255920 kb
Host smart-ec714982-171f-4fc0-bd51-8e7f4f0cd66f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35753
76534 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_alert_accum.3575376534
Directory /workspace/27.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/27.alert_handler_esc_intr_timeout.3920862210
Short name T620
Test name
Test status
Simulation time 29197034 ps
CPU time 3.1 seconds
Started Jul 24 05:34:25 PM PDT 24
Finished Jul 24 05:34:28 PM PDT 24
Peak memory 240368 kb
Host smart-5f8ef5cf-d225-4759-8d98-91e15472cdf4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39208
62210 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_intr_timeout.3920862210
Directory /workspace/27.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_lpg.4052532869
Short name T675
Test name
Test status
Simulation time 37364441981 ps
CPU time 1755.04 seconds
Started Jul 24 05:34:25 PM PDT 24
Finished Jul 24 06:03:40 PM PDT 24
Peak memory 283800 kb
Host smart-603534fa-0aaf-4475-9c0a-9420f684f3a5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052532869 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg.4052532869
Directory /workspace/27.alert_handler_lpg/latest

Test location /workspace/coverage/default/27.alert_handler_lpg_stub_clk.726385032
Short name T68
Test name
Test status
Simulation time 44557707093 ps
CPU time 926.77 seconds
Started Jul 24 05:34:30 PM PDT 24
Finished Jul 24 05:49:57 PM PDT 24
Peak memory 268012 kb
Host smart-5d42e813-3c07-4d13-9933-8e7c363d1797
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726385032 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg_stub_clk.726385032
Directory /workspace/27.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/27.alert_handler_ping_timeout.1996778251
Short name T273
Test name
Test status
Simulation time 38824331378 ps
CPU time 384.66 seconds
Started Jul 24 05:34:30 PM PDT 24
Finished Jul 24 05:40:55 PM PDT 24
Peak memory 248432 kb
Host smart-aecc75ea-164d-4105-90d4-7b4e84ff74a1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996778251 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_ping_timeout.1996778251
Directory /workspace/27.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_random_alerts.3245713820
Short name T442
Test name
Test status
Simulation time 1763332706 ps
CPU time 37.24 seconds
Started Jul 24 05:34:26 PM PDT 24
Finished Jul 24 05:35:04 PM PDT 24
Peak memory 256792 kb
Host smart-8d580c75-c301-40ab-8aac-572a03d49992
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32457
13820 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_alerts.3245713820
Directory /workspace/27.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/27.alert_handler_random_classes.2404519093
Short name T289
Test name
Test status
Simulation time 3751384023 ps
CPU time 34.25 seconds
Started Jul 24 05:34:21 PM PDT 24
Finished Jul 24 05:34:55 PM PDT 24
Peak memory 248644 kb
Host smart-9ffcf601-d8ed-4b11-acd5-9705b39874cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24045
19093 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_classes.2404519093
Directory /workspace/27.alert_handler_random_classes/latest

Test location /workspace/coverage/default/27.alert_handler_sig_int_fail.2042158900
Short name T667
Test name
Test status
Simulation time 2328623588 ps
CPU time 38.14 seconds
Started Jul 24 05:34:24 PM PDT 24
Finished Jul 24 05:35:03 PM PDT 24
Peak memory 256448 kb
Host smart-cbe7ca77-9616-4b29-a7af-688fa35565b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20421
58900 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_sig_int_fail.2042158900
Directory /workspace/27.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/27.alert_handler_smoke.397511926
Short name T506
Test name
Test status
Simulation time 237305265 ps
CPU time 6.34 seconds
Started Jul 24 05:34:29 PM PDT 24
Finished Jul 24 05:34:35 PM PDT 24
Peak memory 256708 kb
Host smart-f69b1e5f-d258-4f5c-afba-cf78e6787783
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39751
1926 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_smoke.397511926
Directory /workspace/27.alert_handler_smoke/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all.1620922204
Short name T621
Test name
Test status
Simulation time 5051097149 ps
CPU time 293.06 seconds
Started Jul 24 05:34:31 PM PDT 24
Finished Jul 24 05:39:24 PM PDT 24
Peak memory 254292 kb
Host smart-c428cc2a-655c-4a2a-a7b0-e1ced53aeb8f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620922204 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_ha
ndler_stress_all.1620922204
Directory /workspace/27.alert_handler_stress_all/latest

Test location /workspace/coverage/default/28.alert_handler_entropy.3031754236
Short name T116
Test name
Test status
Simulation time 5488041850 ps
CPU time 695.59 seconds
Started Jul 24 05:34:29 PM PDT 24
Finished Jul 24 05:46:05 PM PDT 24
Peak memory 272568 kb
Host smart-16326af3-92a6-4c7e-b1b8-10c8eef9c9bb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3031754236 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_entropy.3031754236
Directory /workspace/28.alert_handler_entropy/latest

Test location /workspace/coverage/default/28.alert_handler_esc_alert_accum.1687987714
Short name T622
Test name
Test status
Simulation time 9560763290 ps
CPU time 275.33 seconds
Started Jul 24 05:34:33 PM PDT 24
Finished Jul 24 05:39:08 PM PDT 24
Peak memory 256328 kb
Host smart-5fe52de6-1d12-44cd-9a9b-d6aeca47dbdc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16879
87714 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_alert_accum.1687987714
Directory /workspace/28.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/28.alert_handler_esc_intr_timeout.450374512
Short name T424
Test name
Test status
Simulation time 144064471 ps
CPU time 13.01 seconds
Started Jul 24 05:34:33 PM PDT 24
Finished Jul 24 05:34:46 PM PDT 24
Peak memory 248088 kb
Host smart-672c3379-7437-48f5-83d0-0c2ade8f4d27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45037
4512 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_intr_timeout.450374512
Directory /workspace/28.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_lpg_stub_clk.3890383116
Short name T7
Test name
Test status
Simulation time 45541709508 ps
CPU time 1540.62 seconds
Started Jul 24 05:34:32 PM PDT 24
Finished Jul 24 06:00:13 PM PDT 24
Peak memory 273236 kb
Host smart-47dca803-d4e2-48cb-8e2e-19896d7bf489
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3890383116 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg_stub_clk.3890383116
Directory /workspace/28.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/28.alert_handler_ping_timeout.2838542463
Short name T287
Test name
Test status
Simulation time 21769064723 ps
CPU time 476.19 seconds
Started Jul 24 05:34:33 PM PDT 24
Finished Jul 24 05:42:29 PM PDT 24
Peak memory 247608 kb
Host smart-166afef9-4050-4328-abe9-76bc5d2e3c87
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838542463 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_ping_timeout.2838542463
Directory /workspace/28.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_random_alerts.3472329402
Short name T23
Test name
Test status
Simulation time 953810968 ps
CPU time 54.5 seconds
Started Jul 24 05:34:31 PM PDT 24
Finished Jul 24 05:35:26 PM PDT 24
Peak memory 248520 kb
Host smart-21662ef7-e8dd-4833-ba1c-6610e849c996
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34723
29402 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_alerts.3472329402
Directory /workspace/28.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/28.alert_handler_random_classes.2475418655
Short name T558
Test name
Test status
Simulation time 287369007 ps
CPU time 16.14 seconds
Started Jul 24 05:34:30 PM PDT 24
Finished Jul 24 05:34:46 PM PDT 24
Peak memory 248164 kb
Host smart-2ff98661-56ad-49d7-8305-961aefe11ee9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24754
18655 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_classes.2475418655
Directory /workspace/28.alert_handler_random_classes/latest

Test location /workspace/coverage/default/28.alert_handler_smoke.1283893594
Short name T610
Test name
Test status
Simulation time 147166664 ps
CPU time 15.5 seconds
Started Jul 24 05:34:33 PM PDT 24
Finished Jul 24 05:34:49 PM PDT 24
Peak memory 256504 kb
Host smart-58d680a6-916a-4b7a-9760-fa275e355b3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12838
93594 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_smoke.1283893594
Directory /workspace/28.alert_handler_smoke/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all.3754096504
Short name T709
Test name
Test status
Simulation time 49674938414 ps
CPU time 3216.91 seconds
Started Jul 24 05:34:32 PM PDT 24
Finished Jul 24 06:28:10 PM PDT 24
Peak memory 289232 kb
Host smart-f098be34-8afa-4ec8-ba93-f44712b3bc9a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754096504 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_ha
ndler_stress_all.3754096504
Directory /workspace/28.alert_handler_stress_all/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all_with_rand_reset.1402414873
Short name T101
Test name
Test status
Simulation time 70523671130 ps
CPU time 4539.46 seconds
Started Jul 24 05:34:31 PM PDT 24
Finished Jul 24 06:50:11 PM PDT 24
Peak memory 305676 kb
Host smart-92c68a09-19e2-4ddc-bcef-2c179e6d6e72
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402414873 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.alert_handler_stress_all_with_rand_reset.1402414873
Directory /workspace/28.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.alert_handler_entropy.503067257
Short name T457
Test name
Test status
Simulation time 78220403189 ps
CPU time 3085.91 seconds
Started Jul 24 05:34:34 PM PDT 24
Finished Jul 24 06:26:00 PM PDT 24
Peak memory 289408 kb
Host smart-b0abf201-7701-451b-b4f9-75df57f9ad5a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503067257 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_entropy.503067257
Directory /workspace/29.alert_handler_entropy/latest

Test location /workspace/coverage/default/29.alert_handler_esc_alert_accum.2028897021
Short name T490
Test name
Test status
Simulation time 618054485 ps
CPU time 28.92 seconds
Started Jul 24 05:34:34 PM PDT 24
Finished Jul 24 05:35:03 PM PDT 24
Peak memory 256316 kb
Host smart-55460bc7-46e8-4b47-855e-887113855eec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20288
97021 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_alert_accum.2028897021
Directory /workspace/29.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/29.alert_handler_esc_intr_timeout.720137203
Short name T552
Test name
Test status
Simulation time 878200175 ps
CPU time 9.52 seconds
Started Jul 24 05:34:31 PM PDT 24
Finished Jul 24 05:34:40 PM PDT 24
Peak memory 248184 kb
Host smart-9e3a8302-4fba-43e3-a685-854c68e96db4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72013
7203 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_intr_timeout.720137203
Directory /workspace/29.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_lpg.1165894892
Short name T325
Test name
Test status
Simulation time 29047641091 ps
CPU time 1781.78 seconds
Started Jul 24 05:34:36 PM PDT 24
Finished Jul 24 06:04:18 PM PDT 24
Peak memory 283276 kb
Host smart-c59e1d45-1bb9-4d9d-b63c-974ab0a76f05
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165894892 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg.1165894892
Directory /workspace/29.alert_handler_lpg/latest

Test location /workspace/coverage/default/29.alert_handler_lpg_stub_clk.3573703923
Short name T380
Test name
Test status
Simulation time 31412775197 ps
CPU time 790.61 seconds
Started Jul 24 05:34:39 PM PDT 24
Finished Jul 24 05:47:50 PM PDT 24
Peak memory 273004 kb
Host smart-e63ccd79-92f9-4c44-b947-ee212b5f3fec
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573703923 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg_stub_clk.3573703923
Directory /workspace/29.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/29.alert_handler_ping_timeout.996595909
Short name T10
Test name
Test status
Simulation time 33921259131 ps
CPU time 361.68 seconds
Started Jul 24 05:34:34 PM PDT 24
Finished Jul 24 05:40:36 PM PDT 24
Peak memory 248604 kb
Host smart-e42ebea5-d6ee-4a4d-b55f-34509a1a19cc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996595909 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_ping_timeout.996595909
Directory /workspace/29.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_random_alerts.827758108
Short name T505
Test name
Test status
Simulation time 1424590879 ps
CPU time 26.32 seconds
Started Jul 24 05:34:32 PM PDT 24
Finished Jul 24 05:34:59 PM PDT 24
Peak memory 248632 kb
Host smart-b323834f-c3fe-49a1-9cb1-88d1866a724f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82775
8108 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_alerts.827758108
Directory /workspace/29.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/29.alert_handler_random_classes.3198869418
Short name T418
Test name
Test status
Simulation time 6515352412 ps
CPU time 50.46 seconds
Started Jul 24 05:34:32 PM PDT 24
Finished Jul 24 05:35:23 PM PDT 24
Peak memory 255968 kb
Host smart-a93adbdb-3f01-44ad-a8ab-bda36c009fe6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31988
69418 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_classes.3198869418
Directory /workspace/29.alert_handler_random_classes/latest

Test location /workspace/coverage/default/29.alert_handler_sig_int_fail.4178821556
Short name T39
Test name
Test status
Simulation time 658830881 ps
CPU time 43.65 seconds
Started Jul 24 05:34:34 PM PDT 24
Finished Jul 24 05:35:18 PM PDT 24
Peak memory 255924 kb
Host smart-d0ac434c-fcb9-4082-8016-d9ba4f9f0d8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41788
21556 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_sig_int_fail.4178821556
Directory /workspace/29.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/29.alert_handler_smoke.2472286245
Short name T419
Test name
Test status
Simulation time 320486999 ps
CPU time 11.8 seconds
Started Jul 24 05:34:32 PM PDT 24
Finished Jul 24 05:34:44 PM PDT 24
Peak memory 253652 kb
Host smart-be9063d6-acea-408a-9de1-91d6544f77cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24722
86245 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_smoke.2472286245
Directory /workspace/29.alert_handler_smoke/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all.3047725503
Short name T295
Test name
Test status
Simulation time 69114660603 ps
CPU time 2214.57 seconds
Started Jul 24 05:34:34 PM PDT 24
Finished Jul 24 06:11:29 PM PDT 24
Peak memory 288792 kb
Host smart-de5b87a8-ccfe-4502-bf89-bf71b138dac3
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047725503 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_ha
ndler_stress_all.3047725503
Directory /workspace/29.alert_handler_stress_all/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all_with_rand_reset.1790718570
Short name T294
Test name
Test status
Simulation time 201539498854 ps
CPU time 3679.91 seconds
Started Jul 24 05:34:39 PM PDT 24
Finished Jul 24 06:36:00 PM PDT 24
Peak memory 305988 kb
Host smart-87b41d19-5f5b-4eb1-91af-6d38ee381bc0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790718570 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 29.alert_handler_stress_all_with_rand_reset.1790718570
Directory /workspace/29.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.alert_handler_alert_accum_saturation.3014389799
Short name T207
Test name
Test status
Simulation time 18182744 ps
CPU time 2.6 seconds
Started Jul 24 05:33:38 PM PDT 24
Finished Jul 24 05:33:41 PM PDT 24
Peak memory 248804 kb
Host smart-fb5f9a62-1634-4a27-acc4-31514090cb14
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3014389799 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_alert_accum_saturation.3014389799
Directory /workspace/3.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/3.alert_handler_entropy.1313526551
Short name T542
Test name
Test status
Simulation time 88610180803 ps
CPU time 3420.02 seconds
Started Jul 24 05:33:38 PM PDT 24
Finished Jul 24 06:30:38 PM PDT 24
Peak memory 288860 kb
Host smart-483d2038-cc72-4eec-89d5-2bf6376944bf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1313526551 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy.1313526551
Directory /workspace/3.alert_handler_entropy/latest

Test location /workspace/coverage/default/3.alert_handler_entropy_stress.201548909
Short name T708
Test name
Test status
Simulation time 450655644 ps
CPU time 21.21 seconds
Started Jul 24 05:33:56 PM PDT 24
Finished Jul 24 05:34:17 PM PDT 24
Peak memory 248536 kb
Host smart-b9ac228b-70d7-4f7f-bc8f-debbb8e6b913
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=201548909 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy_stress.201548909
Directory /workspace/3.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/3.alert_handler_esc_alert_accum.3553713423
Short name T210
Test name
Test status
Simulation time 11271230961 ps
CPU time 195.37 seconds
Started Jul 24 05:33:34 PM PDT 24
Finished Jul 24 05:36:50 PM PDT 24
Peak memory 249132 kb
Host smart-ebb5e163-ffb0-4c9e-82bd-77bc3abd9a39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35537
13423 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_alert_accum.3553713423
Directory /workspace/3.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/3.alert_handler_esc_intr_timeout.1801729658
Short name T75
Test name
Test status
Simulation time 692373382 ps
CPU time 41.34 seconds
Started Jul 24 05:33:37 PM PDT 24
Finished Jul 24 05:34:19 PM PDT 24
Peak memory 248576 kb
Host smart-47dac0d2-60ce-436b-8c82-109d465277c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18017
29658 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_intr_timeout.1801729658
Directory /workspace/3.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_lpg.920788942
Short name T323
Test name
Test status
Simulation time 155199357545 ps
CPU time 2685.42 seconds
Started Jul 24 05:33:40 PM PDT 24
Finished Jul 24 06:18:26 PM PDT 24
Peak memory 281400 kb
Host smart-99da68fe-20ea-42b3-8581-5c0463587123
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920788942 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg.920788942
Directory /workspace/3.alert_handler_lpg/latest

Test location /workspace/coverage/default/3.alert_handler_lpg_stub_clk.3618406491
Short name T566
Test name
Test status
Simulation time 234637143210 ps
CPU time 1502.45 seconds
Started Jul 24 05:33:35 PM PDT 24
Finished Jul 24 05:58:38 PM PDT 24
Peak memory 273268 kb
Host smart-ea9b379c-8ca5-4ba4-9149-2d7913531b6b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618406491 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg_stub_clk.3618406491
Directory /workspace/3.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/3.alert_handler_random_alerts.3238025185
Short name T582
Test name
Test status
Simulation time 3408365140 ps
CPU time 53.06 seconds
Started Jul 24 05:33:28 PM PDT 24
Finished Jul 24 05:34:21 PM PDT 24
Peak memory 256912 kb
Host smart-a4a1b07e-4ad2-45c2-bab4-5d6ee5aa4dc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32380
25185 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_alerts.3238025185
Directory /workspace/3.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/3.alert_handler_random_classes.3209947735
Short name T711
Test name
Test status
Simulation time 476825586 ps
CPU time 29.77 seconds
Started Jul 24 05:33:33 PM PDT 24
Finished Jul 24 05:34:03 PM PDT 24
Peak memory 255936 kb
Host smart-abe9b19e-f931-4d37-a1ca-a6ade2128ce6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32099
47735 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_classes.3209947735
Directory /workspace/3.alert_handler_random_classes/latest

Test location /workspace/coverage/default/3.alert_handler_sec_cm.441087069
Short name T11
Test name
Test status
Simulation time 619930755 ps
CPU time 27.79 seconds
Started Jul 24 05:33:40 PM PDT 24
Finished Jul 24 05:34:08 PM PDT 24
Peak memory 273908 kb
Host smart-33aed3bd-1e74-47de-ac2b-d09aa2a7473e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=441087069 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sec_cm.441087069
Directory /workspace/3.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/3.alert_handler_sig_int_fail.2058426670
Short name T634
Test name
Test status
Simulation time 58749684 ps
CPU time 7.02 seconds
Started Jul 24 05:33:41 PM PDT 24
Finished Jul 24 05:33:48 PM PDT 24
Peak memory 248644 kb
Host smart-41f4d347-4be3-4408-84d8-5c92f5aec074
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20584
26670 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sig_int_fail.2058426670
Directory /workspace/3.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/3.alert_handler_smoke.3482031818
Short name T366
Test name
Test status
Simulation time 603146630 ps
CPU time 35.56 seconds
Started Jul 24 05:33:33 PM PDT 24
Finished Jul 24 05:34:09 PM PDT 24
Peak memory 256220 kb
Host smart-67fa91d1-cbc4-4f0b-bee2-d04adc4d7fb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34820
31818 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_smoke.3482031818
Directory /workspace/3.alert_handler_smoke/latest

Test location /workspace/coverage/default/30.alert_handler_entropy.3789899686
Short name T546
Test name
Test status
Simulation time 11874520194 ps
CPU time 1168.23 seconds
Started Jul 24 05:34:34 PM PDT 24
Finished Jul 24 05:54:02 PM PDT 24
Peak memory 272616 kb
Host smart-0e541e59-76d4-420b-9323-9778e4623ebb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789899686 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_entropy.3789899686
Directory /workspace/30.alert_handler_entropy/latest

Test location /workspace/coverage/default/30.alert_handler_esc_alert_accum.2074570966
Short name T600
Test name
Test status
Simulation time 9298238474 ps
CPU time 132.82 seconds
Started Jul 24 05:34:35 PM PDT 24
Finished Jul 24 05:36:48 PM PDT 24
Peak memory 256408 kb
Host smart-882a4c7a-d0b0-48a4-9b5c-05fcc84f506c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20745
70966 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_alert_accum.2074570966
Directory /workspace/30.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/30.alert_handler_esc_intr_timeout.279042673
Short name T82
Test name
Test status
Simulation time 199637138 ps
CPU time 12.6 seconds
Started Jul 24 05:34:35 PM PDT 24
Finished Jul 24 05:34:47 PM PDT 24
Peak memory 247928 kb
Host smart-7f14bfa4-f5c3-4af3-9a83-0c710a460e4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27904
2673 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_intr_timeout.279042673
Directory /workspace/30.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_lpg_stub_clk.4202965211
Short name T478
Test name
Test status
Simulation time 88206435682 ps
CPU time 1539.62 seconds
Started Jul 24 05:34:35 PM PDT 24
Finished Jul 24 06:00:15 PM PDT 24
Peak memory 272652 kb
Host smart-a0e5fdf2-b403-4e43-bd5a-d3ebbfedd6a3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4202965211 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg_stub_clk.4202965211
Directory /workspace/30.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/30.alert_handler_ping_timeout.3915862858
Short name T276
Test name
Test status
Simulation time 97786337325 ps
CPU time 416.6 seconds
Started Jul 24 05:34:32 PM PDT 24
Finished Jul 24 05:41:29 PM PDT 24
Peak memory 255408 kb
Host smart-ff63b8cd-09f9-445f-b951-b77df40e6870
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915862858 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_ping_timeout.3915862858
Directory /workspace/30.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_random_alerts.3295468060
Short name T51
Test name
Test status
Simulation time 1098821356 ps
CPU time 28.07 seconds
Started Jul 24 05:34:40 PM PDT 24
Finished Jul 24 05:35:08 PM PDT 24
Peak memory 248584 kb
Host smart-6e0fc58b-989e-4594-8ad7-a487f82c1ce3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32954
68060 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_alerts.3295468060
Directory /workspace/30.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/30.alert_handler_random_classes.534744413
Short name T412
Test name
Test status
Simulation time 418671348 ps
CPU time 14.26 seconds
Started Jul 24 05:34:40 PM PDT 24
Finished Jul 24 05:34:54 PM PDT 24
Peak memory 253564 kb
Host smart-a5f67a72-7339-4c8d-8733-facdb4ee53bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53474
4413 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_classes.534744413
Directory /workspace/30.alert_handler_random_classes/latest

Test location /workspace/coverage/default/30.alert_handler_sig_int_fail.3785697233
Short name T459
Test name
Test status
Simulation time 800208538 ps
CPU time 50.25 seconds
Started Jul 24 05:34:36 PM PDT 24
Finished Jul 24 05:35:26 PM PDT 24
Peak memory 255964 kb
Host smart-4b1256ef-7786-4e70-b28c-e9494cd11b06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37856
97233 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_sig_int_fail.3785697233
Directory /workspace/30.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/30.alert_handler_smoke.2233005700
Short name T348
Test name
Test status
Simulation time 2808361484 ps
CPU time 48.19 seconds
Started Jul 24 05:34:33 PM PDT 24
Finished Jul 24 05:35:22 PM PDT 24
Peak memory 248804 kb
Host smart-0ca8deeb-23d5-4799-a88f-c88d05953c29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22330
05700 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_smoke.2233005700
Directory /workspace/30.alert_handler_smoke/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all.2461239799
Short name T607
Test name
Test status
Simulation time 192870163747 ps
CPU time 1241.25 seconds
Started Jul 24 05:34:36 PM PDT 24
Finished Jul 24 05:55:17 PM PDT 24
Peak memory 272760 kb
Host smart-a6046f34-762e-40a3-8cc9-ef56fc8a574b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461239799 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_ha
ndler_stress_all.2461239799
Directory /workspace/30.alert_handler_stress_all/latest

Test location /workspace/coverage/default/31.alert_handler_entropy.2284371841
Short name T56
Test name
Test status
Simulation time 27373389465 ps
CPU time 1908.03 seconds
Started Jul 24 05:34:42 PM PDT 24
Finished Jul 24 06:06:31 PM PDT 24
Peak memory 282148 kb
Host smart-5e3256d9-5db3-41be-84e5-db056bdb1c5f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284371841 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_entropy.2284371841
Directory /workspace/31.alert_handler_entropy/latest

Test location /workspace/coverage/default/31.alert_handler_esc_alert_accum.1813768366
Short name T411
Test name
Test status
Simulation time 41540037613 ps
CPU time 250.11 seconds
Started Jul 24 05:34:40 PM PDT 24
Finished Jul 24 05:38:50 PM PDT 24
Peak memory 256868 kb
Host smart-335d4bcb-b096-42dc-b3a4-3a02a65f7964
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18137
68366 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_alert_accum.1813768366
Directory /workspace/31.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/31.alert_handler_esc_intr_timeout.2742851712
Short name T643
Test name
Test status
Simulation time 209075782 ps
CPU time 8.53 seconds
Started Jul 24 05:34:39 PM PDT 24
Finished Jul 24 05:34:48 PM PDT 24
Peak memory 248100 kb
Host smart-99a58ae3-e57d-420a-83d7-3aeb4bd40f33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27428
51712 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_intr_timeout.2742851712
Directory /workspace/31.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_lpg.572544180
Short name T330
Test name
Test status
Simulation time 56589011675 ps
CPU time 3093.56 seconds
Started Jul 24 05:34:37 PM PDT 24
Finished Jul 24 06:26:11 PM PDT 24
Peak memory 288900 kb
Host smart-180950df-5a88-49fa-aec5-ae894102c91e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=572544180 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg.572544180
Directory /workspace/31.alert_handler_lpg/latest

Test location /workspace/coverage/default/31.alert_handler_lpg_stub_clk.1197225098
Short name T216
Test name
Test status
Simulation time 35090482341 ps
CPU time 2322.8 seconds
Started Jul 24 05:34:41 PM PDT 24
Finished Jul 24 06:13:24 PM PDT 24
Peak memory 288984 kb
Host smart-61ba85da-f302-4c52-80d8-4aff97c33b3d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197225098 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg_stub_clk.1197225098
Directory /workspace/31.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/31.alert_handler_random_alerts.1720959042
Short name T637
Test name
Test status
Simulation time 138735323 ps
CPU time 12.73 seconds
Started Jul 24 05:34:38 PM PDT 24
Finished Jul 24 05:34:51 PM PDT 24
Peak memory 256168 kb
Host smart-8fe6d629-30b6-43e0-8f8c-824259c8cb7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17209
59042 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_alerts.1720959042
Directory /workspace/31.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/31.alert_handler_random_classes.1290240186
Short name T456
Test name
Test status
Simulation time 121544876 ps
CPU time 8.9 seconds
Started Jul 24 05:34:41 PM PDT 24
Finished Jul 24 05:34:50 PM PDT 24
Peak memory 248164 kb
Host smart-d34e553a-5e6e-4850-95ab-dede93bbf4f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12902
40186 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_classes.1290240186
Directory /workspace/31.alert_handler_random_classes/latest

Test location /workspace/coverage/default/31.alert_handler_sig_int_fail.2800389490
Short name T100
Test name
Test status
Simulation time 1353901696 ps
CPU time 26.77 seconds
Started Jul 24 05:34:41 PM PDT 24
Finished Jul 24 05:35:08 PM PDT 24
Peak memory 249044 kb
Host smart-d6615fe9-7e4d-47de-8fce-afbb19e81b1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28003
89490 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_sig_int_fail.2800389490
Directory /workspace/31.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/31.alert_handler_smoke.2842859165
Short name T462
Test name
Test status
Simulation time 804703078 ps
CPU time 7.15 seconds
Started Jul 24 05:34:40 PM PDT 24
Finished Jul 24 05:34:48 PM PDT 24
Peak memory 248540 kb
Host smart-08f5e047-79f5-4d92-9f72-ec5be677aeb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28428
59165 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_smoke.2842859165
Directory /workspace/31.alert_handler_smoke/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all.788997036
Short name T243
Test name
Test status
Simulation time 5428746903 ps
CPU time 352.8 seconds
Started Jul 24 05:34:38 PM PDT 24
Finished Jul 24 05:40:31 PM PDT 24
Peak memory 256764 kb
Host smart-4369f61a-f940-4a6a-b466-d411d97ef520
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788997036 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_han
dler_stress_all.788997036
Directory /workspace/31.alert_handler_stress_all/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all_with_rand_reset.2591097539
Short name T640
Test name
Test status
Simulation time 28314010278 ps
CPU time 1593.22 seconds
Started Jul 24 05:34:39 PM PDT 24
Finished Jul 24 06:01:13 PM PDT 24
Peak memory 289700 kb
Host smart-d88e85cb-3c8a-455d-83b9-8d59b49c98d6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591097539 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 31.alert_handler_stress_all_with_rand_reset.2591097539
Directory /workspace/31.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.alert_handler_entropy.241031456
Short name T571
Test name
Test status
Simulation time 115723855889 ps
CPU time 872.97 seconds
Started Jul 24 05:34:45 PM PDT 24
Finished Jul 24 05:49:19 PM PDT 24
Peak memory 272800 kb
Host smart-06cc64af-fa97-471f-91b4-34f531dfc0e0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241031456 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_entropy.241031456
Directory /workspace/32.alert_handler_entropy/latest

Test location /workspace/coverage/default/32.alert_handler_esc_alert_accum.889572578
Short name T614
Test name
Test status
Simulation time 33221849714 ps
CPU time 159.61 seconds
Started Jul 24 05:34:45 PM PDT 24
Finished Jul 24 05:37:25 PM PDT 24
Peak memory 256884 kb
Host smart-def5059d-529a-4e99-8400-1ba4f0338354
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88957
2578 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_alert_accum.889572578
Directory /workspace/32.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/32.alert_handler_esc_intr_timeout.1092296034
Short name T678
Test name
Test status
Simulation time 67568200 ps
CPU time 5.29 seconds
Started Jul 24 05:34:44 PM PDT 24
Finished Jul 24 05:34:50 PM PDT 24
Peak memory 248180 kb
Host smart-4c9c5833-6354-4ff6-8dad-065fc3488aa8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10922
96034 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_intr_timeout.1092296034
Directory /workspace/32.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_lpg.2388603233
Short name T102
Test name
Test status
Simulation time 33198501211 ps
CPU time 1916.68 seconds
Started Jul 24 05:34:43 PM PDT 24
Finished Jul 24 06:06:40 PM PDT 24
Peak memory 288940 kb
Host smart-13548426-d65f-4008-917c-c7e4d83344ff
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388603233 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg.2388603233
Directory /workspace/32.alert_handler_lpg/latest

Test location /workspace/coverage/default/32.alert_handler_lpg_stub_clk.4243864356
Short name T400
Test name
Test status
Simulation time 48252612431 ps
CPU time 2988.38 seconds
Started Jul 24 05:34:44 PM PDT 24
Finished Jul 24 06:24:33 PM PDT 24
Peak memory 288652 kb
Host smart-e5cbde5a-7b34-439d-abf6-35c7a1654168
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243864356 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg_stub_clk.4243864356
Directory /workspace/32.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/32.alert_handler_ping_timeout.2665225507
Short name T38
Test name
Test status
Simulation time 15855229641 ps
CPU time 118.1 seconds
Started Jul 24 05:34:43 PM PDT 24
Finished Jul 24 05:36:41 PM PDT 24
Peak memory 248668 kb
Host smart-882b121b-8868-4a65-a328-808b0bd44ade
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665225507 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_ping_timeout.2665225507
Directory /workspace/32.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_random_alerts.2438535601
Short name T682
Test name
Test status
Simulation time 654146534 ps
CPU time 12.95 seconds
Started Jul 24 05:34:38 PM PDT 24
Finished Jul 24 05:34:51 PM PDT 24
Peak memory 248600 kb
Host smart-92e476f2-52f2-4b87-80ac-2a859aec6d40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24385
35601 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_alerts.2438535601
Directory /workspace/32.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/32.alert_handler_random_classes.2659463461
Short name T376
Test name
Test status
Simulation time 1240946525 ps
CPU time 39.03 seconds
Started Jul 24 05:34:39 PM PDT 24
Finished Jul 24 05:35:18 PM PDT 24
Peak memory 248312 kb
Host smart-23d1d1aa-0573-4e6c-939e-b6fbd1a80b42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26594
63461 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_classes.2659463461
Directory /workspace/32.alert_handler_random_classes/latest

Test location /workspace/coverage/default/32.alert_handler_sig_int_fail.1269304882
Short name T21
Test name
Test status
Simulation time 943222147 ps
CPU time 35.7 seconds
Started Jul 24 05:34:43 PM PDT 24
Finished Jul 24 05:35:19 PM PDT 24
Peak memory 248512 kb
Host smart-eef97307-f3f1-425b-b1d3-392942f20269
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12693
04882 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_sig_int_fail.1269304882
Directory /workspace/32.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/32.alert_handler_smoke.2146251817
Short name T555
Test name
Test status
Simulation time 524996795 ps
CPU time 32.74 seconds
Started Jul 24 05:34:40 PM PDT 24
Finished Jul 24 05:35:13 PM PDT 24
Peak memory 256708 kb
Host smart-f88fdd56-e9f0-4d8a-872c-b91793a67165
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21462
51817 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_smoke.2146251817
Directory /workspace/32.alert_handler_smoke/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all_with_rand_reset.3236748361
Short name T36
Test name
Test status
Simulation time 246752894322 ps
CPU time 3726.05 seconds
Started Jul 24 05:34:47 PM PDT 24
Finished Jul 24 06:36:54 PM PDT 24
Peak memory 304880 kb
Host smart-07c01076-4876-4460-aac8-b53d3489cfa5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236748361 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 32.alert_handler_stress_all_with_rand_reset.3236748361
Directory /workspace/32.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.alert_handler_entropy.2792528437
Short name T64
Test name
Test status
Simulation time 98615772878 ps
CPU time 1431.95 seconds
Started Jul 24 05:34:42 PM PDT 24
Finished Jul 24 05:58:34 PM PDT 24
Peak memory 272540 kb
Host smart-918a9209-d9f5-4cf7-ae76-7fde3d2bdfd9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792528437 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_entropy.2792528437
Directory /workspace/33.alert_handler_entropy/latest

Test location /workspace/coverage/default/33.alert_handler_esc_alert_accum.982297484
Short name T519
Test name
Test status
Simulation time 1102303612 ps
CPU time 61.79 seconds
Started Jul 24 05:34:44 PM PDT 24
Finished Jul 24 05:35:46 PM PDT 24
Peak memory 256476 kb
Host smart-e1b84e7d-7438-4205-9eb6-e4c4c001a429
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98229
7484 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_alert_accum.982297484
Directory /workspace/33.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/33.alert_handler_esc_intr_timeout.215114331
Short name T83
Test name
Test status
Simulation time 1841453446 ps
CPU time 29.21 seconds
Started Jul 24 05:34:45 PM PDT 24
Finished Jul 24 05:35:14 PM PDT 24
Peak memory 248196 kb
Host smart-cb7532b9-1bd7-489c-988d-99129d7f599e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21511
4331 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_intr_timeout.215114331
Directory /workspace/33.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_lpg.3564824279
Short name T321
Test name
Test status
Simulation time 9954352053 ps
CPU time 650.81 seconds
Started Jul 24 05:34:44 PM PDT 24
Finished Jul 24 05:45:35 PM PDT 24
Peak memory 273192 kb
Host smart-2edf1122-4f9e-406b-9df7-1e70e595b617
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564824279 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg.3564824279
Directory /workspace/33.alert_handler_lpg/latest

Test location /workspace/coverage/default/33.alert_handler_lpg_stub_clk.303190696
Short name T377
Test name
Test status
Simulation time 60073986060 ps
CPU time 1939.74 seconds
Started Jul 24 05:34:43 PM PDT 24
Finished Jul 24 06:07:03 PM PDT 24
Peak memory 273348 kb
Host smart-0b47a5b3-4fc3-4f8f-a63a-18c039a4f50b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303190696 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg_stub_clk.303190696
Directory /workspace/33.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/33.alert_handler_random_alerts.1658271239
Short name T681
Test name
Test status
Simulation time 406475616 ps
CPU time 36 seconds
Started Jul 24 05:34:44 PM PDT 24
Finished Jul 24 05:35:20 PM PDT 24
Peak memory 256144 kb
Host smart-51e8ce53-8a4b-428a-9cc1-d2c8fa24047c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16582
71239 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_alerts.1658271239
Directory /workspace/33.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/33.alert_handler_random_classes.1217116255
Short name T94
Test name
Test status
Simulation time 3662818641 ps
CPU time 52.38 seconds
Started Jul 24 05:34:45 PM PDT 24
Finished Jul 24 05:35:38 PM PDT 24
Peak memory 248592 kb
Host smart-1db95370-1641-44f5-a346-8262ee6b53a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12171
16255 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_classes.1217116255
Directory /workspace/33.alert_handler_random_classes/latest

Test location /workspace/coverage/default/33.alert_handler_sig_int_fail.3441792809
Short name T443
Test name
Test status
Simulation time 59763783 ps
CPU time 2.82 seconds
Started Jul 24 05:34:42 PM PDT 24
Finished Jul 24 05:34:45 PM PDT 24
Peak memory 240364 kb
Host smart-8283a481-c928-45c3-8765-c6459f017f23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34417
92809 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_sig_int_fail.3441792809
Directory /workspace/33.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/33.alert_handler_smoke.3793409003
Short name T565
Test name
Test status
Simulation time 16307970827 ps
CPU time 55.94 seconds
Started Jul 24 05:34:48 PM PDT 24
Finished Jul 24 05:35:44 PM PDT 24
Peak memory 256256 kb
Host smart-e0fcdeaf-bf58-4158-94dc-f4287c6f3079
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37934
09003 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_smoke.3793409003
Directory /workspace/33.alert_handler_smoke/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all.2211818704
Short name T469
Test name
Test status
Simulation time 105771632348 ps
CPU time 1353.66 seconds
Started Jul 24 05:34:50 PM PDT 24
Finished Jul 24 05:57:24 PM PDT 24
Peak memory 289280 kb
Host smart-2ca96c66-cce4-4fdf-ab1f-c36354fc71fe
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211818704 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_ha
ndler_stress_all.2211818704
Directory /workspace/33.alert_handler_stress_all/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all_with_rand_reset.4049896096
Short name T58
Test name
Test status
Simulation time 132029815167 ps
CPU time 4151.31 seconds
Started Jul 24 05:34:54 PM PDT 24
Finished Jul 24 06:44:06 PM PDT 24
Peak memory 321988 kb
Host smart-fc9abf52-b433-44dd-bf53-88f2c373cc3b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049896096 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 33.alert_handler_stress_all_with_rand_reset.4049896096
Directory /workspace/33.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.alert_handler_entropy.3669841280
Short name T615
Test name
Test status
Simulation time 25563066834 ps
CPU time 1810.47 seconds
Started Jul 24 05:34:48 PM PDT 24
Finished Jul 24 06:04:58 PM PDT 24
Peak memory 289560 kb
Host smart-6e3aa3e9-da65-4a42-8b65-66d01de1266a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3669841280 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_entropy.3669841280
Directory /workspace/34.alert_handler_entropy/latest

Test location /workspace/coverage/default/34.alert_handler_esc_alert_accum.2931678605
Short name T361
Test name
Test status
Simulation time 4382027498 ps
CPU time 127.36 seconds
Started Jul 24 05:34:59 PM PDT 24
Finished Jul 24 05:37:07 PM PDT 24
Peak memory 256376 kb
Host smart-44e48bf6-a9ed-4a8e-82b7-7dde243bb096
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29316
78605 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_alert_accum.2931678605
Directory /workspace/34.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/34.alert_handler_esc_intr_timeout.1747427777
Short name T368
Test name
Test status
Simulation time 353882324 ps
CPU time 28.5 seconds
Started Jul 24 05:34:51 PM PDT 24
Finished Jul 24 05:35:20 PM PDT 24
Peak memory 255944 kb
Host smart-080eac21-bd9c-403f-911a-9cedd8d46ea7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17474
27777 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_intr_timeout.1747427777
Directory /workspace/34.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_lpg_stub_clk.3650067596
Short name T533
Test name
Test status
Simulation time 179595446340 ps
CPU time 2615.91 seconds
Started Jul 24 05:34:53 PM PDT 24
Finished Jul 24 06:18:29 PM PDT 24
Peak memory 289408 kb
Host smart-4f36ee65-a8b8-4c31-b844-f0577b352f86
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650067596 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg_stub_clk.3650067596
Directory /workspace/34.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/34.alert_handler_ping_timeout.3056613039
Short name T563
Test name
Test status
Simulation time 59221264033 ps
CPU time 678.45 seconds
Started Jul 24 05:34:47 PM PDT 24
Finished Jul 24 05:46:05 PM PDT 24
Peak memory 248660 kb
Host smart-87985a36-ee3b-4b81-9be4-10ee0942df18
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056613039 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_ping_timeout.3056613039
Directory /workspace/34.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_random_alerts.4153165372
Short name T704
Test name
Test status
Simulation time 1655042845 ps
CPU time 28.51 seconds
Started Jul 24 05:34:47 PM PDT 24
Finished Jul 24 05:35:16 PM PDT 24
Peak memory 255996 kb
Host smart-e9be77be-17e8-42a5-9423-9aa56b5ceafc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41531
65372 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_alerts.4153165372
Directory /workspace/34.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/34.alert_handler_random_classes.1655977028
Short name T573
Test name
Test status
Simulation time 816960124 ps
CPU time 21.77 seconds
Started Jul 24 05:34:50 PM PDT 24
Finished Jul 24 05:35:12 PM PDT 24
Peak memory 248120 kb
Host smart-d364b092-7c37-4351-9a1a-427b1c06168c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16559
77028 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_classes.1655977028
Directory /workspace/34.alert_handler_random_classes/latest

Test location /workspace/coverage/default/34.alert_handler_sig_int_fail.765848228
Short name T480
Test name
Test status
Simulation time 212222372 ps
CPU time 25.68 seconds
Started Jul 24 05:34:48 PM PDT 24
Finished Jul 24 05:35:14 PM PDT 24
Peak memory 248604 kb
Host smart-35082c9c-4315-4233-a1b0-13371c496f11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76584
8228 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_sig_int_fail.765848228
Directory /workspace/34.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/34.alert_handler_smoke.1358981409
Short name T676
Test name
Test status
Simulation time 1391775309 ps
CPU time 70.37 seconds
Started Jul 24 05:34:50 PM PDT 24
Finished Jul 24 05:36:01 PM PDT 24
Peak memory 256688 kb
Host smart-e33a3c2b-8066-4a56-beef-a2955bcaef51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13589
81409 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_smoke.1358981409
Directory /workspace/34.alert_handler_smoke/latest

Test location /workspace/coverage/default/35.alert_handler_entropy.1526439802
Short name T710
Test name
Test status
Simulation time 20658696218 ps
CPU time 1230.7 seconds
Started Jul 24 05:34:55 PM PDT 24
Finished Jul 24 05:55:26 PM PDT 24
Peak memory 273276 kb
Host smart-212b7db2-060e-47f8-8d8e-4c62f6207a9d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526439802 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_entropy.1526439802
Directory /workspace/35.alert_handler_entropy/latest

Test location /workspace/coverage/default/35.alert_handler_esc_alert_accum.3681356393
Short name T228
Test name
Test status
Simulation time 4063160440 ps
CPU time 82.63 seconds
Started Jul 24 05:35:01 PM PDT 24
Finished Jul 24 05:36:24 PM PDT 24
Peak memory 249624 kb
Host smart-e36b11c7-1c1a-4f03-8058-3ed401c5b539
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36813
56393 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_alert_accum.3681356393
Directory /workspace/35.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/35.alert_handler_esc_intr_timeout.3277003512
Short name T22
Test name
Test status
Simulation time 163855695 ps
CPU time 3.95 seconds
Started Jul 24 05:34:50 PM PDT 24
Finished Jul 24 05:34:54 PM PDT 24
Peak memory 239916 kb
Host smart-abda6e58-56d9-43b1-8e21-a9133473eb80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32770
03512 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_intr_timeout.3277003512
Directory /workspace/35.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_lpg.625229896
Short name T113
Test name
Test status
Simulation time 69638483384 ps
CPU time 1418.27 seconds
Started Jul 24 05:34:57 PM PDT 24
Finished Jul 24 05:58:36 PM PDT 24
Peak memory 288976 kb
Host smart-c8f4108d-b558-4fd9-a722-03e65819247a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625229896 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg.625229896
Directory /workspace/35.alert_handler_lpg/latest

Test location /workspace/coverage/default/35.alert_handler_lpg_stub_clk.235050805
Short name T97
Test name
Test status
Simulation time 76440004224 ps
CPU time 1100.5 seconds
Started Jul 24 05:35:00 PM PDT 24
Finished Jul 24 05:53:21 PM PDT 24
Peak memory 266060 kb
Host smart-d0c42401-a87a-4e07-aec5-629b938ea7db
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=235050805 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg_stub_clk.235050805
Directory /workspace/35.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/35.alert_handler_ping_timeout.3454356594
Short name T262
Test name
Test status
Simulation time 37012348092 ps
CPU time 293.18 seconds
Started Jul 24 05:34:56 PM PDT 24
Finished Jul 24 05:39:50 PM PDT 24
Peak memory 253864 kb
Host smart-c5930137-0908-410b-8966-51965fe463fb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3454356594 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_ping_timeout.3454356594
Directory /workspace/35.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_random_alerts.232447436
Short name T658
Test name
Test status
Simulation time 243696005 ps
CPU time 8.04 seconds
Started Jul 24 05:34:51 PM PDT 24
Finished Jul 24 05:34:59 PM PDT 24
Peak memory 251548 kb
Host smart-11cf51eb-8e5e-46c0-a224-2197b279297c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23244
7436 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_alerts.232447436
Directory /workspace/35.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/35.alert_handler_random_classes.125472252
Short name T521
Test name
Test status
Simulation time 454408739 ps
CPU time 22.72 seconds
Started Jul 24 05:34:50 PM PDT 24
Finished Jul 24 05:35:13 PM PDT 24
Peak memory 255900 kb
Host smart-30d4e06d-c969-4be0-a3b3-b9718a891e17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12547
2252 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_classes.125472252
Directory /workspace/35.alert_handler_random_classes/latest

Test location /workspace/coverage/default/35.alert_handler_sig_int_fail.812225815
Short name T702
Test name
Test status
Simulation time 1772396183 ps
CPU time 29.98 seconds
Started Jul 24 05:34:49 PM PDT 24
Finished Jul 24 05:35:19 PM PDT 24
Peak memory 248180 kb
Host smart-15d6ce3e-7d70-440f-8985-06ab31579761
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81222
5815 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_sig_int_fail.812225815
Directory /workspace/35.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/35.alert_handler_smoke.3951940905
Short name T599
Test name
Test status
Simulation time 1595698979 ps
CPU time 42.4 seconds
Started Jul 24 05:34:50 PM PDT 24
Finished Jul 24 05:35:33 PM PDT 24
Peak memory 256796 kb
Host smart-72cc9e51-7d50-449c-984d-6a3af9f1ccb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39519
40905 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_smoke.3951940905
Directory /workspace/35.alert_handler_smoke/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all.715699140
Short name T390
Test name
Test status
Simulation time 77955271807 ps
CPU time 2329.08 seconds
Started Jul 24 05:34:59 PM PDT 24
Finished Jul 24 06:13:49 PM PDT 24
Peak memory 286276 kb
Host smart-d7308fff-4bd8-462e-8d1e-ef5fb201d6ff
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715699140 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_han
dler_stress_all.715699140
Directory /workspace/35.alert_handler_stress_all/latest

Test location /workspace/coverage/default/36.alert_handler_entropy.2342696714
Short name T611
Test name
Test status
Simulation time 7697335581 ps
CPU time 727.19 seconds
Started Jul 24 05:34:59 PM PDT 24
Finished Jul 24 05:47:06 PM PDT 24
Peak memory 272964 kb
Host smart-d6c5e437-cb1f-4947-b6fa-7d2863958e48
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2342696714 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_entropy.2342696714
Directory /workspace/36.alert_handler_entropy/latest

Test location /workspace/coverage/default/36.alert_handler_esc_alert_accum.2539596217
Short name T356
Test name
Test status
Simulation time 3497254807 ps
CPU time 222.47 seconds
Started Jul 24 05:34:57 PM PDT 24
Finished Jul 24 05:38:40 PM PDT 24
Peak memory 256796 kb
Host smart-57ffac9e-60b4-4791-a33f-850442b80f74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25395
96217 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_alert_accum.2539596217
Directory /workspace/36.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/36.alert_handler_esc_intr_timeout.2286487892
Short name T591
Test name
Test status
Simulation time 6255889319 ps
CPU time 24.64 seconds
Started Jul 24 05:35:03 PM PDT 24
Finished Jul 24 05:35:28 PM PDT 24
Peak memory 256824 kb
Host smart-2370d05c-0c54-45f5-9011-a7137fbeeaab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22864
87892 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_intr_timeout.2286487892
Directory /workspace/36.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_lpg_stub_clk.4092873646
Short name T209
Test name
Test status
Simulation time 97816256077 ps
CPU time 1412.83 seconds
Started Jul 24 05:34:57 PM PDT 24
Finished Jul 24 05:58:30 PM PDT 24
Peak memory 288032 kb
Host smart-74912fb6-e2e2-4b01-8aa7-d9e77a1ddcd6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092873646 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg_stub_clk.4092873646
Directory /workspace/36.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/36.alert_handler_ping_timeout.1442058107
Short name T660
Test name
Test status
Simulation time 47645373973 ps
CPU time 305.16 seconds
Started Jul 24 05:34:59 PM PDT 24
Finished Jul 24 05:40:04 PM PDT 24
Peak memory 247544 kb
Host smart-aa151683-0675-4d64-8c8a-df70955529e4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1442058107 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_ping_timeout.1442058107
Directory /workspace/36.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_random_alerts.1487372176
Short name T544
Test name
Test status
Simulation time 2961746225 ps
CPU time 46 seconds
Started Jul 24 05:34:57 PM PDT 24
Finished Jul 24 05:35:43 PM PDT 24
Peak memory 248700 kb
Host smart-85f8ce2d-1fd5-4549-bb51-e0eb5fc4a8be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14873
72176 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_alerts.1487372176
Directory /workspace/36.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/36.alert_handler_random_classes.1841872572
Short name T695
Test name
Test status
Simulation time 338473164 ps
CPU time 5.71 seconds
Started Jul 24 05:34:56 PM PDT 24
Finished Jul 24 05:35:02 PM PDT 24
Peak memory 239504 kb
Host smart-167acdd1-90a4-4a57-bc23-5ee06e9a8a24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18418
72572 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_classes.1841872572
Directory /workspace/36.alert_handler_random_classes/latest

Test location /workspace/coverage/default/36.alert_handler_sig_int_fail.1571040908
Short name T35
Test name
Test status
Simulation time 92152452 ps
CPU time 11.65 seconds
Started Jul 24 05:34:57 PM PDT 24
Finished Jul 24 05:35:09 PM PDT 24
Peak memory 248756 kb
Host smart-547623ee-bc9b-43f9-b43d-0553741479e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15710
40908 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_sig_int_fail.1571040908
Directory /workspace/36.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/36.alert_handler_smoke.3396616901
Short name T405
Test name
Test status
Simulation time 1120137660 ps
CPU time 39.87 seconds
Started Jul 24 05:34:58 PM PDT 24
Finished Jul 24 05:35:38 PM PDT 24
Peak memory 256744 kb
Host smart-5b73701b-57e1-41e3-b5f7-4f9dc15996ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33966
16901 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_smoke.3396616901
Directory /workspace/36.alert_handler_smoke/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all.1936299146
Short name T666
Test name
Test status
Simulation time 3975382689 ps
CPU time 99.07 seconds
Started Jul 24 05:34:56 PM PDT 24
Finished Jul 24 05:36:36 PM PDT 24
Peak memory 256844 kb
Host smart-72bb7dde-e266-4570-b835-b89f0cf43890
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936299146 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_ha
ndler_stress_all.1936299146
Directory /workspace/36.alert_handler_stress_all/latest

Test location /workspace/coverage/default/37.alert_handler_entropy.223095024
Short name T104
Test name
Test status
Simulation time 30721638074 ps
CPU time 883.12 seconds
Started Jul 24 05:34:57 PM PDT 24
Finished Jul 24 05:49:40 PM PDT 24
Peak memory 273052 kb
Host smart-ceb01e9f-a909-4eea-817a-f6f125d78a99
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223095024 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_entropy.223095024
Directory /workspace/37.alert_handler_entropy/latest

Test location /workspace/coverage/default/37.alert_handler_esc_alert_accum.666613271
Short name T399
Test name
Test status
Simulation time 932459844 ps
CPU time 95.01 seconds
Started Jul 24 05:35:05 PM PDT 24
Finished Jul 24 05:36:40 PM PDT 24
Peak memory 256368 kb
Host smart-ecef212d-e831-4626-9a67-7be59166d8fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66661
3271 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_alert_accum.666613271
Directory /workspace/37.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/37.alert_handler_esc_intr_timeout.1805861012
Short name T501
Test name
Test status
Simulation time 830359248 ps
CPU time 64.47 seconds
Started Jul 24 05:34:59 PM PDT 24
Finished Jul 24 05:36:03 PM PDT 24
Peak memory 248504 kb
Host smart-3a03022d-2a06-4dc4-9dcc-8c7b2b9e1196
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18058
61012 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_intr_timeout.1805861012
Directory /workspace/37.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_lpg_stub_clk.4024741490
Short name T534
Test name
Test status
Simulation time 151288165761 ps
CPU time 2265 seconds
Started Jul 24 05:34:58 PM PDT 24
Finished Jul 24 06:12:44 PM PDT 24
Peak memory 272872 kb
Host smart-1b2a0371-379b-4db8-a075-415577993ac1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024741490 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg_stub_clk.4024741490
Directory /workspace/37.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/37.alert_handler_random_alerts.1694806792
Short name T499
Test name
Test status
Simulation time 280646523 ps
CPU time 25.48 seconds
Started Jul 24 05:34:57 PM PDT 24
Finished Jul 24 05:35:22 PM PDT 24
Peak memory 248564 kb
Host smart-836648cf-426e-4ebf-85df-ba4449590d9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16948
06792 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_alerts.1694806792
Directory /workspace/37.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/37.alert_handler_random_classes.853858461
Short name T371
Test name
Test status
Simulation time 203145999 ps
CPU time 7.5 seconds
Started Jul 24 05:35:00 PM PDT 24
Finished Jul 24 05:35:08 PM PDT 24
Peak memory 248592 kb
Host smart-98fdf7bb-259e-4a3f-8466-98a68d774e19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85385
8461 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_classes.853858461
Directory /workspace/37.alert_handler_random_classes/latest

Test location /workspace/coverage/default/37.alert_handler_sig_int_fail.3219491070
Short name T24
Test name
Test status
Simulation time 2036933941 ps
CPU time 43.14 seconds
Started Jul 24 05:34:56 PM PDT 24
Finished Jul 24 05:35:40 PM PDT 24
Peak memory 248556 kb
Host smart-beb9944e-2db7-4cf1-8004-da084b2c8159
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32194
91070 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_sig_int_fail.3219491070
Directory /workspace/37.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/37.alert_handler_smoke.1191826612
Short name T706
Test name
Test status
Simulation time 287079975 ps
CPU time 15.58 seconds
Started Jul 24 05:35:04 PM PDT 24
Finished Jul 24 05:35:19 PM PDT 24
Peak memory 256700 kb
Host smart-1f495420-d7e3-40ae-a603-adab5d29f36e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11918
26612 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_smoke.1191826612
Directory /workspace/37.alert_handler_smoke/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all.2229564233
Short name T535
Test name
Test status
Simulation time 74884526970 ps
CPU time 1878.36 seconds
Started Jul 24 05:35:04 PM PDT 24
Finished Jul 24 06:06:23 PM PDT 24
Peak memory 281340 kb
Host smart-ec16fc3a-85b8-4665-9919-53c07a9c7640
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229564233 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_ha
ndler_stress_all.2229564233
Directory /workspace/37.alert_handler_stress_all/latest

Test location /workspace/coverage/default/38.alert_handler_entropy.3103520332
Short name T353
Test name
Test status
Simulation time 21059015634 ps
CPU time 797.41 seconds
Started Jul 24 05:35:04 PM PDT 24
Finished Jul 24 05:48:22 PM PDT 24
Peak memory 272884 kb
Host smart-119247a7-48d8-4560-b9c1-9c9ae765f1e1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103520332 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_entropy.3103520332
Directory /workspace/38.alert_handler_entropy/latest

Test location /workspace/coverage/default/38.alert_handler_esc_alert_accum.1302736447
Short name T655
Test name
Test status
Simulation time 1055261557 ps
CPU time 80.94 seconds
Started Jul 24 05:35:00 PM PDT 24
Finished Jul 24 05:36:21 PM PDT 24
Peak memory 256348 kb
Host smart-6c74add8-b400-4f13-9f75-be1ed2efb780
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13027
36447 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_alert_accum.1302736447
Directory /workspace/38.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/38.alert_handler_esc_intr_timeout.946549935
Short name T89
Test name
Test status
Simulation time 1492754955 ps
CPU time 28.2 seconds
Started Jul 24 05:35:00 PM PDT 24
Finished Jul 24 05:35:29 PM PDT 24
Peak memory 248808 kb
Host smart-b014eab0-27f8-49e3-a4b7-59ae8e7f692a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94654
9935 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_intr_timeout.946549935
Directory /workspace/38.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_lpg.2518961182
Short name T461
Test name
Test status
Simulation time 72070047827 ps
CPU time 1110.99 seconds
Started Jul 24 05:35:04 PM PDT 24
Finished Jul 24 05:53:35 PM PDT 24
Peak memory 272988 kb
Host smart-4867d1f2-7d26-47bd-a890-91278cc9b89f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2518961182 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg.2518961182
Directory /workspace/38.alert_handler_lpg/latest

Test location /workspace/coverage/default/38.alert_handler_lpg_stub_clk.565325831
Short name T696
Test name
Test status
Simulation time 251781781340 ps
CPU time 2542.69 seconds
Started Jul 24 05:34:59 PM PDT 24
Finished Jul 24 06:17:22 PM PDT 24
Peak memory 289480 kb
Host smart-c1593db5-ea14-41f5-8417-d45b0c720a24
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565325831 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg_stub_clk.565325831
Directory /workspace/38.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/38.alert_handler_ping_timeout.3738991407
Short name T608
Test name
Test status
Simulation time 43272643640 ps
CPU time 438.78 seconds
Started Jul 24 05:35:00 PM PDT 24
Finished Jul 24 05:42:19 PM PDT 24
Peak memory 248396 kb
Host smart-8fe3d922-8f19-4ca7-b011-13702b4651d3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738991407 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_ping_timeout.3738991407
Directory /workspace/38.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_random_alerts.3490231355
Short name T373
Test name
Test status
Simulation time 517524732 ps
CPU time 11.31 seconds
Started Jul 24 05:35:04 PM PDT 24
Finished Jul 24 05:35:15 PM PDT 24
Peak memory 253732 kb
Host smart-3f83d343-972d-4bbf-8e1c-31d9d60e1b71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34902
31355 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_alerts.3490231355
Directory /workspace/38.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/38.alert_handler_random_classes.3497062102
Short name T363
Test name
Test status
Simulation time 35118968 ps
CPU time 3.18 seconds
Started Jul 24 05:34:59 PM PDT 24
Finished Jul 24 05:35:02 PM PDT 24
Peak memory 248684 kb
Host smart-8aeffc16-21f5-45d6-ae20-04a89899f55b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34970
62102 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_classes.3497062102
Directory /workspace/38.alert_handler_random_classes/latest

Test location /workspace/coverage/default/38.alert_handler_sig_int_fail.1037007962
Short name T78
Test name
Test status
Simulation time 4280121200 ps
CPU time 31.42 seconds
Started Jul 24 05:35:04 PM PDT 24
Finished Jul 24 05:35:36 PM PDT 24
Peak memory 255988 kb
Host smart-563d479d-09c8-4144-a062-e5d580bde0c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10370
07962 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_sig_int_fail.1037007962
Directory /workspace/38.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/38.alert_handler_smoke.1292265669
Short name T450
Test name
Test status
Simulation time 777067251 ps
CPU time 39.05 seconds
Started Jul 24 05:34:58 PM PDT 24
Finished Jul 24 05:35:37 PM PDT 24
Peak memory 256696 kb
Host smart-69798bda-e895-4461-a9e1-2cb54886f7f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12922
65669 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_smoke.1292265669
Directory /workspace/38.alert_handler_smoke/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all.4100994374
Short name T688
Test name
Test status
Simulation time 57261734386 ps
CPU time 3389.45 seconds
Started Jul 24 05:35:00 PM PDT 24
Finished Jul 24 06:31:30 PM PDT 24
Peak memory 289268 kb
Host smart-f9218846-dc7a-4d73-ad1b-abaef7b2364f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100994374 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_ha
ndler_stress_all.4100994374
Directory /workspace/38.alert_handler_stress_all/latest

Test location /workspace/coverage/default/39.alert_handler_entropy.1078983516
Short name T504
Test name
Test status
Simulation time 57963248325 ps
CPU time 1403.55 seconds
Started Jul 24 05:35:00 PM PDT 24
Finished Jul 24 05:58:24 PM PDT 24
Peak memory 285628 kb
Host smart-01289530-6079-4996-bb73-e808f670ab2a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078983516 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_entropy.1078983516
Directory /workspace/39.alert_handler_entropy/latest

Test location /workspace/coverage/default/39.alert_handler_esc_alert_accum.1324905313
Short name T420
Test name
Test status
Simulation time 50544074 ps
CPU time 4.06 seconds
Started Jul 24 05:35:01 PM PDT 24
Finished Jul 24 05:35:05 PM PDT 24
Peak memory 239904 kb
Host smart-780f2994-6c5b-40b4-b959-2aeaacd7b616
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13249
05313 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_alert_accum.1324905313
Directory /workspace/39.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/39.alert_handler_esc_intr_timeout.329794871
Short name T448
Test name
Test status
Simulation time 2041407284 ps
CPU time 29.92 seconds
Started Jul 24 05:35:03 PM PDT 24
Finished Jul 24 05:35:33 PM PDT 24
Peak memory 256376 kb
Host smart-0fe3b88b-aec2-47e7-8dae-3bce24eaca58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32979
4871 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_intr_timeout.329794871
Directory /workspace/39.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_lpg.4245453757
Short name T319
Test name
Test status
Simulation time 523052414057 ps
CPU time 2485.9 seconds
Started Jul 24 05:35:07 PM PDT 24
Finished Jul 24 06:16:33 PM PDT 24
Peak memory 273272 kb
Host smart-2287e638-2c8b-4396-b2bb-f184c6f98c83
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245453757 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg.4245453757
Directory /workspace/39.alert_handler_lpg/latest

Test location /workspace/coverage/default/39.alert_handler_lpg_stub_clk.289650415
Short name T119
Test name
Test status
Simulation time 43375253544 ps
CPU time 2536.37 seconds
Started Jul 24 05:35:01 PM PDT 24
Finished Jul 24 06:17:18 PM PDT 24
Peak memory 281520 kb
Host smart-13d50e83-5993-4f7c-85c1-d1bbe7132774
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289650415 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg_stub_clk.289650415
Directory /workspace/39.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/39.alert_handler_ping_timeout.242106625
Short name T268
Test name
Test status
Simulation time 42259929585 ps
CPU time 412.3 seconds
Started Jul 24 05:35:04 PM PDT 24
Finished Jul 24 05:41:56 PM PDT 24
Peak memory 248672 kb
Host smart-53e37d1b-e098-486e-bca7-37c92d5c5042
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=242106625 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_ping_timeout.242106625
Directory /workspace/39.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_random_alerts.2406881175
Short name T90
Test name
Test status
Simulation time 4223284178 ps
CPU time 62.01 seconds
Started Jul 24 05:35:04 PM PDT 24
Finished Jul 24 05:36:06 PM PDT 24
Peak memory 256716 kb
Host smart-231407f7-8e12-4a4b-b9b0-f70c90658ee5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24068
81175 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_alerts.2406881175
Directory /workspace/39.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/39.alert_handler_random_classes.2432036670
Short name T297
Test name
Test status
Simulation time 707295907 ps
CPU time 29.01 seconds
Started Jul 24 05:35:02 PM PDT 24
Finished Jul 24 05:35:31 PM PDT 24
Peak memory 248040 kb
Host smart-a8f3212d-3052-4214-a253-5cca6459f0f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24320
36670 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_classes.2432036670
Directory /workspace/39.alert_handler_random_classes/latest

Test location /workspace/coverage/default/39.alert_handler_smoke.472724522
Short name T494
Test name
Test status
Simulation time 513369144 ps
CPU time 19.77 seconds
Started Jul 24 05:35:04 PM PDT 24
Finished Jul 24 05:35:24 PM PDT 24
Peak memory 256452 kb
Host smart-8818bfb9-f082-4299-8104-bc4d9b92576a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47272
4522 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_smoke.472724522
Directory /workspace/39.alert_handler_smoke/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all.4133078339
Short name T648
Test name
Test status
Simulation time 31392452262 ps
CPU time 2063.26 seconds
Started Jul 24 05:35:02 PM PDT 24
Finished Jul 24 06:09:26 PM PDT 24
Peak memory 287860 kb
Host smart-6587333e-9439-4a13-adc2-7645c186fbc5
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133078339 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_ha
ndler_stress_all.4133078339
Directory /workspace/39.alert_handler_stress_all/latest

Test location /workspace/coverage/default/4.alert_handler_alert_accum_saturation.2307899997
Short name T206
Test name
Test status
Simulation time 35308796 ps
CPU time 2.33 seconds
Started Jul 24 05:33:39 PM PDT 24
Finished Jul 24 05:33:41 PM PDT 24
Peak memory 248852 kb
Host smart-88025571-5793-4f1a-911e-3d88e8277993
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2307899997 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_alert_accum_saturation.2307899997
Directory /workspace/4.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/4.alert_handler_entropy.2020012380
Short name T484
Test name
Test status
Simulation time 197323831371 ps
CPU time 1802.75 seconds
Started Jul 24 05:33:52 PM PDT 24
Finished Jul 24 06:03:55 PM PDT 24
Peak memory 272592 kb
Host smart-88f0fa0b-20db-42cf-8db4-bf308f8fb528
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020012380 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy.2020012380
Directory /workspace/4.alert_handler_entropy/latest

Test location /workspace/coverage/default/4.alert_handler_entropy_stress.3295226771
Short name T645
Test name
Test status
Simulation time 951083521 ps
CPU time 39.81 seconds
Started Jul 24 05:33:46 PM PDT 24
Finished Jul 24 05:34:26 PM PDT 24
Peak memory 248380 kb
Host smart-4fed957d-757f-417c-ac95-7bf3d31dcbc4
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3295226771 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy_stress.3295226771
Directory /workspace/4.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/4.alert_handler_esc_alert_accum.2415887611
Short name T230
Test name
Test status
Simulation time 15566359804 ps
CPU time 136.99 seconds
Started Jul 24 05:33:40 PM PDT 24
Finished Jul 24 05:35:57 PM PDT 24
Peak memory 248928 kb
Host smart-4ffb4f67-0a4c-453f-8b1c-7094ef1ba168
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24158
87611 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_alert_accum.2415887611
Directory /workspace/4.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/4.alert_handler_esc_intr_timeout.496999834
Short name T394
Test name
Test status
Simulation time 241682178 ps
CPU time 14.26 seconds
Started Jul 24 05:33:38 PM PDT 24
Finished Jul 24 05:33:52 PM PDT 24
Peak memory 248176 kb
Host smart-309d6802-02c0-4b0b-bb3b-f93dff8ece77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49699
9834 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_intr_timeout.496999834
Directory /workspace/4.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_lpg_stub_clk.4010050304
Short name T649
Test name
Test status
Simulation time 4998633419 ps
CPU time 710.2 seconds
Started Jul 24 05:33:40 PM PDT 24
Finished Jul 24 05:45:30 PM PDT 24
Peak memory 273092 kb
Host smart-40a68fa3-bea9-40b2-bc7e-e15033ff3326
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010050304 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg_stub_clk.4010050304
Directory /workspace/4.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/4.alert_handler_ping_timeout.3879429613
Short name T9
Test name
Test status
Simulation time 7029529733 ps
CPU time 286.43 seconds
Started Jul 24 05:33:42 PM PDT 24
Finished Jul 24 05:38:29 PM PDT 24
Peak memory 255100 kb
Host smart-00790dcf-207f-4847-b3a2-9b68b31a467a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879429613 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_ping_timeout.3879429613
Directory /workspace/4.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_random_alerts.29703985
Short name T291
Test name
Test status
Simulation time 1252783968 ps
CPU time 36.47 seconds
Started Jul 24 05:33:42 PM PDT 24
Finished Jul 24 05:34:19 PM PDT 24
Peak memory 248640 kb
Host smart-5ccaea08-d39d-4304-a3ca-aa9a42e6bc07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29703
985 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_alerts.29703985
Directory /workspace/4.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/4.alert_handler_random_classes.1747022489
Short name T106
Test name
Test status
Simulation time 2967052069 ps
CPU time 49.22 seconds
Started Jul 24 05:33:41 PM PDT 24
Finished Jul 24 05:34:30 PM PDT 24
Peak memory 248528 kb
Host smart-b047e63f-175c-4908-ad0e-f8cb140faaf7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17470
22489 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_classes.1747022489
Directory /workspace/4.alert_handler_random_classes/latest

Test location /workspace/coverage/default/4.alert_handler_sec_cm.703420135
Short name T33
Test name
Test status
Simulation time 317605833 ps
CPU time 11.46 seconds
Started Jul 24 05:33:43 PM PDT 24
Finished Jul 24 05:33:55 PM PDT 24
Peak memory 271552 kb
Host smart-6f7051d9-b7de-47cf-a225-c31b721356f1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=703420135 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sec_cm.703420135
Directory /workspace/4.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/4.alert_handler_sig_int_fail.3608797314
Short name T48
Test name
Test status
Simulation time 1716838411 ps
CPU time 65.22 seconds
Started Jul 24 05:33:33 PM PDT 24
Finished Jul 24 05:34:39 PM PDT 24
Peak memory 249456 kb
Host smart-96f3bcf0-86e4-47c7-a042-f82c90f8270b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36087
97314 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sig_int_fail.3608797314
Directory /workspace/4.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/4.alert_handler_smoke.1137230318
Short name T385
Test name
Test status
Simulation time 560606000 ps
CPU time 16.13 seconds
Started Jul 24 05:33:41 PM PDT 24
Finished Jul 24 05:33:57 PM PDT 24
Peak memory 255200 kb
Host smart-af5094dd-a3ef-40fc-a21a-af7d3ba3a221
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11372
30318 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_smoke.1137230318
Directory /workspace/4.alert_handler_smoke/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all.3780511805
Short name T63
Test name
Test status
Simulation time 40343808682 ps
CPU time 2396.21 seconds
Started Jul 24 05:33:35 PM PDT 24
Finished Jul 24 06:13:31 PM PDT 24
Peak memory 289300 kb
Host smart-41fae3c3-0666-4739-81a2-71900f377dc3
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780511805 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_han
dler_stress_all.3780511805
Directory /workspace/4.alert_handler_stress_all/latest

Test location /workspace/coverage/default/40.alert_handler_entropy.2456205421
Short name T4
Test name
Test status
Simulation time 253383755462 ps
CPU time 2342.72 seconds
Started Jul 24 05:35:08 PM PDT 24
Finished Jul 24 06:14:11 PM PDT 24
Peak memory 273188 kb
Host smart-b58917ce-bd03-4c88-a366-569d3966c0f5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2456205421 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_entropy.2456205421
Directory /workspace/40.alert_handler_entropy/latest

Test location /workspace/coverage/default/40.alert_handler_esc_alert_accum.4089258458
Short name T598
Test name
Test status
Simulation time 9361500811 ps
CPU time 152.74 seconds
Started Jul 24 05:35:03 PM PDT 24
Finished Jul 24 05:37:36 PM PDT 24
Peak memory 256596 kb
Host smart-72f178d7-8d0d-4a9c-b56f-5ffa8c9cc369
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40892
58458 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_alert_accum.4089258458
Directory /workspace/40.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/40.alert_handler_esc_intr_timeout.3852542186
Short name T474
Test name
Test status
Simulation time 1623861867 ps
CPU time 25.77 seconds
Started Jul 24 05:35:01 PM PDT 24
Finished Jul 24 05:35:27 PM PDT 24
Peak memory 256820 kb
Host smart-23bb808b-336e-491a-9917-c825d3c39609
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38525
42186 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_intr_timeout.3852542186
Directory /workspace/40.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_lpg.1090882048
Short name T686
Test name
Test status
Simulation time 157415605708 ps
CPU time 1675.43 seconds
Started Jul 24 05:35:08 PM PDT 24
Finished Jul 24 06:03:04 PM PDT 24
Peak memory 273048 kb
Host smart-d2910afe-db65-40ba-9f96-ad68dad0f069
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090882048 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg.1090882048
Directory /workspace/40.alert_handler_lpg/latest

Test location /workspace/coverage/default/40.alert_handler_lpg_stub_clk.568595184
Short name T560
Test name
Test status
Simulation time 346819075001 ps
CPU time 2685.92 seconds
Started Jul 24 05:35:10 PM PDT 24
Finished Jul 24 06:19:56 PM PDT 24
Peak memory 289560 kb
Host smart-727a1d79-0067-40f8-b64a-441f9a042865
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568595184 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg_stub_clk.568595184
Directory /workspace/40.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/40.alert_handler_ping_timeout.2895308290
Short name T597
Test name
Test status
Simulation time 10562420089 ps
CPU time 217.77 seconds
Started Jul 24 05:35:08 PM PDT 24
Finished Jul 24 05:38:46 PM PDT 24
Peak memory 254876 kb
Host smart-d060a5c7-eb34-4b92-85d0-ae77fdf7f52b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895308290 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_ping_timeout.2895308290
Directory /workspace/40.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_random_alerts.3806480860
Short name T425
Test name
Test status
Simulation time 7640023754 ps
CPU time 66.89 seconds
Started Jul 24 05:35:02 PM PDT 24
Finished Jul 24 05:36:09 PM PDT 24
Peak memory 256736 kb
Host smart-601d95b6-2757-440b-91ed-56bef051e20c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38064
80860 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_alerts.3806480860
Directory /workspace/40.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/40.alert_handler_random_classes.4006342746
Short name T122
Test name
Test status
Simulation time 2644759031 ps
CPU time 43.62 seconds
Started Jul 24 05:35:08 PM PDT 24
Finished Jul 24 05:35:51 PM PDT 24
Peak memory 256312 kb
Host smart-013682c9-3250-4ddd-a7f8-d1c71090c697
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40063
42746 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_classes.4006342746
Directory /workspace/40.alert_handler_random_classes/latest

Test location /workspace/coverage/default/40.alert_handler_sig_int_fail.922106841
Short name T315
Test name
Test status
Simulation time 766233710 ps
CPU time 17.9 seconds
Started Jul 24 05:35:07 PM PDT 24
Finished Jul 24 05:35:26 PM PDT 24
Peak memory 256272 kb
Host smart-a48d59d7-fff5-4a76-8298-3b988aff7bcd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92210
6841 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_sig_int_fail.922106841
Directory /workspace/40.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/40.alert_handler_smoke.3091799331
Short name T693
Test name
Test status
Simulation time 341041690 ps
CPU time 10.69 seconds
Started Jul 24 05:35:01 PM PDT 24
Finished Jul 24 05:35:12 PM PDT 24
Peak memory 248548 kb
Host smart-c85ac53f-f872-46c2-b872-7ea726c58eaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30917
99331 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_smoke.3091799331
Directory /workspace/40.alert_handler_smoke/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all.1404296158
Short name T59
Test name
Test status
Simulation time 62312921640 ps
CPU time 3738.15 seconds
Started Jul 24 05:35:07 PM PDT 24
Finished Jul 24 06:37:26 PM PDT 24
Peak memory 289172 kb
Host smart-d0943c16-5d60-4d58-89b2-a9cfa27cb7ee
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404296158 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_ha
ndler_stress_all.1404296158
Directory /workspace/40.alert_handler_stress_all/latest

Test location /workspace/coverage/default/41.alert_handler_entropy.3382176733
Short name T432
Test name
Test status
Simulation time 18406549910 ps
CPU time 1668.28 seconds
Started Jul 24 05:35:08 PM PDT 24
Finished Jul 24 06:02:57 PM PDT 24
Peak memory 281460 kb
Host smart-7ddff681-15c2-4391-8c18-22818e48766f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3382176733 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_entropy.3382176733
Directory /workspace/41.alert_handler_entropy/latest

Test location /workspace/coverage/default/41.alert_handler_esc_alert_accum.3971583164
Short name T703
Test name
Test status
Simulation time 21135167255 ps
CPU time 130.34 seconds
Started Jul 24 05:35:05 PM PDT 24
Finished Jul 24 05:37:16 PM PDT 24
Peak memory 256828 kb
Host smart-1dc1e2ce-19eb-4433-96f8-152b62e37021
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39715
83164 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_alert_accum.3971583164
Directory /workspace/41.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/41.alert_handler_esc_intr_timeout.1642498696
Short name T357
Test name
Test status
Simulation time 613157344 ps
CPU time 49.65 seconds
Started Jul 24 05:35:05 PM PDT 24
Finished Jul 24 05:35:55 PM PDT 24
Peak memory 248464 kb
Host smart-cfcdc903-1cfb-4274-9a19-583085113513
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16424
98696 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_intr_timeout.1642498696
Directory /workspace/41.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_lpg.2517349284
Short name T304
Test name
Test status
Simulation time 30605966269 ps
CPU time 793.76 seconds
Started Jul 24 05:35:09 PM PDT 24
Finished Jul 24 05:48:23 PM PDT 24
Peak memory 272500 kb
Host smart-5db8a09d-cce8-4a20-8132-e0eb321e8ad7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517349284 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg.2517349284
Directory /workspace/41.alert_handler_lpg/latest

Test location /workspace/coverage/default/41.alert_handler_lpg_stub_clk.2333304750
Short name T227
Test name
Test status
Simulation time 23206024567 ps
CPU time 1577.63 seconds
Started Jul 24 05:35:13 PM PDT 24
Finished Jul 24 06:01:31 PM PDT 24
Peak memory 272676 kb
Host smart-20e539e7-208f-4d78-9aeb-4e0e42cd2c38
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2333304750 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg_stub_clk.2333304750
Directory /workspace/41.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/41.alert_handler_ping_timeout.2706241084
Short name T277
Test name
Test status
Simulation time 23988766353 ps
CPU time 505.52 seconds
Started Jul 24 05:35:09 PM PDT 24
Finished Jul 24 05:43:35 PM PDT 24
Peak memory 247512 kb
Host smart-f35449a9-8b5a-47cc-8080-23c280300700
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2706241084 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_ping_timeout.2706241084
Directory /workspace/41.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_random_alerts.692205124
Short name T483
Test name
Test status
Simulation time 2178726641 ps
CPU time 44.01 seconds
Started Jul 24 05:35:06 PM PDT 24
Finished Jul 24 05:35:50 PM PDT 24
Peak memory 255868 kb
Host smart-6526c348-2179-4a41-a465-322ba477974d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69220
5124 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_alerts.692205124
Directory /workspace/41.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/41.alert_handler_random_classes.3279906274
Short name T701
Test name
Test status
Simulation time 301436181 ps
CPU time 18.55 seconds
Started Jul 24 05:35:09 PM PDT 24
Finished Jul 24 05:35:27 PM PDT 24
Peak memory 255488 kb
Host smart-fbf93d9a-de08-438d-b963-415020f5e25e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32799
06274 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_classes.3279906274
Directory /workspace/41.alert_handler_random_classes/latest

Test location /workspace/coverage/default/41.alert_handler_sig_int_fail.2208345139
Short name T45
Test name
Test status
Simulation time 362981415 ps
CPU time 22.37 seconds
Started Jul 24 05:35:08 PM PDT 24
Finished Jul 24 05:35:30 PM PDT 24
Peak memory 256716 kb
Host smart-ed5d0bd0-c040-4177-9128-e54a36a0b87a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22083
45139 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_sig_int_fail.2208345139
Directory /workspace/41.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/41.alert_handler_smoke.3789009310
Short name T365
Test name
Test status
Simulation time 268185186 ps
CPU time 32.83 seconds
Started Jul 24 05:35:09 PM PDT 24
Finished Jul 24 05:35:42 PM PDT 24
Peak memory 256752 kb
Host smart-54c37e88-57d4-4ee9-8ec4-5fbd4c3cb299
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37890
09310 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_smoke.3789009310
Directory /workspace/41.alert_handler_smoke/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all.555325784
Short name T568
Test name
Test status
Simulation time 102239128410 ps
CPU time 1506.54 seconds
Started Jul 24 05:35:13 PM PDT 24
Finished Jul 24 06:00:20 PM PDT 24
Peak memory 283456 kb
Host smart-5d1a13fa-d2a0-433d-8a27-cb72a40d06c5
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555325784 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_han
dler_stress_all.555325784
Directory /workspace/41.alert_handler_stress_all/latest

Test location /workspace/coverage/default/42.alert_handler_entropy.2676634678
Short name T485
Test name
Test status
Simulation time 105883592343 ps
CPU time 1608.63 seconds
Started Jul 24 05:35:15 PM PDT 24
Finished Jul 24 06:02:04 PM PDT 24
Peak memory 281392 kb
Host smart-ce5e601e-a4b9-493d-a987-b79f7843f862
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676634678 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_entropy.2676634678
Directory /workspace/42.alert_handler_entropy/latest

Test location /workspace/coverage/default/42.alert_handler_esc_alert_accum.3918374956
Short name T538
Test name
Test status
Simulation time 2960195677 ps
CPU time 155.71 seconds
Started Jul 24 05:35:11 PM PDT 24
Finished Jul 24 05:37:47 PM PDT 24
Peak memory 256856 kb
Host smart-d6b83e9d-479c-4f9b-b0be-542f8a1d4ce4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39183
74956 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_alert_accum.3918374956
Directory /workspace/42.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/42.alert_handler_esc_intr_timeout.2302007074
Short name T507
Test name
Test status
Simulation time 1472322561 ps
CPU time 24.53 seconds
Started Jul 24 05:35:12 PM PDT 24
Finished Jul 24 05:35:36 PM PDT 24
Peak memory 256628 kb
Host smart-64e4b994-3879-4b37-b7e0-2d7f02d0c743
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23020
07074 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_intr_timeout.2302007074
Directory /workspace/42.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_lpg.2712869941
Short name T662
Test name
Test status
Simulation time 121455005330 ps
CPU time 1097.7 seconds
Started Jul 24 05:35:15 PM PDT 24
Finished Jul 24 05:53:33 PM PDT 24
Peak memory 272620 kb
Host smart-79939728-3cf8-4f1e-8a4e-23e1f405089e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712869941 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg.2712869941
Directory /workspace/42.alert_handler_lpg/latest

Test location /workspace/coverage/default/42.alert_handler_lpg_stub_clk.1787649059
Short name T414
Test name
Test status
Simulation time 173802983621 ps
CPU time 2577.04 seconds
Started Jul 24 05:35:11 PM PDT 24
Finished Jul 24 06:18:08 PM PDT 24
Peak memory 288924 kb
Host smart-744f2a72-09d0-4e48-98fd-b906e127e22f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1787649059 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg_stub_clk.1787649059
Directory /workspace/42.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/42.alert_handler_ping_timeout.1016749601
Short name T267
Test name
Test status
Simulation time 48874271024 ps
CPU time 379.86 seconds
Started Jul 24 05:35:12 PM PDT 24
Finished Jul 24 05:41:32 PM PDT 24
Peak memory 247544 kb
Host smart-c7b44570-46b1-43d0-a615-5d2e67a77c60
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016749601 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_ping_timeout.1016749601
Directory /workspace/42.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_random_alerts.1283003549
Short name T431
Test name
Test status
Simulation time 72637734 ps
CPU time 9.62 seconds
Started Jul 24 05:35:15 PM PDT 24
Finished Jul 24 05:35:25 PM PDT 24
Peak memory 255036 kb
Host smart-38db0681-dc7c-4190-b03c-0a922dc858fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12830
03549 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_alerts.1283003549
Directory /workspace/42.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/42.alert_handler_random_classes.2595331343
Short name T447
Test name
Test status
Simulation time 288912802 ps
CPU time 22.51 seconds
Started Jul 24 05:35:12 PM PDT 24
Finished Jul 24 05:35:35 PM PDT 24
Peak memory 249028 kb
Host smart-68430b1b-d292-447f-b75e-ef87f10e29f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25953
31343 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_classes.2595331343
Directory /workspace/42.alert_handler_random_classes/latest

Test location /workspace/coverage/default/42.alert_handler_sig_int_fail.4229371089
Short name T398
Test name
Test status
Simulation time 1147690822 ps
CPU time 30.83 seconds
Started Jul 24 05:35:15 PM PDT 24
Finished Jul 24 05:35:46 PM PDT 24
Peak memory 248568 kb
Host smart-d436e63d-b687-4038-b84c-b62635ba0665
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42293
71089 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_sig_int_fail.4229371089
Directory /workspace/42.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/42.alert_handler_smoke.356759857
Short name T311
Test name
Test status
Simulation time 452991588 ps
CPU time 32.29 seconds
Started Jul 24 05:35:12 PM PDT 24
Finished Jul 24 05:35:44 PM PDT 24
Peak memory 256592 kb
Host smart-ea2cb0fb-355a-47a1-a538-838f703ef848
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35675
9857 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_smoke.356759857
Directory /workspace/42.alert_handler_smoke/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all.891421897
Short name T532
Test name
Test status
Simulation time 201741475827 ps
CPU time 1462.97 seconds
Started Jul 24 05:35:13 PM PDT 24
Finished Jul 24 05:59:36 PM PDT 24
Peak memory 265252 kb
Host smart-4780ac4a-713c-4851-8176-0b5a50690b72
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891421897 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_han
dler_stress_all.891421897
Directory /workspace/42.alert_handler_stress_all/latest

Test location /workspace/coverage/default/43.alert_handler_entropy.3126105043
Short name T15
Test name
Test status
Simulation time 204091057595 ps
CPU time 1480.44 seconds
Started Jul 24 05:35:15 PM PDT 24
Finished Jul 24 05:59:56 PM PDT 24
Peak memory 272956 kb
Host smart-09caba0c-3b30-46bb-ab67-51d32dc82b38
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126105043 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_entropy.3126105043
Directory /workspace/43.alert_handler_entropy/latest

Test location /workspace/coverage/default/43.alert_handler_esc_alert_accum.1931592648
Short name T47
Test name
Test status
Simulation time 13337638476 ps
CPU time 167.71 seconds
Started Jul 24 05:35:17 PM PDT 24
Finished Jul 24 05:38:04 PM PDT 24
Peak memory 249868 kb
Host smart-e6e31018-ff18-4788-8f56-1b8976938df4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19315
92648 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_alert_accum.1931592648
Directory /workspace/43.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/43.alert_handler_esc_intr_timeout.3452515266
Short name T429
Test name
Test status
Simulation time 165010151 ps
CPU time 17.69 seconds
Started Jul 24 05:35:16 PM PDT 24
Finished Jul 24 05:35:34 PM PDT 24
Peak memory 248484 kb
Host smart-f4fc01d2-d4b8-4166-969e-0c78f92e7876
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34525
15266 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_intr_timeout.3452515266
Directory /workspace/43.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_lpg.1726725615
Short name T486
Test name
Test status
Simulation time 159252186128 ps
CPU time 1328.83 seconds
Started Jul 24 05:35:19 PM PDT 24
Finished Jul 24 05:57:28 PM PDT 24
Peak memory 271344 kb
Host smart-78f3c762-cd23-4363-8dcd-108303859d3a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726725615 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg.1726725615
Directory /workspace/43.alert_handler_lpg/latest

Test location /workspace/coverage/default/43.alert_handler_lpg_stub_clk.2607000666
Short name T680
Test name
Test status
Simulation time 23419347229 ps
CPU time 1663.23 seconds
Started Jul 24 05:35:19 PM PDT 24
Finished Jul 24 06:03:02 PM PDT 24
Peak memory 282124 kb
Host smart-eb7903ec-ef09-4277-819d-18a849abe17e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607000666 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg_stub_clk.2607000666
Directory /workspace/43.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/43.alert_handler_ping_timeout.1745222691
Short name T511
Test name
Test status
Simulation time 4370833282 ps
CPU time 182.91 seconds
Started Jul 24 05:35:17 PM PDT 24
Finished Jul 24 05:38:20 PM PDT 24
Peak memory 248852 kb
Host smart-ee296acb-7104-48f2-8156-cebfd1354490
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745222691 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_ping_timeout.1745222691
Directory /workspace/43.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_random_alerts.4226251263
Short name T392
Test name
Test status
Simulation time 1559703350 ps
CPU time 46.79 seconds
Started Jul 24 05:35:12 PM PDT 24
Finished Jul 24 05:35:59 PM PDT 24
Peak memory 248508 kb
Host smart-b62f9ffc-4451-4df8-8742-9ba02b31ae62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42262
51263 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_alerts.4226251263
Directory /workspace/43.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/43.alert_handler_random_classes.993781505
Short name T460
Test name
Test status
Simulation time 540534333 ps
CPU time 18.37 seconds
Started Jul 24 05:35:13 PM PDT 24
Finished Jul 24 05:35:32 PM PDT 24
Peak memory 255560 kb
Host smart-92757aee-903b-41f2-8db6-ac20b19d0665
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99378
1505 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_classes.993781505
Directory /workspace/43.alert_handler_random_classes/latest

Test location /workspace/coverage/default/43.alert_handler_sig_int_fail.3916674471
Short name T577
Test name
Test status
Simulation time 74513528 ps
CPU time 8.1 seconds
Started Jul 24 05:35:18 PM PDT 24
Finished Jul 24 05:35:26 PM PDT 24
Peak memory 248976 kb
Host smart-e3c4ca7d-27ab-4d8f-8663-4a3d8e16c14a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39166
74471 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_sig_int_fail.3916674471
Directory /workspace/43.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/43.alert_handler_smoke.1697071545
Short name T440
Test name
Test status
Simulation time 814665064 ps
CPU time 58.8 seconds
Started Jul 24 05:35:10 PM PDT 24
Finished Jul 24 05:36:09 PM PDT 24
Peak memory 256596 kb
Host smart-40a5341c-c482-47ee-88f9-2d07c35d64b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16970
71545 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_smoke.1697071545
Directory /workspace/43.alert_handler_smoke/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all.1014058366
Short name T574
Test name
Test status
Simulation time 109321616226 ps
CPU time 3176.65 seconds
Started Jul 24 05:35:21 PM PDT 24
Finished Jul 24 06:28:18 PM PDT 24
Peak memory 289308 kb
Host smart-44313d3e-851c-4835-b343-83b32a8cb157
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014058366 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_ha
ndler_stress_all.1014058366
Directory /workspace/43.alert_handler_stress_all/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all_with_rand_reset.1515287862
Short name T88
Test name
Test status
Simulation time 86037253389 ps
CPU time 4884.36 seconds
Started Jul 24 05:35:17 PM PDT 24
Finished Jul 24 06:56:42 PM PDT 24
Peak memory 288848 kb
Host smart-6357f7de-f1d5-4edf-b3a2-e6c642b17fa6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515287862 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 43.alert_handler_stress_all_with_rand_reset.1515287862
Directory /workspace/43.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.alert_handler_entropy.92662227
Short name T17
Test name
Test status
Simulation time 22635934358 ps
CPU time 1518.31 seconds
Started Jul 24 05:35:23 PM PDT 24
Finished Jul 24 06:00:41 PM PDT 24
Peak memory 271100 kb
Host smart-f63752cd-f257-4d33-8fe0-0b8ad02161ad
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92662227 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_entropy.92662227
Directory /workspace/44.alert_handler_entropy/latest

Test location /workspace/coverage/default/44.alert_handler_esc_alert_accum.3267737360
Short name T713
Test name
Test status
Simulation time 5170657186 ps
CPU time 101.65 seconds
Started Jul 24 05:35:17 PM PDT 24
Finished Jul 24 05:36:59 PM PDT 24
Peak memory 256440 kb
Host smart-9811c41a-9c5f-474f-a515-87f053c54123
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32677
37360 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_alert_accum.3267737360
Directory /workspace/44.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/44.alert_handler_esc_intr_timeout.1512536514
Short name T522
Test name
Test status
Simulation time 368967649 ps
CPU time 19.89 seconds
Started Jul 24 05:35:17 PM PDT 24
Finished Jul 24 05:35:37 PM PDT 24
Peak memory 248088 kb
Host smart-347ba057-48b5-44b8-9018-a75e94332142
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15125
36514 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_intr_timeout.1512536514
Directory /workspace/44.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_lpg.3190320726
Short name T324
Test name
Test status
Simulation time 27025968409 ps
CPU time 1450.46 seconds
Started Jul 24 05:35:21 PM PDT 24
Finished Jul 24 05:59:31 PM PDT 24
Peak memory 264960 kb
Host smart-caea015c-8304-4708-9872-c7df66b260f2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190320726 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg.3190320726
Directory /workspace/44.alert_handler_lpg/latest

Test location /workspace/coverage/default/44.alert_handler_lpg_stub_clk.2570468029
Short name T406
Test name
Test status
Simulation time 26010676967 ps
CPU time 984.36 seconds
Started Jul 24 05:35:30 PM PDT 24
Finished Jul 24 05:51:54 PM PDT 24
Peak memory 273208 kb
Host smart-c8004e55-14aa-4bc6-ae9a-116d1b351717
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570468029 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg_stub_clk.2570468029
Directory /workspace/44.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/44.alert_handler_ping_timeout.1195171377
Short name T226
Test name
Test status
Simulation time 4983431502 ps
CPU time 206.95 seconds
Started Jul 24 05:35:20 PM PDT 24
Finished Jul 24 05:38:47 PM PDT 24
Peak memory 248676 kb
Host smart-d0942a4f-f4ac-4e7f-a002-2ccf1aade5ec
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195171377 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_ping_timeout.1195171377
Directory /workspace/44.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_random_alerts.1302120585
Short name T37
Test name
Test status
Simulation time 1580497355 ps
CPU time 51.26 seconds
Started Jul 24 05:35:17 PM PDT 24
Finished Jul 24 05:36:08 PM PDT 24
Peak memory 255828 kb
Host smart-467b97a2-6d54-4a4c-8e66-792578a8d9ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13021
20585 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_alerts.1302120585
Directory /workspace/44.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/44.alert_handler_random_classes.4001505276
Short name T604
Test name
Test status
Simulation time 104385646 ps
CPU time 13.36 seconds
Started Jul 24 05:35:16 PM PDT 24
Finished Jul 24 05:35:29 PM PDT 24
Peak memory 254744 kb
Host smart-68f1fa4b-6b8c-435c-b2b8-0a0e1552fefa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40015
05276 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_classes.4001505276
Directory /workspace/44.alert_handler_random_classes/latest

Test location /workspace/coverage/default/44.alert_handler_sig_int_fail.3540954037
Short name T570
Test name
Test status
Simulation time 536387050 ps
CPU time 35.05 seconds
Started Jul 24 05:35:16 PM PDT 24
Finished Jul 24 05:35:51 PM PDT 24
Peak memory 249152 kb
Host smart-37febadf-88f4-46a0-9301-0b6001684007
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35409
54037 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_sig_int_fail.3540954037
Directory /workspace/44.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/44.alert_handler_smoke.1624138434
Short name T561
Test name
Test status
Simulation time 2283506076 ps
CPU time 24.92 seconds
Started Jul 24 05:35:16 PM PDT 24
Finished Jul 24 05:35:41 PM PDT 24
Peak memory 248888 kb
Host smart-889b74c6-8258-41ae-97db-3580c6226a56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16241
38434 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_smoke.1624138434
Directory /workspace/44.alert_handler_smoke/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all.2385637674
Short name T585
Test name
Test status
Simulation time 36480429635 ps
CPU time 2279.58 seconds
Started Jul 24 05:35:21 PM PDT 24
Finished Jul 24 06:13:21 PM PDT 24
Peak memory 289456 kb
Host smart-f6d64a18-a0a7-4e0e-a378-c7729e224efb
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385637674 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_ha
ndler_stress_all.2385637674
Directory /workspace/44.alert_handler_stress_all/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all_with_rand_reset.4105612208
Short name T44
Test name
Test status
Simulation time 283800007845 ps
CPU time 7118.87 seconds
Started Jul 24 05:35:21 PM PDT 24
Finished Jul 24 07:34:00 PM PDT 24
Peak memory 353644 kb
Host smart-aa6fca22-56fb-4f33-8020-a32429174be2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105612208 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 44.alert_handler_stress_all_with_rand_reset.4105612208
Directory /workspace/44.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.alert_handler_entropy.2210517527
Short name T623
Test name
Test status
Simulation time 33786424547 ps
CPU time 593.33 seconds
Started Jul 24 05:35:25 PM PDT 24
Finished Jul 24 05:45:19 PM PDT 24
Peak memory 265064 kb
Host smart-b9f57a66-73d2-4bd8-9a33-ae39b6400061
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210517527 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_entropy.2210517527
Directory /workspace/45.alert_handler_entropy/latest

Test location /workspace/coverage/default/45.alert_handler_esc_alert_accum.2581801373
Short name T684
Test name
Test status
Simulation time 10299118508 ps
CPU time 148.25 seconds
Started Jul 24 05:35:21 PM PDT 24
Finished Jul 24 05:37:50 PM PDT 24
Peak memory 250680 kb
Host smart-63767475-b9a3-4c54-aa06-7731c329f1c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25818
01373 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_alert_accum.2581801373
Directory /workspace/45.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/45.alert_handler_esc_intr_timeout.3830883819
Short name T404
Test name
Test status
Simulation time 353446754 ps
CPU time 13.81 seconds
Started Jul 24 05:35:20 PM PDT 24
Finished Jul 24 05:35:34 PM PDT 24
Peak memory 248304 kb
Host smart-bd56b522-a3da-4a6b-89c2-afdca28d628e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38308
83819 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_intr_timeout.3830883819
Directory /workspace/45.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_lpg.2648212349
Short name T318
Test name
Test status
Simulation time 49397920134 ps
CPU time 2960.49 seconds
Started Jul 24 05:35:30 PM PDT 24
Finished Jul 24 06:24:51 PM PDT 24
Peak memory 281320 kb
Host smart-02d22edc-7869-49a1-a2e8-dd8147367b9f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648212349 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg.2648212349
Directory /workspace/45.alert_handler_lpg/latest

Test location /workspace/coverage/default/45.alert_handler_lpg_stub_clk.2914965385
Short name T396
Test name
Test status
Simulation time 147666305433 ps
CPU time 2369.68 seconds
Started Jul 24 05:35:19 PM PDT 24
Finished Jul 24 06:14:49 PM PDT 24
Peak memory 288744 kb
Host smart-467e11ec-0f06-4daa-99b1-a464b0d0489b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914965385 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg_stub_clk.2914965385
Directory /workspace/45.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/45.alert_handler_ping_timeout.841428023
Short name T282
Test name
Test status
Simulation time 20146804641 ps
CPU time 421.77 seconds
Started Jul 24 05:35:30 PM PDT 24
Finished Jul 24 05:42:32 PM PDT 24
Peak memory 248712 kb
Host smart-cdc52f80-347f-4cc6-9996-20ee091b91fc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=841428023 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_ping_timeout.841428023
Directory /workspace/45.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_random_alerts.2122106952
Short name T673
Test name
Test status
Simulation time 658088278 ps
CPU time 35.4 seconds
Started Jul 24 05:35:18 PM PDT 24
Finished Jul 24 05:35:53 PM PDT 24
Peak memory 256232 kb
Host smart-9eba55e6-0c81-4f42-867c-55b2005dc1d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21221
06952 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_alerts.2122106952
Directory /workspace/45.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/45.alert_handler_random_classes.2535011074
Short name T118
Test name
Test status
Simulation time 317938605 ps
CPU time 21.22 seconds
Started Jul 24 05:35:21 PM PDT 24
Finished Jul 24 05:35:43 PM PDT 24
Peak memory 247800 kb
Host smart-35567013-2313-4be2-baee-7a5764777e3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25350
11074 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_classes.2535011074
Directory /workspace/45.alert_handler_random_classes/latest

Test location /workspace/coverage/default/45.alert_handler_sig_int_fail.2000922467
Short name T74
Test name
Test status
Simulation time 357204207 ps
CPU time 6.48 seconds
Started Jul 24 05:35:30 PM PDT 24
Finished Jul 24 05:35:36 PM PDT 24
Peak memory 253840 kb
Host smart-f647027f-c9d7-4686-8aab-a1f5642b6333
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20009
22467 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_sig_int_fail.2000922467
Directory /workspace/45.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/45.alert_handler_smoke.4263505313
Short name T491
Test name
Test status
Simulation time 204611480 ps
CPU time 20.32 seconds
Started Jul 24 05:35:21 PM PDT 24
Finished Jul 24 05:35:41 PM PDT 24
Peak memory 256764 kb
Host smart-aa9808ba-7e3a-4428-865b-cc420b10b14e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42635
05313 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_smoke.4263505313
Directory /workspace/45.alert_handler_smoke/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all.670210381
Short name T670
Test name
Test status
Simulation time 852936756 ps
CPU time 53.66 seconds
Started Jul 24 05:35:19 PM PDT 24
Finished Jul 24 05:36:13 PM PDT 24
Peak memory 256788 kb
Host smart-789fa1b9-4dae-4774-92f7-58ab13995647
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670210381 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_han
dler_stress_all.670210381
Directory /workspace/45.alert_handler_stress_all/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all_with_rand_reset.394979447
Short name T49
Test name
Test status
Simulation time 91696354659 ps
CPU time 3919.5 seconds
Started Jul 24 05:35:22 PM PDT 24
Finished Jul 24 06:40:42 PM PDT 24
Peak memory 338468 kb
Host smart-717c2300-6496-4b52-8b23-d764f250f246
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394979447 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 45.alert_handler_stress_all_with_rand_reset.394979447
Directory /workspace/45.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.alert_handler_entropy.81440205
Short name T677
Test name
Test status
Simulation time 72654594743 ps
CPU time 2442.7 seconds
Started Jul 24 05:35:27 PM PDT 24
Finished Jul 24 06:16:10 PM PDT 24
Peak memory 289444 kb
Host smart-5fbc0fe1-4782-490d-b497-2f97f8396866
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81440205 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_entropy.81440205
Directory /workspace/46.alert_handler_entropy/latest

Test location /workspace/coverage/default/46.alert_handler_esc_alert_accum.1921202225
Short name T500
Test name
Test status
Simulation time 14765221611 ps
CPU time 208.69 seconds
Started Jul 24 05:35:27 PM PDT 24
Finished Jul 24 05:38:56 PM PDT 24
Peak memory 256320 kb
Host smart-f1e865f9-352f-4178-8627-855a2eb61872
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19212
02225 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_alert_accum.1921202225
Directory /workspace/46.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/46.alert_handler_esc_intr_timeout.3978639834
Short name T581
Test name
Test status
Simulation time 4444318837 ps
CPU time 65.5 seconds
Started Jul 24 05:35:22 PM PDT 24
Finished Jul 24 05:36:28 PM PDT 24
Peak memory 248532 kb
Host smart-1b13706b-5bde-4f00-ba3c-1f3f0fffb664
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39786
39834 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_intr_timeout.3978639834
Directory /workspace/46.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_lpg.2182763421
Short name T320
Test name
Test status
Simulation time 244988113386 ps
CPU time 1392.36 seconds
Started Jul 24 05:35:27 PM PDT 24
Finished Jul 24 05:58:40 PM PDT 24
Peak memory 285844 kb
Host smart-54462a4e-8d08-40f5-b0a0-83088680a614
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2182763421 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg.2182763421
Directory /workspace/46.alert_handler_lpg/latest

Test location /workspace/coverage/default/46.alert_handler_lpg_stub_clk.717003860
Short name T288
Test name
Test status
Simulation time 31603826785 ps
CPU time 1435.86 seconds
Started Jul 24 05:35:30 PM PDT 24
Finished Jul 24 05:59:26 PM PDT 24
Peak memory 272948 kb
Host smart-4bd3d421-9db9-46d8-966a-d0103b2b59b0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717003860 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg_stub_clk.717003860
Directory /workspace/46.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/46.alert_handler_random_alerts.3207291886
Short name T631
Test name
Test status
Simulation time 774284090 ps
CPU time 14.55 seconds
Started Jul 24 05:35:23 PM PDT 24
Finished Jul 24 05:35:38 PM PDT 24
Peak memory 248644 kb
Host smart-a9d6c897-415d-414b-a2e6-789297c80c84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32072
91886 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_alerts.3207291886
Directory /workspace/46.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/46.alert_handler_random_classes.4017412901
Short name T679
Test name
Test status
Simulation time 1381689572 ps
CPU time 27.91 seconds
Started Jul 24 05:35:30 PM PDT 24
Finished Jul 24 05:35:59 PM PDT 24
Peak memory 247904 kb
Host smart-f409e4e2-9420-40eb-a0e1-7e11fd1ed4f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40174
12901 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_classes.4017412901
Directory /workspace/46.alert_handler_random_classes/latest

Test location /workspace/coverage/default/46.alert_handler_sig_int_fail.1499994550
Short name T239
Test name
Test status
Simulation time 624383733 ps
CPU time 28.88 seconds
Started Jul 24 05:35:26 PM PDT 24
Finished Jul 24 05:35:55 PM PDT 24
Peak memory 248536 kb
Host smart-3a4dd9ab-8d07-4e33-96cf-c7e4782b37eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14999
94550 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_sig_int_fail.1499994550
Directory /workspace/46.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/46.alert_handler_smoke.3895465022
Short name T547
Test name
Test status
Simulation time 1905820626 ps
CPU time 61.85 seconds
Started Jul 24 05:35:22 PM PDT 24
Finished Jul 24 05:36:24 PM PDT 24
Peak memory 256776 kb
Host smart-bdfe440a-0520-4084-844c-be47d09b402e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38954
65022 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_smoke.3895465022
Directory /workspace/46.alert_handler_smoke/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all.1184293677
Short name T110
Test name
Test status
Simulation time 13687503987 ps
CPU time 180.08 seconds
Started Jul 24 05:35:29 PM PDT 24
Finished Jul 24 05:38:29 PM PDT 24
Peak memory 256912 kb
Host smart-19b99023-b53d-4d61-b622-d79147d24d3d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184293677 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_ha
ndler_stress_all.1184293677
Directory /workspace/46.alert_handler_stress_all/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all_with_rand_reset.875020785
Short name T71
Test name
Test status
Simulation time 84989477790 ps
CPU time 1477.95 seconds
Started Jul 24 05:35:29 PM PDT 24
Finished Jul 24 06:00:07 PM PDT 24
Peak memory 289744 kb
Host smart-376ceaec-96b0-4a40-a162-222bdc0a3b76
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875020785 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 46.alert_handler_stress_all_with_rand_reset.875020785
Directory /workspace/46.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.alert_handler_entropy.2119580310
Short name T548
Test name
Test status
Simulation time 123546224494 ps
CPU time 1130 seconds
Started Jul 24 05:35:28 PM PDT 24
Finished Jul 24 05:54:18 PM PDT 24
Peak memory 288936 kb
Host smart-f717db3f-294f-439f-9a0d-ba315f9ad115
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119580310 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_entropy.2119580310
Directory /workspace/47.alert_handler_entropy/latest

Test location /workspace/coverage/default/47.alert_handler_esc_alert_accum.3302463243
Short name T451
Test name
Test status
Simulation time 17013930354 ps
CPU time 229.65 seconds
Started Jul 24 05:35:27 PM PDT 24
Finished Jul 24 05:39:16 PM PDT 24
Peak memory 250712 kb
Host smart-120bc28e-48a1-4cd7-b3e6-28903047bfb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33024
63243 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_alert_accum.3302463243
Directory /workspace/47.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/47.alert_handler_esc_intr_timeout.2252672687
Short name T464
Test name
Test status
Simulation time 217883050 ps
CPU time 26.16 seconds
Started Jul 24 05:35:28 PM PDT 24
Finished Jul 24 05:35:54 PM PDT 24
Peak memory 248640 kb
Host smart-8a8f2341-5498-4ab8-886e-ffbfab086b8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22526
72687 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_intr_timeout.2252672687
Directory /workspace/47.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_lpg.3224493722
Short name T111
Test name
Test status
Simulation time 31931284691 ps
CPU time 1511.33 seconds
Started Jul 24 05:35:32 PM PDT 24
Finished Jul 24 06:00:44 PM PDT 24
Peak memory 288856 kb
Host smart-a5e776a8-73bf-42b8-a105-d482b03b03a5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224493722 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg.3224493722
Directory /workspace/47.alert_handler_lpg/latest

Test location /workspace/coverage/default/47.alert_handler_lpg_stub_clk.3980652256
Short name T671
Test name
Test status
Simulation time 5953513752 ps
CPU time 639.06 seconds
Started Jul 24 05:35:32 PM PDT 24
Finished Jul 24 05:46:11 PM PDT 24
Peak memory 273280 kb
Host smart-3454b712-cf14-44c2-a19f-4306a133fbbc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980652256 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg_stub_clk.3980652256
Directory /workspace/47.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/47.alert_handler_ping_timeout.3776009122
Short name T644
Test name
Test status
Simulation time 12195946197 ps
CPU time 511.87 seconds
Started Jul 24 05:35:31 PM PDT 24
Finished Jul 24 05:44:03 PM PDT 24
Peak memory 248596 kb
Host smart-2cd51175-20cc-494a-bb39-62e81583caf5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3776009122 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_ping_timeout.3776009122
Directory /workspace/47.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_random_alerts.740819069
Short name T381
Test name
Test status
Simulation time 2070616289 ps
CPU time 17.35 seconds
Started Jul 24 05:35:26 PM PDT 24
Finished Jul 24 05:35:44 PM PDT 24
Peak memory 256044 kb
Host smart-660d69e0-6352-42f1-aa7d-6e084a6d1e07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74081
9069 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_alerts.740819069
Directory /workspace/47.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/47.alert_handler_random_classes.2785617337
Short name T652
Test name
Test status
Simulation time 2681572347 ps
CPU time 47.41 seconds
Started Jul 24 05:35:32 PM PDT 24
Finished Jul 24 05:36:19 PM PDT 24
Peak memory 248640 kb
Host smart-e4194cf6-891a-44bb-a83f-8f98097a1029
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27856
17337 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_classes.2785617337
Directory /workspace/47.alert_handler_random_classes/latest

Test location /workspace/coverage/default/47.alert_handler_sig_int_fail.166184423
Short name T498
Test name
Test status
Simulation time 5190193815 ps
CPU time 48.4 seconds
Started Jul 24 05:35:29 PM PDT 24
Finished Jul 24 05:36:17 PM PDT 24
Peak memory 248680 kb
Host smart-db478cd2-593b-40a7-a070-6d505cdb2c9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16618
4423 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_sig_int_fail.166184423
Directory /workspace/47.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/47.alert_handler_smoke.3831076189
Short name T508
Test name
Test status
Simulation time 26505466 ps
CPU time 3.7 seconds
Started Jul 24 05:35:27 PM PDT 24
Finished Jul 24 05:35:30 PM PDT 24
Peak memory 250732 kb
Host smart-c3634f4f-a6ac-42c7-a3c8-6978ccc4b8ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38310
76189 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_smoke.3831076189
Directory /workspace/47.alert_handler_smoke/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all.2766695225
Short name T436
Test name
Test status
Simulation time 22040152417 ps
CPU time 1280.36 seconds
Started Jul 24 05:35:31 PM PDT 24
Finished Jul 24 05:56:52 PM PDT 24
Peak memory 289492 kb
Host smart-c7d69eb5-b79e-4cbe-b6e8-9c74481f936f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766695225 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_ha
ndler_stress_all.2766695225
Directory /workspace/47.alert_handler_stress_all/latest

Test location /workspace/coverage/default/48.alert_handler_entropy.3290340560
Short name T516
Test name
Test status
Simulation time 45569888556 ps
CPU time 2597.1 seconds
Started Jul 24 05:35:31 PM PDT 24
Finished Jul 24 06:18:49 PM PDT 24
Peak memory 285640 kb
Host smart-a8cdfc33-03ea-4179-8b3a-31ccba95671c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290340560 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_entropy.3290340560
Directory /workspace/48.alert_handler_entropy/latest

Test location /workspace/coverage/default/48.alert_handler_esc_alert_accum.2426241279
Short name T112
Test name
Test status
Simulation time 2862770703 ps
CPU time 164.36 seconds
Started Jul 24 05:35:34 PM PDT 24
Finished Jul 24 05:38:19 PM PDT 24
Peak memory 256852 kb
Host smart-6c6e9bb7-add1-40da-8598-6edceaaa1164
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24262
41279 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_alert_accum.2426241279
Directory /workspace/48.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/48.alert_handler_esc_intr_timeout.525351000
Short name T355
Test name
Test status
Simulation time 107920002 ps
CPU time 7.3 seconds
Started Jul 24 05:35:36 PM PDT 24
Finished Jul 24 05:35:43 PM PDT 24
Peak memory 247856 kb
Host smart-0a9cdca6-746d-475a-90ff-c8fa59e2a5f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52535
1000 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_intr_timeout.525351000
Directory /workspace/48.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_lpg.3089973741
Short name T41
Test name
Test status
Simulation time 17799010998 ps
CPU time 1488.59 seconds
Started Jul 24 05:35:30 PM PDT 24
Finished Jul 24 06:00:19 PM PDT 24
Peak memory 284996 kb
Host smart-da764619-c9cc-4bf7-bc65-94494a226611
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089973741 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg.3089973741
Directory /workspace/48.alert_handler_lpg/latest

Test location /workspace/coverage/default/48.alert_handler_lpg_stub_clk.2296742633
Short name T625
Test name
Test status
Simulation time 29056377822 ps
CPU time 1709.07 seconds
Started Jul 24 05:35:38 PM PDT 24
Finished Jul 24 06:04:07 PM PDT 24
Peak memory 273292 kb
Host smart-b3fcb801-05bd-437b-b127-ebbb4ae5fd8d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296742633 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg_stub_clk.2296742633
Directory /workspace/48.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/48.alert_handler_random_alerts.2478371114
Short name T537
Test name
Test status
Simulation time 820280152 ps
CPU time 14.01 seconds
Started Jul 24 05:35:32 PM PDT 24
Finished Jul 24 05:35:46 PM PDT 24
Peak memory 248604 kb
Host smart-b377cc75-f1c2-4e3f-b93e-e6905483266c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24783
71114 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_alerts.2478371114
Directory /workspace/48.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/48.alert_handler_random_classes.3809237911
Short name T384
Test name
Test status
Simulation time 1077517053 ps
CPU time 19.67 seconds
Started Jul 24 05:35:32 PM PDT 24
Finished Jul 24 05:35:52 PM PDT 24
Peak memory 248036 kb
Host smart-8156353e-1052-4852-a902-f299b8041f79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38092
37911 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_classes.3809237911
Directory /workspace/48.alert_handler_random_classes/latest

Test location /workspace/coverage/default/48.alert_handler_sig_int_fail.3273598971
Short name T300
Test name
Test status
Simulation time 797189210 ps
CPU time 49.73 seconds
Started Jul 24 05:35:30 PM PDT 24
Finished Jul 24 05:36:20 PM PDT 24
Peak memory 255916 kb
Host smart-c1577d46-0a7c-418b-8c3a-d1dd4665bd60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32735
98971 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_sig_int_fail.3273598971
Directory /workspace/48.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/48.alert_handler_smoke.2765724402
Short name T672
Test name
Test status
Simulation time 527605931 ps
CPU time 11.98 seconds
Started Jul 24 05:35:35 PM PDT 24
Finished Jul 24 05:35:47 PM PDT 24
Peak memory 248596 kb
Host smart-b621719a-7d34-4338-994b-c2b1c560eab4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27657
24402 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_smoke.2765724402
Directory /workspace/48.alert_handler_smoke/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all.4262888842
Short name T310
Test name
Test status
Simulation time 2382984064 ps
CPU time 64.47 seconds
Started Jul 24 05:35:50 PM PDT 24
Finished Jul 24 05:36:55 PM PDT 24
Peak memory 256832 kb
Host smart-e04f1db8-a9cb-47c0-92b3-494601c61566
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262888842 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_ha
ndler_stress_all.4262888842
Directory /workspace/48.alert_handler_stress_all/latest

Test location /workspace/coverage/default/49.alert_handler_esc_alert_accum.1560372592
Short name T530
Test name
Test status
Simulation time 459915092 ps
CPU time 33.38 seconds
Started Jul 24 05:35:40 PM PDT 24
Finished Jul 24 05:36:14 PM PDT 24
Peak memory 255908 kb
Host smart-1d36c53d-7e5d-4be2-afb7-1118cc86b7fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15603
72592 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_alert_accum.1560372592
Directory /workspace/49.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/49.alert_handler_esc_intr_timeout.1864870899
Short name T603
Test name
Test status
Simulation time 348067041 ps
CPU time 6.62 seconds
Started Jul 24 05:35:52 PM PDT 24
Finished Jul 24 05:35:59 PM PDT 24
Peak memory 248568 kb
Host smart-4ed94240-fe17-4a7e-a049-d01ad0832d3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18648
70899 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_intr_timeout.1864870899
Directory /workspace/49.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_lpg.374053419
Short name T329
Test name
Test status
Simulation time 185197132659 ps
CPU time 2657.98 seconds
Started Jul 24 05:35:38 PM PDT 24
Finished Jul 24 06:19:57 PM PDT 24
Peak memory 289588 kb
Host smart-7681599c-39ad-48c1-aa97-e1aa2f3d47e5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=374053419 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg.374053419
Directory /workspace/49.alert_handler_lpg/latest

Test location /workspace/coverage/default/49.alert_handler_lpg_stub_clk.573291260
Short name T397
Test name
Test status
Simulation time 161783297667 ps
CPU time 2519.09 seconds
Started Jul 24 05:35:50 PM PDT 24
Finished Jul 24 06:17:50 PM PDT 24
Peak memory 281432 kb
Host smart-823215af-4152-4170-b9a2-f51f85c5a2aa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573291260 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg_stub_clk.573291260
Directory /workspace/49.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/49.alert_handler_ping_timeout.2496412858
Short name T279
Test name
Test status
Simulation time 8328068752 ps
CPU time 179.22 seconds
Started Jul 24 05:35:40 PM PDT 24
Finished Jul 24 05:38:40 PM PDT 24
Peak memory 248356 kb
Host smart-de6715c0-dea5-4bac-add7-443cff72b4fa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496412858 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_ping_timeout.2496412858
Directory /workspace/49.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_random_alerts.1257791217
Short name T550
Test name
Test status
Simulation time 390211472 ps
CPU time 9.81 seconds
Started Jul 24 05:35:51 PM PDT 24
Finished Jul 24 05:36:01 PM PDT 24
Peak memory 253196 kb
Host smart-808e7e52-7de2-4449-914e-1e8f5ddec553
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12577
91217 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_alerts.1257791217
Directory /workspace/49.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/49.alert_handler_random_classes.1326158152
Short name T53
Test name
Test status
Simulation time 910141397 ps
CPU time 25.75 seconds
Started Jul 24 05:35:41 PM PDT 24
Finished Jul 24 05:36:07 PM PDT 24
Peak memory 248980 kb
Host smart-c5ef32a9-6a00-481e-a2fe-b3d3d8537a9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13261
58152 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_classes.1326158152
Directory /workspace/49.alert_handler_random_classes/latest

Test location /workspace/coverage/default/49.alert_handler_sig_int_fail.1500703488
Short name T685
Test name
Test status
Simulation time 1032808246 ps
CPU time 31.93 seconds
Started Jul 24 05:35:40 PM PDT 24
Finished Jul 24 05:36:12 PM PDT 24
Peak memory 248468 kb
Host smart-09203957-32fd-43dd-8aa4-fd1f8894b976
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15007
03488 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_sig_int_fail.1500703488
Directory /workspace/49.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/49.alert_handler_smoke.2715076781
Short name T213
Test name
Test status
Simulation time 4695897790 ps
CPU time 72.4 seconds
Started Jul 24 05:35:41 PM PDT 24
Finished Jul 24 05:36:53 PM PDT 24
Peak memory 256608 kb
Host smart-3c273ccb-bc1b-4b70-b31f-77d89e4f14b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27150
76781 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_smoke.2715076781
Directory /workspace/49.alert_handler_smoke/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all_with_rand_reset.2721721033
Short name T70
Test name
Test status
Simulation time 130729526598 ps
CPU time 6185.33 seconds
Started Jul 24 05:35:47 PM PDT 24
Finished Jul 24 07:18:53 PM PDT 24
Peak memory 338176 kb
Host smart-9a52e880-7a8b-463b-9344-255d83ca58fa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721721033 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 49.alert_handler_stress_all_with_rand_reset.2721721033
Directory /workspace/49.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.alert_handler_alert_accum_saturation.601370142
Short name T194
Test name
Test status
Simulation time 16654914 ps
CPU time 2.75 seconds
Started Jul 24 05:33:44 PM PDT 24
Finished Jul 24 05:33:47 PM PDT 24
Peak memory 248864 kb
Host smart-5076787d-72ec-4e5a-bf35-e14d608d0ce7
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=601370142 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_alert_accum_saturation.601370142
Directory /workspace/5.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/5.alert_handler_entropy.3085311701
Short name T421
Test name
Test status
Simulation time 89581839719 ps
CPU time 2626.29 seconds
Started Jul 24 05:33:43 PM PDT 24
Finished Jul 24 06:17:30 PM PDT 24
Peak memory 287040 kb
Host smart-4b03c5bf-6e0b-4eea-8a99-a26ea84bfaa9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085311701 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy.3085311701
Directory /workspace/5.alert_handler_entropy/latest

Test location /workspace/coverage/default/5.alert_handler_entropy_stress.142178491
Short name T42
Test name
Test status
Simulation time 1259873351 ps
CPU time 56.36 seconds
Started Jul 24 05:33:43 PM PDT 24
Finished Jul 24 05:34:40 PM PDT 24
Peak memory 248620 kb
Host smart-c5357b7c-9732-4c81-8407-9821cf45204a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=142178491 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy_stress.142178491
Directory /workspace/5.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/5.alert_handler_esc_alert_accum.3598992180
Short name T438
Test name
Test status
Simulation time 982872962 ps
CPU time 19.3 seconds
Started Jul 24 05:33:42 PM PDT 24
Finished Jul 24 05:34:02 PM PDT 24
Peak memory 256700 kb
Host smart-b3f85224-f09f-41bd-ad39-0eee4ae45dda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35989
92180 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_alert_accum.3598992180
Directory /workspace/5.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/5.alert_handler_esc_intr_timeout.377701313
Short name T449
Test name
Test status
Simulation time 1542142377 ps
CPU time 24.76 seconds
Started Jul 24 05:33:38 PM PDT 24
Finished Jul 24 05:34:03 PM PDT 24
Peak memory 248084 kb
Host smart-1ef89555-8406-4cc9-adac-d78ac93868e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37770
1313 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_intr_timeout.377701313
Directory /workspace/5.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_lpg.3130565933
Short name T715
Test name
Test status
Simulation time 15367608474 ps
CPU time 1483.34 seconds
Started Jul 24 05:33:56 PM PDT 24
Finished Jul 24 05:58:40 PM PDT 24
Peak memory 289648 kb
Host smart-10016b71-0013-4b7c-a2b7-9bf1963e71e3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130565933 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg.3130565933
Directory /workspace/5.alert_handler_lpg/latest

Test location /workspace/coverage/default/5.alert_handler_lpg_stub_clk.2083758988
Short name T517
Test name
Test status
Simulation time 14138491743 ps
CPU time 1320.69 seconds
Started Jul 24 05:33:49 PM PDT 24
Finished Jul 24 05:55:50 PM PDT 24
Peak memory 288852 kb
Host smart-b7a8058b-80b7-4fb4-a217-2966f30e4fe7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083758988 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg_stub_clk.2083758988
Directory /workspace/5.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/5.alert_handler_ping_timeout.3836919136
Short name T559
Test name
Test status
Simulation time 6693116497 ps
CPU time 275.98 seconds
Started Jul 24 05:33:49 PM PDT 24
Finished Jul 24 05:38:25 PM PDT 24
Peak memory 248648 kb
Host smart-fcadffbb-4dd6-44a3-8b91-8ff9805e1a2b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836919136 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_ping_timeout.3836919136
Directory /workspace/5.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_random_alerts.3411458018
Short name T633
Test name
Test status
Simulation time 857829260 ps
CPU time 21.85 seconds
Started Jul 24 05:33:44 PM PDT 24
Finished Jul 24 05:34:06 PM PDT 24
Peak memory 255992 kb
Host smart-4a6cf1a7-e4af-44ea-bc3d-6fe07e7bdce8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34114
58018 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_alerts.3411458018
Directory /workspace/5.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/5.alert_handler_random_classes.1385098862
Short name T475
Test name
Test status
Simulation time 54766280 ps
CPU time 5.58 seconds
Started Jul 24 05:33:42 PM PDT 24
Finished Jul 24 05:33:48 PM PDT 24
Peak memory 248048 kb
Host smart-16196b1c-34ee-418d-bfa1-b945c026a285
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13850
98862 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_classes.1385098862
Directory /workspace/5.alert_handler_random_classes/latest

Test location /workspace/coverage/default/5.alert_handler_sig_int_fail.4047568132
Short name T115
Test name
Test status
Simulation time 227266332 ps
CPU time 9.73 seconds
Started Jul 24 05:33:40 PM PDT 24
Finished Jul 24 05:33:50 PM PDT 24
Peak memory 248584 kb
Host smart-aa3766ef-6f3a-4dc4-b005-c6e06ad47859
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40475
68132 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_sig_int_fail.4047568132
Directory /workspace/5.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/5.alert_handler_smoke.1415555693
Short name T564
Test name
Test status
Simulation time 450658786 ps
CPU time 21.23 seconds
Started Jul 24 05:33:43 PM PDT 24
Finished Jul 24 05:34:04 PM PDT 24
Peak memory 255760 kb
Host smart-223457f1-6446-403b-ba05-7fbcc35c180a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14155
55693 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_smoke.1415555693
Directory /workspace/5.alert_handler_smoke/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all_with_rand_reset.3968636389
Short name T62
Test name
Test status
Simulation time 119241073335 ps
CPU time 6246.16 seconds
Started Jul 24 05:33:47 PM PDT 24
Finished Jul 24 07:17:54 PM PDT 24
Peak memory 370884 kb
Host smart-fae0ade4-935e-4eae-8346-6182fc69ed5b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968636389 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 5.alert_handler_stress_all_with_rand_reset.3968636389
Directory /workspace/5.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.alert_handler_alert_accum_saturation.832534167
Short name T109
Test name
Test status
Simulation time 107234288 ps
CPU time 3.12 seconds
Started Jul 24 05:33:45 PM PDT 24
Finished Jul 24 05:33:48 PM PDT 24
Peak memory 248872 kb
Host smart-7a9e9352-15c1-4653-a9ee-64b30463e7d6
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=832534167 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_alert_accum_saturation.832534167
Directory /workspace/6.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/6.alert_handler_entropy.1167443797
Short name T632
Test name
Test status
Simulation time 113178627304 ps
CPU time 2938.36 seconds
Started Jul 24 05:33:43 PM PDT 24
Finished Jul 24 06:22:42 PM PDT 24
Peak memory 289556 kb
Host smart-b2ba94dd-b8d1-4590-b187-b91460a1abae
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167443797 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy.1167443797
Directory /workspace/6.alert_handler_entropy/latest

Test location /workspace/coverage/default/6.alert_handler_entropy_stress.287268740
Short name T473
Test name
Test status
Simulation time 945167612 ps
CPU time 36.29 seconds
Started Jul 24 05:33:42 PM PDT 24
Finished Jul 24 05:34:19 PM PDT 24
Peak memory 248628 kb
Host smart-f72342ed-56c8-4ae9-b5fa-c46e2ed8077c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=287268740 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy_stress.287268740
Directory /workspace/6.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/6.alert_handler_esc_alert_accum.2063756399
Short name T370
Test name
Test status
Simulation time 315140733 ps
CPU time 34.61 seconds
Started Jul 24 05:33:39 PM PDT 24
Finished Jul 24 05:34:14 PM PDT 24
Peak memory 248364 kb
Host smart-ee1aa60f-fd7c-496e-81bf-3011afe9108d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20637
56399 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_alert_accum.2063756399
Directory /workspace/6.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/6.alert_handler_esc_intr_timeout.1481831161
Short name T114
Test name
Test status
Simulation time 6209857178 ps
CPU time 33.87 seconds
Started Jul 24 05:33:44 PM PDT 24
Finished Jul 24 05:34:18 PM PDT 24
Peak memory 256720 kb
Host smart-3e6a8b9f-2c22-4f9b-afda-74be9e085da4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14818
31161 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_intr_timeout.1481831161
Directory /workspace/6.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_lpg.3827794637
Short name T691
Test name
Test status
Simulation time 90959987547 ps
CPU time 2781.8 seconds
Started Jul 24 05:33:58 PM PDT 24
Finished Jul 24 06:20:20 PM PDT 24
Peak memory 288676 kb
Host smart-a4a8670c-207e-42f7-90e4-4cd60eaa4fc6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3827794637 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg.3827794637
Directory /workspace/6.alert_handler_lpg/latest

Test location /workspace/coverage/default/6.alert_handler_lpg_stub_clk.3967138814
Short name T439
Test name
Test status
Simulation time 123041873618 ps
CPU time 2018.51 seconds
Started Jul 24 05:33:41 PM PDT 24
Finished Jul 24 06:07:20 PM PDT 24
Peak memory 288996 kb
Host smart-00020619-0466-4af2-9887-1444b5f2aef3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967138814 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg_stub_clk.3967138814
Directory /workspace/6.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/6.alert_handler_ping_timeout.3885286135
Short name T567
Test name
Test status
Simulation time 5436326745 ps
CPU time 211.03 seconds
Started Jul 24 05:33:58 PM PDT 24
Finished Jul 24 05:37:29 PM PDT 24
Peak memory 248672 kb
Host smart-02d79d3b-5227-46c5-bdd6-24b010967255
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885286135 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_ping_timeout.3885286135
Directory /workspace/6.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_random_alerts.3074555458
Short name T605
Test name
Test status
Simulation time 3353717684 ps
CPU time 56.7 seconds
Started Jul 24 05:33:47 PM PDT 24
Finished Jul 24 05:34:44 PM PDT 24
Peak memory 256304 kb
Host smart-b69aa73b-d49b-4bca-90f7-1ed8c66874a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30745
55458 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_alerts.3074555458
Directory /workspace/6.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/6.alert_handler_random_classes.3281653389
Short name T586
Test name
Test status
Simulation time 980286072 ps
CPU time 56.85 seconds
Started Jul 24 05:33:49 PM PDT 24
Finished Jul 24 05:34:46 PM PDT 24
Peak memory 256268 kb
Host smart-babe9779-3bd6-45b3-8724-20ecdd03d407
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32816
53389 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_classes.3281653389
Directory /workspace/6.alert_handler_random_classes/latest

Test location /workspace/coverage/default/6.alert_handler_sig_int_fail.553213784
Short name T428
Test name
Test status
Simulation time 33664515 ps
CPU time 4.97 seconds
Started Jul 24 05:33:50 PM PDT 24
Finished Jul 24 05:33:55 PM PDT 24
Peak memory 248556 kb
Host smart-46d487bf-e08a-43d8-96f0-be68f2536124
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55321
3784 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_sig_int_fail.553213784
Directory /workspace/6.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/6.alert_handler_smoke.1034929229
Short name T430
Test name
Test status
Simulation time 638009864 ps
CPU time 39.77 seconds
Started Jul 24 05:33:41 PM PDT 24
Finished Jul 24 05:34:21 PM PDT 24
Peak memory 256804 kb
Host smart-dd74281a-a49b-4cf0-bd7f-80806aeb3239
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10349
29229 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_smoke.1034929229
Directory /workspace/6.alert_handler_smoke/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all.1609934386
Short name T426
Test name
Test status
Simulation time 4617328792 ps
CPU time 108.51 seconds
Started Jul 24 05:33:45 PM PDT 24
Finished Jul 24 05:35:34 PM PDT 24
Peak memory 256736 kb
Host smart-3eb84663-258c-41d7-ba63-76a4a2127cb5
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609934386 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_han
dler_stress_all.1609934386
Directory /workspace/6.alert_handler_stress_all/latest

Test location /workspace/coverage/default/7.alert_handler_alert_accum_saturation.451243847
Short name T200
Test name
Test status
Simulation time 32001071 ps
CPU time 3.2 seconds
Started Jul 24 05:33:42 PM PDT 24
Finished Jul 24 05:33:45 PM PDT 24
Peak memory 248928 kb
Host smart-1e69bcb3-bb1d-47cb-a62e-a6f1be8097d1
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=451243847 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_alert_accum_saturation.451243847
Directory /workspace/7.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/7.alert_handler_entropy.3322314617
Short name T120
Test name
Test status
Simulation time 15498802170 ps
CPU time 787.42 seconds
Started Jul 24 05:33:43 PM PDT 24
Finished Jul 24 05:46:51 PM PDT 24
Peak memory 272628 kb
Host smart-d3e6856b-e39c-4aeb-9967-416f232e7161
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322314617 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy.3322314617
Directory /workspace/7.alert_handler_entropy/latest

Test location /workspace/coverage/default/7.alert_handler_entropy_stress.1220051141
Short name T540
Test name
Test status
Simulation time 1357478418 ps
CPU time 6.87 seconds
Started Jul 24 05:33:42 PM PDT 24
Finished Jul 24 05:33:50 PM PDT 24
Peak memory 248600 kb
Host smart-7763f5ec-17de-4165-aeba-84dd76992dcb
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1220051141 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy_stress.1220051141
Directory /workspace/7.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/7.alert_handler_esc_alert_accum.107999088
Short name T389
Test name
Test status
Simulation time 7237241433 ps
CPU time 231.9 seconds
Started Jul 24 05:33:45 PM PDT 24
Finished Jul 24 05:37:37 PM PDT 24
Peak memory 256876 kb
Host smart-1cdf8e1f-3008-4811-8af8-48071b5d8cd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10799
9088 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_alert_accum.107999088
Directory /workspace/7.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/7.alert_handler_esc_intr_timeout.4054196015
Short name T81
Test name
Test status
Simulation time 153096409 ps
CPU time 13.87 seconds
Started Jul 24 05:33:38 PM PDT 24
Finished Jul 24 05:33:52 PM PDT 24
Peak memory 248708 kb
Host smart-95b20df8-b208-460f-89f2-52ec5e295381
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40541
96015 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_intr_timeout.4054196015
Directory /workspace/7.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_lpg.1298745301
Short name T270
Test name
Test status
Simulation time 79314960945 ps
CPU time 2233.88 seconds
Started Jul 24 05:33:42 PM PDT 24
Finished Jul 24 06:10:56 PM PDT 24
Peak memory 273260 kb
Host smart-976ee0e8-e085-4004-814f-441245314e3b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298745301 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg.1298745301
Directory /workspace/7.alert_handler_lpg/latest

Test location /workspace/coverage/default/7.alert_handler_lpg_stub_clk.1689341375
Short name T635
Test name
Test status
Simulation time 42561781625 ps
CPU time 967.58 seconds
Started Jul 24 05:33:44 PM PDT 24
Finished Jul 24 05:49:52 PM PDT 24
Peak memory 281452 kb
Host smart-54ba1848-7e40-4ed8-8199-bf4095a6aa46
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689341375 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg_stub_clk.1689341375
Directory /workspace/7.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/7.alert_handler_ping_timeout.3564469837
Short name T264
Test name
Test status
Simulation time 11840777015 ps
CPU time 511.8 seconds
Started Jul 24 05:33:47 PM PDT 24
Finished Jul 24 05:42:19 PM PDT 24
Peak memory 256468 kb
Host smart-a3e6ff1c-1066-442f-a9c2-c13edca7f02b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564469837 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_ping_timeout.3564469837
Directory /workspace/7.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_random_alerts.3637473163
Short name T50
Test name
Test status
Simulation time 1220336311 ps
CPU time 44.81 seconds
Started Jul 24 05:34:01 PM PDT 24
Finished Jul 24 05:34:46 PM PDT 24
Peak memory 256800 kb
Host smart-eb72089c-c112-4544-bea8-55751b65237c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36374
73163 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_alerts.3637473163
Directory /workspace/7.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/7.alert_handler_random_classes.4243295270
Short name T383
Test name
Test status
Simulation time 3907458027 ps
CPU time 57.12 seconds
Started Jul 24 05:33:56 PM PDT 24
Finished Jul 24 05:34:53 PM PDT 24
Peak memory 248552 kb
Host smart-30f88bf7-5ec3-4545-9997-f2f3f3f52c9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42432
95270 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_classes.4243295270
Directory /workspace/7.alert_handler_random_classes/latest

Test location /workspace/coverage/default/7.alert_handler_smoke.1409837745
Short name T359
Test name
Test status
Simulation time 5565435585 ps
CPU time 58.46 seconds
Started Jul 24 05:33:38 PM PDT 24
Finished Jul 24 05:34:37 PM PDT 24
Peak memory 256340 kb
Host smart-892cac74-7ba1-4ea6-a1e8-52754b35ae94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14098
37745 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_smoke.1409837745
Directory /workspace/7.alert_handler_smoke/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all.2151619014
Short name T85
Test name
Test status
Simulation time 32341486274 ps
CPU time 2033.67 seconds
Started Jul 24 05:33:40 PM PDT 24
Finished Jul 24 06:07:34 PM PDT 24
Peak memory 289644 kb
Host smart-34eed0ab-7e40-4b72-8a87-9855352d8291
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151619014 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_han
dler_stress_all.2151619014
Directory /workspace/7.alert_handler_stress_all/latest

Test location /workspace/coverage/default/8.alert_handler_alert_accum_saturation.2745115846
Short name T199
Test name
Test status
Simulation time 34005083 ps
CPU time 3.64 seconds
Started Jul 24 05:33:48 PM PDT 24
Finished Jul 24 05:33:51 PM PDT 24
Peak memory 248872 kb
Host smart-eaa8256c-761d-40d3-81d6-db2f0633211a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2745115846 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_alert_accum_saturation.2745115846
Directory /workspace/8.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/8.alert_handler_entropy.182087038
Short name T647
Test name
Test status
Simulation time 23874912531 ps
CPU time 1511.33 seconds
Started Jul 24 05:33:43 PM PDT 24
Finished Jul 24 05:58:55 PM PDT 24
Peak memory 273216 kb
Host smart-bd1b7547-681e-403e-8ef4-864a94c7f903
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182087038 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy.182087038
Directory /workspace/8.alert_handler_entropy/latest

Test location /workspace/coverage/default/8.alert_handler_entropy_stress.3963125190
Short name T612
Test name
Test status
Simulation time 603643938 ps
CPU time 14.44 seconds
Started Jul 24 05:33:44 PM PDT 24
Finished Jul 24 05:33:59 PM PDT 24
Peak memory 248560 kb
Host smart-33c89ae4-2835-42b5-ab16-cc1187bd6f34
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3963125190 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy_stress.3963125190
Directory /workspace/8.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/8.alert_handler_esc_alert_accum.356359158
Short name T65
Test name
Test status
Simulation time 2355625332 ps
CPU time 52.98 seconds
Started Jul 24 05:33:44 PM PDT 24
Finished Jul 24 05:34:37 PM PDT 24
Peak memory 256380 kb
Host smart-7946fc78-b94a-4c0a-9ba0-c61064f14cd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35635
9158 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_alert_accum.356359158
Directory /workspace/8.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/8.alert_handler_esc_intr_timeout.4106528893
Short name T467
Test name
Test status
Simulation time 608044341 ps
CPU time 31.71 seconds
Started Jul 24 05:33:58 PM PDT 24
Finished Jul 24 05:34:29 PM PDT 24
Peak memory 248044 kb
Host smart-343be649-6171-47f0-b20c-ed1fcb34be93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41065
28893 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_intr_timeout.4106528893
Directory /workspace/8.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_lpg.1363799383
Short name T514
Test name
Test status
Simulation time 20726881927 ps
CPU time 870.36 seconds
Started Jul 24 05:33:43 PM PDT 24
Finished Jul 24 05:48:14 PM PDT 24
Peak memory 272640 kb
Host smart-3ab446e0-6926-4680-983f-03dde656a365
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363799383 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg.1363799383
Directory /workspace/8.alert_handler_lpg/latest

Test location /workspace/coverage/default/8.alert_handler_lpg_stub_clk.736314286
Short name T626
Test name
Test status
Simulation time 29957755822 ps
CPU time 1940.04 seconds
Started Jul 24 05:33:45 PM PDT 24
Finished Jul 24 06:06:06 PM PDT 24
Peak memory 272600 kb
Host smart-30bb2049-40f0-4a1c-b812-5f844994e619
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736314286 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg_stub_clk.736314286
Directory /workspace/8.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/8.alert_handler_ping_timeout.3455279127
Short name T265
Test name
Test status
Simulation time 11667285974 ps
CPU time 457.3 seconds
Started Jul 24 05:33:42 PM PDT 24
Finished Jul 24 05:41:19 PM PDT 24
Peak memory 248720 kb
Host smart-a6160848-8da7-40dc-b666-04fe0867b750
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455279127 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_ping_timeout.3455279127
Directory /workspace/8.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_random_alerts.1295607458
Short name T716
Test name
Test status
Simulation time 2019200265 ps
CPU time 27.74 seconds
Started Jul 24 05:33:49 PM PDT 24
Finished Jul 24 05:34:17 PM PDT 24
Peak memory 248592 kb
Host smart-eb22eee8-6e11-4c65-a83b-7a1c3260398c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12956
07458 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_alerts.1295607458
Directory /workspace/8.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/8.alert_handler_random_classes.3431133929
Short name T579
Test name
Test status
Simulation time 289007098 ps
CPU time 28.8 seconds
Started Jul 24 05:33:40 PM PDT 24
Finished Jul 24 05:34:08 PM PDT 24
Peak memory 248372 kb
Host smart-f266ee9f-d6eb-4816-b9d9-8795d4faa8b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34311
33929 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_classes.3431133929
Directory /workspace/8.alert_handler_random_classes/latest

Test location /workspace/coverage/default/8.alert_handler_sig_int_fail.1412605756
Short name T240
Test name
Test status
Simulation time 4066349913 ps
CPU time 38.14 seconds
Started Jul 24 05:33:48 PM PDT 24
Finished Jul 24 05:34:26 PM PDT 24
Peak memory 256456 kb
Host smart-22b5786e-79a5-442d-92fc-3bdf0a64ceeb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14126
05756 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_sig_int_fail.1412605756
Directory /workspace/8.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/8.alert_handler_smoke.2072922116
Short name T402
Test name
Test status
Simulation time 727896830 ps
CPU time 33.42 seconds
Started Jul 24 05:33:42 PM PDT 24
Finished Jul 24 05:34:16 PM PDT 24
Peak memory 256752 kb
Host smart-454f7aaa-03f4-4495-b4a1-927c41b90dd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20729
22116 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_smoke.2072922116
Directory /workspace/8.alert_handler_smoke/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all_with_rand_reset.443874425
Short name T224
Test name
Test status
Simulation time 78999335014 ps
CPU time 2210.76 seconds
Started Jul 24 05:33:48 PM PDT 24
Finished Jul 24 06:10:39 PM PDT 24
Peak memory 289636 kb
Host smart-64972225-32f5-40ad-bf0f-c097a7438a5f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443874425 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 8.alert_handler_stress_all_with_rand_reset.443874425
Directory /workspace/8.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.alert_handler_alert_accum_saturation.1819109175
Short name T193
Test name
Test status
Simulation time 50468743 ps
CPU time 4.25 seconds
Started Jul 24 05:33:47 PM PDT 24
Finished Jul 24 05:33:51 PM PDT 24
Peak memory 248888 kb
Host smart-ee2bedf0-fb07-4f17-89b6-c505074519c8
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1819109175 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_alert_accum_saturation.1819109175
Directory /workspace/9.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/9.alert_handler_entropy.58535379
Short name T661
Test name
Test status
Simulation time 31513929063 ps
CPU time 1913.81 seconds
Started Jul 24 05:33:49 PM PDT 24
Finished Jul 24 06:05:43 PM PDT 24
Peak memory 273232 kb
Host smart-230e8166-581d-4ca8-be09-48718b7c46a4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58535379 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy.58535379
Directory /workspace/9.alert_handler_entropy/latest

Test location /workspace/coverage/default/9.alert_handler_entropy_stress.2479507963
Short name T502
Test name
Test status
Simulation time 345522694 ps
CPU time 9.91 seconds
Started Jul 24 05:33:43 PM PDT 24
Finished Jul 24 05:33:54 PM PDT 24
Peak memory 248604 kb
Host smart-5b886aac-40b6-4ca6-8b71-3ef1d98fb854
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2479507963 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy_stress.2479507963
Directory /workspace/9.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/9.alert_handler_esc_alert_accum.622771642
Short name T545
Test name
Test status
Simulation time 543689417 ps
CPU time 41.22 seconds
Started Jul 24 05:33:44 PM PDT 24
Finished Jul 24 05:34:26 PM PDT 24
Peak memory 256356 kb
Host smart-3fa692cb-75a2-4338-a5f3-a628be5ea3b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62277
1642 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_alert_accum.622771642
Directory /workspace/9.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/9.alert_handler_esc_intr_timeout.3391590824
Short name T34
Test name
Test status
Simulation time 270946140 ps
CPU time 28.56 seconds
Started Jul 24 05:33:41 PM PDT 24
Finished Jul 24 05:34:10 PM PDT 24
Peak memory 256288 kb
Host smart-efa6925b-0b43-46c8-98f2-18d7503a8ce8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33915
90824 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_intr_timeout.3391590824
Directory /workspace/9.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_lpg_stub_clk.2668554558
Short name T509
Test name
Test status
Simulation time 129721509571 ps
CPU time 1614.71 seconds
Started Jul 24 05:33:50 PM PDT 24
Finished Jul 24 06:00:45 PM PDT 24
Peak memory 288904 kb
Host smart-d80d2d37-d2a5-4374-a626-7f0661ef07b2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668554558 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg_stub_clk.2668554558
Directory /workspace/9.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/9.alert_handler_ping_timeout.4125907952
Short name T269
Test name
Test status
Simulation time 6131025461 ps
CPU time 246.44 seconds
Started Jul 24 05:33:57 PM PDT 24
Finished Jul 24 05:38:04 PM PDT 24
Peak memory 248696 kb
Host smart-01506e26-e19f-42f4-9d6d-8c589699f8df
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125907952 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_ping_timeout.4125907952
Directory /workspace/9.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_random_alerts.738350715
Short name T77
Test name
Test status
Simulation time 487958797 ps
CPU time 22.98 seconds
Started Jul 24 05:33:47 PM PDT 24
Finished Jul 24 05:34:10 PM PDT 24
Peak memory 248532 kb
Host smart-e7e95376-d099-49d2-a2da-b5f0a354755d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73835
0715 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_alerts.738350715
Directory /workspace/9.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/9.alert_handler_random_classes.2373458358
Short name T437
Test name
Test status
Simulation time 899722507 ps
CPU time 57.15 seconds
Started Jul 24 05:33:49 PM PDT 24
Finished Jul 24 05:34:46 PM PDT 24
Peak memory 256252 kb
Host smart-943e5670-4cac-4a3b-82af-fa919bcb12b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23734
58358 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_classes.2373458358
Directory /workspace/9.alert_handler_random_classes/latest

Test location /workspace/coverage/default/9.alert_handler_sig_int_fail.3363953430
Short name T699
Test name
Test status
Simulation time 957969341 ps
CPU time 34.2 seconds
Started Jul 24 05:33:50 PM PDT 24
Finished Jul 24 05:34:24 PM PDT 24
Peak memory 248140 kb
Host smart-2eaa5807-6841-455d-8cac-7558e9eb710b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33639
53430 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_sig_int_fail.3363953430
Directory /workspace/9.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/9.alert_handler_smoke.748268837
Short name T298
Test name
Test status
Simulation time 1168723276 ps
CPU time 43.9 seconds
Started Jul 24 05:33:47 PM PDT 24
Finished Jul 24 05:34:31 PM PDT 24
Peak memory 256684 kb
Host smart-40276917-d22f-4c78-96c2-536b56a59aba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74826
8837 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_smoke.748268837
Directory /workspace/9.alert_handler_smoke/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all.1563978415
Short name T306
Test name
Test status
Simulation time 41375470024 ps
CPU time 2344.16 seconds
Started Jul 24 05:33:43 PM PDT 24
Finished Jul 24 06:12:48 PM PDT 24
Peak memory 283148 kb
Host smart-8df7f77a-24d0-4023-abb6-2e1ef8a11706
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563978415 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_han
dler_stress_all.1563978415
Directory /workspace/9.alert_handler_stress_all/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all_with_rand_reset.1876859717
Short name T249
Test name
Test status
Simulation time 165292711755 ps
CPU time 1448.15 seconds
Started Jul 24 05:33:57 PM PDT 24
Finished Jul 24 05:58:06 PM PDT 24
Peak memory 281500 kb
Host smart-c1d7c5ce-72dd-4be5-83dc-488a26c33728
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876859717 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 9.alert_handler_stress_all_with_rand_reset.1876859717
Directory /workspace/9.alert_handler_stress_all_with_rand_reset/latest
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