Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
esc_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	8	0	8	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	65615	1			T1	60		T6	10		T7	6
class_i[0x1]	62196	1			T1	67		T18	216		T66	14
class_i[0x2]	53480	1			T1	17		T18	74		T7	1
class_i[0x3]	75627	1			T1	18		T6	21		T5	1372

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Summary for Variable esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	62411	1			T1	25		T6	5		T18	15
alert[0x1]	63006	1			T1	28		T6	8		T18	1
alert[0x2]	67969	1			T1	94		T6	11		T18	65
alert[0x3]	63532	1			T1	15		T6	7		T18	209

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Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

esc_integrity_fail

256597

1

T1

162

T6

21

T18

290

esc_ping_fail

321

1

T6

10

T7

7

T12

8

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Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	esc_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	alert[0x0]	62312	1			T1	25		T6	3		T18	15
esc_integrity_fail	alert[0x1]	62936	1			T1	28		T6	5		T18	1
esc_integrity_fail	alert[0x2]	67898	1			T1	94		T6	8		T18	65
esc_integrity_fail	alert[0x3]	63451	1			T1	15		T6	5		T18	209
esc_ping_fail	alert[0x0]	99	1			T6	2		T7	3		T12	4
esc_ping_fail	alert[0x1]	70	1			T6	3		T7	1		T321	2
esc_ping_fail	alert[0x2]	71	1			T6	3		T7	1		T12	2
esc_ping_fail	alert[0x3]	81	1			T6	2		T7	2		T12	2

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Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	class_i[0x0]	65499	1			T1	60		T5	3056		T16	1
esc_integrity_fail	class_i[0x1]	62132	1			T1	67		T18	216		T66	14
esc_integrity_fail	class_i[0x2]	53372	1			T1	17		T18	74		T34	2079
esc_integrity_fail	class_i[0x3]	75594	1			T1	18		T6	21		T5	1372
esc_ping_fail	class_i[0x0]	116	1			T6	10		T7	6		T12	2
esc_ping_fail	class_i[0x1]	64	1			T12	6		T125	1		T325	1
esc_ping_fail	class_i[0x2]	108	1			T7	1		T321	3		T297	7
esc_ping_fail	class_i[0x3]	33	1			T295	1		T125	2		T324	1